Operational amplifier

Abstract

This technology can suppress and reduce the impact of high-frequency external noise intrusion from power nodes. [Solution] The operational amplifier comprises a differential amplifier circuit 100A, an amplification circuit 200A, and an output circuit 300A. In the output circuit 300A, a vertical PNP transistor is used as the first transistor 1, which is the output transistor. A positive power supply voltage is applied to the isolation node that electrically isolates the first transistor 1 via a first noise suppression resistor 51. This configuration suppresses and prevents malfunctions even if high-frequency external noise enters from the power supply node and further enters the inside of the operational amplifier from the isolation node.

Description

Technical Field

[0001] The present invention relates to an operational amplifier, and particularly to an improvement in resistance to high-frequency external noise and reliability.

Background Art

[0002] One of the factors causing deterioration of the output characteristics of an operational amplifier is the intrusion of high-frequency external noise. As a method for suppressing and reducing the intrusion of such external noise, for example, a method of applying a shield by covering the chip surface layer with a metal maintained at a ground potential is known (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the above noise countermeasures are effective against high-frequency external noise that directly penetrates from the chip surface into its interior. However, to shield the chip surface layer, a multilayer wiring process is required, which causes an increase in cost. By the way, in an operational amplifier, particularly when high speed is required, vertical (vertical) PNP transistors are used instead of lateral (horizontal) PNP transistors, which are inferior in high-speed operability.

[0005] When using vertical PNP transistors, the epitaxial layer, which provides isolation, is typically connected to the power supply node, which is at the highest potential. However, this connection creates a parasitic capacitance between the collector node of the vertical PNP transistor and the power supply node. This parasitic capacitance allows high-frequency external noise to enter the power supply node, which in turn enters the operational amplifier from the collector of the vertical PNP transistor, causing circuit malfunction.

[0006] This invention has been made in view of the above circumstances and provides an operational amplifier that can suppress and reduce the effects of high-frequency external noise intrusion from power supply nodes. [Means for solving the problem]

[0007] To achieve the above-mentioned objectives of the present invention, the operational amplifier according to the present invention is An operational amplifier comprising: a differential amplifier circuit configured to enable differential amplification of an input signal; an amplification circuit for amplifying the output signal of the differential amplifier circuit; and an output circuit configured to amplify and output the output signal of the amplification circuit, The output circuit is provided with a final stage circuit using an output transistor which is a vertical PNP transistor, and the vertical PNP transistor is provided with an isolation node that electrically isolates the vertical PNP transistor, to which the power supply voltage can be applied via a resistor. [Effects of the Invention]

[0008] According to the present invention, the epitaxial layer that isolates the vertical PNP transistor is connected to the power supply node via a resistor. As a result, high-frequency external noise that enters the power supply node is suppressed and reduced by the resistor, thereby reducing its intrusion into the operational amplifier. Consequently, malfunctions of the operational amplifier can be reduced and prevented, and output fluctuations caused by the intrusion of high-frequency external noise can be suppressed and reduced. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram showing a first example of the circuit configuration of an operational amplifier in an embodiment of the present invention. [Figure 2] This is a circuit diagram showing a second example of the circuit configuration of an operational amplifier in an embodiment of the present invention. [Figure 3] This is a circuit diagram showing a third example of the circuit configuration of an operational amplifier in an embodiment of the present invention. [Figure 4] This is a circuit diagram showing a fourth example of the circuit configuration of an operational amplifier in an embodiment of the present invention. [Figure 5] This circuit diagram schematically shows the propagation path of high-frequency external noise into the circuit in a conventional operational amplifier using a vertical PNP transistor. [Figure 6] This is a schematic diagram illustrating a general cross-section of a vertical PNP transistor. [Figure 7] This is an equivalent circuit diagram for a vertical PNP transistor, taking into account parasitic diodes. [Figure 8] This is an equivalent circuit diagram that takes into account the parasitic capacitance of a vertical PNP transistor. [Figure 9] This is an equivalent circuit diagram that takes into account parasitic transistors in a vertical PNP transistor. [Figure 10] This is a circuit diagram showing an example of a measurement circuit configuration for measuring the operating voltage of a parasitic transistor in a vertical PNP transistor. [Figure 11] This is a characteristic curve showing the change in emitter current in response to a change in the isolation node voltage in a vertical PNP transistor. [Figure 12] This is a circuit diagram showing an example of a measurement circuit configuration for measuring the current flowing through the isolation node of a vertical PNP transistor. [Figure 13] This is a characteristic curve showing the current change characteristics at the isolation node of a vertical PNP transistor. [Figure 14]It is a circuit diagram showing a configuration example of a measurement circuit for measuring the output voltage change characteristics with respect to a high-frequency signal input from the power supply node of an operational amplifier. [Figure 15] It is a characteristic diagram showing an example of the output voltage change characteristics with respect to the input change of a high-frequency signal in the first circuit configuration example of the operational amplifier in the embodiment of the present invention. [Figure 16] It is a characteristic diagram showing an example of the output voltage change characteristics with respect to the input change of a high-frequency signal in the second circuit configuration example of the operational amplifier in the embodiment of the present invention.

Embodiments of the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 16. Note that the members, arrangements, etc. described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention. First, a first circuit configuration example of the operational amplifier in the embodiment of the present invention will be described with reference to FIG. 1. The operational amplifier in this first circuit configuration example is roughly divided into a differential amplifier circuit 100A constituting an input stage, an amplifier circuit 200A for amplifying the output of the differential amplifier circuit 100A, and an output circuit 300A for amplifying and outputting the output of the amplifier circuit 200A. The differential amplifier circuit 100A is configured using an operational amplifier 101, and an input signal is applied from the outside via an inverting input terminal (denoted as "INM" in FIG. 1) 81 and a non-inverting input terminal (denoted as "IMP" in FIG. 1) 82.

[0011] The amplifier circuit 200A amplifies and outputs the output of the differential amplifier circuit 100A to an input level required for the output circuit 300A, and has a configuration in which two outputs are input to the output circuit 300A described later. The output circuit 300A is roughly divided into an output control circuit (denoted as "CTL" in FIG. 1) 300A1 and a final stage circuit 300A2. The output control circuit 300A1 has a configuration similar to conventional circuits, controlling the output signal of the final stage circuit 300A in accordance with the output signal of the amplification circuit 200A.

[0012] The final stage circuit 300A2 is configured as a push-pull circuit using first and second transistors 1 and 2 (labeled "Q1" and "Q2" respectively in Figure 1). In this embodiment of the present invention, a vertical PNP transistor is used for the first transistor 1, and an NPN transistor is used for the second transistor 2. However, the collectors of the first and second transistors 1 and 2 are interconnected and connected to the output terminal 85, while the emitter of the first transistor 1 is supplied with a positive power supply voltage VCC via the positive power supply terminal 83, and the emitter of the second transistor 2 is supplied with a negative power supply voltage VEE via the negative power supply terminal 84.

[0013] Furthermore, in the first transistor 1, the collector is connected to the positive power supply terminal 83 via the parasitic diode 1a and the first noise suppression resistor (labeled "RX1" in Figure 1) 51, so that the positive power supply voltage VCC is applied. Here, parasitic diode 1a is an equivalent representation of the parasitic diode that occurs between the n-type epitaxial layer for isolation and the p-type diffusion collector node in a vertical PNP transistor. In this parasitic diode 1a, the cathode serves as an isolation node.

[0014] Thus, in this first circuit configuration example, by connecting the isolation node of the first transistor 1, which is a vertical PNP transistor, to the positive power supply voltage VCC via the first noise suppression resistor 51, malfunctions are suppressed and prevented even if high-frequency external noise enters from the power supply node and further enters the operational amplifier from the isolation node. Furthermore, unlike conventional countermeasures against high-frequency external noise, such as covering the chip surface with metal wiring at ground potential, this first circuit configuration example reduces malfunctions of operational amplifiers caused by high-frequency external noise entering the power supply node without using a multi-layer wiring process.

[0015] Here, we will explain the vertical PNP transistor used in the first transistor 1. First, standard bipolar process PNP transistors often utilize lateral PNP transistors, which can be realized using the same manufacturing process as NPN transistors. However, when high speed is required for operational amplifiers, lateral PNP transistors are insufficient, and vertical PNP transistors, which are suitable for high-speed operation, are used.

[0016] Figure 6 shows a schematic diagram illustrating the cross-sectional structure of a vertical PNP transistor. The following explanation of the cross-sectional structure of a vertical PNP transistor will refer to this figure. Since the cross-sectional structure of a vertical PNP transistor, as shown in Figure 6, is already well known, we will only provide a general explanation below.

[0017] A vertical PNP transistor is constructed by first using a p-type substrate 21 as the base, on which n+ embedding layers 22 and p+ embedding layers 23 are stacked, and an n-type epitaxial layer 24 is formed in an island-like manner through these layers. Then, a p-layer 25, which will become the collector C, is embedded in this n-type epitaxial layer 24 so as to surround a p-layer 26, which will become the emitter E, and an n-layer 27, which will become the base B, is embedded between the emitter E and the collector C. Furthermore, an n-layer 28, which serves as an isolation node IS for electrical element isolation of the vertical PNP transistor, is provided near the p-layer 25 that forms the collector C.

[0018] Figure 7 shows an equivalent circuit diagram that takes into account the parasitic diodes that occur in such a vertical PNP transistor, and this figure will be explained below. In a vertical PNP transistor, as has been known for some time, there is a parasitic diode 30a between the base B and the emitter E, with the emitter E side as the anode, and a parasitic diode 30b between the base B and the collector C, with the collector C side as the anode. Furthermore, a parasitic diode 30c exists between the collector C and the isolation node IS, with the collector C side acting as the anode, and a parasitic diode 30d exists between the isolation node IS and the substrate SUB, with the substrate SUB side acting as the anode.

[0019] Figure 8 shows an equivalent circuit diagram that takes into account the parasitic capacitance occurring in a vertical PNP transistor, and this figure will be explained below. As is well known, vertical PNP transistors have the following capacitances: base-emitter capacitance Cbe, base-collector capacitance Cbc, collector-isolation capacitance Cci, and isolation-substrate capacitance Cis. In Figure 8, "IS" refers to the isolation node and "SUB" refers to the substrate.

[0020] Due to its structure, this vertical PNP transistor differs from the lateral PNP transistor in that it achieves high speed, and therefore its base-emitter capacitance is about an order of magnitude smaller than that of the lateral PNP transistor. As can be seen from the equivalent circuit diagram explained earlier, such vertical PNP transistors are used with the isolation node connected to the highest potential, meaning the isolation node is also connected to the power supply node. Therefore, high-frequency external noise can enter the collector node through the isolation node and then into the operational amplifier, potentially causing malfunctions.

[0021] Next, Figure 5 shows a schematic circuit diagram illustrating the propagation path of high-frequency external noise into the circuit in a conventional operational amplifier using a vertical PNP transistor. The following explanation will describe the intrusion and propagation path of high-frequency external noise in conventional circuits, referring to this figure. This operational amplifier is broadly composed of a differential amplifier circuit 100X that constitutes the input stage, an amplification circuit 200X that amplifies the output of the differential amplifier circuit 100X, and an output circuit 300X. Furthermore, the output circuit 300X is broadly composed of an output control circuit (labeled "CTL" in Figure 5) 301X and a final stage circuit 302X. The final stage circuit 302X is a push-pull circuit consisting of the first and second transistors (labeled "Q1X" and "Q2X" respectively in Figure 5), 1X and 2X.

[0022] Note that the differential amplifier circuit 100X corresponds to the differential amplifier circuit 100A in Figure 1, the amplifier circuit 200X corresponds to the amplifier circuit 200A in Figure 1, the output circuit 300X corresponds to the output circuit 300A shown in Figure 1, the output control circuit 301X corresponds to the output control circuit 300A1 shown in Figure 1, and the final stage circuit 302X corresponds to the final stage circuit 300A2 shown in Figure 1. Since they basically have the same function and operation, a further detailed explanation will be omitted here.

[0023] In the operational amplifier shown in Figure 5, when high-frequency external noise RF enters the power supply node, the first transistor 1X is a vertical PNP transistor, so its base-emitter capacitance is smaller than that of a lateral PNP transistor, and less high-frequency external noise enters from the emitter node than when a lateral PNP transistor is used.

[0024] However, because the isolation node is directly connected to the power node, high-frequency external noise can enter the collector and base nodes from the isolation node (see the thick arrow in Figure 5). This high-frequency external noise that enters from the isolation node then enters the operational amplifier, causing malfunctions and resulting in fluctuations in the output voltage.

[0025] In contrast, in the present invention, as described above, the isolation node of the first transistor 1 is connected to the positive power supply voltage VCC via the first noise suppression resistor 51. Therefore, even if high-frequency external noise intrudes from the isolation node into the operational amplifier, malfunctions are suppressed and prevented.

[0026] Next, we will explain the selection of the resistance value of the first noise suppression resistor 51. First, when the isolation node of a vertical PNP transistor is directly connected to the power supply node, if the amplitude of the high-frequency external noise entering the power supply node is VRF, the high-frequency current flowing through the isolation node is IRF, and the frequency of the high-frequency external noise is f, then the high-frequency current IRF can be expressed as shown in Equation 1 below. For simplicity, parasitic capacitance between the isolation node and the substrate is ignored here.

[0027] IRF∝VRF / {1 / (2πfC)}...Equation 1

[0028] From Equation 1, it can be understood that in order to reduce the intrusion of high-frequency external noise into the operational amplifier, that is, to reduce the above current, it is necessary to insert a resistor R in series to increase the impedance.

[0029] If the high-frequency current when a resistor R is inserted is denoted as IRFr, then the high-frequency current IRFr can be expressed as shown in Equation 2 below.

[0030] IRFr∝VRF / {R 2 +1 / (2πfC) 2} 1 / 2 ...Formula 2

[0031] The larger the resistance R, the better the reduction effect on high-frequency currents. However, it is not unlimited and must meet the upper limit described below. First, Figure 9 shows an equivalent circuit considering parasitic transistors in a vertical PNP transistor having the structure described earlier in Figure 6. This equivalent circuit will be explained below. In Figure 9, the vertical PNP transistor Qx is formed by the generation of parasitic NPN transistors Qxp1 and Qxp2 by the p+ and n+ embedding layers.

[0032] As the collector-emitter voltage Vce of a vertical PNP transistor Qx decreases, the transistor Qx enters the saturation region, and its current amplification factor β(Ic / Ib) decreases. At this time, the base current of transistor Qx is supplied from the isolation node IS by the operation of the parasitic transistor Qxp1. In other words, the base current becomes almost the same as the current flowing through the isolation node IS. On the other hand, in the present invention, since the isolation node of the vertical PNP transistor is connected to the power supply node via a resistor, when the vertical PNP transistor operates in the saturation region, the current flowing through the isolation node and the voltage drop across the resistor connected between the isolation node and the power supply node cause the isolation node to be at a lower potential than the power supply node.

[0033] If the isolation node IS of the vertical PNP transistor Qx becomes significantly lower than the emitter potential, parasitic transistors Qxp1 and Qxp2 will activate. When these parasitic transistors Qxp1 and Qxp2 begin to operate, the emitter current of transistor Qx does not flow to the collector but instead flows to the substrate SUB, preventing normal transistor operation. Therefore, even when the vertical PNP transistor Qx is operating in the saturation region, it is necessary to prevent the parasitic transistors Qxp1 and Qxp2 from operating.

[0034] When the parasitic transistors Qxp1 and Qxp2 of a vertical PNP transistor Qx begin to operate, Vp_op (=VE-VISO) is the potential difference between the emitter node and the isolation node, I_iso is the current flowing through the isolation node of the vertical PNP transistor Qx, and R_iso ​​is the resistance inserted into the isolation node. The value of this resistance must be selected to satisfy equation 3 below. Note that VE is the emitter voltage of the vertical PNP transistor Qx, and VISO is the isolation node voltage of the vertical PNP transistor Qx.

[0035] Vp_op>I_iso×R_iso···Equation 3

[0036] Based on the above, the resistance value RX1 of the first noise suppression resistor 51 in the first circuit configuration example shown in Figure 1 will be explained. The first transistor 1, which is a vertical PNP transistor, is the output transistor, and its base current is maximum when it operates in the saturation region. Here, we will explain how to determine the voltage Vp_op at which the parasitic transistor described above operates. Figure 10 shows the measurement circuit used to determine the voltage Vp_op. The measurement circuit will be explained below with reference to this figure.

[0037] First, in Figure 10, Q1p1 and Q1p2 are parasitic transistors that occur in the vertical PNP transistor Q1x, and correspond to Qxp1 and Qxp2, respectively, which were explained earlier in Figure 9. Next, in Figure 10, the emitter of the vertical PNP transistor Q1x is connected to a 5V DC power supply 32 via an ammeter 31 that measures the emitter current IE. Furthermore, a first variable DC power supply 33 is connected to the collector of the vertical PNP transistor Q1x. This first variable DC power supply 33 can output voltages such as 4.9V, 4.95V, 4.975V, and 5V as desired, in order to operate the vertical PNP transistor Q1x in the saturation region.

[0038] Therefore, the collector-emitter voltages of transistor Q1x for each of the collector voltages mentioned above are 0.1V, 0.05V, 0.025V, and 0V. Furthermore, in this measurement circuit, the substrate SUB is given the ground potential, which is the lowest potential. Furthermore, a current source 34 is connected to the base of transistor Q1x, supplying a base current of 1mA. This base current is the maximum base current that flows when transistor Q1x is used as an output transistor, i.e., the DC current assumed to be the current I_iso flowing through the isolation node.

[0039] Furthermore, a second variable DC power supply 35 is connected to the isolation node IS. This second variable DC power supply 35 can change its output voltage between 5V and 4.5V in steps of, for example, 0.01V. However, as the potential of the isolation node IS falls below the highest potential, the parasitic transistors Q1p1 and Q1p2 begin to operate, and the emitter current increases. Therefore, the potential difference Vp_op between the emitter node and the isolation node at that point can be considered as the operating start voltage of the parasitic transistors Q1p1 and Q1p2.

[0040] FIG. 11 shows a characteristic diagram showing the change characteristics of the emitter current with respect to the change in the isolation node voltage of the vertical PNP transistor measured by the measurement circuit shown in FIG. 10. Hereinafter, this figure will be described. This characteristic diagram is the measurement result at an ambient temperature of 150 degrees, where the parasitic transistor is more likely to operate, that is, under severe conditions. In FIG. 11, the horizontal axis represents the isolation node voltage, and the vertical axis represents the emitter current.

[0041] Also, in FIG. 11, four characteristic lines showing the change characteristics of the emitter current with respect to the change in the isolation node voltage are shown with the collector voltage and the collector-emitter voltage as parameters. Among the four characteristic lines, the operating condition is the most severe when the collector-emitter voltage VCE = 0V. In this case, since the point where the emitter current changes is in the region where the isolation node voltage is 4.9V or less (see FIG. 11), the allowable value at which the isolation node can operate without problems even when it becomes lower than the highest potential is 5V - 4.9V = 0.1V. Therefore, when the potential difference Vp_op between the emitter node and the isolation node is 0.1V, the resistance value R_iso to be inserted into the isolation node based on the previous formula 3 is obtained as follows. First, when the previous formula 3 is transformed into an inequality for R_iso, the following formula 4 is obtained.

[0042] R_iso < Vp_op / I_iso ··· Formula 4

[0043] Substituting the previous Vp_op = 0.1V and I_iso = 1mA into Formula 4, the following Formula 5 is obtained.

[0044] R_iso < 0.1V / 1mA = 100Ω ··· Formula 5

[0045] That is, the resistance value RX1 of the first noise countermeasure resistor 51 connected to the isolation node of the first transistor 1 which is the output transistor needs to be selected to be less than 100Ω.

[0046] Next, Figure 15 shows a characteristic curve illustrating an example of the output voltage change characteristics in response to a change in the input of a high-frequency (RF) signal in the operational amplifier of the first circuit configuration example, and Figure 14 shows a circuit diagram illustrating an example of a measurement circuit for the output voltage change characteristics in response to a high-frequency input signal in the operational amplifier. The output voltage change characteristics of the operational amplifier of the first circuit configuration example in response to a high-frequency input signal will be explained below with reference to these figures. First, let's explain the characteristic curve shown in Figure 15. In the figure, the horizontal axis represents the RF signal power, and the vertical axis represents the operational amplifier output voltage of the operational amplifier.

[0047] Furthermore, in Figure 15, the solid characteristic curve represents the output voltage change in the operational amplifier of the first circuit configuration example with respect to a high-frequency input signal, while the dotted characteristic curve represents a similar characteristic curve of a conventional operational amplifier. The solid characteristic curve shown in Figure 15 is based on measurement results when the resistance value RX1 of the first noise suppression resistor 51 is set to 10Ω and 1GHz high-frequency noise (RF signal) is injected into the power node. This solid characteristic curve confirms that the output voltage remains almost constant regardless of the magnitude of the RF signal power.

[0048] On the other hand, in the case of an operational amplifier that does not take measures against high-frequency external noise from the power supply node, unlike conventional operational amplifiers, that is, unlike the operational amplifier in the embodiment of the present invention, as shown by the dotted line characteristic curve in Figure 15, the output voltage increases along with the RF signal power when the RF signal power exceeds approximately 27 dBm, and it can be confirmed that a stable output characteristic cannot be obtained.

[0049] Next, we will explain the measurement circuit shown in Figure 14. The measurement circuit shown in Figure 14 is a circuit for measuring the output voltage change characteristics in an operational amplifier in response to a high-frequency signal input from a power supply node. To explain the circuit configuration in detail, first, the operational amplifier OP1 constitutes a voltage follower circuit. A DC voltage of 6V, V2, is applied to the non-inverting input terminal of the operational amplifier OP1. Additionally, a DC voltage of 12V, V1, is applied to the positive power supply terminal VCC of the operational amplifier OP1 via an inductor LA. The inductor LA is used to block the propagation of AC signals to the DC voltage source.

[0050] Furthermore, a high-frequency signal from the AC voltage source RF is applied to the positive power supply terminal VCC of the operational amplifier OP1 via a DC-blocking capacitor CA, simulating high-frequency external noise. The output terminal of the operational amplifier OP1 is connected to the inverting input terminal and also to a DC voltmeter. In this measurement circuit configuration, the input power Pin of the high-frequency signal from the AC voltage source RF is sequentially increased, and the DC level of the output voltage Vout of the operational amplifier OP1 is measured at each step using a DC voltmeter. The result is shown by the dotted line in Figure 15. The frequency of the high-frequency signal output from the AC voltage source RF is 1 GHz.

[0051] Next, we will explain the second example of a circuit configuration with reference to Figure 2. The operational amplifier in the second circuit configuration example shown in Figure 2 is a specific circuit configuration example of the output control circuit 300A1. Note that components identical to those shown in Figure 1 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. In this second circuit configuration example of the operational amplifier, the output control circuit 300A1 is composed of a first idling current control circuit 301 and a second idling current control circuit 302, and these first and second idling current control circuits 301 and 302 are configured to control the idling currents of the first and second transistors 1 and 2 of the final stage circuit 300A2.

[0052] The first idling current control circuit 301 is composed of third to fifth transistors 3 to 5 (labeled "Q3," "Q4," and "Q5" respectively in Figure 2) and first and second constant current sources 61 and 62. NPN transistors are used for the third to fifth transistors 3 to 5. Furthermore, the second idling current control circuit 302 is composed of the sixth to eighth transistors (labeled "Q6," "Q7," and "Q8" respectively in Figure 2) 6 to 8, the third and fourth constant currents 63 and 64, and the second noise suppression resistor (labeled "RX2" in Figure 2) 52. Vertical PNP transistors are used for the sixth to eighth transistors 6 to 8. Furthermore, in Figure 2, the parasitic diodes 6a to 8a, as explained earlier in Figure 7, are equivalently represented in the sixth to eighth transistors 6 to 8, which are vertical PNP transistors.

[0053] In the first idling current control circuit 301, the bases of the third and fourth transistors 3 and 4 are connected to each other, and the collector of the third transistor 3 is connected to the base of the third transistor 3, so the third transistor 3 is in a so-called diode connection. Furthermore, the first constant current source 61 is provided in series between the collector of the third transistor 3 and the positive power supply terminal 83. Furthermore, the collector of the fourth transistor 4 is connected to one output terminal of the amplification circuit 200A, the base of the first transistor 1, and the emitter of the seventh transistor 7.

[0054] On the other hand, the emitter of the third transistor 3 is connected to the collector of the fifth transistor 5. This fifth transistor 5 is configured in a so-called diode configuration, with its collector and base interconnected, and its emitter connected to the negative power supply terminal 84. Furthermore, the emitter of the fourth transistor 4 is connected to the other output terminal of the amplification circuit 200A, the base of the second transistor 2, and the collector of the seventh transistor 7, and a second constant current source 62 is provided in series between the emitter and the negative power supply terminal 84.

[0055] Next, in the second idling current control circuit 302, first, the bases of the seventh and eighth transistors 7 and 8 are connected to each other, and the collector of the eighth transistor 8 is connected to the base of the seventh transistor 7 and 8, respectively, so the eighth transistor 8 is in a so-called diode connection. Furthermore, a third constant current source 63 is provided in series between the emitter of the seventh transistor 7 and the positive power supply terminal 83. On the other hand, the emitter of the eighth transistor 8 is connected to the collector of the sixth transistor 6. The sixth transistor 6 is configured in a so-called diode configuration, with its collector and base interconnected, and its emitter connected to the positive power supply terminal 83.

[0056] Furthermore, a fourth constant current source 64 is connected in series between the collector of the eighth transistor 8 and the negative power supply terminal 84. Furthermore, the cathodes of the parasitic diodes 7a and 8a of the seventh and eighth transistors 7 and 8, and the cathode of the parasitic diode 6a of the sixth transistor 6 are connected to the positive power supply terminal 83 via a second noise suppression resistor 52. These first and second idling current control circuits 301 and 302, along with the first and second transistors 1 and 2, constitute a cross-coupled feedforward class AB amplifier circuit.

[0057] In this second circuit configuration example, as in the first circuit configuration example, the isolation nodes of the sixth to eighth transistors 6-8, which are vertical PNP transistors, are connected to the power supply node via the second noise suppression resistor 52. Therefore, the intrusion of high-frequency external noise into the operational amplifier through the isolation nodes of these sixth to eighth transistors 6-8 is reduced, thereby suppressing and preventing malfunctions.

[0058] Next, we will explain the selection of the resistance value RX2 of the second noise suppression resistor 52. First, unlike the case of the first transistor 1, transistors 6 through 8 always operate in the non-saturation region in order to perform the idling current control function. Therefore, the resistance value R_iso ​​required to prevent the parasitic transistors from operating must be selected to satisfy equation 3 above, where Vp_op is the voltage at which the parasitic transistors of the vertical PNP transistor operate and I_iso is the leakage current flowing through the isolation node.

[0059] Figure 12 shows an example of a circuit configuration for a measurement circuit that measures leakage current I_iso, and this figure will be explained below. A DC voltage source 72, VE=5V, is applied to the emitter of the vertical PNP transistor Qx via an ammeter 71. Furthermore, since the vertical PNP transistor Qx operates in the non-saturation region, a DC voltage source 73, VC=4.5V, is applied to the collector so that the emitter-collector voltage VCE becomes VCE=4.5V-5V=-0.5V.

[0060] Furthermore, a variable DC voltage source 74 allows a base voltage VB of 5V to 4.2V to be applied to the base of the vertical PNP transistor Qx in order to observe the emitter current and isolation current due to changes in the base-emitter voltage. Furthermore, the isolation node IS, like the emitter, has VE=5V applied to it via DC ammeter 75. Furthermore, in Figure 12, the collector-isolation node parasitic diode of the vertical PNP transistor Qx is shown as Dp1, and the isolation node-substrate parasitic diode is shown as Dp2. In Figure 12, "IS" refers to the isolation node, and "SUB" refers to the substrate.

[0061] The results of measuring the base-emitter voltage characteristics of the emitter current and isolation current of a vertical PNP transistor Qx under the most severe temperature conditions of 150°C using this measurement circuit are shown in Figure 13, which will be explained below. In Figure 13, the horizontal axis represents the base-emitter voltage VBE of the vertical PNP transistor Qx, and the vertical axis represents the emitter current and isolation current of the vertical PNP transistor Qx. In Figure 13, the solid characteristic curve represents the characteristic change in emitter current in response to a change in the base-emitter voltage VBE, while the dashed-dot characteristic curve represents the characteristic change in isolation current in response to a change in the base-emitter voltage VBE.

[0062] For example, when designing first and second idle current control circuits 301 and 302 such that the emitter currents of the sixth to eighth transistors 6 to 8 in the second circuit configuration example shown in Figure 2 are each 20 μA, the required isolation current can be calculated as follows. In other words, in Figure 13, the isolation current at the point on the characteristic curve of the isolation current change corresponding to the point where the emitter current is 20 μA (see the solid characteristic curve) (see the dashed-dotted characteristic curve) is the current required in this case, and in the example in Figure 13, it is 0.06 μA. In other words, the isolation current required for transistors 6 to 8, which are vertical PNP transistors, is 0.06 μA.

[0063] On the other hand, since the three transistors 6 to 8 of the second noise countermeasure resistor 52 are connected, the isolation current to be passed through the second noise countermeasure resistor 52 is three times the isolation current per vertical PNP transistor described above. Therefore, the sum of the isolation currents of the transistors 6 to 8 of the sixth to eighth transistors is 0.06 μA × 3 = 0.18 μA. Here, the voltage Vp_op at which the parasitic transistor of the vertical PNP transistor operates is set to 0.1 V as in the previous first circuit configuration example as the value in the most severe saturation region, and R_iso under the above-described isolation current I_iso = 0.18 μA is calculated based on the previous equation 4, and the following equation 6 holds.

[0064] R_iso < Vp_op / I_iso = 0.1 V / 0.18 μA = 556 kΩ ··· Equation 6

[0065] That is, R_iso < 556 kΩ. In the second circuit configuration example, in fact, a resistance value of 2 kΩ is selected for the second noise countermeasure resistor 52. The reason is that it is preferable to use the same type of resistor as other resistors, and under this premise, if the order of the resistance value is extremely different, it will cause an increase in cost, so such a situation is avoided. [[ID=z15]] Also, the reason for selecting 2 kΩ as the resistance value of the second noise countermeasure resistor 52 is the same as in the previous first circuit configuration example and the third and fourth circuit configuration examples described later, but it is also to ensure a sufficient margin in consideration of the increase in current due to mass production variations.

[0066] FIG. 16 shows a characteristic diagram showing an example of the output voltage change characteristic with respect to the input change of the high-frequency signal in the operational amplifier of the second circuit configuration example. Hereinafter, this figure will be described. The characteristic diagram shown in this FIG. 16 is the result measured by the measurement circuit shown in FIG. 14, similar to that described in the previous first circuit configuration example. In Figure 16, the horizontal axis represents the RF signal power, and the vertical axis represents the operational amplifier output voltage of the operational amplifier.

[0067] Furthermore, in Figure 16, the solid characteristic curve represents the output voltage change in response to a high-frequency input signal in the operational amplifier of the second circuit configuration example, while the dotted characteristic curve represents a similar characteristic curve for a conventional operational amplifier. The solid characteristic curves shown in Figure 16 represent the measurement results when the resistance value RX1 of the first noise suppression resistor 51 is set to 10Ω, the resistance value RX2 of the second noise suppression resistor 52 is set to 2kΩ, and a 100MHz high-frequency noise (RF signal) is injected into the power supply node.

[0068] As shown in Figure 16, in the case of the operational amplifier in the second circuit configuration example, it can be confirmed that the output voltage Vout can be maintained at 6V up to an input power of around 22dBm (see the solid characteristic curve). In contrast, with conventional operational amplifiers, the output voltage begins to fluctuate when the input power exceeds approximately 8 dBm, and it can be confirmed that the stability of the output characteristics cannot be ensured (see the dotted characteristic curve in Figure 16). Thus, it can be confirmed that the operational amplifier in the second circuit configuration example, like the operational amplifier in the first circuit configuration example, does not experience fluctuations in output voltage even with higher input power compared to conventional operational amplifiers, and that the influence of high-frequency external noise on the output voltage is reliably suppressed and reduced.

[0069] Next, we will explain a third circuit configuration example with reference to Figure 3. The operational amplifier in this third circuit configuration example is a specific circuit configuration example of the differential amplifier circuit 100A and the amplifier circuit 200A shown earlier in Figure 1. Note that components identical to those shown in Figures 1 and 2 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. First, we will explain a specific circuit configuration example of the differential amplifier circuit 100A. In the third circuit configuration example, the differential amplifier circuit 100A is mainly composed of the ninth and tenth transistors (labeled "Q9" and "Q10" respectively in Figure 3) 9 and 10, the fifth constant current source 65, and the third noise suppression resistor (labeled "RX3" in Figure 3) 53.

[0070] The ninth and tenth transistors, 9 and 10, are vertical PNP transistors, and are connected as described below to form an emitter-coupled differential pair, enabling differential amplification. The emitters of the ninth and tenth transistors 9 and 10 are interconnected, and a fifth constant current source 65 is connected between this connection point and the positive power supply terminal 83. On the other hand, the collectors of the ninth and tenth transistors 9 and 10 are connected to the input stage of the amplifier circuit 200A, which will be described below.

[0071] Furthermore, the cathodes of the parasitic diodes 9a and 10a of the ninth and tenth transistors 9 and 10, i.e., the isolation nodes, are interconnected and connected to the positive power supply terminal 83 via a third noise suppression resistor 53. The base of the ninth transistor 9 is connected to the inverting input terminal 81, and the base of the tenth transistor 10 is connected to the non-inverting input terminal 82.

[0072] Next, in the third circuit configuration example, the amplification circuit 200A is broadly composed of a pre-amplification section 200A1, a constant current source section 200A2, and a buffer amplifier 200A3. The preamplifier section 200A1 is primarily composed of 13th and 14th transistors (labeled "Q13" and "Q14" respectively in Figure 3) 13 and 14, which are NPN type transistors, and 3rd and 4th resistors (labeled "R3" and "R4" respectively in Figure 3) 43 and 44. The preceding amplifier section 200A1 is configured as a common-base amplifier circuit using the 13th and 14th transistors 13 and 14.

[0073] Specifically, the bases of the 13th and 14th transistors 13 and 14 are interconnected, and the collector of the 13th transistor 13 is connected to them. The collector of the 13th transistor 13 is connected to the constant current source 200A2, which will be described later. On the other hand, the collector of the 14th transistor 14 is connected to the constant current source 200A2, which will be described later, and its connection point is connected to the input stage of the buffer amplifier 200A3. Furthermore, the emitter of the 13th transistor 13 is connected to the collector of the 9th transistor 9, and via the third resistor 43, the emitter of the 14th transistor 14 is connected to the collector of the 10th transistor 10, and via the fourth resistor 44, both are connected to the negative power supply terminal 84.

[0074] Next, the constant current source section 200A2, which is a circuit that supplies a constant current to the aforementioned preamplifier section 200A1, is mainly composed of 11th and 12th transistors (labeled "Q11" and "Q12" respectively in Figure 3) 11 and 12 using vertical PNP transistors, 1st and 2nd resistors (labeled "R1" and "R2" respectively in Figure 3) 41 and 42, and a 4th noise suppression resistor (labeled "RX4" in Figure 3) 54.

[0075] First, the emitter of the 11th transistor 11 is connected to the positive power supply terminal 83 via the first resistor 41, and the emitter of the 12th transistor 12 is connected to the positive power supply terminal 83 via the second resistor 42. Furthermore, the collector of the 11th transistor 11 is connected to the collector of the aforementioned 13th transistor 13. Furthermore, the collector of the 12th transistor 12, along with the collector of the aforementioned 14th transistor 14, is connected to the input stage of the buffer amplifier 200A3.

[0076] Furthermore, the cathodes of the parasitic diodes 11a and 12a of the 11th and 12th transistors 11 and 12, i.e., the isolation nodes, are interconnected and connected to the positive power supply terminal 83 via a fourth noise suppression resistor 54. Furthermore, a required bias voltage Vbias, generated by a circuit (not shown) within the operational amplifier, is applied to the bases of the 11th and 12th transistors 11 and 12, respectively.

[0077] The buffer amplifier 200A3 has a conventional and well-known configuration, buffering and amplifying the output of the preamplifier 200A1, with two outputs input to the output circuit 300A. In this third circuit configuration example of the operational amplifier, the isolation nodes of the 9th and 10th transistors 9 and 10 are connected to the power supply node via the third noise suppression resistor 53, and the isolation nodes of the 11th and 12th transistors 11 and 12 are connected to the power supply node via the fourth noise suppression resistor 54. Therefore, similar to the first and second circuit configuration examples, malfunctions caused by high-frequency external noise entering the operational amplifier from the power supply node via the isolation nodes are suppressed and reduced.

[0078] Next, we will explain the fourth circuit configuration example with reference to Figure 4. In this fourth circuit configuration example, the operational amplifier differs in that the differential amplifier circuit 100A that constitutes the input stage shown in Figures 1 and 3 is replaced with a differential amplifier circuit 100B having the configuration described below. The remaining circuit configuration is the same as that of the third circuit configuration example shown in Figure 3. Note that components identical to those shown in Figures 1 and 3 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences.

[0079] The differential amplifier circuit 100B is configured to enable differential amplification by having two differential pair circuits 100B1 and 100B2 arranged in parallel with respect to the input. The first differential pair circuit 100B1 is basically the same as the differential amplifier circuit 100A described in the third circuit configuration example. Therefore, a detailed explanation of the circuit configuration of the first differential pair circuit 100B1 will be omitted here.

[0080] The second differential pair circuit 100B2 is mainly composed of 15th and 16th transistors (labeled "Q15" and "Q16" respectively in Figure 4) 15 and 16, which are NPN type transistors, and a sixth constant current source 66. First, the emitters of the 15th and 16th transistors 15 and 16 are interconnected, and a sixth constant current source 66 is connected between this connection point and the negative power supply terminal 84.

[0081] Furthermore, the collector of the 15th transistor 15 is connected to the emitter of the 11th transistor 11 of the amplification circuit 200A, and the collector of the 16th transistor 16 is connected to the emitter of the 12th transistor 12 of the amplification circuit 200A. The base of the 15th transistor 15 is connected to the inverting input terminal 81, and the base of the 16th transistor 16 is connected to the non-inverting input terminal 82. Thus, by providing the second differential pair circuit 100B2, it becomes possible to handle a wider range of input signal levels and stabilize the output voltage. The operational amplifier in this fourth circuit configuration example, like the operational amplifier in the third circuit configuration example shown in Figure 3, is designed to suppress and reduce malfunctions caused by high-frequency external noise entering the operational amplifier from the power supply node via the isolation node. [Industrial applicability]

[0082] This technology can be applied to operational amplifiers using vertical PNP transistors where suppression and reduction of the effects of high-frequency external noise intrusion from power supply nodes are desired. [Explanation of Symbols]

[0083] 1…First transistor 2…Second transistor 51…First noise suppression resistor 52…Second noise suppression resistor 53…Third noise suppression resistor 54…Fourth noise suppression resistor 100A, 100B... Differential amplifier circuit 200A... Amplifier circuit 300A…Output circuit

Claims

1. An operational amplifier comprising: a differential amplifier circuit configured to enable differential amplification of an input signal; an amplification circuit for amplifying the output signal of the differential amplifier circuit; and an output circuit configured to amplify and output the output signal of the amplification circuit, The output circuit is provided with a final stage circuit using an output transistor which is a vertical PNP transistor, and the vertical PNP transistor is characterized in that an isolation node for electrically isolating the vertical PNP transistor is provided so that a power supply voltage can be applied to it via a resistor.

2. The output circuit comprises an output control circuit and a final stage circuit, wherein the output control circuit controls the output signal of the final stage circuit in accordance with the output signal of the amplification circuit, and the final stage circuit is configured such that the output level of the output signal is controlled by the output control circuit. The final stage circuit is configured as a push-pull circuit using first and second output transistors, and the first transistor is a vertical PNP transistor. The output control circuit comprises a first idling current control circuit configured to control the idling current of the second transistor, and a second idling current control circuit configured to control the idling current of the first transistor. The second idling current control circuit comprises a sixth to eighth transistor using a vertical PNP transistor, The operational amplifier according to claim 1, characterized in that the seventh and eighth transistors have their bases connected to each other, and the connection point is connected to the collector of the eighth transistor, the emitter of the seventh transistor is connected to the base of the first transistor and to which a positive power supply voltage can be applied via a third constant current source, the collector of the seventh transistor is connected to the base of the second transistor, the emitter of the eighth transistor is connected to the collector and base of the sixth transistor, the emitter of the sixth transistor is connected to which the positive power supply voltage can be applied, the collector of the eighth transistor is connected to which a negative power supply voltage can be applied via a fourth constant current source, and the cathodes of the parasitic transistors of the seventh and eighth transistors and the isolation nodes of the sixth to eighth transistors are both configured to be able to receive the positive power supply voltage via a second noise suppression resistor.

3. The differential amplifier circuit comprises a ninth and a tenth transistor using vertical PNP transistors, and the isolation nodes of the ninth and tenth transistors are configured to receive the positive power supply voltage via a third noise suppression resistor, The amplification circuit comprises a pre-amplifier section that amplifies the output of the differential amplification circuit, a buffer amplifier that buffers and amplifies the output of the pre-amplifier section, and a constant current source section that supplies current to the pre-amplifier section. The constant current source section comprises 11th and 12th transistors using vertical PNP transistors, and the isolation nodes of the 11th and 12th transistors are configured to be able to receive the positive power supply voltage via a fourth noise suppression resistor, characterized in that the operational amplifier is as described in claim 1 or 2.

4. The operational amplifier according to claim 3, characterized in that the differential amplifier circuit has a differential pair circuit composed of the 9th and 10th transistors as the first differential pair circuit, and in addition to the first differential pair circuit, a second differential pair circuit composed of the 15th and 16th transistors is provided in parallel with the input of the first differential pair circuit.

5. The operational amplifier according to claim 1 or 2, characterized in that the resistance value of the noise suppression resistor connected between the isolation node and the power node of the vertical PNP transistor is selected such that the inequality Vp_op > I_iso × R_iso ​​is satisfied when Vp_op is the voltage at which the parasitic transistor of the vertical PNP transistor operates, I_iso is the current flowing through the isolation node of the vertical PNP transistor, and R_iso ​​is the resistance value of the noise suppression resistor.

6. The operational amplifier according to claim 3, characterized in that the resistance value of the noise suppression resistor connected between the isolation node and the power node of the vertical PNP transistor is selected such that the inequality Vp_op > I_iso × R_iso ​​is satisfied when Vp_op is the voltage at which the parasitic transistor of the vertical PNP transistor operates, I_iso is the current flowing through the isolation node of the vertical PNP transistor, and R_iso ​​is the resistance value of the noise suppression resistor.

7. The operational amplifier according to claim 4, characterized in that the resistance value of the noise suppression resistor connected between the isolation node and the power node of the vertical PNP transistor is selected such that the inequality Vp_op > I_iso × R_iso ​​is satisfied when Vp_op is the voltage at which the parasitic transistor of the vertical PNP transistor operates, I_iso is the current flowing through the isolation node of the vertical PNP transistor, and R_iso ​​is the resistance value of the noise suppression resistor.

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