SiC epitaxial wafer, method for manufacturing a SiC epitaxial wafer, and SiC device

Abstract

It is possible to estimate the carrier lifetime, and the Z-axis in the depth direction of the SiC epitaxial layer. 1 / 2 The present invention provides a SiC epitaxial wafer and a SiC device having a SiC epitaxial layer in which variations in center density are suppressed. [Solution] The SiC epitaxial wafer consists of a SiC substrate 1 and a first surface 1A of the substrate, Z 1 / 2 A SiC epitaxial layer 2 having a center 3 inside, and the Z of the SiC epitaxial layer 1 / 2 The uniformity of the center density in the depth direction is less than 0.5% / μm.

Description

[Technical Field]

[0001] The present invention relates to a SiC epitaxial wafer, a method for manufacturing a SiC epitaxial wafer, and a SiC device. [Background technology]

[0002] Silicon carbide (SiC) has a dielectric breakdown field that is an order of magnitude larger and a band gap that is three times larger than that of silicon (Si). Furthermore, SiC has properties such as a thermal conductivity that is approximately three times higher than that of silicon (Si). Therefore, SiC is expected to have applications in power devices, high-frequency devices, and high-temperature operating devices. For this reason, SiC epitaxial wafers have recently come into use in semiconductor devices such as those mentioned above.

[0003] SiC epitaxial wafers are obtained by depositing a SiC epitaxial layer on a SiC substrate using chemical vapor deposition (CVD). The SiC epitaxial layer serves as the active region of the SiC device.

[0004] Defects within the SiC epitaxial layer of a SiC epitaxial wafer affect the properties of SiC devices. For example, Patent Document 1 describes Z defects within the SiC epitaxial layer. 1 / 2 It is stated that the center can affect career lifespan.

[0005] Non-patent document 1 contains Z 1 / 2 The text describes a procedure to reduce centers by performing a surface treatment after forming a SiC epitaxial layer. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2016-132604 [Non-patent literature]

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] <000028F>As described above, since the Z 1 / 2 center affects the characteristics of the SiC device, it is preferable to be able to control the density and distribution of the Z 1 / 2 center in the SiC epitaxial layer. However, it is difficult to control the density of the Z 1 / 2 center during the film formation process of the epitaxial layer.

[0009] In Patent Document 1, ten arbitrary regions in the SiC epitaxial layer are measured by DLTS, and the average value of the density of the Z 1 / 2 center in the ten regions is preferably 5×10 11 cm -3 or less. Patent Document 1 discloses that chemical mechanical polishing (CMP) is performed on the main surface of the SiC epitaxial wafer after epitaxial layer formation, and it is considered that the density of the Z 1 / 2 center in the SiC epitaxial wafer can be reduced by such post-treatment after epitaxial layer formation. Incidentally, in Patent Document 1, the selection criteria for the ten measurement regions for measuring the Z 1 / 2 center density are not specified, and it is unclear which region is preferably such that the average value of the Z 1 / 2 center density is within the above numerical range.

[0010] Non-Patent Document 1 states that the Z 1 / 2 center density of a SiC epitaxial wafer having a 100-μm-thick SiC epitaxial layer by the CVD method is 1.5×10 12 ~3.0×10 12 (cm -3) is said to have been. Non-patent document 1 describes the Z at positions where the depth component is different in a measurement area with the same in-plane direction. 1 / 2 The measurement results for the center density are shown. According to these measurement results, the Z in the SiC epitaxial layer 1 / 2 The center density is highest at the outermost surface, at 2.0 × 10⁻⁶ 12 cm -3 The lowest value is 1.2 × 10⁻⁶ at a depth of 100 μm. 12 cm -3 And Z in the depth direction 1 / 2 The variation in center density was shown to be 0.66% per μm (0.66 (% / μm)). Furthermore, the Z of the SiC epitaxial layer... 1 / 2 The center density is reduced by post-treatment involving carbon ion implantation and heat treatment after epitaxial growth, and after post-treatment, the detection limit (1.0 × 10⁻¹⁰) is reduced at any depth. 11 cm -3 It is said to be less than ).

[0011] Z in such a SiC epitaxial layer 1 / 2 When the center density is below the detection limit, it is difficult to estimate the carrier lifetime, and the Z-axis in the depth direction is also problematic. 1 / 2 The variation in center density is unknown.

[0012] This invention was made in view of the above circumstances, and makes it possible to estimate the carrier lifetime, and the Z in the depth direction of the SiC epitaxial layer. 1 / 2 The objective is to provide a SiC epitaxial wafer, a method for manufacturing a SiC epitaxial wafer, and a SiC device in which variations in center density are suppressed. [Means for solving the problem]

[0013] To solve the above problems, the present invention provides the following means.

[0014] (1) A SiC epitaxial wafer according to one embodiment of the present invention comprises a SiC substrate and a SiC epitaxial layer formed on the first surface of the SiC substrate, wherein the Z of the SiC epitaxial layer 1 / 2 The uniformity of the center density in the depth direction is less than 0.5% / μm.

[0015] (2) The diameter of the SiC epitaxial wafer in (1) above may be 149 mm or more.

[0016] (3) The diameter of the SiC epitaxial wafer in (1) above may be 199 mm or more.

[0017] (4) The SiC epitaxial wafers described in (1) to (3) above have a central coordinate in plan view of (0,0) and a radius of R, and the Z coordinates of the surface near the outermost surface in the depth direction of the surface at coordinates (0,0), (±R / 2,0) and (0,±R / 2) and the surface near the first surface are 10 Z coordinates 1 / 2 Center density is 1 × 10 11 cm -3 The above 1 x 10 13 cm -3 The following is also acceptable.

[0018] (5) The SiC epitaxial wafers described in (1) to (4) above have a central coordinate in plan view of (0,0) and a radius of R, and the Z coordinates of the surface near the outermost surface in the depth direction of the surface at coordinates (0,0), (±R / 2,0) and (0,±R / 2) and the surface near the first surface are 10 Z coordinates 1 / 2 The maximum and minimum values ​​of the center density (Max and Min) may satisfy equation (1). [{(Max-Min) / mean}×100]<(5+0.5×D)···(1) (D: Distance (μm) between the surface near the outermost surface and the surface near the first surface, mean: 10 Zs 1 / 2 Average center density (cm -3 ))

[0019] (6) A method for manufacturing a SiC epitaxial wafer according to one embodiment of the present invention comprises a forming step of forming a SiC epitaxial layer on the first surface of a SiC substrate by chemical vapor deposition using a growth apparatus having a gas supply port and a gas outlet for supplying Si-based gas and C-based gas, wherein the forming step includes an adjustment step of analyzing the gas discharged from the gas outlet by quadrupole mass spectrometry, increasing the amount of C-based gas supplied to the Si-based gas if the analyzed C / Si ratio is lower than a target value, and decreasing the amount of C-based gas supplied to the Si-based gas if the analyzed C / Si ratio is higher than the target value.

[0020] (7) The method for manufacturing a SiC epitaxial wafer described in (6) above further comprises a test step and a feedback step prior to the formation step, The aforementioned test process is: A preliminary measurement step for measuring the weight and surface area of ​​by-products in the growth apparatus, A first forming step involves forming a SiC epitaxial layer on the first surface of a test SiC substrate while analyzing the gas discharged from the gas outlet using the growth apparatus that performed the preliminary measurement step, using quadrupole mass spectrometry. The Z of the SiC epitaxial layer of the SiC epitaxial wafer formed in the first formation step. 1 / 2 An analysis process to analyze the uniformity of the center density in the depth direction, The measurement step includes measuring the weight and surface area of ​​the by-products in the growth apparatus after the first forming step, The feedback process may set the target value based on the results of the test process.

[0021] (8) In the method for manufacturing SiC epitaxial wafers described in (6) and (7) above, The aforementioned analysis process is performed on a SiC epitaxial wafer with a planar center (0,0) and radius R, A film thickness measurement process for measuring the film thickness of a SiC epitaxial layer, Z at five locations: (0,0), (±R / 2,0), and (0,±R / 2). 1 / 2A first evaluation step in which the center density is evaluated from the outermost surface of the SiC epitaxial wafer by the DLTS method, A removal step of removing the SiC epitaxial layer to a predetermined thickness, After the removal process, the Z at five locations: (0,0), (±R / 2,0), and (0,±R / 2) 1 / 2 The process includes a second evaluation step of evaluating the center density from the outermost surface of the SiC epitaxial wafer using the DLTS method, Z in the first evaluation step at the same location in plan view 1 / 2 Center density and Z in the second evaluation step 1 / 2 The difference from the center density is divided by the predetermined thickness to obtain Z 1 / 2 The uniformity of the center density in the depth direction may also be analyzed.

[0022] (9) A SiC device according to one aspect of the present invention comprises a SiC substrate and a SiC epitaxial layer formed on the first surface of the SiC substrate, wherein the Z of the SiC epitaxial layer 1 / 2 The uniformity of the center density in the depth direction is less than 0.5% / μm. [Effects of the Invention]

[0023] According to the present invention, it is possible to estimate the carrier lifetime, and the Z in the depth direction of the SiC epitaxial layer. 1 / 2 This invention provides a SiC epitaxial wafer with suppressed variations in center density, a method for manufacturing the SiC epitaxial wafer, and a SiC device. [Brief explanation of the drawing]

[0024] [Figure 1] This is a cross-sectional view showing an example of the configuration of a SiC epitaxial wafer according to one embodiment of the present invention. [Figure 2] Figure 1 is a plan view showing an example of the configuration of a SiC epitaxial wafer. [Figure 3] This is a schematic diagram showing an example of the configuration of a measuring device for measuring the density of Z1 / 2 centers. [Figure 4]This is a plan view showing an example of the cross-sectional configuration along the cutting line III-III of the SiC epitaxial wafer shown in Figure 1. [Figure 5] Figure 5(a) is an enlarged view of the region enclosed by the dashed line in Figure 1, and Figures 5(a) and 5(b) are schematic diagrams illustrating the depth-direction uniformity of the Z1 / 2 center density of a SiC epitaxial wafer according to one embodiment of the present invention. [Figure 6] This is a schematic diagram showing an example of a method for manufacturing a SiC epitaxial wafer according to one embodiment of the present invention. [Figure 7] This is an example of setting a target value for the exhaust gas C / Si ratio. [Figure 8] This is an image illustrating the setting of the target value for the exhaust gas C / Si ratio, corresponding to the change in Z1 / 2 center density over time. [Figure 9] This is an illustrative diagram showing how the target exhaust gas C / Si ratio is adjusted based on the deposit area. [Figure 10] This is a plan view illustrating the configuration of a SiC device according to one embodiment of the present invention. [Figure 11] This graph shows the calculated Z1 / 2 center density fluctuation when a SiC epitaxial wafer manufacturing method including C / Si ratio control (in-situ) according to Example 1 is performed. [Figure 12] This graph shows the calculated Z1 / 2 center density fluctuation when a SiC epitaxial wafer manufacturing method without C / Si ratio control (in-situ) is performed according to Comparative Example 1. [Modes for carrying out the invention]

[0025] The present embodiment will be described in detail below with reference to the drawings as appropriate. In the drawings used in the following description, characteristic parts may be enlarged for convenience in order to make the features of the present invention easier to understand, and the dimensional ratios of each component may differ from those in reality. The materials, dimensions, etc. exemplified in the following description are examples only, and the present invention is not limited to them, and can be implemented with appropriate modifications without changing the essence of the invention.

[0026] [SiC epitaxial wafer] Figure 1 is a cross-sectional view showing an example of the configuration of a SiC epitaxial wafer according to one embodiment of the present invention. The SiC epitaxial wafer 10 shown in Figure 1 comprises a SiC substrate 1 and a SiC epitaxial layer 2 formed on the first surface 1A of the SiC substrate 1, and the Z of the SiC epitaxial layer 2 1 / 2 The uniformity of the center density in the depth direction is less than 0.5% / μm.

[0027] The SiC substrate 1 is, for example, cut from a SiC ingot. The SiC ingot is grown on a SiC seed crystal using, for example, a sublimation method.

[0028] The SiC epitaxial layer 2 is formed on the first surface 1A of the SiC substrate 1. The thickness of the SiC epitaxial layer is, for example, 8 μm to 500 μm, preferably 15 μm or more, more preferably 30 μm or more, and even more preferably 50 μm or more. The thicker the SiC epitaxial layer 2, the longer the deposition time and the more uniform the growth conditions are considered to be within the same surface. However, when growing on surfaces with different depth positions, there is a concern that the growth conditions may change due to the influence of external factors such as deposition. 1 / 2 Controlling the depth-direction uniformity of the center density tends to be difficult.

[0029] The SiC epitaxial layer 2 is deposited on the SiC substrate 1, for example, using the CVD method. The SiC epitaxial layer 2 may have internal defects. These defects include stacking faults and point defects. The SiC epitaxial layer 2 may have, for example, Z 1 / 2 It has Center 3 internally. Z 1 / 2 Center 3 is a point defect associated with a carbon vacancy. Z 1 / 2 Center 3 is a deep level (E c It has -0.65(eV) and becomes an SRH (Shockley-Read-Hall) recombination center. That is, Z 1 / 2 Center 3 is one of the career lifetime killer defects and affects career longevity.

[0030] Z in SiC epitaxial layer 2 1 / 2 As mentioned above, the density uniformity in the depth direction of center 3 is less than 0.5 (% / μm). Z in SiC epitaxial layer 2 1 / 2 The depth-direction uniformity of density at center 3 is analyzed by the analysis method described below. The following describes the Z-axis in the SiC epitaxial layer 2, referring to the plan view of the SiC epitaxial wafer 10. 1 / 2 This section describes the method for analyzing the depth-direction uniformity of density in center 3.

[0031] Figure 2 is a plan view showing an example of the configuration of the SiC epitaxial wafer shown in Figure 1. Figure 2 shows Z 1 / 2 Measurement point SP for measuring center density a1 ~SP e1 The following is shown. When the central coordinates of the SiC epitaxial wafer 10 in plan view are (0,0) and the radius is R, the measurement point SP a1 SP b1 SP c1 SP d1 SP e1 The (X,Y) coordinates are represented as (0,0), (-R / 2,0), (0,-R / 2), (R / 2,0), and (0,R / 2), respectively.

[0032] The above measurement point SP a1 ~SP e1 For this, the DLTS (Deep Level Transient Spectroscopy) method was used to obtain Z 1 / 2 Measure the density of the center. Figure 3 shows Z 1 / 2 This is a schematic diagram showing an example of the configuration of a measuring device for measuring the density of centers. The measuring device 90 includes a stage 91, a contactor 92, a probe 93, a pulse power supply 94, a capacitance meter 95, and an evaluation unit 96.

[0033] The SiC epitaxial wafer 10 is placed on the stage 91. The stage 91 or probe 93 is movable, and the relative position between the probe 93 and the SiC epitaxial wafer 10 can be changed.

[0034] The contactor 92 is located at the tip of the probe 93. The contactor 92 contacts the SiC epitaxial layer 2 of the SiC epitaxial wafer 10 during measurement. The contactor 92 is a terminal for applying voltage to the SiC epitaxial wafer 10 and functions as a Schottky electrode. The contactor 92 is, for example, mercury. Mercury is a liquid at room temperature, and there is no need to deposit a metal electrode as would be the case when using a metal that is solid at room temperature as a Schottky electrode. Therefore, the Z near the outermost surface 1 / 2 When measuring the center density, it is not necessary to cut or otherwise prepare the SiC epitaxial wafer 10.

[0035] The pulse power supply 94 intermittently applies voltage to the contact 92. When the contact 92 is in contact with the SiC epitaxial wafer 10, the voltage applied from the pulse power supply 94 is intermittently applied to the SiC epitaxial layer 2.

[0036] DLTS method 1 / 2 The density of the centers is measured using an applied voltage that extends to a depth of approximately 10 μm from the surface S of the SiC epitaxial wafer 10. For example, an applied voltage is applied to the SiC epitaxial wafer 10 that extends to a depth of approximately 7 to 10 μm from the surface S of the SiC epitaxial wafer 10.

[0037] Z 1 / 2 To obtain uniformity of the center density in the depth direction, then, in the vicinity of the first surface 1A of the SiC substrate 1, Z 1 / 2 The center density needs to be measured. Figure 4 is a plan view showing an example of the cross-sectional configuration along the cutting line III-III of the SiC epitaxial wafer in Figure 1. Figure 4 shows the surface S' near the first surface 1A of the SiC epitaxial wafer 10. Measurement point SP shown in Figure 4. a2 ~SP e2 Each of these is measured at point SP a1 ~SP e1 Each of these overlaps in the depth direction. That is, measurement point SP a2 SP b2 SP c2 SP d2 SPe2 The (X, Y) coordinates are represented as (0, 0), (-R / 2, 0), (0, -R / 2), (R / 2, 0), and (0, R / 2), respectively.

[0038] FIG. 5(a) is an enlarged view of the region surrounded by the two-dot chain line in FIG. 1, and FIGS. 5(a) and 5(b) are the Z 1 / 2 It is a schematic diagram for explaining the depth direction uniformity of the center density of the SiC epitaxial wafer 10. The outermost surface S of the SiC epitaxial wafer 10 shown in FIG. 2 and the surface S' near the first surface 1A of the SiC epitaxial wafer 10 shown in FIG. 4 are separated by a distance D in the depth direction. In FIGS. 5(a) and 5(b), the measurement points SP a1 ~SP e1 where any of the Z 1 / 2 center density measurement regions R1 when measured, and SP shown in FIG. 4 a2 ~SP e2 where any of the Z 1 / 2 center density measurement regions R2 when measured are shown. As shown in FIGS. 5(a) and 5(b), the outermost surface S and the surface S' near the first surface 1A are separated by a distance D in the depth direction, and due to the setting of the applied voltage when performing the DLTS method, the measurement regions R1 and R2 do not overlap. The thicknesses of the measurement regions Rl and R2 are the same. The thicknesses of the measurement regions R1 and R2 can be, for example, 2 to 5 μm.

[0039] The Z 1 / 2 center density depth direction uniformity of the SiC epitaxial wafer 10 is the measurement points SP a1 and SP a2 、SP b1 and SP b2 、SP c1 and SP c2 、SP d1 and SP d2 、and, SP e1 and SP e2 The value obtained by multiplying the difference by 100 and dividing by the depth D (μm) can be calculated as the unit (% / μm). For example, at the center of the SiC epitaxial wafer 10 in plan view, the Z 1 / 2The uniformity of the center density in the depth direction is measured at point SP. a1 Z 1 / 2 Center density and measurement point SP a2 Z 1 / 2 Difference in center density (cm -3 The value of D is calculated in units (% / μm) by multiplying the value by 100 and dividing by the depth distance D (μm) at the measurement point. For example, the value of D is 5±1μm, 9±2μm, 20±3μm, 40±4μm, 80±5μm, and 180±5μm for SiC epitaxial layer 2 thicknesses of 10μm, 15μm, 30μm, 50μm, 100μm, and 200μm, respectively.

[0040] In this embodiment, the SiC epitaxial wafer 10 has a depth-direction uniformity of less than 0.5% / μm in the five measurement areas in the plan view, preferably less than 0.4% / μm, and more preferably less than 0.3% / μm.

[0041] Measurement point SP a1 ~SP e1 and SP a2 ~SP e2 Z 1 / 2 The center density is 1 × 10⁻⁶ 11 cm -3 That's all. 1 × 10 13 cm -3 The following is preferable: 5 × 10 12 cm -3 The following is more preferable: Z 1 / 2 Center density 1 × 10 11 cm -3 Therefore, the Z method according to DLTS is as described above. 1 / 2 It becomes possible to determine the center density, which in turn allows for the estimation of carrier lifetime.

[0042] Z 1 / 2 Center density may vary depending on the position in the in-plane direction. That is, the five measurement points SP on the outermost surface S a1 ~SP e1 and five measurement points SP on the surface S' near the first surface 1A a2 ~SP e2The values ​​of each may differ. Z at the above measurement point 1 / 2 The variation in center density within the same plane is preferably 5% or less. 1 / 2 The variation in center density is measured at the measurement point SP, in the case of the outermost surface S. a1 ~SP e1 Z 1 / 2 It is calculated by dividing the difference between the maximum and minimum center density by the average value, multiplying the result by 100, and expressing it in units of percentage (%).

[0043] The above 10 measurement points SP a1 ~SP e1 SP a2 ~SP e2 Z 1 / 2 When the maximum value of the center density is denoted as Max and the minimum value as Min, it is preferable that the maximum value Max and the minimum value Min satisfy the following equation (1). Note that the maximum value Max and the minimum value Min are typically the Z of the measurement points on different surfaces. 1 / 2 This is the center density.

[0044] [{(Max-Min) / mean}×100]<(5+0.5×D)···(1) (D: Distance (μm) between the surface near the outermost surface and the surface near the first surface, mean: 10 Zs 1 / 2 Average center density (cm -3 )) The doping concentration of the SiC epitaxial layer 2 is, for example, 1 × 10⁻⁶ 13 cm -3 The above 1 x 10 17 cm -3 The following applies. However, the lower the doping concentration, the lower the detection limit for point defects by the DLTS method described later. Therefore, Z 1 / 2 The density of center 3 is 1 × 10 13 cm -3 In the following SiC epitaxial layer 2, the doping concentration is 1 × 10⁻⁶ 15 cm -3 The following is preferable: Doping concentration is 1 × 10⁻⁶ 13 cm -3In this case, the lower limit for detecting point defects using the DLTS method is 1.0 × 10⁻⁶. 11 cm -3 This is what is likely to happen.

[0045] For n-type doping, the effective doping concentration is the donor concentration minus the acceptor concentration, and for p-type doping, it is the acceptor concentration minus the donor concentration. For n-type doping, a lower acceptor concentration is preferable, and for p-type doping, a lower donor concentration is preferable. For n-type doping, the acceptor concentration is, for example, 1 × 10⁻⁶. 13 cm -3 The following, preferably 1 × 10 12 cm -3 The following applies: For type p, the donor concentration is, for example, 1 × 10⁻⁶. 13 cm -3 The following, preferably 1 × 10 12 cm -3 The following applies:

[0046] Furthermore, the interstitial carbon-induced point defects in the SiC epitaxial layer 2 are, for example, 1 × 10⁻¹⁶ 12 cm -3 The following is true: 1 × 10 11 cm -3 The following is preferable. Furthermore, interstitial carbon-induced point defects do not necessarily have to be contained within the SiC epitaxial layer 2, for example. Interstitial carbon-induced point defects are defects caused by carbon present in the gaps between the lattice. Examples of interstitial carbon-induced point defects are EH1 centers, EH3 centers, RD3 centers, ON1 centers, and ON2 centers. The density of each of the EH1, EH3, and RD3 centers is 1 × 10⁻⁶ 11 cm -3 Preferably, the density of the ON1 center and the ON2 center are 1 × 10⁻⁶. 11 cm -3 The following is preferable:

[0047] Carbon elements that cause point defects due to interstitial carbon are reduced by heat treatment. 1 / 2Eliminate center 3. On the other hand, the defect at that point itself affects the characteristics of the SiC device. 1 / 2 The number of centers 3 can be controlled by irradiating the SiC epitaxial layer 2 with an electron beam, but irradiating the SiC epitaxial layer 2 with an electron beam simultaneously generates point defects caused by interstitial carbon (e.g., EH1 centers, EH3 centers, RD3 centers). Note that ON1 centers and ON2 centers are generated by carbon ion implantation or thermal oxidation. 1 / 2 This is a defect that is simultaneously generated during the process of eliminating centers, and it is difficult to completely reduce it by heat treatment. However, ON1 centers and ON2 centers do not exist in the SiC epitaxial layer 2 as it is epitaxially grown, or if they do exist, their concentration is sufficiently low. Therefore, as will be described later, without post-treatment, Z 1 / 2 According to a method for manufacturing SiC epitaxial wafers that can produce SiC epitaxial wafers with high depth-direction uniformity of center density, as described above, point defects and Z 1 / 2 We can provide options with low center density in both cases.

[0048] The diameter of the SiC epitaxial wafer 10 is, for example, 100 mm or more, preferably 150 mm or more, and more preferably 200 mm or more. Here, the diameters described in this paragraph are not strict, and an error of about ±1 mm is permitted. That is, a wafer with a diameter of 100 mm means a wafer with a diameter of 99 mm or more and 101 mm or less, a wafer with a diameter of 150 mm means a wafer with a diameter of 149 mm or more and 151 mm or less, and a wafer with a diameter of 200 mm means a wafer with a diameter of 199 mm or more and 201 mm or less. In addition, the diameter of the SiC epitaxial wafer 10 may be, for example, 305 mm or less (306 mm or less with an error of 1 mm permitted).

[0049] The drift layer is the layer through which drift current flows, and where elements such as transistors are formed when fabricating SiC devices, as described later. Drift current is the current generated by the flow of carriers when a voltage is applied to a semiconductor.

[0050] Next, in order to describe the method for manufacturing SiC epitaxial wafers according to this embodiment, we will first describe a growth apparatus that can be used for manufacturing SiC epitaxial wafers.

[0051] [Growth equipment] Figure 6 is a schematic diagram showing an example of a method for manufacturing a SiC epitaxial wafer according to one embodiment of the present invention. The growth apparatus 100 shown in Figure 6 includes, for example, a chamber 20, a support 30, a susceptor 40, a lower heater 50, and an upper heater 60. Figure 6 shows the state in which the SiC substrate 1 is placed on the susceptor 40. The growth apparatus 100 shown in Figure 6 is an example of an apparatus that can be used in the method for manufacturing a SiC epitaxial wafer according to this embodiment, and other configurations are also possible. For example, the growth apparatus 100 is a vertical furnace that supplies raw material gas from above the first surface 1A of the SiC substrate 1, but it may also be a horizontal furnace that supplies raw material gas parallel to the first surface 1A of the SiC substrate 1. Alternatively, a single-wafer furnace capable of simultaneously depositing films on multiple SiC substrates 1 may be used.

[0052] The chamber 20 includes, for example, a main body 21, a gas supply port 22, and a gas outlet 23. The gas outlet 23 is connected to an exhaust pump 80. An analyzer 70 is also provided at the gas outlet 23. The analyzer 70 is, for example, a quadrupole mass analyzer. The analyzer 70 can analyze the components of the gas exhausted from the gas outlet 23.

[0053] The support 30 supports the SiC substrate 1. The support 30 is rotatable around its axis. The SiC substrate 1 is placed on the support 30, for example, with the SiC substrate 1 placed on the susceptor 40. The susceptor 40, with the SiC substrate 1 placed on it, is transported into the chamber 20. The lower heater 50 is located, for example, inside the support 30 and heats the SiC substrate 1. The upper heater 60 heats the upper part of the chamber 20. The member exposed in the film deposition space S is, for example, a carbon member, and its surface may be coated with SiC or TaC.

[0054] [Method for manufacturing SiC epitaxial wafers] A method for manufacturing a SiC epitaxial wafer according to one embodiment of the present invention includes a formation step of forming a SiC epitaxial layer on the first surface of a SiC substrate by chemical vapor deposition using a growth apparatus having a gas supply port and a gas outlet for supplying Si-based gas and C-based gas.

[0055] <Formation process> The forming process includes an adjustment step in which the gas discharged from the gas outlet 23 is analyzed by quadrupole mass spectrometry, and if the analyzed C / Si ratio is lower than a target value, the amount of C-based gas supplied to the Si-based gas is increased, and if the analyzed C / Si ratio is higher than the target value, the amount of C-based gas supplied to the Si-based gas is decreased.

[0056] The formation process includes, for example, a heating step, a growth step, and a cooling step.

[0057] The heating process raises the temperature inside the growth apparatus 100 to the growth temperature T2. The growth temperature T2 is, for example, a temperature within the range of 1500°C to 1750°C.

[0058] The growth process is a process that follows the heating process, in which Si-based gas and C-based gas are supplied at a growth temperature T2, and a SiC epitaxial layer 2 is epitaxially grown on the SiC substrate 1. The adjustment process described above is a process that takes place during the growth process.

[0059] The cooling process is a process that follows the growth process and lowers the temperature inside the growth apparatus 100.

[0060] Here, the temperature inside the growth apparatus 100 is the temperature of the SiC substrate 1 or SiC epitaxial wafer 10 as measured by a radiation thermometer (pyrometer).

[0061] Si-based gases are source gases that contain Si in their molecules. Examples of Si-based gases include silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and tetrachlorosilane (SiCl4). C-based gases are source gases that contain C in their molecules. Examples of C-based gases include propane (C3H8) and ethylene (C2H4). Dopant gases are gases that contain a carrier element. Examples of dopant gases include nitrogen and ammonia. Purge gases are gases that transport these gases to the SiC substrate 1 and are inert to SiC, such as hydrogen.

[0062] The formation process includes an adjustment step in which, as described above, the gas discharged from the gas outlet is analyzed by quadrupole mass spectrometry (QMS analysis), and if the C / Si ratio of the analyzed gas is lower than the target value, the amount of C-based gas supplied to the Si-based gas is increased, and if the C / Si ratio of the analyzed gas is higher than the target value, the amount of C-based gas supplied to the Si-based gas is decreased. The adjustment step is a process during the growth process and is carried out in parallel with the formation of the SiC epitaxial layer 2 on the SiC substrate 1. In other words, the adjustment step is a process performed in situ.

[0063] During the formation process, the raw material gas supplied into the chamber 20 may not be supplied to the SiC substrate 1 at the intended C / Si ratio due to factors such as deposit formation on the upstream side of the chamber 20, closer to the gas supply port 22 relative to the SiC substrate 1.

[0064] In such cases, during the adjustment process, if the C / Si ratio of the raw material gas discharged from the gas outlet 23 is lower than the target value, the supply amount of C-based gas is increased. Conversely, if the C / Si ratio of the raw material gas discharged from the gas outlet 23 is higher than the target value, the supply amount of C-based gas is decreased. The adjustment process is preferably carried out so that the C / Si ratio is always within the range of ±0.005 of the target value, and more preferably within the range of ±0.003 of the target value.

[0065] As described above, by controlling the flow rate of the raw material gas in the growth process, the C / Si ratio supplied to the SiC substrate 1 can be brought closer to the ideal. In this embodiment, Z associated with carbon vacancies 1 / 2 This suppresses the formation of centers and Z within the SiC epitaxial layer 2. 1 / 2 This can improve the uniformity of the center density in the depth direction.

[0066] Furthermore, the method for manufacturing a SiC epitaxial wafer according to this embodiment may further include one or more test steps and feedback steps before the formation step, and a target value for the raw material gas supply in the formation step may be set based on the results of the test steps.

[0067] In the formation process of the SiC epitaxial layer 2, if the C / Si ratio changes by 0.005, Z 1 / 2 Center density (cm -3 Since the C / Si ratio is expected to fluctuate by 5%, controlling the C / Si ratio during growth is important. Furthermore, the external environment may be changing in the early stages of growth and just before completion, so it is desirable that the C / Si ratio in the supplied raw material gas takes the external environment into consideration.

[0068] <Testing Process> The testing process includes a first forming step, an analysis step, and a measurement step, and more preferably further includes a preliminary measurement step. The testing process is performed at least once, but may be performed multiple times.

[0069] (Preliminary measurement process) In the preliminary measurement step, the weight and specific surface area of ​​the by-product (depot) in the growth apparatus 100 are measured. In the growth apparatus 100, by-products may be generated in the chamber 20 in the region between the gas supply port 22 and the gas outlet 23 (i.e., the region between the growth area and the exhaust gas). The weight of the by-product in the growth apparatus 100 is measured, for example, by an electronic weighing scale. The above region is a specific region at any position between the gas supply port 22 and the gas outlet 23. In the series of steps of this test process, the above specific region is fixed and not changed.

[0070] The surface area of ​​the by-products within the growth apparatus 100 can be confirmed by sampling the by-products in the above-mentioned area (growth area to exhaust gas) and measuring them with a laser microscope. The deposit area (weight of deposit × specific surface area) measured in the preliminary measurement step may be used to correct the predetermined target value of the C / Si ratio by using the same method as described later.

[0071] (1st formation step) In the first forming step, a SiC epitaxial layer is formed on the first surface of a test SiC substrate using the growth apparatus 100 that performed the preliminary measurement step, while analyzing the gas discharged from the gas outlet 23 by quadrupole mass spectrometry. The growth is carried out while analyzing the gas discharged from the gas outlet by quadrupole mass spectrometry (QMS analysis). The growth is carried out so that the C / Si ratio of the gas analyzed by QMS analysis is constant at a target value. For example, the first forming step includes an adjustment step in which the amount of C-based gas supplied to the Si-based gas is increased if it is lower than the target value, and the amount of C-based gas supplied to the Si-based gas is decreased if the analyzed C / Si ratio is higher than the target value. The adjustment step is a step in the first forming step and is carried out in parallel with the formation of the SiC epitaxial layer 2 on the SiC substrate 1. That is, the adjustment step is a step carried out in situ. It is preferable to control the C / Si ratio by PID control (Proportional-Integral-Differential Controller). During growth, the C / Si ratio of the analyzed gas is controlled to remain constant at a predetermined target value. Preferably, the C / Si ratio of the analyzed gas is controlled to always be within the range of ±0.005 of the predetermined value, more preferably to ±0.004, and even more preferably to ±0.003. In other words, the C / Si ratio in the exhaust gas is preferably controlled so that the difference from the target value is ±0.005 or less, more preferably to ±0.004 or less, and even more preferably to ±0.003 or less. Note that the C / Si ratio represents 1 when the flow rates of the C-based gas and the Si-based gas are the same. That is, when the C / Si ratio is 1, it means that the ratio of the flow rate of the C-based gas to the flow rate of the Si-based gas is 100%. Therefore, a C / Si ratio of 0.001 corresponds to 0.1%, 0.003 to 0.3%, 0.004 to 0.4%, and 0.005 to 0.5%.

[0072] In the adjustment process, QMS analysis primarily measures the gas species contributing to the reaction to perform a qualitative evaluation of the C / Si ratio. For systems containing only Si-based gases and C-based gases, for example, [C2H2 + ] / [Si+ ], if the system includes a Cl-based gas in addition to Si-based and C-based gases, for example [C2H2 + ] / [SiCl2 + The ion species to be measured is determined according to each reaction process, and the increase or decrease in their ratio is adjusted so that it remains constant at a certain target value as a qualitative increase or decrease in the C / Si ratio.

[0073] (Analysis process) In the analysis process, the Z of the SiC epitaxial layer of the SiC epitaxial wafer formed in the first formation process is analyzed. 1 / 2 We will analyze the uniformity of the center density in the depth direction.

[0074] Z in SiC epitaxial layer 1 / 2 The center density variation in the depth direction is measured. In the analysis process, the Z in the SiC epitaxial layer is measured. 1 / 2 When measuring the depth-direction variation in center density, it is possible to measure it using the same method as in the above embodiment. That is, the analysis process, for example, when performed by destructive testing, includes a film thickness measurement step, a first evaluation step, a removal step, and a second evaluation step. In addition, in the DLTS method, if it is possible to measure by controlling the applied voltage from the outermost surface S such that the measurement range of measurement area R2, which is spaced at a distance D from the measurement area R1 on the outermost surface S side, is approximately the same as the width of the depth of measurement area R1, then the measurement may be performed non-destructively. That is, when the depth of measurement area R1 is a to b μm from the outermost surface S, if it is possible to measure from the outermost surface S by voltage control in a region where the distance from a surface spaced at a distance D in the depth direction from the upper surface of measurement area R1 is a to b μm (D + a to b (μm) from the outermost surface S), then the removal step can be omitted. In this case, the analysis process includes a film thickness measurement step, a first evaluation step, and a second evaluation step.

[0075] In the film thickness measurement process, the film thickness of the SiC epitaxial layer 2 is measured using Fourier transform infrared spectroscopy (FT-IR method).

[0076] In the first evaluation step, measurements were taken using the DLTS method at five locations: (0,0), (±R / 2,0), and (0,±R / 2) on the outermost surface S of a SiC epitaxial wafer with a planar center (0,0) and radius R, and the Z-axis of the plane near the outermost surface was measured. 1 / 2 The center density is measured. To measure the Z1 / 2 center density on the surface near the outermost surface, for example, in the DLTS method, a voltage is applied to the SiC epitaxial wafer 10 such that it extends from the surface S of the SiC epitaxial wafer 10 to a depth of about 7 to 10 μm. In this way, the voltage is applied so that the thickness of the measurement region R1 is about 2 to 5 μm, such as (10-7=)3 μm.

[0077] In destructive testing, the removal process involves thinning the SiC epitaxial layer 2 by a thickness D until the distance between the surface of the SiC epitaxial layer 2 and the first surface 1A becomes, for example, 12 μm, according to the results of the film thickness measurement process. The removal process can be carried out, for example, by grinding or polishing.

[0078] In the second evaluation step, the DLTS method is used to determine the Z-axis of the plane near the first plane. 1 / 2 Center density is measured. The conditions for the second evaluation step are the same as those for the first evaluation step. That is, at five locations in a plan view, (0,0), (±R / 2,0), and (0,±R / 2), the DLTS method is used so that the depth of the measurement area from the surface S that is removed and exposed is 7 to 10 μm. 1 / 2 The center density is measured. Furthermore, when performing the analysis process using non-destructive testing via voltage application control, the applied voltage is controlled so that the measurement area is at a distance of 2 to 5 μm from the first surface 1A.

[0079] The surface near the outermost surface S and the surface near the first surface 1A of the SiC substrate 1 obtained by the above measurement, and Z 1 / 2 From the center density and the thickness D (μm) of the removed SiC epitaxial layer, Z 1 / 2 The uniformity of the center density in the depth direction will be analyzed. Also, the Z at the 10 locations mentioned above. 1 / 2 Using the maximum and minimum values ​​of the center density, Max and Min, the Z density within the SiC epitaxial layer 2 is calculated based on equation (1).1 / 2 You may also analyze the variability in center density.

[0080] [{(Max-Min) / mean}×100]<(5+0.5×D)···(1) (D: Distance (μm) between the surface near the outermost surface and the surface near the first surface, mean: 10 Zs 1 / 2 Average center density (cm -3 )) (Measurement process) In the measurement step, the weight and surface area of ​​the by-products in the growth apparatus 100 after the first forming step are measured. The weight and surface area of ​​the by-products in the growth apparatus 100 can be measured in the same manner as in the preliminary measurement step described above. The area in which the measurement is performed in the measurement step is the area between the gas supply port 22 and the gas outlet port 23, and is the same specific area as the area in which the measurement step was performed.

[0081] <Feedback Process> The feedback process sets target values ​​for the supply amounts of Si-based gas and C-based gas in the formation process of the actual manufacturing of the SiC epitaxial wafer 10, based on the results of the test process. That is, a standard (target value) for the amount of raw material gas to be flowed in the formation process is set based on the results of the (preliminary measurement process,) analysis process and measurement process. The standard (target value) for the raw material gas may be constant over time or may change over time. First, a constant value is set as the target value of the exhaust gas C / Si ratio based on the C / Si ratio in the exhaust gas QMS analysis. Figure 7 shows an image of setting the target value of the exhaust gas C / Si ratio.

[0082] Next, Z 1 / 2 If the center density undergoes a specific change over time, a target value for the C / Si ratio that changes over time should be set to correspond to that change. For example, the target value can be made proportional to the growth time. Specifically, Z 1 / 2 If the center density decreases over time, set the reference (target) C / Si ratio so that it decreases over time, Z 1 / 2If the center density increases with the growth time, the reference (target) C / Si ratio is set to increase over time (first adjustment step). Figure 8 shows the formed Z 1 / 2 This is an image illustrating the setting of the target value for the exhaust gas C / Si ratio in accordance with the change in center density over time. The adjustment can be made according to the dashed line in Figure 8(b) in accordance with the result of the dashed line in Figure 8(a), or according to the dashed line in Figure 8(b) in accordance with the result of the dashed line in Figure 8(a).

[0083] Next, considering that a discrepancy occurs between the measured exhaust gas C / Si ratio and the C / Si ratio of the growth area in relation to the deposit area within the apparatus (weight of the deposit × specific surface area of ​​the deposit), the target value of the exhaust gas C / Si ratio set in the first adjustment step is corrected in relation to the deposit area within the apparatus (second adjustment step). Figure 9 is an illustrative diagram of how the target value of the exhaust gas C / Si ratio is corrected based on the deposit area. The correction amount is set based on a map like Figure 9(a) obtained in advance through multiple tests. Here, it is preferable to use a map relating to the deposit area measurement locations. Figure 9(b) shows the case where the required correction amount (p) calculated from the map in Figure 9(a) is corrected from the measured deposit area, as shown by the solid line graph in Figure 9(b). The larger the deposit area, the greater the discrepancy between the measured exhaust gas C / Si ratio and the growth area C / Si, the C / Si ratio of the by-product deposit is < 1, and the amount of by-product generated increases with the deposit area. Therefore, the deposit area needs to be larger than the growth area C / Si measured in the exhaust gas.

[0084] In this way, target values ​​can be set for the supply amounts of Si-based gas and C-based gas in the formation process of this step.

[0085] According to the method for manufacturing a SiC epitaxial wafer according to the above embodiment, Z 1 / 2 The ability to measure the center density allows for the estimation of carrier lifetime, and the Z-axis in the depth direction of the SiC epitaxial layer. 1 / 2This method provides a SiC epitaxial wafer with suppressed variations in center density. Furthermore, according to the manufacturing method of the SiC epitaxial wafer according to the above embodiment, after the formation of the SiC epitaxial layer 2, Z 1 / 2 Without performing a process to reduce the center density, Z 1 / 2 This allows us to provide SiC epitaxial wafers with uniform center density.

[0086] [SiC devices] A SiC device according to one embodiment of the present invention comprises a SiC substrate and a SiC epitaxial layer formed on the first surface of the SiC substrate, wherein the Z in the SiC epitaxial layer 1 / 2 The depth-direction uniformity of the center density is less than 0.5% / μm. As the SiC substrate and SiC epitaxial layer provided in the SiC device, the SiC substrate and SiC epitaxial layer of the SiC epitaxial wafer according to the above embodiment can be used.

[0087] The SiC device is obtained from the SiC epitaxial wafer 10 according to the above embodiment. Figure 10 is a plan view illustrating the configuration of a SiC device according to one embodiment of the present invention. The SiC device 200 can be manufactured by forming devices such as transistors on the SiC epitaxial wafer 10 and then chipping it. In Figure 10, each rectangular section of the SiC epitaxial wafer 10 is a SiC device. The SiC device 200 may also be manufactured by forming devices such as transistors and diodes on the SiC epitaxial wafer 10 after chipping it.

[0088] The SiC device 200 according to this embodiment comprises a chipped SiC substrate and a SiC epitaxial layer provided on one surface of the chipped SiC substrate. Devices such as transistors are formed in the drift layer of the SiC epitaxial layer. The configurations of the SiC substrate, buffer layer, and drift layer in the SiC device 200 are the same as those of the SiC epitaxial wafer 10 before chipping.

[0089] If the SiC device 200 further comprises components other than the SiC substrate and the SiC epitaxial layer, the Z in the SiC epitaxial layer of the SiC device 200 1 / 2 The center density can be measured after removing regions other than the SiC substrate and SiC epitaxial layer from the SiC device 200. These regions can be removed, for example, by grinding or polishing. During the removal of these regions, the Z-axis in the SiC epitaxial layer is also measured. 1 / 2 There is no change in the distribution of Z in the SiC epitaxial layer of SiC device 200. 1 / 2 Center density measurement is performed by SP at a single point, the center 201 in the plan view of the SiC device 200, to determine depth-direction uniformity using an epiwafer. a1 and SP a2 The measurement should be performed in the same way as the measurement method. That is, first, in the SiC epitaxial layer of the SiC device, at the measurement point SP a1 Z 1 / 2 The center density is measured, and then the applied voltage is adjusted to measure point SP. a2 Z 1 / 2 We just need to measure the center density.

[0090] Z of the SiC epitaxial layer in SiC device 200 1 / 2 The depth-direction uniformity of the center density is less than 0.5% / μm, preferably less than 0.4% / μm, and more preferably less than 0.3% / μm.

[0091] Furthermore, the Z of the SiC epitaxial layer in SiC device 200 1 / 2 The center density is 1 × 10⁻⁶ 11 cm -3 That's all. 1 × 10 13 cm -3 The following is preferable: 5 × 10 12 cm -3 The following is more preferable:

[0092] As described above, the SiC epitaxial wafer 10 according to the above embodiment has a buffer layer Z 1 / 2The center density exhibits excellent depth-direction uniformity, and the Z of the SiC epitaxial layer in SiC device 200 is superior. 1 / 2 The depth-direction uniformity of the center density is also excellent. Therefore, carrier lifetime can be evaluated more accurately.

[0093] Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the gist of the invention as described in the claims. Furthermore, the upper and / or lower limits of the numerical ranges described herein can be arbitrarily combined to define a preferred range. For example, a preferred range can be defined by arbitrarily combining the upper and lower limits of the numerical ranges, by arbitrarily combining the upper limits of the numerical ranges, and by arbitrarily combining the lower limits of the numerical ranges. [Examples]

[0094] [Example 1] The present invention's method for manufacturing SiC epitaxial wafers allows for in-situ adjustment of the C / Si ratio and the Z-axis of the SiC epitaxial wafer. 1 / 2 The dependence of the center density on the thickness of the SiC epitaxial layer was determined. Specifically, the variation in the C / Si ratio when the C / Si ratio was adjusted in situ and the thickness of the SiC epitaxial layer were considered to correspond to the Z value, which is thought to change approximately linearly with respect to the thickness of the SiC epitaxial layer. 1 / 2 Assuming factors causing center density fluctuations, the C / Si ratio and other Z 1 / 2 The Z value that can be taken when the center density fluctuation factor is maximized. 1 / 2 The center density fluctuation value was calculated. In Example 1, we assume a configuration in which the C / Si ratio in the exhaust gas is adjusted so that the difference from the target value of the C / Si ratio in the exhaust gas is within ±0.005. By adjusting the C / Si ratio in situ, it is expected that the difference from the target value of the C / Si ratio will change in a sinusoidal curve with respect to the thickness of the SiC epitaxial layer, as shown in Figure 11.

[0095] Figure 11 shows the Z ratio when a SiC epitaxial wafer manufacturing method including C / Si ratio control (in-situ) according to Example 1 is performed. 1 / 2 This graph shows the calculated variation in center density. Figure 11 shows the dependence of the difference between the target value of the C / Si ratio and the thickness of the SiC epitaxial layer, and Z other than the C / Si ratio. 1 / 2 The dependence of the SiC epitaxial layer thickness on the center density fluctuation factors is also shown. In Figure 11, Z 1 / 2 The variable is thought to take on one of the values ​​within the region enclosed by the dashed line. In Figure 11, Z 1 / 2 The variable is expressed as {(thickness of the SiC epitaxial layer - 25) × 0.0092} × 100 (%). Using this, Z 1 / 2 The variation in center density is expressed by the following equation (2).

[0096] Z 1 / 2 Center density variation = {(Difference from target value of C / Si ratio) × 10 + (Thickness of SiC epitaxial layer - 25) × 0.0092} × 100 (%) ... (2)

[0097] The difference between the target value and the C / Si ratio at SiC epitaxial layer thicknesses of 0 μm, 50 μm, 100 μm, and 150 μm, and Z 1 / 2 Table 1 summarizes the fluctuations in center density. In Table 1, the difference between the target value and the C / Si ratio represents a positive value when the C-based gas flow rate ratio in the exhaust gas is higher than the C-based gas flow rate ratio at the target value.

[0098] [Table 1]

[0099] [Comparative Example 1] The only change from Example 1 is that it assumes a case where the C / Si ratio is not controlled in situ, Z 1 / 2The dependence of center density fluctuations on the film thickness of the SiC epitaxial layer was calculated. In Comparative Example 1, since the C / Si ratio was not controlled in situ, the C / Si ratio could be expected to either increase or decrease over time. In Comparative Example 1, an increasing trend was assumed, so it was assumed that the C / Si ratio would increase as the film thickness of the SiC epitaxial layer increased. 1 / 2 The factors causing the center density fluctuation were estimated in the same manner as in Example 1. That is, in Comparative Example 1 as well, Z was calculated using equation (2). 1 / 2 The dependence of center density fluctuations on the film thickness of the SiC epitaxial layer was calculated.

[0100] Figure 12 shows the Z ratio when the SiC epitaxial wafer manufacturing method without C / Si ratio control (in-situ) according to Comparative Example 1 is used. 1 / 2 This is a graph showing the calculated fluctuations in center density.

[0101] The difference between the target value and the C / Si ratio at SiC epitaxial layer thicknesses of 0 μm, 50 μm, 100 μm, and 150 μm, and Z 1 / 2 Table 2 summarizes the fluctuations in center density.

[0102] [Table 2]

[0103] As can be seen by comparing Figures 11 and 12, or Tables 1 and 2, in the formation process of forming a SiC epitaxial layer by supplying Si-based gas and C-based gas, the C / Si ratio is controlled in situ, and the difference from the target value of the C / Si ratio is controlled to be small, thereby reducing the Z at any film thickness. 1 / 2 It was confirmed that the fluctuation in center density could be reduced. 1 / 2 Center density variation is Z in the depth direction of the SiC epitaxial layer. 1 / 2 This parameter relates to the distribution of center density, and is such as the value of [{(Max-Min) / mean}×100] in equation (1). 1 / 2 There is a correlation with the variability of center density. [Explanation of Symbols]

[0104] 1: SiC substrate, 1A: First surface, 2: SiC epitaxial layer, 3: Z 1 / 2 Center, 10: SiC epitaxial wafer, 20: Chamber, 21: Main body, 22: Gas supply port, 23: Gas exhaust port, 30: Support, 40: Susceptor, 50: Lower heater, 60: Upper heater, 100: Growth apparatus, S: Outer surface

Claims

1. The device comprises a SiC substrate and a SiC epitaxial layer formed on the first surface of the SiC substrate, The Z of the SiC epitaxial layer １／２ A SiC epitaxial wafer having a depth-direction uniformity of center density of less than 0.5% (% / μm).

2. The SiC epitaxial wafer according to claim 1, wherein the diameter is 149 mm or more.

3. A SiC epitaxial wafer according to claim 1, wherein the diameter is 199 mm or more.

4. When the center coordinates in a plan view are (0,0) and the radius is R, Ten Z coordinates on the surface near the outermost surface in the depth direction at coordinates (0,0), (±R / 2,0), and (0,±R / 2), and on the surface near the first surface. １／２ Center density is 1 × 10 １１ cm －３ The above 1.0 x 10 １３ cm －３ The SiC epitaxial wafer according to claim 1, which is as follows:

5. When the center coordinates in a plan view are (0,0) and the radius is R, Ten Z coordinates on the surface near the outermost surface in the depth direction at coordinates (0,0), (±R / 2,0), and (0,±R / 2), and on the surface near the first surface. １／２ The SiC epitaxial wafer according to claim 1, wherein the maximum and minimum values ​​of the center density, Max and Min, satisfy formula (1). [{(Max-Min) / mean}×100]<(5+0.5×D)...(1) (D: Distance (μm) between the surface near the outermost surface and the surface near the first surface) mean: Z at 10 locations １／２ Average value of center density (cm －３ )).

6. The process includes a formation step of forming a SiC epitaxial layer on the first surface of a SiC substrate by chemical vapor deposition using a growth apparatus having a gas supply port and a gas outlet for supplying Si-based gas and C-based gas. A method for manufacturing a SiC epitaxial wafer, comprising a forming step which includes an adjustment step in which the gas discharged from the gas outlet is analyzed by quadrupole mass spectrometry, the amount of C-based gas supplied to the Si-based gas is increased if the analyzed C / Si ratio is lower than a target value, and the amount of C-based gas supplied to the Si-based gas is decreased if the analyzed C / Si ratio is higher than the target value.

7. The process further includes a testing step and a feedback step prior to the forming step. The aforementioned test process is: A preliminary measurement step for measuring the weight and surface area of ​​by-products in the growth apparatus, A first forming step involves forming a SiC epitaxial layer on the first surface of a test SiC substrate while analyzing the gas discharged from the gas outlet using the growth apparatus that performed the preliminary measurement step, using quadrupole mass spectrometry. Z of the SiC epitaxial layer of the SiC epitaxial wafer formed in the first formation step １／２ An analysis process to analyze the uniformity of the center density in the depth direction, A measurement step for measuring the weight and surface area of ​​the by-products in the growth apparatus after the first forming step, Includes, The feedback process sets the target value based on the results of the test process. A method for manufacturing a SiC epitaxial wafer according to claim 6.

8. The aforementioned analysis process is performed on a SiC epitaxial wafer with a planar center (0,0) and radius R, A film thickness measurement process for measuring the film thickness of the SiC epitaxial layer, Z at five locations: (0,0), (±R / 2,0), and (0,±R / 2). １／２ A first evaluation step in which the center density is evaluated from the outermost surface of the SiC epitaxial wafer by the DLTS method, A removal step of removing the SiC epitaxial layer to a predetermined thickness, After the removal process, the Z at five locations: (0,0), (±R / 2,0), and (0,±R / 2) １／２ A second evaluation step in which the center density is evaluated from the outermost surface of the SiC epitaxial wafer by the DLTS method, Includes, Z in the first evaluation step at the same location in plan view １／２ Center density and Z in the second evaluation step １／２ The difference from the center density is divided by the predetermined thickness to obtain Z １／２ Analyze the uniformity of density in the depth direction at the center. A method for manufacturing a SiC epitaxial wafer according to claim 7.

9. The device comprises a SiC substrate and a SiC epitaxial layer formed on the first surface of the SiC substrate, The Z of the SiC epitaxial layer １／２ A SiC device having a depth-direction uniformity of center density of less than 0.5% / μm.

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