Nanofabrication of high aspect ratio nanostructures that do not collapse

Abstract

This invention relates to catalyst-induced chemical etching. [Solution] A method for fabricating silicon nanostructures. An etching uniformity improvement layer is deposited on a substrate. A catalyst (e.g., a thin film of Ti / Au) is deposited on the substrate or etching uniformity improvement layer, and the catalyst comes into contact with a portion of the substrate or etching uniformity layer. The catalyst and the substrate or etching uniformity improvement layer are exposed to an etchant, and the catalyst causes etching of the substrate, thereby creating an etched nanostructure.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 020,408, filed on 5 May 2020, entitled "Nanofabrication of Collapse-Free High Aspect Ratio Nanostructures," which is incorporated herein by reference in its entirety.

[0002] This invention generally relates to catalyst-influenced chemical etching (CICE), and more specifically to catalyst patterning and achieving large-area etching uniformity. [Background technology]

[0003] Catalytically affected chemical etching (CICE) is a catalyst-based etching method that can be used to create features in semiconductors such as silicon and germanium, such as high aspect ratio, low sidewall taper, low sidewall roughness, and / or controllable porosity. Silicon nanostructures fabricated using CICE can enable low-cost, high-performance devices for sensors, batteries, thermoelectrics, particle separation arrays, and metamaterials.

[0004] Large-area wafer-scale uniform etching (CICE) has been documented in the literature using silver as a catalyst to create periodic microscale silicon wires or microscale holes. Nanoscale features have been demonstrated on wafers using nanosphere lithography and gold sputtering to obtain black silicon. However, these processes cannot be easily converted to CICE using the associated patterning and nanoimprint lithography. Catalyst patterning plays a crucial role in ensuring large-area etching uniformity. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] U.S. Patent No. 10,026,609 [Patent Document 2] U.S. Patent Application Publication No. 2020 / 0365464 [Overview of the Initiative] [Means for solving the problem]

[0006] In one embodiment of the present invention, a method for fabricating silicon nanostructures includes the step of depositing an etch uniformity improving layer on a substrate. The method further includes the step of depositing a catalyst on the substrate or etch uniformity improving layer, wherein the catalyst is in contact with a portion of the substrate or etch uniformity improving layer during deposition. The method further includes the step of exposing the catalyst and the substrate or etch uniformity improving layer to an etchant, wherein the catalyst causes etching of the substrate, thereby creating an etched nanostructure.

[0007] In another embodiment of the present invention, a method for fabricating silicon nanostructures includes the step of depositing an etching uniformity improvement layer on a substrate. The method further includes the step of depositing and patterning a resist to form a resist layer having a plurality of features, wherein the resist layer includes a residual layer less than 100 nm thick. The method further includes the step of etching the resist layer to remove the residual layer. Furthermore, the method includes the step of depositing a catalyst on the substrate or etching uniformity improvement layer, wherein the catalyst comes into contact with a portion of the substrate or etching uniformity improvement layer. Furthermore, the method includes the step of exposing the catalyst and the substrate or etching uniformity improvement layer to an etchant, wherein the catalyst causes etching of the substrate, thereby creating an etched nanostructure.

[0008] In a further embodiment of the present invention, a method for fabricating nanostructures of different heights includes the step of supplying a catalyst layer onto the surface of a semiconductor substrate, wherein the catalyst layer comprises a plurality of features and one or more intentional discontinuities. The method further includes the step of exposing the catalyst layer on the surface of the semiconductor substrate to an etchant, wherein the catalyst layer causes etching of the semiconductor substrate sequentially from one or more intentional discontinuities, and the fabricated structure has height variations due to the features closest to the one or more intentional discontinuities having the greatest height.

[0009] In another embodiment of the present invention, a method for fabricating silicon nanostructures includes the step of patterning a polymer resist having a plurality of features on a substrate. The method further includes the step of conformally depositing a material on the polymer resist to reduce the spacing between the plurality of features. The method further includes the step of supplying a catalyst layer onto a substrate, wherein the catalyst layer is patterned with the plurality of features at reduced spacing such that the catalyst layer contacts only a portion of the substrate. Furthermore, the method further includes the step of exposing the catalyst layer to an etchant, wherein the catalyst layer causes etching of the substrate, thereby creating an etched nanostructure.

[0010] In a further embodiment of the present invention, a method for fabricating a nanostructure with a material includes the step of etching a silicon structure using catalytically affected chemical etching, wherein the etched silicon structure is designed to avoid substantial collapse. The method further includes the step of conformally depositing one or more materials on the etched silicon structure. The method further includes the step of creating access to the etched silicon structure and the step of selectively removing the etched silicon structure to leave substantially the same one or more materials.

[0011] In another embodiment of the present invention, a method for fabricating silicon layer nanostructures on a non-silicon layer includes the step of etching silicon nanostructures using metal-assisted chemical etching, wherein the etched nanostructures are designed to avoid substantial collapse. The method further includes the step of partially or completely oxidizing the etched nanostructures.

[0012] A further embodiment of the present invention is a nanostructure of a silicon layer on a non-silicon layer having optical lens properties, wherein the core geometry is first etched into the silicon layer while substantially avoiding collapse, and then the core geometry is partially or completely oxidized.

[0013] In another embodiment of the present invention, a device using silicon nanostructures comprises silicon nanostructures designed to separate particles in a fluid medium having different sizes, shapes or flow characteristics within a nanostructure array, wherein the spacing between at least one pair of silicon nanostructures is less than 50 nm, and the nanostructure wall angle of one or more of the silicon nanostructures is greater than 89.5 degrees at all points on the sidewalls, except for the upper and lower parts of the sidewalls.

[0014] In a further embodiment of the present invention, a device for the separation and detection of biological species comprises a silicon nanostructure fabricated using catalytically induced chemical etching, the silicon nanostructure being designed for particle separation in a fluid medium. The device further comprises a sensor used to detect a target species within the separated particles, the sensor generating an electrical and / or optical signal based on the detection of the desired target species.

[0015] The foregoing outlines the features and technical advantages of one or more embodiments of the present invention in a fairly general manner, so that the subsequent detailed description of the invention may be better understood. Additional features and advantages of the invention that may form the subject matter of the claims of the present invention are described below.

[0016] A better understanding of the present invention can be obtained by considering the following detailed description along with the following drawings. [Brief explanation of the drawing]

[0017] [Figure 1] This is a flowchart of a method for patterning a catalyst after imprinting, according to an embodiment of the present invention. [Figure 2A]A cross-sectional view showing the patterning of a catalyst after imprinting using the steps described in FIG. 1 according to an embodiment of the present invention. [Figure 2B] A cross-sectional view showing the patterning of a catalyst after imprinting using the steps described in FIG. 1 according to an embodiment of the present invention. [Figure 2C] A cross-sectional view showing the patterning of a catalyst after imprinting using the steps described in FIG. 1 according to an embodiment of the present invention. [Figure 2D] A cross-sectional view showing the patterning of a catalyst after imprinting using the steps described in FIG. 1 according to an embodiment of the present invention. [Figure 2E] A cross-sectional view showing the patterning of a catalyst after imprinting using the steps described in FIG. 1 according to an embodiment of the present invention. [Figure 2F] A cross-sectional view showing the patterning of a catalyst after imprinting using the steps described in FIG. 1 according to an embodiment of the present invention. [Figure 2G] A cross-sectional view showing the patterning of a catalyst after imprinting using the steps described in FIG. 1 according to an embodiment of the present invention. [Figure 3] A process flow for a uniform CICE with an underlying oxide layer and an undercut as described in the method of FIG. 1 according to an embodiment of the present invention. [Figure 4] A flowchart of an alternative method for patterning a catalyst after imprinting according to an embodiment of the present invention. [Figure 5A] A cross-sectional view showing the patterning of a catalyst after imprinting using the steps described in FIG. 4 according to an embodiment of the present invention. [Figure 5B] A cross-sectional view showing the patterning of a catalyst after imprinting using the steps described in FIG. 4 according to an embodiment of the present invention. [Figure 5C] A cross-sectional view showing the patterning of a catalyst after imprinting using the steps described in FIG. 4 according to an embodiment of the present invention. [Figure 5D]This is a cross-sectional view showing the patterning of a catalyst after imprinting, using the steps described in Figure 4, according to an embodiment of the present invention. [Figure 5E] This is a cross-sectional view showing the patterning of a catalyst after imprinting, using the steps described in Figure 4, according to an embodiment of the present invention. [Figure 5F] This is a cross-sectional view showing the patterning of a catalyst after imprinting, using the steps described in Figure 4, according to an embodiment of the present invention. [Figure 5G] This is a cross-sectional view showing the patterning of a catalyst after imprinting, using the steps described in Figure 4, according to an embodiment of the present invention. [Figure 5H] This is a cross-sectional view showing the patterning of a catalyst after imprinting, using the steps described in Figure 4, according to an embodiment of the present invention. [Figure 6] This is a flowchart of a further alternative method for patterning a catalyst after imprinting, according to an embodiment of the present invention. [Figure 7A] This is a cross-sectional view showing the patterning of an imprinted catalyst using the steps described in Figure 6, according to an embodiment of the present invention. [Figure 7B] This is a cross-sectional view showing the patterning of an imprinted catalyst using the steps described in Figure 6, according to an embodiment of the present invention. [Figure 7C] This is a cross-sectional view showing the patterning of an imprinted catalyst using the steps described in Figure 6, according to an embodiment of the present invention. [Figure 7D] This is a cross-sectional view showing the patterning of an imprinted catalyst using the steps described in Figure 6, according to an embodiment of the present invention. [Figure 7E] This is a cross-sectional view showing the patterning of an imprinted catalyst using the steps described in Figure 6, according to an embodiment of the present invention. [Figure 7F] This is a cross-sectional view showing the patterning of an imprinted catalyst using the steps described in Figure 6, according to an embodiment of the present invention. [Figure 8]This is a flowchart of an additional alternative method for patterning a catalyst after imprinting, according to an embodiment of the present invention. [Figure 9A] This is a cross-sectional view showing the patterning of the imprinted catalyst using the steps described in Figure 8, according to an embodiment of the present invention. [Figure 9B] This is a cross-sectional view showing the patterning of the imprinted catalyst using the steps described in Figure 8, according to an embodiment of the present invention. [Figure 9C] This is a cross-sectional view showing the patterning of the imprinted catalyst using the steps described in Figure 8, according to an embodiment of the present invention. [Figure 9D] This is a cross-sectional view showing the patterning of the imprinted catalyst using the steps described in Figure 8, according to an embodiment of the present invention. [Figure 9E] This is a cross-sectional view showing the patterning of the imprinted catalyst using the steps described in Figure 8, according to an embodiment of the present invention. [Figure 10A] This figure shows the effect of continuous versus discontinuous catalytic action on the variation of CICE etching according to an embodiment of the present invention. [Figure 10B] This figure shows the effect of continuous versus discontinuous catalytic action on the variation of CICE etching according to an embodiment of the present invention. [Figure 11A] This figure shows the variation in analog etch depth in CICE using pinholes in the catalyst film according to an embodiment of the present invention. [Figure 11B] This figure shows the variation in analog etch depth in CICE using pinholes in the catalyst film according to an embodiment of the present invention. [Figure 11C] This figure shows the variation in analog etch depth in CICE using pinholes in the catalyst film according to an embodiment of the present invention. [Figure 12]This figure shows a process step according to an embodiment of the present invention, in which the diameter of an imprinted resist pattern is varied to produce silicon nanowires with precisely controlled feature dimensions at a constant pitch. [Figure 13] This is a flowchart of a method for a conformal deposition process to obtain desired material high aspect ratio (HAR) nanostructures with atypical nanostructure geometric shapes without using substitution steps, according to embodiments of the present invention. [Figure 14A] This is a cross-sectional view showing how to obtain a HAR nanostructure using the steps described in Figure 13, according to an embodiment of the present invention. [Figure 14B] This is a cross-sectional view showing how to obtain a HAR nanostructure using the steps described in Figure 13, according to an embodiment of the present invention. [Figure 14C] This is a cross-sectional view showing how to obtain a HAR nanostructure using the steps described in Figure 13, according to an embodiment of the present invention. [Figure 14D] This is a cross-sectional view showing how to obtain a HAR nanostructure using the steps described in Figure 13, according to an embodiment of the present invention. [Figure 15A] This figure shows a variant of the nanostructure geometric shape using the conformal deposition process shown in Figure 13, according to an embodiment of the present invention. [Figure 15B] This figure shows a variant of the nanostructure geometric shape using the conformal deposition process shown in Figure 13, according to an embodiment of the present invention. [Figure 15C] This figure shows a variant of the nanostructure geometric shape using the conformal deposition process shown in Figure 13, according to an embodiment of the present invention. [Figure 16A] This figure shows different variations of nanostructure geometric shapes using the conformal deposition process shown in Figure 13, according to embodiments of the present invention. [Figure 16B] This figure shows different variations of nanostructure geometric shapes using the conformal deposition process shown in Figure 13, according to embodiments of the present invention. [Figure 16C]This figure shows different variations of nanostructure geometric shapes using the conformal deposition process shown in Figure 13, according to embodiments of the present invention. [Figure 17] This figure illustrates a method for obtaining a desired material high aspect ratio (HAR) nanostructure using a substitution process and atomic layer deposition (ALD) according to embodiments of the present invention. [Figure 18A] This is a cross-sectional view showing how to obtain a desired HAR nanostructure using the steps described in Figure 17, according to an embodiment of the present invention. [Figure 18B] This is a cross-sectional view showing how to obtain a desired HAR nanostructure using the steps described in Figure 17, according to an embodiment of the present invention. [Figure 18C] This is a cross-sectional view showing how to obtain a desired HAR nanostructure using the steps described in Figure 17, according to an embodiment of the present invention. [Figure 18D] This is a cross-sectional view showing how to obtain a desired HAR nanostructure using the steps described in Figure 17, according to an embodiment of the present invention. [Figure 18E] This is a cross-sectional view showing how to obtain a desired HAR nanostructure using the steps described in Figure 17, according to an embodiment of the present invention. [Figure 19] This is a flowchart of a method for obtaining a desired material high aspect ratio (HAR) nanostructure using a silicon exfoliation replacement process and atomic layer deposition (ALD) according to embodiments of the present invention. [Figure 20A] This is a cross-sectional view showing how to obtain a desired HAR nanostructure using the steps described in Figure 19, according to an embodiment of the present invention. [Figure 20B] This is a cross-sectional view showing how to obtain a desired HAR nanostructure using the steps described in Figure 19, according to an embodiment of the present invention. [Figure 20C] This is a cross-sectional view showing how to obtain a desired HAR nanostructure using the steps described in Figure 19, according to an embodiment of the present invention. [Figure 20D] This is a cross-sectional view showing how to obtain a desired HAR nanostructure using the steps described in Figure 19, according to an embodiment of the present invention. [Figure 20E] This is a cross-sectional view showing how to obtain a desired HAR nanostructure using the steps described in Figure 19, according to an embodiment of the present invention. [Figure 21] This is a flowchart of a method for achieving nanostructures in a desired material according to embodiments of the present invention. [Figure 22A] This is a cross-sectional view showing how nanostructures are achieved in a desired material using the steps described in Figure 21, according to an embodiment of the present invention. [Figure 22B] This is a cross-sectional view showing how nanostructures are achieved in a desired material using the steps described in Figure 21, according to an embodiment of the present invention. [Figure 22C] This is a cross-sectional view showing how nanostructures are achieved in a desired material using the steps described in Figure 21, according to an embodiment of the present invention. [Figure 22D] This is a cross-sectional view showing how nanostructures are achieved in a desired material using the steps described in Figure 21, according to an embodiment of the present invention. [Figure 23] This figure shows a silicon nanopillar manufactured using CICE for DLD-based particle separation according to an embodiment of the present invention. [Modes for carrying out the invention]

[0018] As mentioned in the background section, large-area wafer-scale uniform etching using catalyst-affected chemical etching (CICE) has been documented in the literature using silver as a catalyst to create periodic microscale silicon wires or microscale holes. Nanoscale features have been demonstrated on wafers using nanosphere lithography and gold sputtering to obtain black silicon. However, these processes cannot be easily converted to CICE using the associated patterning and nanoimprint lithography. Catalyst patterning plays a crucial role in ensuring large-area etching uniformity.

[0019] The principle of the present invention provides means for patterning catalysts, means for improving large-area etching uniformity, and means for achieving intentional etch variability and control. Furthermore, embodiments of the present invention are used for patterning silicon nanostructures with very high aspect ratios. Furthermore, embodiments of the present invention are used for patterning non-silicon nanostructures by post-CICE post-treatment, which may enable applications with high aspect ratio metallic / semiconductor / insulator / permeable nanostructures. Packaging of the fabricated devices is also described herein.

[0020] Next, referring to the figures in detail, Figure 1 is a flowchart of Method 100 for patterning a catalyst after imprinting, according to an embodiment of the present invention. Figures 2A to 2G show cross-sectional views illustrating the patterning of a catalyst after imprinting using the steps described in Figure 1, according to an embodiment of the present invention.

[0021] Referring to Figure 1 in conjunction with Figures 2A to 2G, in step 101, as shown in Figures 2A and 2B, an etching uniformity improvement layer (e.g., silicon oxide) 202 is deposited (e.g., underlay deposition) onto the substrate 201 (e.g., a silicon substrate). In one embodiment, the thickness of the etching uniformity improvement layer 202 ranges from 5 nm to 100 nm. In one embodiment, the etching uniformity improvement layer 202 is thermally grown on the substrate 201 (e.g., a crystalline silicon substrate). In one embodiment, the etching uniformity improvement layer 202 is a native silicon oxide layer.

[0022] In step 102, as shown in Figure 2C, an imprint resist 203 (e.g., a monomer or polymer formulation) is deposited and patterned (forming a nanostructure) on the etching uniformity improvement layer 202 via nanoimprint lithography.

[0023] In step 103, as shown in Figure 2D, residual layers (residual imprint resist 203), such as those between nanostructures, are removed by plasma etching.

[0024] In step 104, isotropic etching is used to etch a portion of the etching uniformity improvement layer 202, including between and beneath the nanostructures, such as through undercuts, as shown in Figure 2E. In one embodiment, the etchant comprises two or more of the following: fluoride species including the chemical HF or NH4F, oxides (e.g., H2O2, KMnO4), alcohols (e.g., ethanol, isopropyl alcohol, ethylene glycol), and solvents (e.g., proton, aproton, polar, and nonpolar solvents).

[0025] In step 105, catalyst 204 is deposited on and between the nanostructure, as shown in Figure 2F. In one embodiment, catalyst 204 is a thin film of Ti / Au.

[0026] In step 106, CICE is performed as shown in Figure 2G. In one embodiment, the portion of the substrate 201 beneath the catalyst 204 is etched in the CICE solution, thereby allowing the catalyst 204 to proceed to etch into the substrate 201. In one embodiment, the resulting structure includes a nanostructure array (etched nanostructure) designed to separate particles in a fluid medium having different sizes, shapes, or flow characteristics, and the spacing within the etched nanostructure is designed to separate the particles. In one embodiment, the geometry of the individual pillars of the nanostructure array is determined by the flow profile. In one embodiment, the geometry of the individual pillars of the nanostructure array is optimized for its shape, and the shape includes one of circular, triangular, rectangular, rhombus, and airfoil. In one embodiment, the individual pillars of the nanostructure array are capped to confine the flow of particles between gaps within the nanostructure array.

[0027] Figure 3 shows a process flow for a uniform CICE with the undercoat oxide layer and undercut described in Method 100, according to an embodiment of the present invention.

[0028] Referring to Figures 1 and 2A to 2G, and also to Figure 3, Figure 3 shows an imprint nanofeature 301 formed by patterning the imprint resist 203 using nanoimprint lithography as shown in Figure 2C.

[0029] As discussed above, the remaining layer thickness and etching uniformity improvement layer 202 (e.g., silicon oxide) are shown in Figure 302 and are etched as shown in Figure 2E.

[0030] Furthermore, as discussed above, thin-film catalysts such as Ti / Au are deposited between nanostructures, as shown in Figure 2F and Image 303.

[0031] Finally, as discussed above, a portion of the substrate 201 beneath the catalyst 204 is etched in the CICE solution and CICE is performed, thereby proceeding to the etching of the catalyst 204 into the substrate 201, as shown in Figure 2G and Image 304.

[0032] In one embodiment, Figure 3 shows experimental results of Method 100 in which an underlayer between the resist and silicon is used to improve etching uniformity by (a) creating undercuts and / or (b) enhancing etchant transfer by etching in the CICE solution and / or improving etchant moisture, thereby enabling a uniform "starting point" throughout the wafer and thus deriving etching uniformity. This ensures that the etch starts at the same point in all parts of the wafer, ensuring uniformity of the etch depth.

[0033] Referring to Figure 4, Figure 4 is a flowchart of an alternative method 400 for patterning a post-imprint catalyst according to an embodiment of the present invention. Figures 5A to 5H show cross-sectional views illustrating the patterning of a post-imprint catalyst using the steps shown in Figure 4 according to an embodiment of the present invention.

[0034] Referring to Figures 5A to 5H, and also to Figure 4, in step 401, an insulating layer (e.g., silicon oxide) 202 is deposited (underlay deposition) on the substrate 201 (e.g., a silicon substrate), as shown in Figures 5A and 5B. In one embodiment, the thickness of the etching uniformity improvement layer 202 ranges from 5 nm to 100 nm. In one embodiment, the etching uniformity improvement layer 202 is thermally grown on the substrate 201 (e.g., a crystalline silicon substrate). In one embodiment, the etching uniformity improvement layer 202 is a native silicon oxide layer.

[0035] In step 402, as shown in Figure 5C, an imprint resist 203 (e.g., a monomer or polymer formulation) is deposited and patterned (forming a nanostructure) on the etching uniformity improvement layer 202 via nanoimprint lithography.

[0036] In step 403, as shown in Figure 5D, residual layers (remnants of the imprint resist 203), such as those between nanostructures formed by the imprint resist 203, are removed by plasma etching.

[0037] In step 404, isotropic etching is used to etch a portion of the etching uniformity improvement layer 202, including between and beneath the nanostructures, such as through undercuts, as shown in Figure 5E. In one embodiment, the etchant comprises two or more of the following: fluoride species including the chemical HF or NH4F, oxides (e.g., H2O2, KMnO4), alcohols (e.g., ethanol, isopropyl alcohol, ethylene glycol), and solvents (e.g., proton, aproton, polar, and nonpolar solvents).

[0038] In step 405, catalyst 204 is deposited on and between the nanostructure, as shown in Figure 5F. In one embodiment, catalyst 204 is a thin film of Ti / Au.

[0039] In step 406, the etching uniformity improvement layer 202 and the imprint resist 203 are removed, for example, via a lift-off process, as shown in Figure 5G.

[0040] In step 407, CICE is performed as shown in Figure 5H. In one embodiment, the portion of the substrate 201 beneath the catalyst 204 is etched in the CICE solution, thereby allowing the catalyst 204 to proceed to etch into the substrate 201. In one embodiment, the resulting structure includes a nanostructure array (etched nanostructure) designed to separate particles in a fluid medium having different sizes, shapes, or flow characteristics, where the spacing within the etched nanostructure is designed to separate the particles. In one embodiment, the geometry of the individual pillars of the nanostructure array is determined by the flow profile. In one embodiment, the geometry of the individual pillars of the nanostructure array is optimized for its shape, and the shape includes one of circular, triangular, rectangular, rhombus, and airfoil. In one embodiment, the individual pillars of the nanostructure array are capped to confine the flow of particles between gaps within the nanostructure array.

[0041] Next, referring to Figure 6, which is a flowchart of a further alternative method 600 for patterning a post-imprint catalyst according to an embodiment of the present invention. Figures 7A to 7F show cross-sectional views illustrating the patterning of a post-imprint catalyst using the steps described in Figure 6 according to an embodiment of the present invention.

[0042] Referring to Figures 7A to 7F, and also to Figure 6, in step 601, as shown in Figures 7A and 7B, an insulating layer (e.g., silicon oxide) 202 is deposited (e.g., underlay deposition) on the substrate 201 (e.g., silicon substrate). In one embodiment, the thickness of the etching uniformity improvement layer 202 ranges from 5 nm to 100 nm. In one embodiment, the etching uniformity improvement layer 202 is thermally grown on the substrate 201 (e.g., crystalline silicon substrate). In one embodiment, the etching uniformity improvement layer 202 is a native silicon oxide layer.

[0043] In step 602, as shown in Figure 7C, an imprint resist 203 (e.g., a monomer or polymer formulation) is deposited and patterned (forming a nanostructure) on the etching uniformity improvement layer 202 via nanoimprint lithography.

[0044] In step 603, as shown in Figure 7D, residual layers (residual imprint resist 203), such as those between nanostructures formed by the imprint resist 203, are removed by plasma etching.

[0045] In step 604, catalyst 204 is deposited on and between the nanostructure, as shown in Figure 7E. In one embodiment, catalyst 204 is a thin film of Ti / Au.

[0046] In step 605, CICE is performed as shown in Figure 7F. In one embodiment, the portion of the substrate 201 beneath the catalyst 204 is etched in the CICE solution, thereby allowing the catalyst 204 to proceed to etch into the substrate 201. In one embodiment, the resulting structure includes a nanostructure array (etched nanostructure) designed to separate particles in a fluid medium having different sizes, shapes, or flow characteristics, where the spacing within the etched nanostructure is designed to separate the particles. In one embodiment, the geometry of the individual pillars of the nanostructure array is determined by the flow profile. In one embodiment, the geometry of the individual pillars of the nanostructure array is optimized for its shape, and the shape includes one of circular, triangular, rectangular, rhombus, and airfoil. In one embodiment, the individual pillars of the nanostructure array are capped to confine the flow of particles between gaps within the nanostructure array.

[0047] Next, referring to Figure 8, which is a flowchart of an additional alternative method 800 for patterning a post-imprint catalyst according to an embodiment of the present invention. Figures 9A to 9E show cross-sectional views illustrating patterning a post-imprint catalyst using the steps described in Figure 8 according to an embodiment of the present invention.

[0048] Referring to Figures 9A to 9E, and also to Figure 8, in step 801, as shown in Figures 9A and 9B, an imprint resist 203 (for example, a monomer or polymer formulation) is deposited and patterned (forming a nanostructure) on the substrate 201 via nanoimprint lithography.

[0049] In step 802, as shown in Figure 9C, residual layers (remnants of the imprint resist 203), such as those between nanostructures formed by the imprint resist 203, are removed by plasma etching.

[0050] In step 803, catalyst 204 is deposited on and between the nanostructure, as shown in Figure 9D. In one embodiment, catalyst 204 is a thin film of Ti / Au.

[0051] In step 804, CICE is performed as shown in Figure 9E. In one embodiment, the portion of the substrate 201 beneath the catalyst 204 is etched in the CICE solution, thereby allowing the catalyst 204 to proceed to etching into the substrate 201. In one embodiment, the resulting structure includes a nanostructure array (etched nanostructure) designed to separate particles in a fluid medium having different sizes, shapes, or flow characteristics, where the spacing within the etched nanostructure is designed to separate the particles. In one embodiment, the geometry of the individual pillars of the nanostructure array is determined by the flow profile. In one embodiment, the geometry of the individual pillars of the nanostructure array is optimized for its shape, and the shape includes one of circular, triangular, rectangular, rhombus, and airfoil. In one embodiment, the individual pillars of the nanostructure array are capped to confine the flow of particles between gaps within the nanostructure array.

[0052] As discussed above, Figures 1, 2A-2G, 3, 4, 5A-5H, 6, 7A-7F, 8, and 9A-9E illustrate five processes related to catalyst patterning for CICE.

[0053] In one embodiment, catalyst 204 comprises one or more of Au, Pt, Pd, Mo, Ir, Ru, Ag, Cu, Ni, W, TiN, TaN, RuO2, IrO2, graphene, Ti, and carbon. In one embodiment, catalyst 204 has an adhesive layer. In one embodiment, catalyst 204 is gold and the adhesive layer is Ti. In another embodiment, catalyst 204 is Ru and the adhesive layer is Ti.

[0054] In one embodiment, the catalyst 204 is patterned using one of the following methods: nanoimprint lithography, photolithography, focused ion beam milling, electron beam lithography, laser interference lithography, nanosphere lithography, block copolymer lithography, and induced self-assembly.

[0055] In one embodiment, a feature fabricated using CICE has a critical dimension of less than 200 nm, a height greater than 200 nm, and a wall taper angle greater than 89.5 degrees. In one embodiment, the wall taper angle at any point along the sidewall is greater than 89.5 degrees. In one embodiment, the taper angle is 89.9 degrees. In another embodiment, the angle is 90 degrees. In one embodiment, points along the sidewall do not include the uppermost and lowermost points (if the angle changes from zero degrees relative to the horizontal plane to 90 degrees on the sidewall surface).

[0056] In one embodiment, the aspect ratio of the feature is greater than 5. In another embodiment, the aspect ratio is greater than 10. In yet another embodiment, the aspect ratio is greater than 20. In one embodiment, the aspect ratio is greater than 100.

[0057] In one embodiment, the nanofeature forms a cross-section with sharp corners having a radius of curvature of less than 10 nm. In another embodiment, the radius of curvature is less than 5 nm. In yet another embodiment, the radius of curvature of the sharp corners is less than 20 nm. The resulting cross-sectional geometric shapes include diamond, triangular, fractal, rectangular, quadrilateral, star, bow tie, airfoil, ellipse, helix, and the like. Lithography for manufacturing such structures is described in U.S. Patent No. 10,026,609, which is incorporated herein by reference in its entirety. In one embodiment, electron beam and optical lithography are used. In another embodiment, multiple patterning techniques (e.g., triple, quad patterning, litho-etch, spacer techniques, etc.) are used to manufacture features or templates for imprint lithography.

[0058] In one embodiment, the features are patterned using nanoimprint lithography. In one embodiment, the residual thickness (RLT) of the resist after patterning using nanoimprint lithography is less than 50 nm. In one embodiment, the RLT is less than 100 nm. In another embodiment, the RLT is less than 20 nm. In yet another embodiment, the RLT is less than 10 nm.

[0059] In one embodiment, the substrate 201 for CICE is a silicon wafer. In another embodiment, the substrate 201 is a silicon-on-nonsilicon wafer, such as an SOI wafer, silicon-on-sapphire, silicon-on-polymer, or silicon-on-metal. In one embodiment, the substrate 201 is a bulk single-crystal silicon wafer, a layer of polycrystalline silicon with a thickness greater than 100 nm deposited on the substrate, a layer of amorphous silicon with a thickness greater than 100 nm deposited on the substrate, an SOI (silicon-on-insulator) wafer, silicon-on-glass, silicon-on-sapphire, epitaxial silicon with a thickness greater than 100 nm on the substrate, alternating layers of semiconductor materials with different doping levels and dopants, highly doped silicon and low-doped silicon, undoped silicon and doped silicon or germanium, silicon and Si x Ge 1-x , differently doped silicon and / or Si x Ge 1-x , silicon and / or Ge doped in different ways, or one of Si and Ge.

[0060] Furthermore, embodiments of the present invention may use analog CICE to perform intentional etch variability. Etching uniformity depends heavily on the resist shape and catalyst thickness. Adjusting these parameters can make intentional analog variability in etch depth visualize collapse behavior at the nanoscale. Etchant transfer to the metal / silicon interface is crucial for uniform MAC etch. Etching uniformity depends heavily on the catalyst patterning method and the thickness of the film used. In one embodiment, gold patterning is performed using lift-off. The lift-off process requires the breakage of the gold film after deposition on a resist feature, which has an "undercut" profile. The gold on the resist feature is removed during wet etch of the resist, leaving the patterned gold on the silicon wafer. Alternatively, CICE can be performed without the lift-off step, as long as there is breakage in the gold film. When a uniform, continuous film is deposited on a patterned resist without metallic fracture, either against an "overcut" resist feature or against a thicker gold film, CICE begins at pinhole defects and discontinuities of the catalyst metal on the wafer. The initiation of such pinholes allows for further lateral etchant transport, causing delayed CICE in the surrounding area, thereby creating nanowires with analogous height variation. In one embodiment, the discontinuities are created using one or more of focused ion beams, photolithography, imprint lithography, laser writing, and pattern geometry. In one embodiment, the shape of the discontinuities includes one or more of circular pinholes, lines, and a series of intersecting lines. Figures 10A–10B show the difference between CICE for gold deposited on an "undercut" feature where an oxide underlayer is used to create undercuts for metallic fracture, compared to an "overcut" feature without an underlayer that creates metallic fracture in the nanoscale pattern. The two CICE patterns demonstrate differences in etching uniformity and the formation of "pinhole locations" where the CICE process begins.

[0061] Next, referring to Figures 10A and 10B, Figures 10A and 10B show the effect of continuous versus discontinuous catalysis on the variation of CICE etching according to embodiments of the present invention. Figure 10A shows the undercut resist profile 1001, and Figure 10B shows the overcut resist profile 1002. Figures 10A and 10B show the effect of the profiles (profiles 1001 and 1002, respectively) on subsequent CICE for fabricating nanowires.

[0062] In one embodiment, the overcut process is used to create regions with different nanowire heights, and the occurrence of collapse can be visualized as the height at which the tips of two or more nanowires begin to contact. Figures 11A to 11C show variations in analog etch depth in CICE using pinholes in a catalyst film according to an embodiment of the present invention. Specifically, Figures 11A to 11C show a 100 mm silicon wafer with circular regions showing variations in etch depth, which appear as collapse of taller nanowires. As shown in Figures 11A to 11C, a top-down SEM shows the collapse of the nanowires.

[0063] In one embodiment, analog CICE is used to intentionally vary the etch depth to detect a critical aspect ratio for collapse occurrence. In one embodiment, silicon nanowires with different diameters and etch depths are fabricated using nanoimprint lithography and analog CICE. Collapse occurrence can be detected using defect detection algorithms such as local binary pattern (LBP). At larger diameters (smaller spacing), the height of the NW (nanowire) for critical collapse is greater than at smaller diameters (larger spacing) at the same pitch. In one embodiment, the combination of increased diameter and experimentally observed associated increased height leads to a significant increase in the surface area of ​​the Si NW.

[0064] Embodiments of the present invention enable feature size control for sublithography spacing for CICE.

[0065] In one embodiment, imprint lithography is used to pattern circular resist pillars with a diameter of 120 nm at a pitch of 200 nm using a template fabricated using electron beam lithography. Varying the diameter of these wires can be done by imprinting with a template having patterns with different diameters. However, this is very expensive due to the cost of fabricating the template and the long electron beam writing time. At a given pitch, plasma etching, chemical vapor deposition, or atomic layer deposition can be used to vary the diameter of the resist after imprinting, before gold deposition and CICE. Figure 12 shows a process modification from a typical CICE process for varying the diameter of circular nanowires (NWs) at a constant pitch.

[0066] Referring to Figure 12, Figure 12 shows a process step of varying the diameter of an imprinted resist pattern 1201 to produce silicon nanowires with precisely controlled feature dimensions at a constant pitch, according to an embodiment of the present invention.

[0067] In one embodiment, NW diameters ranging from 75 to 110 nm are obtained by a standard process shown in Figures 1 and 2A to 2G, with increasing residual layer thickness etching time (see element 1202). This is done using oxygen and argon plasma, along with a vertical etching rate of 30 nm / min and a lateral etching rate of 5 nm / min. Simultaneously varying the etching time to remove RLT and reduce the diameter allows for a reduction in nanowire diameter.

[0068] In one embodiment, for NW diameters ranging from 110 nm to 140 nm, a chemical vapor deposition (CVD) process is used to deposit a fluoropolymer on the imprinted resist 1201 by flowing C4F8 gas in a plasma reactor (see element 1203). A thin conformal layer of fluoropolymer is deposited, increasing the diameter of the resist. Varying the RLT etching time (see element 1204) is used to remove the RLT and decrease the diameter.

[0069] In one embodiment, for diameters ranging from 140 to 175 nm, a conformal layer of the film (etchable in a CICE solution, e.g., silicon oxide, aluminum oxide) is deposited using atomic layer deposition (ALD) after imprint and RLT etching (see element 1205) (see element 1206). In one embodiment, 30 nm of aluminum oxide is deposited (after RLT etching) on ​​a 110 nm diameter resist pillar, resulting in the formation of a pillar with a diameter of 170 nm. Gold deposition and CICE result in a silicon nanowire with a diameter of 170 nm. In one embodiment, the wire thickness is variable by changing the ALD film thickness. The ALD oxide is etched off during the CICE process.

[0070] The following discusses nanostructures utilizing CICE.

[0071] CICE is used to fabricate high aspect ratio (HAR) Si nanostructures with arbitrary geometric shapes. In one embodiment, these structures are fabricated in silicon on a non-silicon substrate. In one embodiment, the silicon is single-crystal silicon, and the non-silicon substrate is a polymer such as silicon oxide, sapphire, or polycarbonate, or a metal such as hastealloy.

[0072] In one embodiment, silicon nanostructures fabricated using CICE are oxidized to convert them to partially or substantially silicon oxide. In one embodiment, silicon is oxidized before the deposition of the desired material using methods such as thermal oxidation, plasma oxidation, anodic oxidation, photo-based oxidation (e.g., vacuum ultraviolet (VUV)), or ozone-based oxidation.

[0073] The geometry of the silicon pillars etched (and subsequently oxidized) by CICE is optimized to take into account the pillar's geometry in order to minimize changes in feature size due to collapse and oxidation.

[0074] In one embodiment, the material is deposited on silicon nanostructures etched using CICE, which employs conformal deposition methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition, thermal oxidation, and electrodeposition. In one embodiment, the deposited (shell) material is TiO2. In another embodiment, the deposited material is SiO2. In yet another embodiment, no material is deposited, and the silicon is completely oxidized. In yet another embodiment, the silicon nanostructures are oxidized to less than 10% of their volume. In yet another embodiment, the silicon nanostructures are oxidized to less than 50% of their volume.

[0075] In another embodiment, the silicon nanostructure (or core) has a space-filling geometric shape. In another embodiment, the silicon nanostructure (or core) has a high degree of rotational symmetry. In one embodiment, high degree of rotational symmetry refers to a core cross-section having rotational symmetry of order 6 or higher. In another embodiment, the silicon nanostructure is asymmetric (Figures 13, 14A-14D, 15A, 15B1, 15B2, and 15C). In another embodiment, the silicon nanostructure has different pitches to adjust the local packaging density of the nanostructure. In another embodiment, the silicon structure is bonded using a maze and takes the shape of a group of undirected acyclic graphs. In another embodiment, only silicon structures consisting of undirected acyclic mazes exist (Figures 14A-14D and 16A-16C).

[0076] In another embodiment, the nanostructure is fabricated using porous silicon (which can be produced using the CICE process) and then oxidized.

[0077] When nanostructures are used in lens applications (such as metalenses), the core, shell, or both are doped either before or after CICE to modify the refractive index. In another embodiment, the nanostructure has a roughness suitable for reducing light loss due to reflection at material interfaces (such as air-Si, SiO2-TiO2, etc.). In yet another embodiment, the nanostructure is coated with an anti-reflective coating to reduce light loss hardening due to reflection at material interfaces.

[0078] In one embodiment, the core structure has a minimum feature size of 50 nm or less. In another embodiment, the core structure has a minimum feature size of 100 nm or less. In yet another embodiment, the core structure has a minimum feature size of 200 nm or less. In one embodiment, the surface of the core structure has a roughness that reduces interfacial reflection loss. In one embodiment, the core structure is coated with an anti-reflective coating.

[0079] In one embodiment, the shell structure has a thickness greater than 10 nm. In another embodiment, the shell structure has a thickness greater than 50 nm. In yet another embodiment, the shell structure has a thickness greater than 100 nm. In one embodiment, the surface of the shell structure has a roughness that reduces interfacial reflection loss. In one embodiment, the shell structure is coated with an anti-reflective coating.

[0080] In one embodiment, the core structure has a height greater than 100 nm. In another embodiment, the core structure has a height greater than 500 nm. In one embodiment, the core structure has a height greater than 1 μm. In another embodiment, the core structure has a height greater than 2 μm.

[0081] Next, referring to Figure 13, Figure 13 is a flowchart of Method 1300 for a conformal deposition process to obtain a desired material high aspect ratio (HAR) nanostructure with a variant of nanostructure geometric shape without using substitution steps, according to embodiments of the present invention. Figures 14A to 14D are cross-sectional views for obtaining HAR nanostructures using the steps described in Figure 13, according to embodiments of the present invention. Figures 15A, 15B1, 15B2 and 15C show variants of nanostructure geometric shape using the conformal deposition process of Figure 13, according to embodiments of the present invention.

[0082] Referring to Figure 13, along with Figures 14A-14D and Figures 15A, 15B1, 15B2, and 15C, in step 1301, CICE is performed on silicon-on-x (e.g., silicon-on-insulator (SOI), silicon-on-sapphire (SOS), silicon-on-glass (SOG), etc.). For example, as shown in Figure 14A, CICE is performed on a silicon-on-x structure, where silicon is represented by 1402 and "x" is represented by 1401. As shown in Figure 14B, after CICE is performed, silicon 1402 is etched to form a nanostructure.

[0083] Referring to Figure 14B, Figure 15A shows a silicon core with a stable I-beam structure. Figures 15B1 to 15B2 show top views of a silicon core with 8 degrees of symmetry. Figure 15C shows a top view of an axisymmetric silicon core. In one embodiment, the silicon core has a geometric shape designed to take into account structural and performance constraints. In one embodiment, the silicon core is doped.

[0084] In the optional step 1302, silicon 1402 is optionally oxidized.

[0085] In step 1303, as shown in Figure 14C, the active material 1403 is deposited on silicon 1402 such as oxidized silicon. In one embodiment, the active material 1403 is titanium dioxide, aluminum oxide, palladium, platinum, tungsten, titanium nitride, tantalum nitride, copper, SiN x SnO x , and ZnO x It includes one of the following.

[0086] In step 1304, the active material 1403 is etched back as shown in Figure 14D, which illustrates the final device.

[0087] Figures 16A to 16C illustrate different shapes of nanostructure geometry using the conformal deposition process shown in Figure 13, which are based on embodiments of the present invention.

[0088] Referring to Figures 16A to 16C along with Figure 14B, Figures 16A to 16C show various top views of different nanostructure geometric shapes of silicon cores.

[0089] In some applications, materials other than silicon are required to improve performance. The substitution process for fabricating nanostructured anisotropic high aspect ratio structures using the desired material is illustrated in Figures 17, 18A–18D, 19, and 20A–20E. In one embodiment, pillars within the active material may require the holes to be etched within silicon. To prevent wandering, the holes may be connected. The connections may be oxidized later or filled using ALD, CVD, etc.

[0090] In one embodiment, the material is deposited on silicon nanostructures etched using CICE, which employs conformal deposition methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition, thermal oxidation, and electrodeposition.

[0091] The deposited material includes metal oxides, metal nitrides, metals, semiconductors, and insulators such as Al2O3, TiN, W, TiO2, Pd, Pt, SiO2, HfO2, and Cu, and is selected based on the desired device properties. The devices include metalens, metamaterials, thermoelectrics, battery electrodes, and gas sensors.

[0092] After the material is deposited, the silicon nanostructures are removed, resulting in nanostructures of the opposite tone within the deposited material. In one embodiment, the silicon nanostructures are removed by accessing the silicon and etching it using methods such as wet etching (tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH), ethylenediamine pyrocatechol (EDP), etc.), plasma etching, or dry etching (XeF2).

[0093] Access to silicon is created by (a) using silicon on a substrate and removing the silicon-to-substrate junction using wet etching (for example, on an SOI wafer where oxides are etched off using hydrogen fluoride (HF)), (b) stripping the silicon to obtain a thin layer of silicon to be subsequently removed, and (c) etching off all silicon from the back.

[0094] Next, referring to Figure 17, Figure 17 shows a method 1700 for obtaining a desired material high aspect ratio (HAR) nanostructure using a substitution process and atomic layer deposition (ALD) according to an embodiment of the present invention. Figures 18A to 18E show cross-sectional views for obtaining a desired HAR nanostructure using the steps described in Figure 17 according to an embodiment of the present invention.

[0095] Referring to FIGS. 17 together with FIGS. 18A - 18E, in step 1701, as shown in FIGS. 18A - 18B, CICE is executed on silicon - on - x (e.g., silicon wafer, silicon - on - insulator (SOI), silicon - on - sapphire (SOS), silicon - on - glass (SOG), etc.). For example, as shown in FIG. 18A, CICE is executed on a silicon - on - x structure, where silicon is represented by 1802 and "x" is represented by 1801. As shown in FIG. 18B, after CICE is executed, silicon 1802 is etched to form a nanostructure, which is the inverse of the desired pattern.

[0096] In step 1702, the active material 1803 is deposited on the structure of FIG. 18B, which includes the etched silicon 1802 and the structure 1801 shown in FIG. 18C. In one embodiment, the active material 1803 includes one of titanium dioxide, aluminum oxide, palladium, platinum, tungsten, titanium nitride, tantalum nitride, copper, SiN x , SnO x , and ZnO x .

[0097] In step 1703, the active material 1803 is etched back as shown in FIG. 18D.

[0098] In step 1704, after etching back the active material 1803, the remaining structure is bonded to the final carrier substrate 1804 (e.g., glass) as shown in FIG. 18D.

[0099] In step 1705, as shown in FIG. 18E which is the final device structure, the structure 1801 and silicon 1802 are etched, for example, via hydrogen fluoride (HF) for the structure 1801 and via KOH for silicon 1802 when the structure 1801 is glass. In one embodiment, the structure 1801 and silicon 1802 are removed using a wet etchant, a dry etchant, or plasma etching.

[0100] Figure 19 is a flowchart of Method 1900 for obtaining a desired material high aspect ratio (HAR) nanostructure using a silicon exfoliation replacement process and atomic layer deposition (ALD) according to an embodiment of the present invention. Figures 20A to 20E show cross-sectional views for obtaining a desired HAR nanostructure using the steps described in Figure 19 according to an embodiment of the present invention.

[0101] Referring to Figure 19 along with Figures 20A to 20E, in step 1901, CICE is performed on silicon 2001 (e.g., an SOI substrate) to form silicon nanowires 2002, as shown in Figure 20A.

[0102] In step 1902, as shown in Figure 20B, the desired material and etch stop layer 2003 are deposited on the silicon nanowires 2002 and silicon 2001. In one embodiment, the etch stop layer is used to stop the etching process.

[0103] In step 1903, an additional layer of material (for example, nickel) 2004 is deposited on top of layer 2003, as shown in Figure 20C.

[0104] In step 1904, the substrate 2001 is peeled off or etched back (for example, by oxide etch) as shown in Figure 20D.

[0105] In step 1905, as shown in Figure 20E, silicon etching is performed to remove the silicon nanowires 2002. In one embodiment, the silicon nanowires 2002 are removed using a wet etchant, a dry etchant, or plasma etching.

[0106] Alternatively, in application examples where removal does not improve the properties of the device, silicon may remain unetched. In one embodiment, silicon is oxidized before the deposition of the desired material. Figure 21 is a flowchart of method 2100 for achieving nanostructures in a desired material according to an embodiment of the present invention. Figures 22A to 22D show cross-sectional views of achieving nanostructures in a desired material using the steps described in Figure 21 according to an embodiment of the present invention.

[0107] Referring to Figure 21 along with Figures 22A to 22D, in step 2101, CICE is performed on silicon-on-x (e.g., silicon wafer, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), silicon-on-glass (SOG), etc.), as shown in Figures 22A to 22B. For example, as shown in Figures 22A to 22B, CICE is performed on a silicon-on-x structure as shown in Figure 22A, where silicon is represented by 2202 and "x" is represented by 2201, resulting in an etched silicon nanostructure as shown in Figure 22B.

[0108] In the optional step 2102, silicon 2202 is optionally oxidized.

[0109] In step 2103, as shown in Figure 22C, the active material 2203 is deposited on silicon 2202, such as oxidized silicon.

[0110] In step 2104, the active material 2203 is etched back as shown in Figure 22D, which illustrates the final device.

[0111] In one embodiment, silicon nanostructures are etched using CICE within a tool fabricated for a uniform, high-throughput CICE process, and the nanostructures are then oxidized using anodic oxidation within the same tool with a desired electrolyte for oxidation.

[0112] The principle of this invention is to perform CICE for particle separation using deterministic lateral displacement (DLD).

[0113] The detection of low concentrations of biomolecules can enable early disease detection and monitoring of patient response to treatment. Such diagnostic tools can inform crucial decisions regarding treatment methods and improve patient treatment outcomes. In the early stages of a disease, the concentrations of disease markers are very low and difficult to detect in common specimens such as blood, urine, plasma, and serum. Capturing and isolating biomarkers such as tumor cells and exosomes can enable sensors to detect these biomarkers. High-density arrays of vertical nanowires exhibit high capture efficiency and yield at high throughput. The geometry of the nanowire array can be adjusted to capture biomolecules of the desired size.

[0114] Deterministic transverse displacement (DLD) is a microfluidic technique that precisely separates particles in a fluid medium, both above and below critical size, using a specific arrangement of pillars in an array placed within a microfluidic channel. The gaps between pillars and the placement of the pillars in the array determine the critical particle size and separation pathway. Particles below critical size follow a zigzag motion, while particles above critical size enter a bumping mode.

[0115] The effects of different column shapes are being investigated at the microscale. Circular columns have a zone at the top where the flow velocity is zero, leading to particle clogging and deformation of soft particles. Triangular, streamlined (airfoil), I-shaped, diamond, and quadrilateral columns are being investigated to increase the effective diameter, with the aim of reducing resistance within the device, increasing flow rates at low-pressure heads, and investigating the irregular and / or deformable particle motion in the fluid medium.

[0116] At the microscale, the flow is primarily layered, and mixing occurs by diffusion. Such diffusion can reduce separation efficiency if the flow velocity falls below a certain range determined by the Peclet number (Pe)—the ratio of diffusion time to convection time. For small particles (size <10 micrometers), the diffusion time and therefore the Peclet number are lower, which can lead to a more pronounced diffusion effect that can reduce separation efficiency. For even smaller particles, the gaps between pillars are smaller, which causes a decrease in flow rate and particle time for a given fluid pressure. Soft particles can deform due to shear stress between pillars. Effective size, rather than actual size, should be considered when designing the pillar array. Irregularly shaped particles flowing in a DLD tend to orient themselves such that their minimum dimension is a critical dimension. In one embodiment, very shallow compression is used to limit the range of possible orientations, but this compression reduces flow rate and increases flow separation time. Reducing the gap between pillars using nanolithography, rather than using microscale pillars, can achieve the same separation rate along with higher throughput.

[0117] Taller pillars lead to higher throughput, limited by the aspect ratio before collapse. The material used in the pillars is important – polydimethylsiloxane (PDMS) pillars cause cell adhesion and deform considerably under pressure. Silicon pillars are more robust. However, fabricating HAR silicon pillars with small gaps using plasma etching leads to etching taper, which alters the gap size. Catalytically influenced chemical etching (CICE) can be used to fabricate HAR silicon pillars with small gaps and sharp corner cross-sections, as shown in Figure 23. Figure 23 shows silicon nanopillars fabricated using CICE for DLD-based particle separation according to an embodiment of the present invention. The aspect ratio of pillars with small gaps can be optimized using analog CICE to experimentally determine the critical collapse height. Nanopillars with optimized shape, size, and pillar array spacing can be tested using analog metal-assisted chemical etching (MACE). In one embodiment, the catalyst for CICE may be Ru, Pd, Pt, Au, Ag, etc.

[0118] In one embodiment, the throughput of particle separation in a fluid medium is increased by designing the pillars such that the pillar height is maximized without causing substantial collapse in order to maximize the throughput of fluid through the structures without increasing the spacing between structures. The height of the nanostructure array is determined by the maximum height before substantial collapse in order to maximize the aspect ratio of the nanostructure array.

[0119] The spacing is determined by the size of the critical particles to be separated. In one embodiment, the pillar size is determined by optimizing the maximum collapse height and minimum pillar size to increase the flow rate between the pillars.

[0120] In one embodiment, the spacing or gap between pillars is less than 100 nm. In another embodiment, the spacing is less than 200 nm. In one embodiment, the spacing is less than 50 nm. In one embodiment, the spacing is less than 25 nm. The aspect ratio of the pillars can vary from greater than 5, greater than 10, and greater than 20. In one embodiment, the aspect ratio of the pillars is greater than 50. The aspect ratio is defined as the ratio of the pillar height to the critical feature size of the pillar cross-section.

[0121] In one embodiment, a nanopillar fabricated using CICE has a critical dimension of less than 200 nm, a height greater than 200 nm, and a wall taper angle greater than 89.5 degrees. In another embodiment, the nanopillar has a cross-sectional geometry with sharp corners and an angular radius of less than 5 nm. As shown in Figure 23, an inlet 2301 (a sample with a mixture of particles of multiple sizes and shapes) is fed into a DLD pillar array 2302 that forms an outlet stream 2303 (multiple streams with particles separated by size and / or shape). The DLD pillar array 2302 includes a pattern generated to maximize separation efficiency and throughput using one or more of the pillar size and spacing, pillar shape (e.g., circular, triangular, diamond, streamlined, etc.), pillar array placement and skew angle, and pillar height before collapse. Figure 23 shows an example of a diamond-shaped silicon nanopillar with a critical dimension of less than 130 nm, a pitch of 200 nm, and an angular radius of diamond tip of less than 5 nm.

[0122] The principle of this invention may also utilize CICE as a sensor.

[0123] Biomarker detection has been demonstrated using silicon nanowire devices that are functionalized with biomolecules such as nucleic acids, antibodies, and aptamers. For nanowire FETs, detection ranges of aM to nM have been reported, while for nanowire memristor sensors, the range is aM to fM.

[0124] However, the nanowires used in the devices (both for capturing desired biomarkers and within sensors for detecting low concentrations of biomarkers) are expensive to fabricate and experience variability in device performance. Plasma etching of nanowires results in rough surfaces and non-perpendicular sidewalls, which reduces capture efficiency. Fabrication involves expensive and unscalable processes, such as electron beam lithography and / or nanowire transfer with precise alignment.

[0125] SiNW field-effect transistor (FET) sensors are patterned using electron beam lithography and etched by plasma etching. Increasing the aspect ratio of the nanowire (for example, by making it a finFET) can improve sensitivity. CICE can be used to etch tall fins without an etching taper to avoid device-to-device variability and improve the signal-to-noise ratio.

[0126] The fabrication of memristor sensors requires highly controlled plasma etching and oxidation. Alternatively, CICE can be used to fabricate multilayer horizontal nanowires, similar to the fabrication of nanosheet FETs using silicon superlattice etching. A description of using CICE to fabricate multilayer horizontal nanowires is provided in U.S. Patent Application Publication 2020 / 0365464, which is incorporated herein by reference in its entirety.

[0127] This results in a fin with alternating layers of non-porous silicon and porous silicon. The porous silicon layer is removable within the sensing area, and the drain and source areas are defined by depositing and annealing a metal such as nickel to obtain nickel silicide. This method enables the cost-effective, precise, large-scale fabrication of highly sensitive silicon nanowire-based memristor sensors, as well as other types of sensors such as transistor-based sensors, resistance-based sensors, capacitance-based sensors, and fluorescence-based sensors.

[0128] Furthermore, the principle of the present invention enables self-aligned imprint lithography (SAIL) for low-cost lithography.

[0129] Patterning of sensing elements (such as nanowires and fins for transistors, and suspended nanowires for memristors) can be performed in conjunction with patterning of source, drain, gate, metal wire, and transducer circuits using self-aligned imprint lithography. This reduces or eliminates the overlay errors and costs of multiple lithography steps. In one embodiment, a multilayer template with the required features is used for single-step lithography, with each layer of the template being used for a specific etching or deposition step to create the sensor. The next patterning step is avoided by using etching to move to the next layer of already imprinted resist features.

[0130] Furthermore, the principle of the present invention enables the implementation of devices manufactured using CICE.

[0131] High aspect ratio nanostructures, manufactured using CICE for various application examples, are post-processed and packaged to prevent collapse and improve mechanical and chemical stability with minimal impact on device performance.

[0132] In metalens applications, the interstitial spaces within the core-shell structure (shown in Figures 22A-22D and 23) can be filled with a transparent material that acts as a protector against mechanical and chemical damage, and potentially against nanostructure collapse (in applications where the nanostructure may be subjected to high acceleration). This material may be one or more polymer coatings (one of the coating layers may be, for example, a thin coating of a fluoropolymer to produce a device surface that is hydrophobic and resistant to moisture damage while maintaining transparency), as well as transparent insulating oxide and nitride films such as SiO2, Al2O3, and Si3N4. In another embodiment, a transparent plate may be used as a cover, and the space between the transparent plate and the core-shell structure may be filled with a fluid such as air or water.

[0133] Deposition techniques such as glancing angle deposition (GLAD), ALD, and CVD may be used to deposit transparent insulating oxide and nitride films. Furthermore, the coating layer adjacent to the metalens nanostructure may be made of an ultra-low refractive index material. This can be integrated into the metalens design without adversely affecting any optical properties, using co-optimization of the metalens and low refractive index material. Additionally, the core-shell structure may also be covered with a plate made from a transparent material that acts as an additional protective layer against mechanical and chemical damage.

[0134] For nanopillar arrays manufactured for DLD applications, a cover plate can be used to seal the device. Precise bubble-free bonding of the top cover on the nanopillar array is required to restrict the movement of particles in the fluid, which will be separated. This can be done using actuators to precisely lower the top cover (machined to have through-holes for fluid inlet and outlet) using multiple sound coil actuators. Furthermore, to improve throughput, multiple chips with pillar arrays can be stacked and bonded to each other. In one embodiment, a conformal film (e.g., a polymer material such as polycarbonate (PC), or a softer material such as polydimethylsiloxane (PDMS)) is bonded to the top of the pillar array, followed by a rigid cover plate such as glass that is sufficiently transparent and conformal (<0.7 mm thick).

[0135] Batteries with nanostructured electrodes are assembled using the desired electrolyte, anode, and cathode. Nanostructured thermoelectric devices are packaged to include electrical connections to a nanowire array. Sensors include electrical circuits and are packaged to expose the sensing element for detection of the analyte.

[0136] While various embodiments of the present invention have been presented for illustrative purposes, they are not intended to be exhaustive or to limit oneself to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described. The terms used herein have been chosen to best describe the principle of implementation, practical applications, or technical improvements to the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. [Explanation of Symbols]

[0137] 100 ways 201 circuit board 202 Etching uniformity improvement layer (e.g., silicon oxide), insulating layer 203 Imprint Resist 204 Catalysts, Thin-film catalysts 301 Imprint NanoFeatures 302 images 303 images 304 images 400 Alternative Method 600 Alternative Method 800 Alternative Method 1001 Undercut Resist Profile, Profile 1002 Overcut Resist Profile, Profile 1201 Resist pattern, resist 1202 elements 1203 elements 1204 elements 1205 elements 1206 elements 1402 Silicone 1403 Active materials 1801 Structure 1802 Silicon 1803 Active materials 1804 Final carrier substrate 2001 Silicon, substrate 2002 Silicon nanowires 2003 Etch stop layer, layer 2203 Active materials 2301 Entrance 2302 DLD Pillar Array 2303 Exit Stream

Claims

1. A method for fabricating silicon nanostructures, A step of depositing an etching uniformity improvement layer on the substrate, A step of depositing a catalyst on the substrate or the etching uniformity improvement layer, wherein the catalyst is in contact with a portion of the substrate or the etching uniformity improvement layer during the deposition process. A step of exposing the catalyst and the substrate or the etching uniformity improving layer to an etchant, wherein the catalyst causes etching of the substrate, thereby creating an etched nanostructure. Methods that include...

2. The catalyst is Au, Pt, Pd, Mo, Ru, Ir, Ag, Cu, Ni, W, TiN, TaN, RuO ２ IrO ２ The method according to claim 1, comprising one or more of graphene, Ti, and carbon.

3. The method according to claim 1, wherein the etching uniformity layer comprises a material etched in a chemically influential etching (CICE) etchant.

4. The method according to claim 1, wherein the etching uniformity layer is a thermally grown silicon oxide or a native silicon oxide layer having a thickness of more than 5 nm.

5. A method for fabricating silicon nanostructures, A step of depositing an etching uniformity improvement layer on the substrate, A step of depositing and patterning a resist to form a resist layer having multiple features, wherein the resist layer includes a residual layer with a thickness of less than 100 nm, The steps include etching the resist layer to remove the residual layer, A step of depositing a catalyst on the substrate or the etching uniformity improvement layer, wherein the catalyst is in contact with a portion of the substrate or the etching uniformity improvement layer during the deposition process. A step of exposing the catalyst and the substrate or the etching uniformity improving layer to an etchant, wherein the catalyst causes etching of the substrate, thereby creating an etched nanostructure. Methods that include...

6. The catalyst is Au, Pt, Pd, Mo, Ru, Ir, Ag, Cu, Ni, W, TiN, TaN, RuO ２ IrO ２ The method according to claim 5, comprising one or more of graphene, Ti, and carbon.

7. The method according to claim 5, wherein the etching uniformity layer comprises a material etched in a chemically influential etching (CICE) etchant.

8. The method according to claim 5, wherein the etching uniformity layer is a thermally grown silicon oxide or a native silicon oxide layer having a thickness of more than 5 nm.

9. A method for fabricating nanostructures of different heights, A step of supplying a catalyst layer onto the surface of a semiconductor substrate, wherein the catalyst layer comprises a plurality of features and one or more intentional discontinuities; A step of exposing the catalyst layer on the surface of the semiconductor substrate to an etchant, wherein the catalyst layer causes etching of the semiconductor substrate sequentially from one or more intentional discontinuities, and the resulting structure has height variations due to the feature closest to the one or more intentional discontinuities having the maximum height. Methods that include...

10. The catalyst layer is made of Au, Pt, Pd, Mo, Ru, Ir, Ag, Cu, Ni, W, TiN, TaN, RuO ２ IrO ２ The method according to claim 9, comprising one or more of graphene, Ti, and carbon.

11. The method according to claim 9, wherein the one or more intentional discontinuities are created using one or more of the focused ion beam, photolithography, imprint lithography, laser writing, and pattern geometry.

12. The method according to claim 9, wherein the shape of the one or more intentional discontinuities includes one of a circular pinhole, a line, and a series of intersecting lines.

13. The method according to claim 9, wherein the gradient of the variation in etching depth is determined by the pattern of one or more intentional discontinuities, as well as the etchant concentration and diffusion.

14. A method for fabricating silicon nanostructures, A step of patterning a polymer resist with multiple features on a substrate, In order to reduce the spacing between the plurality of features, the step of conformally depositing a material onto the polymer resist, A step of supplying a catalyst layer onto the substrate, wherein the catalyst layer is patterned using the plurality of features having reduced spacing such that the catalyst layer contacts only a portion of the substrate; A step of exposing the catalyst layer to an etchant, wherein the catalyst layer causes etching of the substrate, thereby creating an etched nanostructure. Methods that include...

15. The catalyst layer is made of Au, Pt, Pd, Mo, Ru, Ir, Ag, Cu, Ni, W, TiN, TaN, RuO ２ IrO ２ The method according to claim 14, comprising one or more of graphene, Ti, and carbon.

16. The method according to claim 14, wherein the conformal material is deposited using one of atomic layer deposition, chemical vapor deposition, and physical vapor deposition.

17. The method according to claim 14, wherein the conformal material is one or more of fluorocarbon, silicon dioxide, aluminum oxide, and titanium nitride.

18. A method for fabricating nanostructures using materials, A step of etching a silicon structure using catalytic chemical etching, wherein the etched silicon structure is designed to avoid substantial collapse; The steps include conformally depositing one or more materials onto the etched silicon structure, The steps include creating access to the etched silicon structure, selectively removing the etched silicon structure, leaving substantially the same one or more of the material; Methods that include...

19. The method according to claim 18, wherein the catalyst-induced chemical etching exposes a patterned catalyst on a semiconductor substrate to the etchant, and the patterned catalyst causes etching of the semiconductor substrate.

20. The patterned catalyst contains one or more of Au, Pt, Pd, Mo, Ru, Ir, Ag, Cu, Ni, W, TiN, TaN, RuO ２ , IrO ２ , graphene, Ti, and carbon, the method according to claim 18.

21. The one or more deposited materials are titanium dioxide, aluminum oxide, palladium, platinum, tungsten, titanium nitride, tantalum nitride, copper, SiN ｘ , SnO ｘ , and ZnO ｘ The method according to claim 18, wherein one or more of the above.

22. The method according to claim 18, wherein access to the etched silicon structure is made possible by one of the following: bonding the top with a backing layer and removing silicon from the back of a silicon wafer; etching back the top of the deposited material and etching the exposed silicon; thinning the top layer of the substrate using peeling before etching the silicon from the back of the substrate; and using a silicon-on-insulator wafer and etching the insulating layer to lift off the patterned layer on top.

23. A method for fabricating nanostructures of silicon layers on non-silicon layers, A step of etching silicon nanostructures using metal-assisted chemical etching, wherein the etched nanostructures are designed to avoid substantial collapse; The steps include partially or completely oxidizing the etched nanostructure and Methods that include...

24. The method according to claim 23, wherein the non-silicon layer is one of silicon oxide, sapphire, polymer, and metal.

25. The patterned catalyst layer is made of Au, Pt, Pd, Mo, Ru, Ir, Ag, Cu, Ni, W, TiN, TaN, RuO ２ IrO ２ The method according to claim 23, comprising one or more of graphene, Ti, and carbon.

26. A nanostructure of a silicon layer on a non-silicon layer having optical lens properties, wherein the core geometric shape is first etched into the silicon layer while substantially avoiding collapse, and then the core geometric shape is partially or completely oxidized.

27. The nanostructure according to claim 26, wherein the core geometric shape is first etched into the silicon layer using catalytic chemical etching.

28. The nanostructure according to claim 26, wherein a shell material is deposited on the core geometric shape.

29. The nanostructure according to claim 28, wherein the shell material comprises one of titanium dioxide and silicon dioxide.

30. The nanostructure according to claim 26, wherein the wall angle of one of the nanostructures exceeds 89.5 degrees at all points on the side wall, except for the upper and lower parts of the side wall.

31. The nanostructure according to claim 26, wherein one or more of the core structures among the nanostructures include an anti-reflective structure.

32. The nanostructure according to claim 26, wherein one or more of the nanostructures include an anti-reflective structure.

33. A device that uses silicon nanostructures, A silicon nanostructure designed to separate particles in a fluid medium having different sizes, shapes or flow characteristics within a nanostructure array, wherein the spacing between at least one pair of the silicon nanostructures is less than 50 nm, and the nanostructure wall angle of one or more of the silicon nanostructures is greater than 89.5 degrees at all points on the sidewalls, except for the upper and lower parts of the sidewalls. A device equipped with the following features.

34. The device according to claim 33, wherein the aspect ratio of the silicon nanostructure is greater than 10.

35. The aforementioned silicon nanostructure A pillar having a nano-shaped cross-sectional geometric shape with a cross section having sharp corners with a radius of curvature of <10 nm. The device according to claim 33, comprising:

36. The device according to claim 33, wherein the silicon nanostructure is fabricated using catalytically induced chemical etching.

37. The device according to claim 33, wherein the nanostructure array is designed to separate particles in a fluid medium having different sizes, shapes or flow characteristics, and the spacing within the nanostructure array is designed to separate the particles.

38. A device for the isolation and detection of biological species, A silicon nanostructure fabricated using catalytic chemical etching, wherein the silicon nanostructure is designed for particle separation in a fluid medium, A sensor used to detect a target species within the separated particles, the sensor and a sensor that generates an electrical and / or optical signal based on the detection of a desired target species. A device equipped with the following features.

39. The device according to claim 38, wherein the silicon nanostructure forms a deterministic transverse displacement array for particle separation, and an increase in particle concentration improves the sensor signal-to-noise ratio.

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