Synchronization of RF pulsed scheme and synchronization of sensor data acquisition

Abstract

A system and method for synchronizing a radio frequency (RF) pulsed scheme and sensor data acquisition. [Solution] One method comprises receiving a first set of one or more variable levels and one or more duty cycles of an RF signal by an RF generator. The method further comprises receiving a synchronization signal having multiple pulses from a pulse controller by an RF generator. The method also comprises generating multiple instances of a first set of states of the RF signal in synchronization with the multiple pulses of the synchronization signal during the clock cycle of the clock signal. Each of the first set of states of the RF signal has a corresponding one of the one or more variable levels of the first set and a corresponding one of the one or more duty cycles of the first set.

Description

Technical Field

[0001] This embodiment relates to a system and method for synchronizing a radio frequency (RF) pulsing scheme and synchronizing sensor data collection.

Background Art

[0002] The description of the background art provided herein is for the purpose of generally presenting the context of the present disclosure. The research by the inventors named at the present time is not admitted as prior art against the present disclosure, whether explicitly or implicitly, in the same manner as the aspects of the description that cannot be separately regarded as prior art at the time of filing within the scope described in this background art section.

[0003] In a plasma tool, multiple radio frequency (RF) generators are used. The RF generators are connected to a plasma chamber via a match. The RF generators generate RF signals and supply the RF signals to the match. The RF signals are combined to output a modified RF signal, which is transmitted to the plasma chamber.

[0004] A substrate is placed in the plasma chamber for processing. A modified signal is supplied together with various gases to process the substrate. It is desirable to process the substrate in a desired manner.

[0005] The embodiments described in the present disclosure arise in this context.

Summary of the Invention

[0006] Embodiments of the present disclosure provide a system, apparatus, method, and computer program for synchronizing a radio frequency (RF) pulsing scheme and synchronizing sensor data collection. It should be understood that this embodiment can be implemented in a number of ways, for example, in a process, apparatus, system, device, or method on a computer-readable medium. Some embodiments are described below.

[0007] In some embodiments of RF pulsation for plasma etching tools, a set of parameter values, such as power values, and the durations of several parameter levels are downloaded to an RF generator. RF pulses are generated by the RF generator according to the power values ​​and durations. Upon receiving or generating a trigger pulse internally, the RF generator emits RF energy at multiple variable levels and durations. The RF generator may receive a number of other parameter values ​​to improve the degree to which the RF power values ​​delivered between variable levels match pre-stored power values.

[0008] When multiple RF generators are present in a plasma system, it is desirable that the RF generators emit RF signals on a synchronized schedule. For example, this can be achieved by providing each RF generator with a logic level synchronization pulse. The logic level synchronization pulse is delivered to the RF generators with the same timing parameters, such as frequency, duty cycle, and phase. To modify the pulsing behavior of the RF generators, the setpoint is updated with respect to the timing and output level of the RF signal pulses. A module controller can be used to perform the setpoint update and transmit the update to the RF generators via the fieldbus. Because the module controller handles so many other real-time control functions of the plasma system, it is difficult for the module controller to update the setpoint precisely on a timescale of less than approximately 0.5 seconds.

[0009] A favorable process exists when the setpoint is updated as frequently as 50 millisecond intervals. For example, to execute the process, an embedded recipe may be downloaded and executed by each RF generator. The recipe, containing extensive specifications for pulse level, width, and the number of pulses emitted, can be downloaded to the RF generators. However, synchronization between stages of these recipes may not occur. That is, a recipe for one RF generator may need to start at a different time than a recipe for another RF generator, or a change in the pulse level of an RF signal generated by one RF generator should be synchronized with a change in the pulse level of another RF signal generated by another RF generator. While synchronization cables could be added between the RF generators corresponding to each desired synchronized change to achieve inter-stage synchronization, this results in a rather complex plasma system that is difficult to configure and program. Furthermore, synchronizing with subsystems such as measurement subsystems for endpoint detection or RF waveform analysis is difficult.

[0010] In one embodiment, a centralized synchronization device for an RF pulsation scheme is described. An example of a centralized synchronization device is a pulse controller. The centralized synchronization device enables repeated changes in pulsation parameter values ​​on a timescale of less than approximately 0.5 seconds. For example, the centralized synchronization device enables changes in pulsation parameter values ​​on a timescale between 0.1 seconds and 0.5 seconds. As another example, the centralized synchronization device enables changes in pulsation parameter values ​​on a timescale between 0.05 seconds and 0.6 seconds.

[0011] In one embodiment, changes to pulsed parameter values ​​are achieved by slave-to-slave direct transfer using an existing control network of the plasma tool, such as a fieldbus. In one embodiment, updates to pulsed parameter values ​​are achieved using a separate high-speed point-to-point communication link, such as an Ethernet cable or a high-speed Ethernet cable, or a system-on-chip to system-on-chip (SoC) direct link. For example, a main SoC is used to implement a pulse controller. The main SoC is directly connected to the RFG controller of an RF generator via a separate high-speed point-to-point communication link, such as a cable or optical fiber. The RFG controller includes at least one of a communication controller, a digital signal processor (DSP), one or more power controllers, and one or more frequency controllers. The cable or optical fiber is the transfer medium for transferring updates to pulsed parameter values. A protocol is applied by the pulse controller to transfer the updated values ​​to the RFG controller. Communication of pulsed parameter values ​​is sometimes referred to herein as inter-central processing unit (CPU) communication. In another example, the pulse controller is directly connected to the match controller or the sensor system controller via a separate high-speed point-to-point communication link, such as a cable or optical fiber. The match controller includes at least one communication controller and a processor. Similarly, the sensor system controller also includes at least one communication controller and a processor. In this example, a protocol is applied by the pulse controller to transfer updates to the match or sensor system controller.

[0012] In one embodiment, the systems and methods described herein include a measurement function that parameterizes an RF signal and compares the RF signal observed at a point in the RF delivery system of a plasma tool with a pre-stored parameter value. For example, the envelope or pulse of the measured signal is compared with a pre-stored envelope. In this example, the results of the comparison may be used to update control parameters to optimize the agreement between the measured signal and the pre-stored parameter value.

[0013] In one embodiment, a pulse controller, which is a centralized controller separate from the module controller, is used to transmit setpoint changes to the RF generator and to send a separate synchronization pulse train to the RF generator for synchronization. The setpoint changes to the RF generator are classified into two classes. The first class includes step-by-step parameter values ​​that are programmed in the system recipe editor and transmitted via the fieldbus at the start of each step, and are not changed during the recipe step. The second class includes high-speed information, such as a smaller number of other parameter values, which are transmitted via the data channel with lower latency.

[0014] In the case of an RF generator, the lower latency data channels include the variable level and duration of the RF signal pulses emitted when a synchronization signal is received. The RF generator does not use higher-level downloaded recipes. The latency of these lower latency data channels allows setpoint changes to be transmitted and actuated in a time shorter than the minimum pulse repetition time. For example, a pulse repetition rate of 10 milliseconds (ms) results in a latency of less than 10 ms. This lower latency is achieved, in one embodiment, by transmitting data over a fieldbus using slave-to-slave technology, and by optimizations made within the RF generator to enable lower latency. In some cases, instead of slave-to-slave technology, completely separate data transmissions, such as point-to-point communication, are provided for high-speed information. For example, the data connection uses a protocol over a 1 gigabit / s (Gbps) Ethernet physical link in a point-to-point configuration. Other more customized embodiments using direct point-to-point links between processors can achieve low latency, such as less than 10 microseconds (μs) for connections up to 25 Gbps.

[0015] While the term "RF generator" is used herein for convenience, it should be noted that any subsystem using updates synchronized with an embedded recipe can be updated in a similar manner. In one embodiment, synchronization of individual pulses is achieved by emitting pulse trains to each of a plurality of subsystems for subsystem synchronization. For example, an emission spectrometer subsystem receives a synchronization pulse that triggers the acquisition of optical data when the synchronization pulse is at a specific logic level. Other subsystems use the rising or falling edge of the synchronization pulse signal to trigger a series of operations. Other subsystems to be synchronized include RF matching units such as impedance matching circuits. Setpoint changes and pulse trains are emitted by the pulse controller on a schedule derived from a recipe transmitted to the pulse controller via the fieldbus. This recipe is modified in conjunction with a new system recipe step.

[0016] In one embodiment, the pulse controller includes an instrument for evaluating the RF signal reaching a physically meaningful point in the plasma tool, such as an RF match output or a location near the wafer plane. An analog-to-digital converter is used to measure either the RF voltage or the RF voltage envelope at that point. The pulse controller can determine in real time whether a match has been achieved between the measured criterion and a pre-stored criterion. These criteria can be used to modify the parameters of the plasma tool. For example, the settings of the RF match network components or the RF generator frequency can be modified to achieve a match, for example, by using a feedback loop or an artificial intelligence system. The match can also be applied to other Equipment Intelligence systems. Other functions related to human-level debugging of the plasma tool, such as RF voltage capture, can also be included for display.

[0017] In one embodiment, a method is described. The method includes receiving a first set of one or more variable levels and one or more duty cycles of an RF signal by an RF generator. The method further includes receiving a synchronization signal having multiple pulses from a pulse controller by the RF generator. The method also includes generating multiple instances of a first set of states of the RF signal in synchronization with the multiple pulses of the synchronization signal during the clock cycle of the clock signal. Each of the first set of states of the RF signal has a corresponding one of the one or more variable levels of the first set and a corresponding one of the one or more duty cycles of the first set.

[0018] In one embodiment, a pulse controller is described. The pulse controller includes a processor configured to transmit a first set of one or more variable levels and one or more duty cycles of an RF signal to an RF generator. The processor is configured to transmit a synchronization signal having multiple pulses to the RF generator. The transmission of the synchronization signal to the RF generator enables the RF generator to generate multiple instances of the first multiple states of the RF signal in synchronization with the multiple pulses of the synchronization signal during the clock cycle of the clock signal. Each of the first multiple states of the RF signal has a corresponding one of the first set of variable levels and a corresponding one of the first set of duty cycles. The pulse controller further includes a memory device connected to the processor.

[0019] In one embodiment, a method is described. The method comprises measuring sensor data by a sensor in a sensor system, the method further comprises receiving a synchronization signal having multiple pulses by the sensor system, the method also comprises collecting portions of the sensor data by the sensor system in synchronization with the multiple pulses of the synchronization signal during the clock cycle of a clock signal, the method further comprises transmitting portions of the sensor data to a pulse controller.

[0020] Some of the advantages of the systems and methods described herein include co-locating a centralized synchronization device for pulse synchronization, pulse measurement, and setpoint updates. There is no need to find a way to download a recipe to the RF generator and then synchronize the RF generator. And with shorter and more accurate process steps, detailed pulsed behavior can be programmed. The requirements of the RF generator are reduced, which is also advantageous in terms of cost.

[0021] Other aspects will become apparent from the following detailed description when taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0022] The present disclosure will be best understood by reference to the following description when taken in conjunction with the accompanying drawings.

[0023] [Figure 1] FIG. 1 is a diagram of one embodiment of a system for illustrating the use of Ethernet for Control Automation Technology (EtherCAT) and synchronization signals for synchronization of RF signals.

[0024] [Figure 2A] FIG. 2A shows a graph for illustrating a first synchronization signal transmitted to a transformer-coupled plasma (TCP) generator.

[0025] [Figure 2B] FIG. 2B shows a graph of another synchronization signal provided to a first bias generator.

[0026] [Figure 2C] FIG. 2C shows a graph of yet another synchronization signal provided to a second bias generator.

[0027] [Figure 2D] FIG. 2D shows a graph for illustrating variables of an RF signal generated by a TCP generator in synchronization with the synchronization signal of FIG. 2A.

[0028] [Figure 2E] Figure 2E shows a graph illustrating the variables of the RF signal generated by the first bias generator in synchronization with the synchronization signal in Figure 2B.

[0029] [Figure 2F] Figure 2F shows a graph illustrating the variables of the RF signal generated by the second bias generator in synchronization with the synchronization signal in Figure 2C.

[0030] [Figure 2G] Figure 2G shows a graph illustrating the variables of the RF signal generated by the first bias generator in synchronization with the synchronization signal in Figure 2B.

[0031] [Figure 3] Figure 3 illustrates one embodiment of the system for using an Ethernet cable to transfer information about variable levels and duty cycles, and information about a portion of the cycle of a master clock signal from which multiple states of the RF signal are generated.

[0032] [Figure 4] Figure 4 illustrates one embodiment of the system to illustrate the use of EtherCAT to sense data from sensors in TCP matches and sensors in bias matches.

[0033] [Figure 5A] Figure 5A shows a graph illustrating the plot of plasma intensity versus time.

[0034] [Figure 5B] Figure 5B shows a graph illustrating the relationship between synchronization signal and time.

[0035] [Figure 6A] Figure 6A shows a graph illustrating a voltage-to-time plot.

[0036] [Figure 6B] Figure 6B shows a graph illustrating the relationship between synchronization signal and time.

[0037] [Figure 6C] Figure 6C shows a graph illustrating a voltage-to-time plot.

[0038] [Figure 6D] Figure 6D shows a graph illustrating the relationship between synchronization signal and time.

[0039] [Figure 7] Figure 7 illustrates one embodiment of the system, illustrating the use of a single EtherCAT train instead of multiple EtherCAT trains to transfer pulsed preset signals from the module controller to the bias match.

[0040] [Figure 8] Figure 8 illustrates one embodiment of the system to show that sensor data is transmitted from the sensor to the pulse controller via an Ethernet cable, rather than via an EtherCAT train.

[0041] [Figure 9] Figure 9 is a diagram illustrating one embodiment of an RF generator, illustrating the components of the RF generator.

[0042] [Figure 10] Figure 10 shows an embodiment of a controller, which is an example of a pulse controller or a module controller.

[0043] [Figure 11] Figure 11 shows an embodiment of a match, which is an example of a TCP match or bias match.

[0044] [Figure 12]Figure 12 shows one embodiment of the sensor system.

[0045] [Figure 13] Figure 13 shows a graph illustrating a clock signal. [Modes for carrying out the invention]

[0046] The following embodiments describe systems and methods for synchronizing radio frequency (RF) pulsed schemes and sensor data acquisition. It will be apparent that these embodiments can be implemented without some or all of these specific details. In other examples, well-known process operations are not described in detail so as not to unnecessarily obscure these embodiments.

[0047] Figure 1 shows one embodiment of System 100 illustrating the use of Ethernet for Control Automation Technology (EtherCAT) and synchronization signals for synchronizing RF signals 102, 104, and 106 generated by multiple RF generators, including a transformer-controlled plasma (TCP) generator, bias generator 1, and bias generator 2. System 100 includes a module controller, pulse controller, TCP generator, bias generator 1, bias generator 2, TCP match, bias match, and plasma chamber 108.

[0048] As used herein, an example of a controller includes a processor and a memory device. The processor is connected to the memory device. Another example of a controller includes an application-specific integrated circuit (ASIC) and a programmable logic device (PLD). Yet another example of a controller includes multiple processors and multiple memory devices. The processor is connected to the memory device. As used herein, the terms processor, microprocessor, and central processing unit (CPU) are used interchangeably.

[0049] Furthermore, as used herein, RF generators operate at frequencies of 400 kilohertz (kHz), 2 megahertz (MHz), 13.56 MHz, 27 MHz, or 60 MHz. For example, the TCP generator operates at a frequency of 13.56 MHz, bias generator 1 operates at a frequency of 400 kHz, and bias generator 2 operates at a frequency of 60 MHz. As another example, the TCP generator operates at a frequency of 27 MHz, bias generator 1 operates at a frequency of 2 MHz, and bias generator 2 operates at a frequency of 27 MHz.

[0050] An example of an impedance matching network used herein is an impedance matching circuit having a network of circuit components such as inductors, resistors, and capacitors. For example, an impedance matching network has one or more series circuits and one or more shunts. Each series circuit includes one or more inductors and one or more capacitors, and the one or more inductors and one or more capacitors are connected in series with each other. Similarly, each shunt includes one or more inductors and one or more capacitors connected in series with each other. One of the one or more inductors and one or more capacitors in a shunt is connected to ground potential. Each of the one or more shunts is connected to the corresponding one of the one or more series circuits. The terms impedance matching network, impedance matching circuit, impedance matching housing, match housing, match enclosure, and match are used synonymously herein.

[0051] The plasma chamber 108 includes a substrate support 110. An example of the substrate support 110 is a chuck such as an electrostatic chuck (ESC). For example, the chuck includes a metal base and a dielectric layer on the metal base. A substrate S, such as a semiconductor wafer, is placed on the upper surface of the substrate support 110 and processed in the plasma chamber 108. The substrate support 110 includes a lower electrode made of a metal such as aluminum or an aluminum alloy. The lower electrode is embedded in the dielectric layer of the chuck. The plasma chamber 108 further includes a TCP coil 112 and a dielectric window 114. The TCP coil 112 is placed on the dielectric window 114, and a gap is formed between the dielectric window 114 and the substrate support 110.

[0052] The module controller is connected to the pulse controller via communication cable 116, and the pulse controller is connected to the TCP generator via communication cable 118. An example of a communication cable used herein is an Ethernet cable. An example of an Ethernet cable used herein is a twisted-pair cable. For example, the Ethernet cable is a 100BASE-TX® or 100BASE-T4® cable capable of transferring data at speeds of 100 megabits per second (Mbps) or higher. Another example is a Category 8 cable capable of transferring data at transfer speeds of up to 40 gigabits per second (Gbps).

[0053] Furthermore, the pulse controller is connected to the TCP generator via transfer cable 122, to the bias generator 1 via transfer cable 122, and to the bias generator 2 via transfer cable 124. An example of a transfer cable used herein is a coaxial cable. For example, the transfer cable is used for data transfer via serial, parallel, or Universal Serial Bus (USB) protocols. The TCP generator is connected to the bias generator 1 via communication cable 126, and the bias generator 1 is connected to the bias generator 2 via communication cable 128.

[0054] Furthermore, the output O1 of the TCP generator is connected to the input I1 of the TCP match via the RF cable 130, and the output O2 of the TCP match is connected to the first end of the TCP coil 112 via the RF transmission line 132. As an example, the RF transmission line 132 includes an RF rod, an insulating material, and an RF sheath. The insulating material is placed between the RF rod and the RF sheath. The insulating material surrounds the RF rod, and the RF sheath surrounds the insulating material.

[0055] The second opposite end of the TCP coil is connected to the earth potential or ground connection. The output O3 of bias generator 1 is connected to the input I2 of bias match via RF cable 134. The output O4 of bias generator 2 is connected to the input I3 of bias match via RF cable 136. The output O5 of bias match is connected to the lower electrode of substrate support 110 via RF transmission line 139. As an example, RF transmission line 139 includes an RF rod, an insulating material, and an RF sheath. The insulating material is placed between the RF rod and the RF sheath. The insulating material of RF transmission line 139 surrounds the RF rod of RF transmission line 139, and the RF sheath of RF transmission line 139 surrounds the insulating material. RF transmission line 139 further includes one or more RF straps and an RF cylinder. The RF rod of RF transmission line 139 is connected to the output O5 of bias match. One or more RF straps of the RF transmission line 139 connect an RF rod to an RF cylinder, and the RF cylinder is connected to the lower electrode of the substrate support 110.

[0056] The module controller generates a pulsed preset signal 138 and transmits it to the pulse controller via the communication cable 116. The pulsed preset signal 138 is an EtherCAT train. For example, the pulsed preset signal 138 includes information about the variable levels and duty cycles of RF signals 102, 104, and 106. The information about the variable levels includes the variable levels for each state of RF signal 102, the variable levels for each state of RF signal 104, and the variable levels for each state of RF signal 106. For example, the variable is power or frequency. Also, in this example, the information about the duty cycle includes the duty cycle for each state of the variable in RF signal 102, the duty cycle for each state of the variable in RF signal 104, and the duty cycle for each state of the variable in RF signal 106. For example, the duty cycle of the RF signals provides the time interval or period during which each state of the variable in the RF signals is generated.

[0057] The pulse controller receives the pulsed preset signal 138 from the module controller and transmits the pulsed preset signal 138 to the TCP generator via the communication cable 118. The TCP generator receives the pulsed preset signal 138, extracts information regarding the variable levels and duty cycle for generating the RF signal 102 from the pulsed preset signal 138, and after extracting the information, transmits the pulsed preset signal 138 to the bias generator 1 via the communication cable 126. The TCP generator also stores the information regarding the variable levels and duty cycle for generating the RF signal 102 in one or more memory devices of the TCP generator.

[0058] The bias generator 1 receives the pulsed preset signal 138, analyzes the pulsed preset signal 138, and obtains information regarding the variable levels and duty cycle for generating the RF signal 104. The bias generator 1 also stores the information regarding the variable levels and duty cycle for generating the RF signal 104 in one or more memory devices of the bias generator 1. After obtaining the information, the bias generator 1 transmits the pulsed preset signal 138 to the bias generator 2 via the communication cable 128.

[0059] The bias generator 2 receives the pulsed preset signal 138, analyzes the pulsed preset signal 138, and extracts information regarding the variable levels and duty cycle for generating the RF signal 106 from the pulsed preset signal 138. The bias generator 2 stores the information regarding the variable levels and duty cycle for generating the RF signal 106 in one or more memory devices of the bias generator 2. After extracting the information, the bias generator 2 sends the pulsed preset signal 138 back to the bias generator 1 via the communication cable 128.

[0060] Bias generator 1 receives a pulsed preset signal 138 from bias generator 2 and sends the pulsed preset signal 138 back to TCP generator via communication cable 126. TCP generator receives a pulsed preset signal 138 from bias generator 1 and sends the pulsed preset signal 138 back to pulse controller via communication cable 118. Pulse controller receives a pulsed preset signal 138 from TCP generator and sends the pulsed preset signal 138 back to module controller.

[0061] The pulse controller also generates a master clock signal 141 and transmits it to the TCP generator via the transfer cable 120. For example, the pulse controller includes a master clock generator such as a clock source or digital clock, and generates a digital clock signal. The digital clock signal is pulsed between logic levels 1 and 0 with a 50% duty cycle. The pulse controller also transmits the master clock signal 141 to bias generator 1 via transfer cable 122 and to bias generator 2 via transfer cable 124.

[0062] The pulse controller generates a synchronization signal 140 and transmits it to the TCP generator via the transfer cable 120. An example of a synchronization signal used herein is a transistor-to-transistor logic (TTL) signal. The pulse controller also generates another synchronization signal 142 and transmits it to the bias generator 1 via the transfer cable 122. The pulse controller generates yet another synchronization signal 144 and transmits it to the bias generator 2 via the transfer cable 124. Synchronization signal 140 is labeled as sync1 in Figure 1, synchronization signal 142 is labeled as sync2 in Figure 1, and synchronization signal 144 is labeled as sync3 in Figure 1.

[0063] As an example, the synchronization signal 144 includes one or more pulses having a different frequency from one or more pulses of the synchronization signal 142. For example, the synchronization signal 144 has two consecutive pulses spaced further apart from each other by a larger time interval compared to two consecutive pulses of the synchronization signal 142. Similarly, as another example, the synchronization signal 146 includes one or more pulses having a different frequency from one or more pulses of the synchronization signal 142. Also, as yet another example, the synchronization signal 146 includes one or more pulses having a different frequency from one or more pulses of the synchronization signal 144.

[0064] Furthermore, as an example, synchronization signal 144 may contain a different number of pulses compared to synchronization signal 142, for example, more or fewer pulses. For example, within one time interval, synchronization signal 144 may contain 10 pulses and synchronization signal 142 may contain 4 pulses. Another example is that within one time interval, synchronization signal 144 may contain 5 pulses and synchronization signal 142 may contain 10 pulses. Similarly, as an example, synchronization signal 144 may contain a different number of pulses compared to synchronization signal 140, for example, more or fewer pulses. Also, as an example, synchronization signal 144 may contain a different number of pulses compared to synchronization signal 142, for example, more or fewer pulses.

[0065] As an example, after information regarding the variable level and duty cycle of RF signal 102 is stored in one or more memory devices of the TCP generator, information regarding the variable level and duty cycle of RF signal 104 is stored in one or more memory devices of bias generator 1, and information regarding the variable level and duty cycle of RF signal 106 is stored in one or more memory devices of bias generator 2, synchronization signals 140, 142, and 144 are generated and transmitted.

[0066] As an example, the pulse controller transmits synchronization signals 140, 142, and 144 in synchronization with the clock cycle of the master clock signal 141. Each of the synchronization signals 140, 142, and 144 has a series of pulses that are repeated during each cycle of the master clock signal 141. In this example, the pulsed preset signal 138 contains information about a portion of the cycle of the master clock signal 141 where multiple states of the RF signal are generated. For example, the pulsed preset signal 138 includes a first time interval during cycle 1 of the master clock signal 141 where a first series of pulses of the RF signal 102 is generated by the TCP generator. During cycle 1, each pulse in the first series transitions between a first variable level and a second variable level. The first variable level is different from the second variable level. The pulsed preset signal 138 also includes a second time interval during cycle 1 of the master clock signal where a second series of pulses of the RF signal 102 is generated by the TCP generator. During cycle 1, each pulse of the second series transitions between a third variable level and a second variable level. The third variable level is different from the second and first variable levels. The first time interval is an example of the first subcycle of cycle 1 of the master clock signal 141, and the second time interval is an example of the second subcycle of cycle 1 of the master clock signal 141.

[0067] As another example, the pulsed preset signal 138 includes information regarding the pulse count of the synchronization signal 140. The pulse count information includes a first count of the number of pulses of the synchronization signal 140 during cycle 1 of the master clock signal 141, in which a first series of pulses of the RF signal 102 transitions between a first variable level and a second variable level. The count information also includes a second count of the number of pulses of the synchronization signal 140 during cycle 1 of the master clock signal 141, in which a second series of pulses of the RF signal 102 transitions between a third variable level and a second variable level. The number of pulses for the first count is generated during a first time interval, which is an example of a first subcycle of cycle 1 of the master clock signal 141. The number of pulses for the second count is generated during a second time interval, which is an example of a second subcycle of cycle 1 of the master clock signal 141. The TCP generator includes a counter that determines whether a first count has been exceeded. If so, it applies the second and third variable levels instead of the first and second variable levels to generate the RF signal 102. The counter is connected to the TCP generator's digital signal processor.

[0068] The TCP generator receives the synchronization signal 140 and, in synchronization with the synchronization signal 140, generates an RF signal 102 having information about the variable levels and duty cycles of each state of the RF signal 102. For example, a first instance of a set of one or more states of the RF signal 102 is generated in response to the reception of a first pulse of the synchronization signal 140, and a second instance of a set of one or more states of the RF signal 102 is generated in response to a second pulse of the synchronization signal 140. The second pulse is continuous with the first pulse in that there are no other pulses between the first and second pulses. For example, the set of states includes a first state and a second state. The first state has a first variable level and a first duty cycle, and the second state has a second variable level and a second duty cycle. The information about the variable levels and duty cycles of the RF signal 102 includes the first variable level, the first duty cycle, the second variable level, and the second duty cycle.

[0069] Similarly, bias generator 1 receives synchronization signal 142 and generates RF signal 104 containing information about the variable levels and duty cycles of each state of RF signal 104 in synchronization with synchronization signal 142. Bias generator 2 also receives synchronization signal 144 and generates RF signal 106 containing information about the variable levels and duty cycles of each state of RF signal 106 in synchronization with synchronization signal 144.

[0070] RF signal 102 is provided at output O1 and transmitted to the TCP match input I1 via RF cable 130. The TCP match corrects the impedance of RF signal 102 by matching the impedance of the load connected to output O2 with the impedance of the source connected to input I1. Examples of sources connected to input I1 include RF cable 130 and the TCP generator. Examples of loads connected to output O2 include RF transmission line 132 and the plasma chamber 108. Once the impedance of RF signal 102 is corrected, a corrected RF signal 146 is provided at output O2 of the TCP match. The corrected RF signal 144 is supplied to the TCP coil 112 via RF transmission line 132.

[0071] Furthermore, RF signal 104 is provided at output O3 of bias generator 1 and transmitted to input I2 of bias match via RF cable 134. In addition, RF signal 106 is provided at output O4 of bias generator 2 and transmitted to input I3 of bias match via RF cable 136. The bias match includes a first branch circuit and a second branch circuit. The first branch circuit includes one or more series circuits, one or more shunts, or a combination thereof. The second branch circuit also includes one or more series circuits, one or more shunts, or a combination thereof.

[0072] When the RF signal 104 is transmitted through the first branch circuit of the bias match, the first branch circuit corrects the impedance of the RF signal 104 by matching the impedance of the load connected to the output O5 of the bias match with the impedance of the source connected to the input I2 of the bias match. An example of a source connected to input I2 is the RF cable 134 and the bias generator 1. An example of a load connected to output O5 is the RF transmission line 139 and the plasma chamber 108. Once the impedance of the RF signal 104 is corrected, the first corrected RF signal is output from the first branch circuit.

[0073] Similarly, when the RF signal 106 is transmitted through the second branch circuit of the bias match, the second branch circuit corrects the impedance of the RF signal 106 by matching the impedance of the load connected to the bias match output O5 with the impedance of the source connected to the bias match input I3. Examples of sources connected to input I3 are the RF cable 136 and the bias generator 2. Once the impedance of the RF signal 106 is corrected, the second corrected RF signal is output from the second branch circuit.

[0074] The first and second modified RF signals are combined within a bias match, for example, by being added together, to provide a combined RF signal 148 at output O5. The combined RF signal 148 is transferred to the lower electrode of the substrate support 110 via the RF transmission line 139.

[0075] Furthermore, one or more process gases, such as an oxygen-containing gas and a fluorine-containing gas, are supplied to the gap between the substrate support 110 and the dielectric window 114. Once one or more process gases, a modified RF signal 146, and a combined RF signal 148 are supplied to the gap in the plasma chamber 108, the plasma is struck or maintained within the plasma chamber 108. The plasma is used to process the substrate S. Examples of processing the substrate S include depositing one or more materials on the substrate S, etching the substrate S, cleaning the substrate S, polishing the substrate S, sputtering the substrate S, or a combination thereof.

[0076] By providing synchronization signals 140, 142, and 144, it becomes unnecessary to store information about the synchronization signals. For example, it is not necessary to store the frequency at which the state of RF signal 102 is repeated in one or more memory devices of the TCP generator. As another example, it is not necessary to store the frequency at which the state of RF signal 104 is repeated in one or more memory devices of bias generator 1. Also, as yet another example, it is not necessary to store the frequency at which the state of RF signal 106 is repeated in one or more memory devices of bias generator 2.

[0077] In one embodiment, in addition to bias generators 1 and 2, a third bias generator is connected to the third input of the bias match.

[0078] In one embodiment, in addition to the TCP generator, a second TCP generator is connected to the second input of the TCP match.

[0079] In one embodiment, in addition to the TCP generator, a second TCP generator is connected to the second input of the TCP match, and a third TCP generator is connected to the third input of the TCP match.

[0080] In one embodiment, instead of the pulse controller generating the master clock signal 141, the module controller generates the master clock signal 141 and transmits it to the pulse controller via a transfer cable. The transfer cable connects the module controller to the pulse controller. The pulse controller generates synchronization signals 140, 142, and 144 in synchronization with the master clock signal 141 received from the module controller.

[0081] In one embodiment, each RF generator, such as a TCP generator, bias generator 1, and bias generator 2, has a clock source that generates a clock signal including cycles 1 and 2. For example, the TCP generator has a clock source that generates a clock signal having clock cycles 1 and 2, bias generator 1 has a clock source that generates a clock signal having clock cycles 1 and 2, and bias generator 2 has a clock source that generates a clock signal having clock cycles 1 and 2. The clock signals of the clock sources of the TCP generator, bias generator 1, and bias generator 2 are synchronized with a master clock signal 141. For example, the clock sources of the TCP generator, bias generator 1, and bias generator 2 receive the master clock signal 141 and generate a clock signal. The clock signal transitions from logic level 0 to logic level 1 at the same time that the master clock signal 141 pulses from logic level 0 to logic level 1, and transitions from logic level 1 to logic level 0 at the same time that the master clock signal 141 pulses from logic level 1 to logic level 0. In this embodiment, each component of the RF generator receives a clock signal generated in synchronization with the master clock signal 141 and operates in synchronization with the clock signal. For example, the TCP generator controller receives a clock signal from the TCP generator's clock source and controls the other components of the TCP generator to generate the RF signal 102 in synchronization with the clock signal.

[0082] In one embodiment, any synchronization signal described herein is generated by the pulse controller after the pulse controller receives a trigger signal from the module controller via a transfer cable. The transfer cable connects the pulse controller to the module controller. The trigger signal includes a single pulse for executing a recipe, such as variable levels and duty cycles within a pulsed preset signal 138.

[0083] In one embodiment, the pulsed preset signal 138 includes multiple schedules for generating multiple synchronization signals, such as synchronization signals 140, 142, and 144. For example, the schedule includes information for generating the synchronization signals. For example, the schedule includes one or more frequencies for generating pulses of the synchronization signals. The pulse controller generates the synchronization signals according to the schedule. For example, synchronization signal 140 is generated according to a first schedule, and synchronization signal 142 is generated according to a second schedule.

[0084] In one embodiment, the master clock signal 141 is transmitted from the pulse controller to the TCP generator via a transfer cable different from the transfer cable 120. The master clock signal 141 is also transmitted from the pulse controller to the bias generator 1 via a transfer cable different from the transfer cable 122, and from the pulse controller to the bias generator 2 via a transfer cable different from the transfer cable 124.

[0085] Figure 2A shows graph 200 illustrating the synchronization signal 202, which is an example of the synchronization signal 140 (Figure 1) sent to the TCP generator. Graph 200 plots the logic level of the synchronization signal 202 against time t. The logic level of the synchronization signal 202 is plotted on the y-axis, and time t is plotted on the x-axis.

[0086] Time t is divided into multiple time intervals. For example, time t is divided into a first time interval between time t0 and time t1, a second time interval between time t1 and time t2, a third time interval between time t2 and time t3, and so on. Note that the first time interval is equal to the second time interval, and the second time interval is equal to the third time interval. Additional times t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t19, t20, t21, t22, t23, t24, t25, t26, t27, t28, t29, and t30 are shown in Figure 2A.

[0087] The synchronization signal 202 becomes pulsed at time t0, resulting in pulse 202-1. For example, the synchronization signal 202 is at logic level 1 at time t0, remains at logic level 1 from time t0 to time t0.5, and time t0.5 is half the time interval between time t0 and time t1. Also, the synchronization signal 202 transitions from logic level 1 to logic level 0 at time t0.5, remains at logic level t0.5 from time t0.5 to time t2, and results in pulse 202-1.

[0088] Similarly, the synchronization signal 202 becomes pulsed at times t2, t4, ..., t16, resulting in multiple pulses 202-2, 202-3, 202-4, 202-5, 202-6, 202-7, and 202-8. As an example, the time interval between the generation of two consecutive pulses of the synchronization signal 202 is less than approximately 0.5 seconds. For example, the time difference between the generation of pulse 202-1 and pulse 202-2 is in the range of 0.05 seconds to 0.6 seconds. As another example, the time difference between the generation of pulse 202-1 and pulse 202-2 is in the range of 0.01 seconds to 0.55 seconds. As yet another example, the time difference between the generation of pulse 202-1 and pulse 202-2 is in the range of 0.005 seconds to 0.6 seconds.

[0089] The eighth pulse 202-8 of the synchronization signal 202 ends at time t16. The synchronization signal 202 remains in a pulsed state from time t16 to t20. For example, the synchronization signal 202 is at logic level 0 between time t14.5 and time t20. Time t14.5 is halfway between time t14 and t15.

[0090] Cycle 1 of the generation of the synchronization signal 202 is generated between times t0 and t20. Cycle 1 of the synchronization signal 202 consists of eight pulses 202-1 through 202-8 of the synchronization signal 202, followed by a pulse-free time interval between times t14.5 and t20.

[0091] During cycle 1 of the master clock signal 141, the synchronization signals 202, 142, and 144 (Figure 1) are divided into multiple subcycles. For example, subcycle 1 of synchronization signals 202, 142, and 144 occurs between time t0 and time t10 of cycle 1. Subcycle 2 of synchronization signals 202, 142, and 144 occurs between time t10 and time t16, and subcycle 3 of synchronization signals 202, 142, and 144 occurs between time t16 and time t20. Similarly to cycle 1, during cycle 2 of the master clock signal 141, each synchronization signal 202, 142, and 144 is divided into multiple subcycles. As an example, during cycle 2, subcycle 1 of synchronization signals 202, 142, and 144 occurs between time t20 and time t30. Cycles 1 and 2 are clock cycles of the master clock signal 141 received from the pulse controller (Figure 1) by the TCP, bias 1, and bias 2 RF generators. Cycle 2 occurs between time t20 and time t40.

[0092] The synchronization signal 202 begins pulsed again at time t20, and repeats eight pulses from time t20, just as eight pulses of the synchronization signal 202 are generated from time t0. For example, the synchronization signal 202 is at logic level 1 at time t20, and remains at that logic level from time t20 to time t20.5, where time t20.5 is halfway between times t20 and t21. Thus, the synchronization signal 202 includes a first series of eight pulses 202-1 to 202-8 and a second series of eight pulses. During cycle 2, the synchronization signal 202 includes eight pulses of the synchronization signal 202, followed by a pulseless time interval between times t34.4 and t40. Time t34.5 is halfway between times t34 and t35. Cycle 2 of the master clock signal 141 is continuous with cycle 1 of the master clock signal 141. For example, there are no other cycles between cycle 1 and cycle 2.

[0093] In one embodiment, instead of eight consecutive pulses, the synchronization signal 202 includes another number of consecutive pulses, such as two or three.

[0094] In one embodiment, instead of being pulsed at a first time interval which is half the period between two consecutive times such as times t0 and t1, each pulse of the synchronization signal described herein is pulsed at a second time interval which is greater than or less than the first time interval. For example, the synchronization signal 202 is pulsed at a second time interval ranging from time t0 to time t0.25, where time t0.25 is at 1 / 4 of the time interval between times t0 and t1. As another example, the synchronization signal 202 is pulsed at a second time interval ranging from time t0 to time t0.75, where time t0.75 is at 3 / 4 of the time interval between times t0 and t1.

[0095] In one embodiment, the pulse frequency of the synchronization signal 202 differs from that illustrated in Figure 2A. For example, instead of occurring at time intervals of two time units, the pulses of the synchronization signal 202 occur at time intervals of four time units. For example, instead of pulse 202-2 occurring at time t2, pulse 202-2 occurs at time t4, pulse 202-3 occurs at time t6, and so on up to time t16. In this example, cycle 1 contains four pulses instead of eight. In this example, a time unit is defined as a time interval between two consecutive times, such as times t0 and t1, or times t1 and t2. The pulse frequency of the synchronization signal 202 is modified by a pulse controller or module controller.

[0096] In one embodiment, each subcycle described herein has a time interval ranging from about 50 milliseconds to about 150 milliseconds. For example, subcycle 1 ranges from 50 milliseconds to 75 milliseconds, subcycle 2 ranges from 45 milliseconds to 160 milliseconds, and subcycle 3 ranges from 55 milliseconds to 140 milliseconds.

[0097] In one embodiment, during each cycle of the master clock signal 141 (Figure 1), there is no change in the one or more process gases supplied to the plasma chamber 108 (Figure 1), and there is no change in the pressure within the plasma chamber 108. For example, the pressure within the plasma chamber 108 and the type of one or more process gases used within the plasma chamber 108 remain the same during cycle 1. In another example, the pressure within the plasma chamber 108 and the type of one or more process gases used within the plasma chamber 108 remain the same during cycle 2. Between cycle 1 and cycle 2, the pressure and / or the type of process gases may change.

[0098] Figure 2B shows graph 204 of another synchronization signal 206, which is an example of the synchronization signal 142 (Figure 1) supplied to the bias generator 1. Graph 204 plots the logic level of the synchronization signal 206 against time t. The logic level of the synchronization signal 206 is plotted on the y-axis, and time t is plotted on the x-axis.

[0099] Synchronization signal 206 is at logic level 0 from time t0 to time t10. Synchronization signal 206 becomes pulsed at time t10, resulting in pulse 206-1. For example, synchronization signal 206 transitions from logic level 0 to logic level 1 at time t10, remains at logic level 1 from time t10 to time t10.5, and time t10.5 is half the time interval between time t10 and time t11. Also, synchronization signal 206 transitions from logic level 1 to logic level 0 at time t10.5, remains at logic level 0 from time t10.5 to time t12, resulting in pulse 206-1.

[0100] Similarly, the synchronization signal 206 pulses at time t12, giving rise to a second pulse 206-2, and pulses at time t14, giving rise to a third pulse 206-3. As an example, the time interval between the generation of two consecutive pulses of the synchronization signal 206 is less than approximately 0.5 seconds. For example, the time difference between the generation of pulse 206-1 and pulse 206-2 is in the range of 0.05 seconds to 0.6 seconds. As another example, the time difference between the generation of pulse 206-1 and pulse 206-2 is in the range of 0.01 seconds to 0.55 seconds. As yet another example, the time difference between the generation of pulse 206-1 and pulse 206-2 is in the range of 0.005 seconds to 0.6 seconds.

[0101] The third pulse 206-3 of the synchronization signal 206 ends at time t16. The synchronization signal 206 remains in a pulsed state from time t16 to time t30. For example, the synchronization signal 206 is at logic level 0 between time t16 and time t30.

[0102] Cycle 1 of the generation of the synchronization signal 206 is generated between times t0 and t20. Cycle 1 of the synchronization signal 206 consists of three pulses of the synchronization signal 206 that follow a pulseless time interval between times t0 and t10.

[0103] The synchronization signal 206 begins a pulsed state again at time t30, and repeats three pulses from time t30, just as three pulses of the synchronization signal 206 are generated from time t10. For example, the synchronization signal 206 is at logic level 1 at time t30, and remains at that logic level from time t30 to time t30.5, where time t30.5 is half the time interval between time t30 and time t31. Thus, the synchronization signal 206 includes a first series of three pulses and a second series of three pulses. During cycle 2 of the master clock signal 141, the synchronization signal 206 includes three pulses of the synchronization signal 202 that follow a pulseless time interval between times t20 and t30.

[0104] In one embodiment, instead of three consecutive pulses, the synchronization signal 206 includes another number of consecutive pulses, such as two or five.

[0105] In one embodiment, the pulse generation frequency of the synchronization signal 206 differs from that illustrated in Figure 2B. For example, instead of occurring at time intervals of two time units, the pulses of the synchronization signal 206 occur at time intervals of three time units. For example, instead of pulse 206-2 occurring at time t12, pulse 206-2 occurs at time t13 and pulse 206-3 occurs at time t16. During cycle 1 of the master clock signal 141, there are no pulses after time t16.5. Time t16.5 is halfway between times t16 and t17. In this example, cycle 1 includes three pulses of the synchronization signal 206. In this example, a time unit is defined as a time interval between two consecutive times, such as times t0 and t1, or times t1 and t2. The pulse generation frequency of the synchronization signal 206 is modified by a pulse controller or module controller.

[0106] Figure 2C shows graph 208 of another synchronization signal 210, which is an example of the synchronization signal 144 (Figure 1) provided to the bias generator 2. Graph 208 plots the logic level of the synchronization signal 210 against time t. The logic level of the synchronization signal 210 is plotted on the y-axis, and time t is plotted on the x-axis.

[0107] Synchronization signal 210, like synchronization signal 206, becomes pulsed, resulting in multiple pulses 210-1, 210-2, and 210-3 during cycle 1. For example, synchronization signal 210 is at logic level 0 from time t0 to time t10. Synchronization signal 210 becomes pulsed at time t10, resulting in pulse 210-1. For example, synchronization signal 210 transitions from logic level 0 to logic level 1 at time t10, and remains at logic level 1 from time t10 to time t10.5. Also, synchronization signal 210 transitions from logic level 1 to logic level 0 at time t10.5, and remains at logic level t10.5 from time t10.5 to time t12, resulting in pulse 210-1. Similarly, synchronization signal 210 becomes pulsed at time t12, resulting in pulse 210-2, and becomes pulsed at time t14, resulting in pulse 210-3. The synchronization signal 210 stops being pulsed at time t16. The synchronization signal 210 becomes pulsed during cycle 2, just as it was during cycle 1.

[0108] In one embodiment, the synchronization signal 210 is different from the synchronization signal 206 (Figure 2B). For example, instead of three consecutive pulses, the synchronization signal 210 includes one or another number of consecutive pulses, such as six.

[0109] In one embodiment, the pulse generation frequency of the synchronization signal 210 differs from that illustrated in Figure 2C. For example, instead of occurring at time intervals of two time units, the pulses of the synchronization signal 206 occur at time intervals of 2.5 time units. For example, instead of pulse 210-2 occurring at time t12, pulse 210-2 occurs at time t12.5 and pulse 212-3 occurs at time t15. Time t12.5 is halfway between times t12 and t13. During cycle 1 of the master clock signal 141, there are no pulses after time t15. In this example, cycle 1 contains three pulses. In this example, a time unit is defined as a time interval between two consecutive times, such as times t0 and t1, or times t1 and t2. The pulse generation frequency of the synchronization signal 210 is modified by a pulse controller or module controller.

[0110] Figure 2D shows graph 212 illustrating the variables 216 of the RF signal 102 (Figure 1) generated by the TCP generator in synchronization with the synchronization signal 202 (Figure 2A). Graph 212 plots the multiple variable levels of the RF signal 102 against time t.

[0111] Each variable level of an RF signal corresponds to a state of the RF signal. For example, the first variable level is defined as the first state, and the second variable level is defined as the second state.

[0112] As an example, the variable levels used herein include those of an RF signal that are at least one value of a variable in the RF signal. For example, a first variable level may have multiple values, and a second variable level may also have multiple values. The values ​​of the first variable level do not include the values ​​of the second variable level. To illustrate further, the minimum value of all values ​​in the first variable level is greater than the maximum value of all values ​​in the second variable level, such that the first variable level is greater than the second variable level. As another example, the variable level of an RF signal is the envelope of the RF signal. For example, the variable level is the maximum amplitude of the RF signal, as the RF signal pulses from maximum amplitude to minimum amplitude.

[0113] The pulsation of RF signal 102 is synchronized with the pulsation of synchronization signal 202. For example, each pulse of RF signal 102 is generated in response to the reception of a pulse of synchronization signal 102. For example, when pulse 202-1 of synchronization signal 202 (Figure 2A) is received by the TCP generator, pulse 216-1 of variable 216 is generated by the TCP generator. When pulse 202-1 of synchronization signal 202 is received by the TCP generator, the TCP generator becomes capable of generating pulse 216-1. For example, variable 216 of RF signal 102 has variable level V3 at time t0 and remains at variable level V3 from time t0 to t1. Variable 216 transitions from variable level V3 to variable level V0 at time t1. Variable 216 remains at variable level V0 from time t1 to time t2, resulting in pulse 216-1. As another example, at time t0 when pulse 202-1 transitions from logic level 0 to logic level 1, pulse 216-1 transitions from variable level V0 to variable level V3. Pulse 216-1 has a first instance of states S1 and S0 of variable 216 of RF signal 102.

[0114] Similarly, additional pulses 216-2, 216-3, 216-4, and 216-5 of variable 216 are generated. The additional pulses 216-3 through 216-5, having variable level V3, are generated by the TCP generator in synchronization with pulses 202-2 through 202-5 (Figure 2A). For example, pulse 216-2 is generated in synchronization with pulse 202-2, pulse 216-3 is generated in synchronization with pulse 202-3, and so on, until pulse 216-5 is generated in synchronization with pulse 202-5. As another example, at time t2 when pulse 202-2 (Figure 2A) transitions from logical level 0 to logical level 1, pulse 216-2 transitions from variable level V0 to variable level V3. Pulse 216-2 has a second instance of states S1 and S0 of the variable 216 of RF signal 102, pulse 216-3 has a third instance of states S1 and S0 of the variable 216 of RF signal 102, and so on, until pulse 216-5 has a fifth instance of states S1 and S0 of the variable 216.

[0115] Note that variable levels V0 and V3 are examples of information regarding variable levels received within the pulsed preset signal 138 (Figure 1). Also, the duty cycle of each pulse 216-1 to 216-5 is an example of information regarding the duty cycle received within the pulsed preset signal 138. For example, the duty cycle of each pulse 216-1 to 216-5 is 50%. For example, the duty cycle of each pulse 216-1 to 216-5 is the time interval during which the pulse has variable level V3.

[0116] Variable level V3 is greater than variable level V0 and is referred to herein as state S1 of variable 216. Variable level V0 is referred to herein as state S0 of variable 216.

[0117] As another example, pulses 216-6, 216-7, and 216-8 of variable 216 are generated in synchronization with pulses 202-6 to 202-8 of the synchronization signal 202 (Figure 2A). In this example, when pulse 202-6 (Figure 2A) of the synchronization signal 102 is received by the TCP generator, pulse 216-6 of variable 216 is generated by the TCP generator. For example, variable 216 of RF signal 102 transitions from variable level V0 to variable level V4 at time t10 and remains at variable level V4 from time t10 to time t11. Variable 216 transitions from variable level V4 to variable level V0 at time t11. Variable 216 remains at variable level V0 from time t11 to time t12. As another example, at time t12 when pulse 202-7 transitions from logic level 0 to logic level 1, pulse 216-7 of variable 216 transitions from variable level V0 to variable level V4. As yet another example, at time t14 when pulse 202-8 of synchronization signal 202 transitions from logic level 0 to logic level 1, pulse 216-8 of variable transitions from variable level V0 to variable level V4. Pulse 216-6 has a first instance of states S1 and S0 of variable 216, pulse 216-7 has a second instance of states S1 and S0 of variable 216, and pulse 216-8 has a third instance of states S1 and S0 of variable 216.

[0118] Note that variable levels V0 and V4 are examples of information regarding variable levels received within the pulsed preset signal 138 (Figure 1). Also, the duty cycle of each pulse 216-6 to 216-8 is an example of information regarding the duty cycle received within the pulsed preset signal 138. For example, the duty cycle of each pulse 216-1 to 216-8 is 50%. For example, the duty cycle of each pulse 216-6 to 216-8 is the time interval during which the pulse has variable level V4.

[0119] Furthermore, the time interval between times t10 and t16 in which RF signal 102 has state S1 at variable level V4 instead of variable level V3 is an example of information regarding a portion of cycle 1 of master clock signal 141 in which states S1 and S0 of RF signal 102 are generated. Similarly, the time interval between times t0 and t10 in which RF signal 102 has state S1 at variable level V3 is an example of information regarding a portion of cycle 1 of master clock signal 141 in which states S1 and S0 of RF signal 102 are generated. Variable level V4 is greater than variable level V3 and is referred to herein as state S1 of variable 216. Thus, eight pulses 216-1 to 216-8 of variable 216 are generated from time t0 to time t16 during cycle 1 of master clock signal 141.

[0120] During the time interval between times t16 and t20, the synchronization signal 202 (Figure 2A) contains no pulses, and therefore, the variable 216 of the RF signal 102 contains no pulses during the time interval between times t16 and t20. During the time interval between times t16 and t20, when the synchronization signal 202 has no pulses, the TCP generator is prevented from generating any pulses for variable 216. For example, the variable 216 of the RF signal 102 does not transition between multiple variable levels during the time interval between times t16 and t20. The variable 216 of the RF signal has a variable level V0 during the time interval between times t16 and t20. The variable 216 has no variable levels other than variable level V0 during the time interval between times t16 and t20. Thus, the variable 216 has a single variable level V0 during the time interval between times t16 and t20. A single variable level V0 represents a single state S0. During a single state S0, no variable levels other than variable level V0 exist. Note that during the time interval between times t16 and t20, a single logic level 0 exists for the synchronization signal 202. No other logic levels exist during the time interval between times t16 and t20.

[0121] Pulses 216-1 through 216-5 are generated during subcycle 1 of cycle 1 of the master clock signal 141. Pulses 216-6 through 216-8 are generated during subcycle 2 of cycle 1 of the master clock signal 141. No pulses for variable 216 are generated during subcycle 3 of cycle 1 of the master clock signal 141. Just as pulses 216-1 through 216-8 for variable 216 are generated during cycle 1 of the master clock signal 141, eight pulses for variable 216 are again generated by the TCP generator during cycle 2 of the master clock signal 141.

[0122] Note that the duty cycle of a given state is the time interval at which that state occurs, as a percentage of the total time intervals of all states in the pulse. For example, the duty cycle of state S1 in pulse 216-1 is 50%.

[0123] In one embodiment, each pulse of variable 216 has a duty cycle greater than or less than 50%. For example, each pulse of variable 216 has a duty cycle of 25%. In another example, each pulse of variable 216 has a duty cycle of 75%. In yet another example, each of pulses 216-1 to 216-5 has a duty cycle of 25%, and each pulse of cycle 2 has a duty cycle of 75%.

[0124] In one embodiment, the terms subcycle and subcycle are used interchangeably herein.

[0125] In one embodiment, the variable level V0 is the 0 power level of the variable.

[0126] In one embodiment, the variable level V0 is the positive power level of the variable.

[0127] In one embodiment, instead of transitioning from variable level V0 to variable level V4, variable 216 transitions to another variable level, such as variable level V2 or variable level V6. Variable level V6 is greater than variable level V4. Variable level V2 is greater than variable level V0 and less than variable level V3.

[0128] In one embodiment, instead of transitioning from variable level V0 to variable level V3, variable 216 transitions to another variable level, such as variable level V2 or variable level V1. Variable level V1 is greater than variable level V0 and less than variable level V2.

[0129] In one embodiment, variable 216 has more than two states. For example, variable 216 has three, four, or five states. For example, instead of transitioning between variable levels V0 and V3, variable 216 transitions between three variable levels, each time a synchronization pulse of synchronization signal 202 is received by the TCP generator. When synchronization pulse 202-1 is received by the TCP generator at time t0, variable 230 transitions between three variable levels for the time interval between times t0 and t2. When synchronization pulse 202-2 is received by the TCP generator at time t2, variable 216 again transitions between three variable levels for the time interval between times t2 and t4.

[0130] Figure 2E shows graph 218 illustrating the variables 220 of the RF signal 104 (Figure 1) generated by the bias generator 1 in synchronization with the synchronization signal 206 (Figure 2B). Graph 218 plots the levels of multiple variables of the RF signal 104 against time t.

[0131] The pulsation of RF signal 104 is synchronized with the pulsation of synchronization signal 206. For example, during the time interval between times t0 and t10 when synchronization signal 206 does not have pulses, bias generator 1 is prevented from generating any pulses of variable 220. For example, during the time interval between times t0 and t10, synchronization signal 206 contains no pulses, and therefore variable 220 of RF signal 104 contains no pulses during the same time interval. Variable 220 of RF signal 104 does not transition between multiple variable levels during the time interval between times t0 and t10. Variable 220 of RF signal 104 has a variable level V0 during the time interval between times t0 and t10. Variable 220 does not have any variable levels other than variable level V0 during the time interval between times t0 and t10. Thus, variable 220 has a single variable level V0 during the time interval between times t0 and t10.

[0132] As another example, each pulse of the RF signal 104 is generated in response to the reception of a pulse of the synchronization signal 206. For example, when pulse 206-1 (Figure 2B) of the synchronization signal 206 is received by the bias generator 1, pulse 220-1 of variable 220 is generated by the bias generator 1, and pulse 220-1 is synchronized with pulse 206-1. When pulse 206-1 of the synchronization signal 206 is received by the bias generator 1, the bias generator 1 becomes capable of generating pulse 220-1. For example, variable 220 of the RF signal 104 transitions from variable level V0 to variable level V6 at time t10 and remains at variable level V6 from time t10 to time t11. Variable 220 transitions from variable level V6 to variable level V0 at time t11. Variable 220 remains at variable level V0 from time t11 to time t12, resulting in pulse 220-1. Pulse 220-1 has a first instance of states S1 and S0 of variable 220.

[0133] In the same manner that pulse 220-1 is generated, additional pulses 220-2 and 220-3 are generated by the bias generator 1 in synchronization with pulses 206-2 and 206-3. For example, pulse 220-2 is generated in synchronization with pulse 206-2, and pulse 220-3 is generated in synchronization with pulse 206-3. As another example, at time t12 when pulse 206-2 (Figure 2B) transitions from logic level 0 to logic level 1, pulse 220-2 transitions from variable level V0 to variable level V6. Pulse 220-2 has a second instance of states S1 and S0 of variable 220, and pulse 220-3 has a third instance of states S1 and S0 of variable 220. Thus, the three pulses 220-1 to 220-3 of variable 220 are generated from time t10 to time t16 during cycle 1 of the master clock signal 141.

[0134] Note that the variable levels V0 and V6 of pulses 220-1 to 220-3 are examples of information regarding the variable levels received within the pulsed preset signal 138 (Figure 1). Also, the duty cycle of each pulse 220-1 to 220-3 is an example of information regarding the duty cycle received within the pulsed preset signal 138. For example, the duty cycle of each pulse 220-1 to 220-3 is 50%. For example, the duty cycle of each pulse 220-1 to 220-3 is the time interval during which the pulse has a variable level V6.

[0135] Variable level V6 is referred to herein as state S1 of variable 220. Similarly, variable level V0 is referred herein as state S0 of variable 220.

[0136] During subcycle 1 of cycle 1 of the master clock signal 141, no pulses of variable 220 are generated. Pulses 220-1 to 220-3 are generated during subcycle 2 of cycle 1 of the master clock signal 141. Also, during subcycle 3 of cycle 1 of the master clock signal 141, no pulses of variable 220 are generated. During the time interval of subcycle 3 in which the synchronization signal 206 does not have pulses, the bias generator 1 is prevented from generating any pulses of variable 220.

[0137] Just as pulses 220-1 to 220-3 of variable 220 are generated during cycle 1 of the master clock signal 141, three additional pulses of variable 220 are again generated by the bias generator 1 during cycle 2 of the master clock signal 141. For example, just as pulses 220-1 to 220-3 are synchronized with pulses 206-1 to 206-3 of the synchronization signal 206 during cycle 1 of the master clock signal 141, three additional pulses of variable 220 are generated during cycle 2 of the master clock signal 141, synchronized with three pulses of the synchronization signal 206.

[0138] In one embodiment, each pulse of variable 220 has a duty cycle greater than or less than 50%. For example, each pulse of variable 220 has a duty cycle of 25%. As another example, each pulse of variable 220 has a duty cycle of 75%. As yet another example, each pulse of variable 220 has a duty cycle of 25%.

[0139] In one embodiment, instead of transitioning from variable level V0 to variable level V6, variable 220 transitions to another variable level, such as variable level V2.

[0140] Figure 2F shows graph 222 illustrating the variables 224 of the RF signal 106 (Figure 1) generated by the bias generator 2 in synchronization with the synchronization signal 210 (Figure 2C). Graph 220 plots the multiple variable levels of the RF signal 106 against time t.

[0141] The pulsation of RF signal 106 is synchronized with the pulsation of synchronization signal 210. For example, in the time interval between times t0 and t10, the synchronization signal 210 contains no pulses, and therefore, the variable 224 of RF signal 106 contains no pulses during the same time interval. The variable 224 of RF signal 106 does not transition between multiple variable levels during the time interval between times t0 and t10. The variable 224 of RF signal 106 has a variable level V0 during the time interval between times t0 and t10. The variable 224 does not have any variable levels other than variable level V0 during the time interval between times t0 and t10. Thus, the variable 224 has a single variable level V0 during the time interval between times t0 and t10.

[0142] As another example, each pulse of the RF signal 106 is generated in response to the reception of a pulse of the synchronization signal 210. When pulse 210-1 of the synchronization signal 210 is received by the bias generator 2, the bias generator 2 becomes capable of generating pulse 224-1. For example, when pulse 210-1 of the synchronization signal 210 (Figure 2C) is received by the bias generator 2, pulse 224-1 of variable 224 is generated by the bias generator 2, and pulse 224-1 is synchronized with pulse 210-1. For example, variable 224 of the RF signal 106 remains at variable level V0 from time t10 to time t11, and then transitions from variable level V0 to variable level V2 at time t11. Variable 224 transitions from variable level V2 to variable level V0 at time t12, resulting in pulse 224-1. Pulse 224-1 has first instances of states S1 and S0 of variable 224.

[0143] Similar to how pulse 224-1 is generated, additional pulses 224-2 and 224-3 are generated by the bias generator 1 in synchronization with pulses 210-2 and 210-3 of the synchronization signal 210. For example, pulse 224-2 is generated in synchronization with pulse 210-2, and pulse 224-3 is generated in synchronization with pulse 210-3. As another example, after time t12 when pulse 210-2 (Figure 2B) transitions from logic level 0 to logic level 1, pulse 224-2 transitions from variable level V0 to variable level V2. Pulse 224-2 remains at variable level V0 from time t12 to time t13, and then transitions from variable level V0 to variable level V2 at time t13. In this way, the three pulses 224-1 to 224-3 of variable 220 are generated from time t10 to time t16 during cycle 1 of the master clock signal 141. Pulse 224-2 has a second instance of states S1 and S0 of variable 224, and pulse 224-3 has a third instance of states S1 and S0 of variable 224.

[0144] Note that the variable levels V0 and V2 of variable 224 are examples of information regarding the variable level received within the pulsed preset signal 138 (Figure 1). Also, the duty cycle of each pulse 224-1 to 224-3 is an example of information regarding the duty cycle received within the pulsed preset signal 138. For example, the duty cycle of each pulse 224-1 to 224-3 is 50%. For example, the duty cycle of each pulse 224-1 to 224-3 is the time interval during which the pulse has variable level V2.

[0145] Just as pulses 224-1 to 224-3 of variable 224 are generated during cycle 1 of the master clock signal 141, three additional pulses of variable 224 are again generated by the bias generator 2 during cycle 2 of the master clock signal 141. For example, just as pulses 224-1 to 224-3 are synchronized with pulses 210-1 to 210-3 of the synchronization signal 210, three additional pulses of variable 224 are generated during cycle 2 of the master clock signal 141, synchronized with three pulses of the synchronization signal 210.

[0146] Variable level V2 is referred to herein as state S1 of variable 224. Similarly, variable level V0 is referred herein as state S0 of variable 224.

[0147] During subcycle 1 of cycle 1 of the master clock signal 141, no pulses of variable 224 are generated. During the time interval between t0 and t10 when the synchronization signal 210 has no pulses, the bias generator 2 is prevented from generating any pulses of variable 224. Pulses 224-1 to 224-3 are generated during subcycle 2 of cycle 1 of the master clock signal 141. Also, during subcycle 3 of cycle 1 of the master clock signal 141, no pulses of variable 224 are generated. During the time interval between t16 and t20 when the synchronization signal 210 has no pulses, the bias generator 2 is prevented from generating any pulses of variable 224.

[0148] In one embodiment, each pulse of variable 224 has a duty cycle greater than or less than 50%. For example, each pulse of variable 224 has a duty cycle of 25%. In another example, each pulse of variable 224 has a duty cycle of 75%. In yet another example, each of pulses 224-1 to 224-5 has a duty cycle of 25%.

[0149] In one embodiment, instead of transitioning from variable level V0 to variable level V2, variable 224 transitions to another variable level such as variable level V6 or variable level V3.

[0150] Figure 2G shows graph 230 illustrating the variables 232 of the RF signal 104 (Figure 1) generated by the bias generator 1 in synchronization with the synchronization signal 206 (Figure 2B). Graph 230 plots multiple variable levels of the variables 232 of the RF signal 104 against time t.

[0151] The pulsation of variable 232 is synchronized with the pulsation of synchronization signal 206. For example, in the time interval between times t0 and t10, synchronization signal 206 contains no pulses, and therefore variable 232 of RF signal 104 contains no pulses during the same time interval. Variable 232 of RF signal 104 does not transition between multiple variable levels during the time interval between times t0 and t10. Variable 232 of RF signal 104 has a variable level V0 during the time interval between times t0 and t10. Variable 232 does not have any variable levels other than variable level V0 during the time interval between times t0 and t10. Thus, variable 232 has a single variable level V0 during the time interval between times t0 and t10.

[0152] As another example, each series of variable levels for variable 232 is generated in response to the reception of a pulse of the synchronization signal 206. For example, when pulse 206-1 (Figure 2B) of the synchronization signal 206 is received by bias generator 1, a series of variable levels 232-1 for variable 232 is generated by bias generator 1, and the series of pulses 232-1 is synchronized with pulse 206-1. For example, variable 232 of RF signal 104 transitions from variable level V0 to variable level V5 at time t10, and remains at variable level V5 from time t10 to time t10.5. Variable level V5 is greater than variable level V4 but less than variable level V6. Also, variable level V5 is defined as state S4 of variable 232. Variable 232 transitions from variable level V5 to variable level V4 at time t10.5. Variable 232 remains at variable level V4 from time t10.5 to time t11. Variable level V4 is defined as state S3 of variable 232. Variable 232 transitions from variable level V4 to variable level V3 at time t11. Variable 232 remains at variable level V3 from time t11 to time t11.5. Time t11.5 is halfway between time t11 and t12. Variable level V3 is defined as state S2 of variable 232. Variable 232 transitions from variable level V3 to variable level V2 at time t11.5. Variable 232 remains at variable level V2 from time t11.5 to time t12, resulting in series 232-1. Variable level V2 is defined as state S1 of variable 232.

[0153] Series 232-1 includes the occurrence of states S4, S3, S2, and S1 of variable 232, for example, a first instance, etc. Each state S1 to S4 in Series 232-1 represents a different variable level of the RF signal 104. For example, state S4 of variable 232 is the first variable level of the RF signal 104, state S3 of variable 232 is the second variable level of the RF signal 104, state S2 of variable 232 is the third variable level of the RF signal 104, and state S1 of variable 232 is the fourth variable level of the RF signal 104. Each state S1 to S4 also has a duty cycle. For example, the duty cycle of each state S1 to S4 in Series 232-1 is 25%.

[0154] Similar to how series 232-1 of the variable level of variable 232 is generated, additional series 232-2 and 232-3 of the variable level of variable 232 are generated by the bias generator 1 in synchronization with pulses 206-2 and 206-3. For example, series 232-2 is generated in synchronization with pulse 206-2, and series 232-3 is generated in synchronization with pulse 206-3. As another example, at time t12 when pulse 206-2 (Figure 2B) transitions from logic level 0 to logic level 1, series 232-2 transitions from variable level V0 to variable level V5, further transitions from variable level V5 to variable level V4, transitions from variable level V4 to variable level V3, and then transitions from variable level V3 to variable level V2. Thus, three series 232-1 to 232-3 of multiple variable levels of variable 232 are generated from time t10 to time t16 during cycle 1 of the master clock signal 141. Series 232-2 includes second instances of states S4, S3, S2, and S1 of variable 232, and series 232-3 includes third instances of states S4, S3, S2, and S1 of variable 232.

[0155] Note that variable levels V5, V4, V3, and V2 are examples of information regarding variable levels received within the pulsed preset signal 138 (Figure 1). Also, the duty cycles of each variable level in each series 232-1 to 232-3 are examples of information regarding duty cycles received within the pulsed preset signal 138. For example, the duty cycle for state S4 in series 232-1 is 25%, the duty cycle for state S3 in series 232-1 is 25%, the duty cycle for state S2 in series 232-1 is 25%, and the duty cycle for state S1 in series 232-1 is 25%. For example, the duty cycle for each variable level in each series 232-1 to 232-3 represents the time interval at which the variable level occurs.

[0156] During subcycle 1 of cycle 1 of the master clock signal 141, no pulses of variable 232 are generated. Pulses 230-1 to 230-3 are generated during subcycle 2 of cycle 1 of the master clock signal 141. Also, during subcycle 3 of cycle 1 of the master clock signal 141, no pulses of variable 232 are generated.

[0157] Just as series 232-1 to 232-3 of variable 232 are generated during cycle 1 of the master clock signal 141, three additional series of variable levels of variable 232 are again generated by the bias generator 1 during cycle 2 of the master clock signal 141. For example, just as series 232-1 to 232-3 are synchronized with pulses 206-1 to 206-3 of the synchronization signal 206, three additional series of variable levels V5, V4, V3, and V2 of variable 232 are generated during cycle 2 of the master clock signal 141, synchronized with three pulses of the synchronization signal 206.

[0158] In one embodiment, one variable level of variable 232 has a different duty cycle from one or more of the remaining variable levels of variable 232, for example, more or less duty cycles. For example, variable level V4 of series 232-1 has a 40% duty cycle, and variable level V3 of series 232-1 has a 30% duty cycle. In this example, variable level V2 of series 232-1 has a 20% duty cycle, and variable level V1 of series 232-1 has a 10% duty cycle. The duty cycle of state S1 to S4 of variable 232 reaches 100%, i.e., a total of 100%. In another example, variable level V4 of series 232-1 has a 25% duty cycle, and variable level V3 of series 232-1 has a 25% duty cycle. In this example, variable level V2 of Series 232-1 has a 30% duty cycle, and variable level V1 of Series 232-1 has a 20% duty cycle.

[0159] In one embodiment, instead of transitioning from a first variable level to a second variable level, variable 232 transitions to a third variable level different from the second variable level. For example, instead of transitioning from variable level V5 to variable level V4, variable 232 transitions from variable level V5 to variable level V3 or variable level V6. As another example, instead of transitioning from variable level V4 to variable level V3, variable 232 transitions from variable level V4 to variable level V2 or variable level V5.

[0160] In one embodiment, the variable 232 includes a number of states other than four. For example, the variable 232 includes three states, five states, or six states. For example, during a time interval starting at time t10 and ending at time t12, when the variable 232 transitions from variable level V0 to variable level V5 at time t10, then further transitions from variable level V5 to variable level V3, and then transitions from variable level V3 to variable level V2 at time t12, a first series of three variable levels or three states of the variable 232 is formed. In this example, during a time interval starting at time t12 and ending at time t14, when the variable 232 transitions from variable level V2 to variable level V5 at time t12, then further transitions from variable level V5 to variable level V3, and then transitions from variable level V3 to variable level V2 at time t14, a second series of three variable levels of the variable 232 is formed. Furthermore, in this example, during the time interval starting at time t14 and ending at time t16, a third series of three variable levels is formed for variable 232, as variable 232 transitions from variable level V2 to variable level V5 at time t14, then further transitions from variable level V5 to variable level V3, and then transitions from variable level V3 to variable level V2 at time t16.

[0161] In one embodiment, a series of variable levels with a different number of variables than those illustrated in Figure 2G is generated. For example, instead of three series 232-1 to 232-3, only two series 232-1 and 230-2 are generated by the bias generator 1. As another example, in addition to the three series 232-1 to 232-3, a fourth series is generated by the bias generator 1. The fourth series is the same as any of the three series 232-1 to 232-3.

[0162] In one embodiment, variable 232 is generated by the bias generator 2 or the TCP generator. For example, if the synchronization signal 206 is an example of the synchronization signal 140 transmitted to the TCP generator, then variable 232 is the RF signal 102 (Figure 1) generated by the TCP generator. In another example, if the synchronization signal 206 is an example of the synchronization signal 144 transmitted to the bias generator 2, then variable 232 is the RF signal 106 (Figure 1) generated by the bias generator 2.

[0163] In one embodiment, the terms series and pulse are used interchangeably herein. For example, series 232-1 is the first pulse of variable 232, and series 232-2 is the second pulse of variable 232.

[0164] In one embodiment, the same synchronization signal, such as a single synchronization signal, is transmitted from the pulse controller to two or more of the TCP generator, bias generator 1, and bias generator 2. For example, synchronization signal 140 is transmitted to the TCP generator, bias generator 1, and bias generator 2. In another example, synchronization signal 142 is transmitted to the TCP generator, bias generator 1, and bias generator 2. In this embodiment, two or more of the TCP generator, bias generator 1, and bias generator 2 generate two or more RF signals 102, 104, and 106 in synchronization with the same synchronization signal. In this embodiment, it should be noted that the variable level of one of the RF signals 102, 104, and 106 may differ from the variable levels of the remaining RF signals 102, 104, and 106. For example, RF signal 102 has three variables, and RF signal 104 has four variables. Since the same synchronization signal is received by two or more RF generators, the frequencies of the variable state instances in RF signals 102, 104, and 106 are the same. For example, when the synchronization signal 202 is received by the TCP generator and bias generator 1, the TCP generator generates RF signal 102 having a first instance of three states of the variable at time t0, and bias generator 1 generates RF signal 104 having a first instance of four states of the variable at time t0. In this example, the TCP generator generates RF signal 102 having a second instance of three states of the variable at time t2, and bias generator 1 generates RF signal 104 having a second instance of four states of the variable at time t2.

[0165] Figure 3 shows one embodiment of System 300 illustrating the use of Ethernet cables 302, 304, and 306 for transferring information regarding variable levels and duty cycles, and information regarding a portion of the cycle of the master clock signal 141, which generates multiple states of the RF signal. In System 300, System 300 is the same as System 100 in Figure 1, except that instead of an EtherCAT train, information regarding variable levels and duty cycles, and information regarding a portion of the cycle of the master clock signal 141 are transferred from the pulse controller to the TCP generator and bias generators 1 and 2 via Ethernet cables 302, 304, and 306. The pulse controller is connected to the TCP generator via Ethernet cable 302, to bias generator 1 via Ethernet cable 304, and to bias generator 2 via Ethernet cable 306.

[0166] System 300 includes a module controller, a pulse controller, a TCP generator, a bias generator 1, a bias generator 2, a TCP match, a bias match, and a plasma chamber 108. The module controller transmits a pulsed preset signal 138 to the pulse controller via a communication cable 116. Upon receiving the pulsed preset signal 138, the pulse controller identifies and extracts from the pulsed preset signal 138 information regarding the variable level and duty cycle of the RF signal 102, and information regarding a portion of the cycle of the master clock signal 141 in which multiple states of the RF signal 102 are generated. For example, the pulse controller identifies from the pulsed preset signal 138 that the duty cycle of variable 216 (Figure 2D) is 50% with respect to the time interval of subcycle 1 of cycle 1 of the master clock signal 141, and that variable 216 transitions between variable levels V3 and V0. Furthermore, the pulse controller identifies from the pulsed preset signal 138 that, with respect to the time interval of subcycle 2 of cycle 1 of the master clock signal 141, the duty cycle of variable 216 is 50%, and variable 216 transitions between variable levels V4 and V0. In addition, the pulse controller identifies from the pulsed preset signal 138 that, with respect to the time interval of subcycle 3 of cycle 1 of the master clock signal 141, the duty cycle of variable 216 is 0%, and variable 216 remains at variable level V0. The pulse controller also identifies from the pulsed preset signal 138 that the variable level and duty cycle of variable 216 are repeated during subcycles 1, 2, and 3 of cycle 2 of the master clock signal 141, similar to how the variable level and duty cycle of variable 216 are generated during subcycles 1, 2, and 3 of cycle 1 of the master clock signal 141.

[0167] The pulse controller generates a pulsed preset signal 308 containing information about the variable level and duty cycle of the RF signal 102, and information about a portion of the cycle of the master clock signal 141 that generates multiple states of the RF signal 102, and transmits the pulsed preset signal 308 to the TCP generator via the Ethernet cable 302. Upon receiving the pulsed preset signal 308, the TCP generator stores the information about the variable level and duty cycle of the RF signal 102, and the information about a portion of the cycle of the master clock signal 141 that generates multiple states of the RF signal 102, in one or more memory devices of the TCP generator. Upon receiving the synchronization signal 140 via the transfer cable 120, the TCP generator generates an RF signal 102 in synchronization with the synchronization signal 140, containing information about the variable level and duty cycle of the RF signal 102, and information about a portion of the cycle of the master clock signal 141 that generates multiple states of the RF signal 102.

[0168] Similarly, upon receiving the pulsed preset signal 138, the pulse controller identifies and extracts information from the pulsed preset signal 138 regarding the variable level and duty cycle of the RF signal 104, and information regarding a portion of the cycle of the master clock signal 141 in which multiple states of the RF signal 104 are generated. For example, the pulse controller identifies from the pulsed preset signal 138 that, with respect to the time interval of subcycle 1 of cycle 1 of the master clock signal 141, the duty cycle of variable 220 (Figure 2E) is 0% and variable 220 remains at variable level V0. The pulse controller also identifies from the pulsed preset signal 138 that, with respect to the time interval of subcycle 2 of cycle 1 of the master clock signal 141, the duty cycle of variable 220 is 50% and variable 220 transitions between variable levels V6 and V0. Furthermore, the pulse controller identifies from the pulsed preset signal 138 that the duty cycle of variable 220 is 0% and that variable 220 remains at variable level V0 with respect to the time interval of subcycle 3 of cycle 1 of the master clock signal 141. The pulse controller also identifies from the pulsed preset signal 138 that the variable level and duty cycle of variable 220 are repeated during subcycles 1, 2, and 3 of cycle 2 of the master clock signal 141, just as the variable level and duty cycle of variable 220 are generated during subcycles 1, 2, and 3 of cycle 1 of the master clock signal 141.

[0169] The pulse controller generates a pulsed preset signal 310 containing information about the variable level and duty cycle of the RF signal 104, and information about a portion of the cycle of the master clock signal 141 that generates multiple states of the RF signal 104, and transmits the pulsed preset signal 310 to the bias generator 1 via the Ethernet cable 304. Upon receiving the pulsed preset signal 310, the bias generator 1 stores the information about the variable level and duty cycle of the RF signal 104, and the information about a portion of the cycle of the master clock signal 141 that generates multiple states of the RF signal 104, in one or more memory devices of the bias generator 1. Upon receiving the synchronization signal 142 via the transfer cable 122, the bias generator 1 generates an RF signal 104 in synchronization with the synchronization signal 142, containing information about the variable level and duty cycle of the RF signal 104, and information about a portion of the cycle of the master clock signal 141 that generates multiple states of the RF signal 104.

[0170] Furthermore, upon receiving the pulsed preset signal 138, the pulse controller identifies and extracts information from the pulsed preset signal 138 regarding the variable level and duty cycle of the RF signal 106, and information regarding a portion of the cycle of the master clock signal 141 in which multiple states of the RF signal 106 are generated. For example, the pulse controller identifies from the pulsed preset signal 138 that, with respect to the time interval of subcycle 1 of cycle 1 of the master clock signal 141, the duty cycle of variable 224 (Figure 2F) is 0% and variable 224 remains at variable level V0. The pulse controller also identifies from the pulsed preset signal 138 that, with respect to the time interval of subcycle 2 of cycle 1 of the master clock signal 141, the duty cycle of variable 224 is 50% and variable 224 transitions between variable levels V2 and V0. Furthermore, the pulse controller identifies from the pulsed preset signal 138 that the duty cycle of variable 224 is 0% and variable 224 remains at variable level V0 with respect to the time interval of subcycle 3 of cycle 1 of the master clock signal 141. The pulse controller also identifies from the pulsed preset signal 138 that the variable level and duty cycle of variable 224 are repeated during subcycles 1, 2, and 3 of cycle 2 of the master clock signal 141, just as the variable level and duty cycle of variable 220 are generated during subcycles 1, 2, and 3 of cycle 1 of the master clock signal 141.

[0171] The pulse controller generates a pulsed preset signal 312 containing information about the variable level and duty cycle of the RF signal 106, and information about a portion of the cycle of the master clock signal 141 that generates multiple states of the RF signal 106, and transmits the pulsed preset signal 312 to the bias generator 2 via the Ethernet cable 306. Upon receiving the pulsed preset signal 312, the bias generator 2 stores the information about the variable level and duty cycle of the RF signal 106, and the information about a portion of the cycle of the master clock signal 141 that generates multiple states of the RF signal 106, in one or more memory devices of the bias generator 2. Upon receiving the synchronization signal 144 via the transfer cable 124, the bias generator 2 generates an RF signal 106 in synchronization with the synchronization signal 144, containing information about the variable level and duty cycle of the RF signal 106, and information about a portion of the cycle of the master clock signal 141 that generates multiple states of the RF signal 106.

[0172] In one embodiment, a connection cable is used instead of each of the Ethernet cables 302, 304, and 306. An example of a connection cable is a cable capable of transferring data at a speed faster than 10 Gbps. The connection cable provides a connection between CPUs. For example, the connection cable can transfer data at a speed ranging from 10 Gbps to 40 Gbps. Another example of a connection cable is a transfer cable.

[0173] Figure 4 shows an embodiment of system 400 illustrating the use of EtherCAT to sense data from sensor 402 in TCP match and sensor 404 in bias match. Examples of sensors 402 and 404 are voltage sensors, current sensors, complex voltage / current sensors, or power sensors. For example, sensors 402 and 404 sense data such as voltage data, current data, power values, or complex voltage / current values. As an example, sensor 402 is connected to input I1 of TCP match. As another example, sensor 402 is connected to output O2 of TCP match. As an example, sensor 404 is connected to input I2 or I3 of bias match. As yet another example, sensor 404 is connected to output O4 of bias match.

[0174] System 400 is the same as system 100 (Figure 1), except that it includes a communication cable 406 and another communication cable 408. System 400 further includes a voltage sensor system 410 and an emission spectrometer (OES) system 412.

[0175] The voltage sensor system 410 includes a voltage detector or sensor, a controller, and an analog-to-digital converter (ADC). The voltage sensor senses wafer bias, such as voltage, on the substrate support 110. For example, the voltage sensor senses data such as voltage data or voltage value. The controller of the voltage sensor system 410 is connected to the ADC and voltage sensor of the voltage sensor system 410. The OES system 412 includes an OES, a controller, and an ADC. The controller of the OES system 412 is connected to the ADC and OES of the OES system 412. The OES senses the intensity of light emitted from the plasma in the plasma chamber 108. For example, the OES measures data on the intensity of light reflected from the upper surface of the substrate S toward the OES.

[0176] System 400 includes a module controller, a pulse controller, a TCP generator, bias generators 1 and 2, a plasma chamber 108, a TCP match with sensor 402, a bias match with sensor 404, a voltage sensor system 410, and an OES system 412. A communication cable 406 connects the pulse controller to the TCP match, and a communication cable 408 connects the TCP match to the bias match. The pulse controller is connected to the TCP match via a transfer cable 414 and to the bias match via a transfer cable 417.

[0177] The voltage sensor system 410 is connected to the substrate support 110. The OES system 412 is located outside the side wall 424 of the plasma chamber 108. For example, there is a window on the side wall 424, and the OES of the OES system 412 faces the window. The pulse controller is connected to the voltage sensor system 410 via a transfer cable 420 and to the OES system 412 via a transfer cable 422.

[0178] The pulse controller generates a factor control signal 415, which is an EtherCAT train, and transmits the factor control signal 415 to the TCP match via the communication cable 406. The factor control signal 415 includes instructions to the match controller in the TCP match to change the factors of the TCP match, such as capacitance, inductance, or a combination thereof, to achieve a predetermined factor. The factor control signal 415 further includes another instruction to the match controller in the bias match to change the factors of the bias match to achieve a pre-set factor.

[0179] Upon receiving the factor control signal 415, the TCP match obtains a predetermined factor related to the TCP match from the factor control signal 415. Based on the predetermined factor, the TCP match controller controls the TCP motor within the TCP match to further control the circuit components of the TCP match. The circuit components of the TCP match are controlled to change the factors of the circuit components to achieve the predetermined factor. For example, the TCP match motor controls the first plate of the TCP match capacitor to rotate it relative to the second plate of the capacitor to achieve a predetermined capacitance.

[0180] After obtaining a predetermined factor from the factor control signal 415, the TCP match transmits the factor control signal 415 to the bias match via the communication cable 408. Upon receiving the factor control signal 415, the bias match obtains a pre-set factor related to the bias match from the factor control signal 415. Based on the pre-set factor, the match controller of the bias match 1 controls the bias motor in the bias match to further control the circuit components of the bias match. The circuit components of the bias match are controlled to change the factors of the circuit components to realize the pre-set factor. For example, the motor controls the first plate of the capacitor in the bias match to rotate relative to the second plate of the capacitor to realize the pre-set capacitance.

[0181] After obtaining the pre-set factor from the factor control signal 415, the bias match sends the factor control signal 415 back to the TCP match via the communication cable 408. The TCP match sends the factor control signal 415 received from the bias match back to the pulse controller.

[0182] Furthermore, after the TCP match controller applies commands to realize predetermined factors and RF signals 102, 104, and 106 are generated, the pulse controller generates a synchronization signal 416 and transmits it to the TCP match via the transfer cable 414. Additionally, after the bias match controller applies commands to realize pre-set factors and RF signals 102, 104, and 106 are generated, the pulse controller generates another synchronization signal 418 and transmits it to the bias match via the transfer cable 417. Synchronization signal 416 is labeled as sync4a in Figure 4, and synchronization signal 418 is labeled as sync4b in Figure 4.

[0183] In response to receiving the synchronization signal 416, the match controller in the TCP match controls the TCP match's ADC to collect data sensed by the sensor 402 in synchronization with the synchronization signal 416. The collected data is transmitted from the TCP match to the pulse controller. For example, the synchronization signal 416 includes a series of pulses, including a first pulse and a second pulse. In response to receiving the first pulse of the synchronization signal 416 for a first time interval, the TCP match controller controls the TCP match's ADC to convert the data sensed by the sensor 402 from analog to digital format for the first time interval and outputs digital data for the first time interval. The TCP match's ADC is connected to the sensor 402. The TCP match controller receives the digital data output from the TCP match's ADC for the first time interval and stores the digital data in the match controller's memory device. Upon receiving the factor control signal 415 returned from the bias match, the match controller accesses the digital data for the first time interval from the memory device. The digital data relating to the time interval is then embedded in the factor control signal 415 and transmitted to the pulse controller via the communication cable 406.

[0184] Similarly, in response to receiving a second pulse of the synchronization signal 416 for the second time interval, the TCP match controller controls the TCP match ADC to convert the data sensed by sensor 402 from analog to digital format for the second time interval and outputs digital data for the second time interval. The TCP match controller receives the digital data output for the second time interval from the TCP match ADC and stores the digital data in the match controller's memory device. Upon receiving the factor control signal 415 returned from bias match, the match controller accesses the digital data for the second time interval from the memory device. The digital data for the second time interval is embedded in the factor control signal 415 and transmitted to the pulse controller via the communication cable 406. During time intervals when no pulse of the synchronization signal 416 is received by TCP match, the TCP match controller does not control the ADC to convert the data sensed by sensor 402 from analog to digital format.

[0185] Similarly, in response to the reception of the synchronization signal 418, the match controller in the bias match controls the sensor 404 to provide the data sensed by the sensor 404 to the pulse controller in synchronization with the synchronization signal 418. For example, the synchronization signal 418 includes a series of pulses, including a first pulse and a second pulse. In response to the reception of the first pulse of the synchronization signal 418 with respect to a first time interval, the match controller in the bias match controls the ADC in the bias match to convert the data sensed by the sensor 404 from analog to digital with respect to the first time interval and output digital data with respect to the first time interval. The ADC in the bias match is connected to the sensor 404. The match controller in the bias match receives the digital data output from the ADC in the bias match with respect to the first time interval and stores the digital data in the match controller's memory device. When the factor control signal 415 is received from the TCP match, the match controller accesses the digital data with respect to the first time interval from the memory device. Digital data relating to the first time interval is embedded in the factor control signal 415 and sent back to TCP Match via the communication cable 408, and from TCP Match it is sent back to the pulse controller via the communication cable 408.

[0186] Similarly, in response to receiving a second pulse of the synchronization signal 418 for the second time interval, the bias match's match controller controls the bias match's ADC to convert the data sensed by the sensor 404 from analog to digital format for the second time interval and outputs digital data for the second time interval. The bias match's match controller receives the digital data output for the second time interval from the bias match's ADC and stores the digital data in the match controller's memory device. When the factor control signal 415 is received from the bias match, the match controller accesses the digital data for the second time interval from the memory device. The digital data for the second time interval is then embedded in the factor control signal 415 and sent back to the TCP match via the communication cable 408, and from the TCP match to the pulse controller. During time intervals when the pulse of the synchronization signal 418 is not received by the bias match, the bias match's match controller does not control the ADC to convert the data sensed by the sensor 404 from analog to digital format.

[0187] The pulse controller also generates a synchronization signal 426 and transmits it to the voltage sensor system 410 via the transfer cable 420. The synchronization signal 426 is labeled as sync5 in Figure 4. In response to receiving the synchronization signal 426, the controller in the voltage sensor system 410 controls the voltage sensor of the voltage sensor system 410 to synchronize with the synchronization signal 426 and provide the data sensed by the voltage sensor to the pulse controller. For example, the synchronization signal 426 includes a series of pulses, including a first pulse and a second pulse. In response to receiving the first pulse of the synchronization signal 426 for a first time interval, the controller in the voltage sensor system 410 controls the ADC of the voltage sensor system 410 to convert the data sensed by the voltage sensor from analog to digital for the first time interval and output digital data for the first time interval. The ADC of the voltage sensor system 410 is connected to the voltage sensor of the voltage sensor system 410. The controller of the voltage sensor system 410 receives digital data output from the ADC of the voltage sensor system 410 for a first time interval and transmits the digital data to the pulse controller via the transfer cable 420. Similarly, in response to the reception of the second pulse of the synchronization signal 426 for a second time interval, the controller of the voltage sensor system 410 controls the ADC of the voltage sensor system 410 to convert the data sensed by the voltage sensor from analog to digital format for the second time interval and outputs the digital data for the second time interval. The controller of the voltage sensor system 410 receives digital data output from the ADC of the voltage sensor system 410 for a second time interval and transmits the digital data to the pulse controller via the transfer cable 420. During time intervals in which the pulse of the synchronization signal 426 is not received by the voltage sensor system 410, the controller of the voltage sensor system 410 does not control the ADC of the voltage sensor system 410 to convert the data sensed by the voltage sensor from analog to digital format.

[0188] Furthermore, the pulse controller generates a synchronization signal 428 and transmits it to the OES system 412 via the transfer cable 422. The synchronization signal 428 is labeled as sync6 in Figure 4. In response to receiving the synchronization signal 428, the controller in the OES system 412 controls the OES of the OES system 412 to provide the data sensed by the OES to the pulse controller in synchronization with the synchronization signal 428. For example, the synchronization signal 428 includes a series of pulses, including a first pulse and a second pulse. In response to receiving the first pulse of the synchronization signal 428 with respect to a first time interval, the controller in the OES system 412 controls the ADC of the OES system 412 to convert the data sensed by the OES from analog to digital with respect to the first time interval and output digital data with respect to the first time interval. The controller in the OES system 412 receives the digital data output from the ADC of the OES system 412 with respect to the first time interval and transmits the digital data to the pulse controller via the transfer cable 422. Similarly, in response to receiving the second pulse of the synchronization signal 428 for the second time interval, the controller of the OES system 412 controls the ADC of the OES system 412 to convert the data sensed by the OES from analog to digital format for the second time interval and output digital data for the second time interval. The controller of the OES system 412 receives the digital data output from the ADC of the OES system 412 for the second time interval and transmits the digital data to the pulse controller via the transfer cable 422. During time intervals in which the pulse of the synchronization signal 428 is not received by the OES system 412, the controller of the OES system 412 does not control the ADC of the OES system 412 to convert the data sensed by the OES from analog to digital format.

[0189] Synchronization signals 416, 418, 426, and 428 are generated by the pulse controller in synchronization with the master clock signal 141. For example, each of the synchronization signals 416, 418, 426, and 428 has a series of pulses that repeat during each cycle of the master clock signal 141.

[0190] In one embodiment, a power sensor or a complex voltage / current sensor is used instead of the voltage sensor in the voltage sensor system 410.

[0191] In one embodiment, instead of placing the sensor 402 inside the TCP match, the sensor 402 is placed outside the TCP match.

[0192] In one embodiment, instead of placing the sensor 404 inside the bias match, the sensor 404 is placed outside the TCP match.

[0193] In one embodiment, the system 400 does not include one or more (but not all) of the sensors 402, 404, voltage sensor system 410, and OES system 412.

[0194] In one embodiment, the module controller generates a factor control signal 415 and transmits the factor control signal 415 to the pulse controller via the communication cable 116. The pulse controller transmits the factor control signal 415 to TCP Match via the communication cable 406.

[0195] In one embodiment, the terms data and value are used interchangeably herein.

[0196] Figure 5A shows Graph 500 to illustrate the plot of plasma intensity 502 against time t. Intensity 502 is detected by OES. Intensity 502 is plotted on the y-axis and time t is plotted on the x-axis.

[0197] Figure 5B shows graph 504 to illustrate the relationship between the synchronization signal 506 and time t. Graph 504 plots the logic level of the synchronization signal 506 on the y-axis and time t on the x-axis. The synchronization signal 506 is an example of the synchronization signal 428 (Figure 4).

[0198] The synchronization signal 506 is not pulsed from time t0 to time t6. For example, the synchronization signal 506 has logic level 0 from time t0 to time t6. The synchronization signal 506 becomes pulsed at time t6. For example, the synchronization signal 506 transitions from logic level 0 to logic level 1 at time t6, remains at logic level 1 from time t6 to time t6.5, and time t6.5 is half the time interval between time t5 and t6. Also, the synchronization signal 506 transitions from logic level 1 to logic level 0 at time t6.5, forming pulse 506-1, and remains at logic level 0 from time t6.5 to time t9. The synchronization signal 506 becomes pulsed again at time t9. For example, the synchronization signal 506 transitions from logic level 0 to logic level 1 at time t9, and remains at logic level 1 from time t9 to time t10. Furthermore, the synchronization signal 506 transitions from logic level 1 to logic level 0 at time t10, forming pulse 506-2, and remains at logic level 0 from time t10 to time t20, with time t20 occurring at the end of cycle 1 of the master clock signal 141.

[0199] During cycle 1 of the master clock signal 141, the synchronization signal 506 includes a pulseless time interval between times t0 and t6, followed by pulse 506-1. Also during cycle 1 of the master clock signal 141, pulse 506-1 is followed by a pulseless time interval between times t6.5 and t9, followed by pulse 506-2. During cycle 1 of the master clock signal 141, pulse 506-2 is followed by a pulseless time interval between times t10 and t20 during cycle 1 of the master clock signal 141.

[0200] Similar to the cycle 1 of the master clock signal 141, the synchronization signal 506 is not pulsed from time t20 to time t26 during the cycle 2 of the master clock signal 141, becomes pulsed at time t26, is not pulsed between time t26.5 and time t29, becomes pulsed again at time t29, and is not pulsed between time t30 and t40. Time t26.5 is at the halfway point of the time interval between time t26 and t27.

[0201] The ADC of the OES system 412 (Figure 4) starts and stops sampling of the data sensed by the OES from analog to digital format in synchronization with the synchronization signal 506. For example, during the time interval between times t0 and t6, the intensity 502 detected by the OES is not sampled by the ADC of the OES system 412. In this example, during the time interval between times t6 and t6.5, the intensity 502 detected by the OES is sampled by the ADC of the OES system 412. The intensity sampled during the time interval between times t6 and t6.5 is represented by part 502-1. Also in this example, during the time interval between times t6.5 and t9, the intensity 502 detected by the OES is not sampled by the ADC of the OES system 412. Continuing the example, during the time interval between times t9 and t10, the intensity 502 detected by the OES is sampled by the ADC of the OES system 412. The intensity sampled during the time interval between times t9 and t10 is represented by part 502-2. Also, in this example, during the time interval between times t10 and t20, the intensity 502 detected by the OES is not sampled by the ADC of the OES system 412. Similar to during cycle 1 of the master clock signal 141, the intensity 502 is sampled or not sampled by the ADC of the OES system 412 during cycle 2 of the master clock signal 141.

[0202] In one embodiment, all pulses of the synchronization signal 506 have the same duration. For example, pulse 506-2 transitions from logic level 1 to logic level 0 at time t9.5 instead of transitioning at time t10. Time t9.5 is halfway between times t9 and t10. In this embodiment, the ADC connected to the OES converts the data sensed by the OES from analog to digital when each pulse of the synchronization signal 506 is received by the ADC. The ADC converts the data sensed by the OES for a fixed time for each pulse of the synchronization signal 506. For example, when the rising edge of pulse 506-1 is received by the ADC, the ADC converts the data sensed by the OES for a fixed time between times t6 and t9, and when the rising edge of pulse 506-2 is received by the ADC, the ADC converts the data sensed by the OES for a fixed time between times t9 and t12. The fixed time begins at time t6, when the rising edge of pulse 506-1 occurs. An example of a fixed time is a time interval that is the difference between one time unit, two time units, or 2.5 time units. In this example, a time unit is defined as the time interval between two consecutive times, such as times t0 and t1, or times t1 and t2. After a fixed time, the ADC stops sampling the data sensed by the OES until the next consecutive pulse of the synchronization signal 506 is received by the ADC. The data sensed by the OES is sampled again by the ADC of the OES system 412 for a fixed time, starting from time t9. At time t9, the rising edge of pulse 506-2 occurs. Note that the rising edge of a pulse as used herein is the edge that transitions from logic level 0 to logic level 1. Note that the rising edge of a pulse as used herein is the edge that transitions from logic level 1 to logic level 0.

[0203] In one embodiment, instead of starting the acquisition of data sensed by the OES at the rising edge of each pulse of the synchronization signal 506, the acquisition is started for a certain period of time at the falling edge of the pulse. For example, suppose pulse 506-2 transitions from logic level 1 to logic level 0 at time t9.5 instead of time t10. In this embodiment, the ADC connected to the OES converts the data sensed by the OES from analog to digital format at the time of the falling edge of each pulse of the synchronization signal 506 received by the ADC. The ADC converts the data sensed by the OES for a certain period of time, starting from the falling edge of the pulse of the synchronization signal 506. For example, the ADC converts the data sensed by the OES for a certain period of time between times t6.5 and t9.5, and this period of time starts at time t6.5 when the falling edge of pulse 506-1 is received by the ADC. The ADC stops sampling the data sensed by the OES after a certain period of time until the ADC receives the falling edge of the next consecutive pulse of the synchronization signal 506, such as the falling edge of pulse 506-2. The data sensed by the OES is sampled again for a certain period of time, starting at time t9.5. Note that the falling edge of a pulse as used herein is the edge that transitions from logic level 0 to logic level 1.

[0204] In one embodiment, instead of two consecutive pulses, the synchronization signal 506 includes another number of consecutive pulses, such as three or four.

[0205] In one embodiment, the frequency of pulse generation of the synchronization signal 506 differs from that illustrated in Figure 5B. For example, instead of occurring at time intervals of three time units, the pulses of the synchronization signal 506 occur at time intervals of two time units. For example, instead of pulse 506-2 occurring at time t9, pulse 506-2 occurs at time t8. In this example, a time unit is defined as a time interval between two consecutive times, such as times t0 and t1, or times t1 and t2.

[0206] Figure 6A shows graph 600 to illustrate the plot of voltage 602 against time t. Voltage 602 is measured by sensor 402 (Figure 4). Voltage 602 is plotted on the y-axis and time t is plotted on the x-axis. Voltage 602 fluctuates between a maximum value Vmax and a minimum value Vmin.

[0207] Figure 6B shows graph 604 to illustrate the relationship between the synchronization signal 606 and time t. Graph 604 plots the logic level of the synchronization signal 606 on the y-axis and time t on the x-axis. The synchronization signal 606 is an example of the synchronization signal 416 (Figure 4).

[0208] The synchronization signal 606 becomes pulsed at time t0. For example, the synchronization signal 606 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t0.5. Then, the synchronization signal 606 transitions from logic level 1 to logic level 0 at time t0.5, forming pulse 606-1, and remains at logic level 0 from time t0.5 to time t4.

[0209] The synchronization signal 606 is not pulsed from time t0.5 to time t4. For example, the synchronization signal 606 has logic level 0 from time t0.5 to time t4. The synchronization signal 606 becomes pulsed at time t4. For example, the synchronization signal 606 transitions from logic level 0 to logic level 1 at time t4 and remains at logic level 1 from time t4 to time t5. Also, the synchronization signal 606 transitions from logic level 1 to logic level 0 at time t5, forming pulse 606-2, and remains at logic level 0 from time t5 to time t20.

[0210] During cycle 1 of the master clock signal 141, pulse 606-1 is followed by a pulseless time interval between times t0.5 and t4, and then pulse 606-2 follows that time interval. During cycle 1 of the master clock signal 141, the synchronization signal 606 includes a pulseless time interval of synchronization signal 606 between times t5 and t20.

[0211] Similar to during cycle 1 of the master clock signal 141, the synchronization signal 606 is pulsed during the time interval between time t20 and time t20.5, non-pulsated from time t20.5 to time t24, pulsed during the time interval between time t24 and t25, and non-pulsated between time t25 and time t40 during cycle 2 of the master clock signal 141.

[0212] The ADC connected to sensor 402 (Figure 4) starts and stops sampling of the data sensed by sensor 402 from analog to digital format in synchronization with the synchronization signal 606. For example, the voltage 602 measured by sensor 402 during the time interval between times t0 and t0.5 is sampled by the ADC connected to sensor 402. The voltage sampled during the time interval between times t0 and t0.5 is represented by part 602-1. In this example, the voltage 602 measured by sensor 402 during the time interval between times t0.5 and t4 is not sampled by the ADC connected to sensor 402. In this example, the voltage 602 detected by sensor 402 during the time interval between times t4 and t5 is sampled by the ADC connected to sensor 402. The voltage 602 sampled during the time interval between times t4 and t5 is represented by part 602-2. In this example, the voltage 602 detected by the sensor 402 is not sampled by the ADC connected to the sensor 402 during the time interval between times t5 and t20. Similarly, during cycle 1 of the master clock signal 141, the voltage 602 is sampled or not sampled by the ADC connected to the sensor 402 during cycle 2 of the master clock signal 141.

[0213] In one embodiment, instead of two consecutive pulses, the synchronization signal 606 includes another number of consecutive pulses, such as three or four.

[0214] In one embodiment, the frequency of pulse generation for the synchronization signal 606 differs from that illustrated in Figure 6B. For example, instead of occurring at time intervals of four time units, the pulses of the synchronization signal 606 occur at time intervals of three time units. For example, instead of pulse 606-2 occurring at time t4, pulse 606-2 occurs at time t3. In this example, a time unit is defined as a time interval between two consecutive times, such as times t0 and t1, or times t1 and t2.

[0215] In one embodiment, the voltage 602 is measured by a sensor 404 (Figure 4) in a bias match instead of sensor 402. In this embodiment, the synchronization signal 606 is an example of a synchronization signal 418 (Figure 4) that is provided to the bias match to receive measurement data from sensor 404 in synchronization with the synchronization signal 418.

[0216] In one embodiment, the voltage 602 is measured by a voltage sensor of a voltage sensor system 410 (Figure 4) instead of sensor 402. In this embodiment, the synchronization signal 606 is an example of a synchronization signal 426 provided to the voltage sensor system 410 in synchronization with the synchronization signal 426 (Figure 4) to receive measurement data from the voltage sensor of the voltage sensor system 410.

[0217] In one embodiment, all pulses of the synchronization signal 606 have the same duration. For example, pulse 606-2 transitions from logic level 1 to logic level 0 at time t4.5 instead of transitioning at time t5. Time t4.5 is halfway between times t4 and t5. In this embodiment, the ADC connected to the sensor 402 converts the data sensed by the sensor 402 from analog to digital when each pulse of the synchronization signal 606 is received by the ADC. The ADC converts the data sensed by the sensor 402 for a certain period of time for each pulse of the synchronization signal 606. For example, when the rising edge of pulse 606-1 is received by the ADC, the data sensed by the sensor 402 is converted for a certain period of time between times t0 and t4, and when the rising edge of pulse 606-2 is received by the ADC, the data sensed by the sensor 402 is converted for a certain period of time between times t4 and t7. For example, the ADC converts the data sensed by the sensor 402 from analog to digital format, starting at time t0 and continuing until a certain period of time is reached. After the certain period of time, the ADC stops sampling the data sensed by the sensor 402 until the next consecutive pulse of the synchronization signal 606 is received by the ADC. For example, the ADC stops converting data from time t2 to time t4. The ADC converts the data sensed by the sensor 402 from analog to digital format, starting at time t4 and continuing until a certain period of time is reached. The certain period of time is reached at time t6.

[0218] In one embodiment, instead of starting data collection by the sensor 402 at the rising edge of the pulse of the synchronization signal 606, collection is started for a fixed time period, which begins at the falling edge of the pulse. In this embodiment, the ADC connected to the sensor 402 converts the data sensed by the sensor 402 from analog to digital format at the time of the falling edge of each pulse of the synchronization signal 606 received by the ADC. The ADC converts the data sensed by the sensor 402 for a fixed time period after the falling edge of the pulse of the synchronization signal 606. For example, after the falling edge of pulse 606-1 is received by the ADC, the ADC converts the data sensed by the sensor 402 for a fixed time period between times t0.5 and t4.5. The fixed time period begins at time t0.5. After the fixed time period, the ADC stops sampling the data sensed by the sensor 402 until the falling edge of the next consecutive pulse of the synchronization signal 606, such as pulse 606-2, is received by the ADC. The ADC further transforms the data sensed by sensor 402 for a certain period of time after the falling edge of pulse 606-2. For example, suppose pulse 606-2 transitions from logic level 1 to logic level 0 at time t4.5 instead of at time t5. The ADC starts at time t4.5 and transforms the data sensed by sensor 402 until a certain period of time is reached.

[0219] Figure 6C shows graph 608 to illustrate the plot of voltage 610 against time t. Voltage 610 is measured by bias-matched sensor 404 (Figure 4). Voltage 610 is plotted on the y-axis and time t is plotted on the x-axis. Voltage 610 fluctuates between a maximum value Vbmax and a minimum value Vbmin.

[0220] Figure 6D shows graph 612 illustrating the relationship between the synchronization signal 614 and time t. Graph 612 plots the logic level of the synchronization signal 614 on the y-axis and time t on the x-axis. The synchronization signal 614 is an example of the synchronization signal 418 (Figure 4) provided for bias matching.

[0221] The synchronization signal 614 becomes pulsed at time t0. For example, the synchronization signal 614 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t2. Then, the synchronization signal 614 transitions from logic level 1 to logic level 0 at time t2, forming pulse 614-1, and remains at logic level 0 from time t2 to time t5.

[0222] The synchronization signal 614 is not pulsed from time t2 to time t5. For example, the synchronization signal 614 has a logic level of 0 from time t2 to time t5. The synchronization signal 614 becomes pulsed at time t5. For example, the synchronization signal 614 transitions from logic level 0 to logic level 1 at time t5 and remains at logic level 1 from time t5 to time t6. Also, the synchronization signal 614 transitions from logic level 1 to logic level 0 at time t6, forming pulse 614-2, and remains at logic level 0 from time t6 to time t20.

[0223] During cycle 1 of the master clock signal 141, pulse 614-1 is followed by a pulseless time interval between times t2 and t5, and then pulse 614-2 follows that time interval. During cycle 1 of the master clock signal 141, pulse 614-2 is followed by a pulseless time interval of the synchronization signal 614 between times t6 and t20.

[0224] Similar to during cycle 1 of the master clock signal 141, the synchronization signal 614 is pulsed during the time interval between time t20 and time t22, non-pulsated from time t22 to time t25, pulsed during the time interval between time t25 and t26, and non-pulsated from time t26 to time t40 during cycle 2 of the master clock signal 141.

[0225] The ADC connected to sensor 404 (Figure 4) starts and stops sampling of the data sensed by sensor 404 from analog to digital format in synchronization with the synchronization signal 614. For example, the voltage 610 measured by sensor 404 during the time interval between times t0 and t2 is sampled by the ADC connected to sensor 404. The voltage sampled during the time interval between times t0 and t2 is represented by part 610-1. In this example, the voltage 610 measured by sensor 404 is not sampled by the ADC connected to sensor 404 during the time interval between times t2 and t5. In this example, the voltage 610 detected by sensor 404 is sampled by the ADC connected to sensor 404 during the time interval between times t5 and t6. The voltage 610 sampled during the time interval between times t5 and t6 is represented by part 610-2. In this example, the voltage 610 detected by the sensor 404 is not sampled by the ADC connected to the sensor 404 during the time interval between times t6 and t20. Similarly, during cycle 1 of the master clock signal 141, the voltage 610 is sampled or not sampled by the ADC connected to the sensor 404 during cycle 2 of the master clock signal 141.

[0226] In one embodiment, instead of two consecutive pulses, the synchronization signal 614 includes another number of consecutive pulses, such as three or four.

[0227] In one embodiment, the frequency of pulse generation for the synchronization signal 614 differs from that illustrated in Figure 6D. For example, instead of occurring at time intervals of five time units, the pulses of the synchronization signal 614 occur at time intervals of six time units. For example, instead of pulse 614-2 occurring at time t5, pulse 614-2 occurs at time t6. In this example, a time unit is defined as a time interval between two consecutive times, such as times t0 and t1, or times t1 and t2.

[0228] In one embodiment, the voltage 610 is measured by sensor 402 (Figure 4) in the TCP match instead of sensor 404. In this embodiment, synchronization signal 614 is an example of synchronization signal 416 provided to the TCP match to receive measurement data from sensor 402 in synchronization with synchronization signal 416 (Figure 4).

[0229] In one embodiment, the voltage 610 is measured by a voltage sensor of a voltage sensor system 410 (Figure 4) instead of sensor 404. In this embodiment, the synchronization signal 614 is an example of a synchronization signal 426 (Figure 4) that is provided to the voltage sensor system 410 to receive measurement data from the voltage sensor of the voltage sensor system 410 in synchronization with the synchronization signal 426 (Figure 4).

[0230] In one embodiment, all pulses of the synchronization signal 614 have the same duration. For example, pulse 614-2 may transition from logic level 1 to logic level 0 at time t7 instead of transitioning at time t6. In this embodiment, the ADC connected to the bias-matched sensor 404 converts the data sensed by the sensor 404 from analog to digital format when each pulse of the synchronization signal 610 is received by the ADC. The ADC converts the data sensed by the sensor 404 for a certain period of time for each pulse of the synchronization signal 610. For example, when the rising edge of pulse 614-1 is received by the ADC, the data sensed by the sensor 404 is converted for a certain period of time between t0 and t5, and when the rising edge of pulse 614-2 is received by the ADC, the data sensed by the sensor 404 is converted for a certain period of time between t5 and t10. For example, the ADC converts the data sensed by the sensor 404 from analog to digital format, starting from time t0 and continuing until a certain period of time is reached. The ADC stops sampling the data sensed by the sensor 404 after a certain period of time until the next consecutive pulse of the synchronization signal 614 is received by the ADC. For example, the ADC stops converting the data from time t3 to time t5. The ADC starts again from time t5 and converts the data sensed by the sensor 404 from analog to digital until a certain period of time is reached.

[0231] In one embodiment, instead of starting data collection by the sensor 404 at the rising edge of the pulse of the synchronization signal 614, collection is started for a fixed time period, which begins at the falling edge of the pulse. In this embodiment, the ADC connected to the sensor 404 converts the data sensed by the sensor 404 from analog to digital format at the time of the falling edge of each pulse of the synchronization signal 614 received by the ADC. The ADC converts the data sensed by the sensor 404 for a fixed time period after the falling edge of the pulse of the synchronization signal 614. For example, after the falling edge of pulse 614-1 is received by the ADC, the ADC converts the data sensed by the sensor 404 for a fixed time period between times t2 and t3. The fixed time period begins at time t2. After the fixed time period, the ADC stops sampling the data sensed by the sensor 404 until the falling edge of the next consecutive pulse of the synchronization signal 614, such as pulse 614-2, is received by the ADC. The ADC further transforms the data sensed by sensor 404 for a certain period of time after the falling edge of pulse 614-2. For example, suppose pulse 614-2 transitions from logic level 1 to logic level 0 at time t7 instead of at time t6. The ADC starts at time t7 and transforms the data sensed by sensor 404 until a certain period of time is reached.

[0232] Figure 7 shows one embodiment of system 700 to illustrate the use of one, for example, a single EtherCAT train instead of multiple EtherCAT trains to transfer a pulsed preset signal 138 from the module controller to the bias match. System 700 includes the same components as system 400 in Figure 4, except that it does not use a communication cable 126 connecting the TCP generator to the bias generator 1. Rather, system 700 includes a communication cable 702 connecting the TCP generator to the TCP match, a communication cable 704 connecting the TCP match to the bias generator 1, and a communication cable 708 connecting the bias generator 2 to the bias match.

[0233] Furthermore, the TCP generator includes sensor 710, bias generator 1 includes sensor 712, and bias generator 2 includes sensor 714. Examples of each sensor 710, 712, and 714 are voltage sensors, current sensors, complex voltage-current sensors, or power sensors. For example, the data sensed by each sensor 710, 712, and 714 includes voltage values, current values, power values, or complex current-voltage values. The pulse controller is connected to the TCP generator via transfer cable 716, to bias generator 1 via transfer cable 718, and to bias generator 2 via transfer cable 720.

[0234] Furthermore, in system 700, the pulsed preset signal 138 includes the same instructions as those included in the factor control signal 415 (Figure 4). For example, the pulsed preset signal 138 includes instructions to the controller in the TCP match to change the TCP match factors to achieve a predetermined factor. The pulsed preset signal 138 further includes other instructions to the controller in the bias match to change the bias match factors to achieve a pre-set factor.

[0235] The pulsed preset signal 138 is transmitted from the TCP generator to the TCP match via the communication cable 702. Upon receiving the pulsed preset signal 138, the TCP match applies an instruction to change the TCP match's factors to achieve a predetermined factor and transmits the pulsed preset signal 138 to the bias generator 1 via the communication cable 704. The bias generator 1 applies the same function to the pulsed preset signal 138 as described above with respect to Figure 1 and transmits the pulsed preset signal to the bias generator 2 via the communication cable 128. The bias generator 2 applies the same function to the pulsed preset signal 138 as described above with respect to Figure 1 and transmits the pulsed preset signal 138 to the bias match via the communication cable 708.

[0236] Upon receiving the pulsed preset signal 138, the bias match applies a command to modify the bias match factor to achieve the pre-set factor. Also, when the pulsed preset signal 138 is received from the bias generator 2, the bias match's match controller receives and collects the data sensed by the sensor 404 using the method described above, referring to Figure 4. The collected data is accessed by the bias match's match controller. The collected data is then embedded in the pulsed preset signal 138 by the bias match. After embedding the data, the bias match transmits the pulsed preset signal 138 to the bias generator 2 via the communication cable 708.

[0237] The pulse controller generates a synchronization signal 724 and transmits it to the TCP generator via the transfer cable 716. Similarly, the pulse controller generates a synchronization signal 726 and transmits it to the bias generator 1 via the transfer cable 718. The pulse controller also generates a synchronization signal 728 and transmits it to the bias generator 2 via the transfer cable 720.

[0238] In response to the reception of the synchronization signal 728, the controller in bias generator 2 controls the ADC of bias generator 2 to collect data sensed by sensor 714 in synchronization with the synchronization signal 728. To send the collected data back to the pulse controller, the collected data is transmitted from bias generator 2 to bias generator 1 via the communication cable 128. For example, the synchronization signal 728 includes a series of pulses, including a first pulse and a second pulse. In response to the reception of the first pulse of the synchronization signal 728 with respect to a first time interval, the controller of bias generator 2 controls the ADC connected to sensor 714 to convert the data sensed by sensor 714 from analog to digital with respect to the first time interval and outputs digital data with respect to the first time interval. The controller of bias generator 2 receives the digital data output from the ADC with respect to the first time interval and stores the digital data in the controller's memory device. When the pulsed preset signal 138 is received from bias match, the controller accesses the digital data with respect to the first time interval from the memory device. Digital data relating to the first time interval is embedded in the pulsed preset signal 138 and transmitted to the bias generator 1 via the communication cable 128. Similarly, in response to the reception of the second pulse of the synchronization signal 728 relating to the second time interval, the controller of the bias generator 2 controls the ADC connected to the sensor 714 to convert the data sensed by the sensor 714 from analog to digital format relating to the second time interval and outputs digital data relating to the second time interval. The controller of the bias generator 2 receives the digital data output from the ADC of the bias generator 2 relating to the second time interval and stores the digital data in the controller's memory device. When the pulsed preset signal 138 is received from the bias match, the controller of the bias generator 2 accesses the digital data relating to the second time interval from the memory device of the bias generator 2. The digital data relating to the second time interval is embedded in the pulsed preset signal 138 and transmitted to the bias generator 1 via the communication cable 128.During time intervals when the pulse of the synchronization signal 728 is not received by the bias generator 2, the controller of the bias generator 2 does not control the ADC of the bias generator 2 to convert the data sensed by the sensor 714 from analog to digital.

[0239] Similarly, in response to the reception of the synchronization signal 726, the controller in the bias generator 1 controls the ADC of the bias generator 1 to collect data sensed by the sensor 712 in synchronization with the synchronization signal 726. The collected data is then sent to TCP Match via the communication cable 704 to send the collected data back to the pulse controller. For example, the synchronization signal 726 includes a series of pulses, including a first pulse and a second pulse. In response to the reception of the first pulse of the synchronization signal 726 with respect to a first time interval, the controller of the bias generator 1 controls the ADC connected to the sensor 712 to convert the data sensed by the sensor 712 from analog to digital with respect to the first time interval and output digital data with respect to the first time interval. The controller of the bias generator 1 receives the digital data output from the ADC with respect to the first time interval and stores the digital data in the controller's memory device. When the pulsed preset signal 138 is received from the bias generator 2, the controller accesses the digital data for the first time interval from the memory device, embeds the digital data into the pulsed preset signal 138, and transmits it to TCP Match via the communication cable 704. Similarly, in response to the reception of the second pulse of the synchronization signal 726 for the second time interval, the controller of bias generator 1 controls the ADC connected to the sensor 712 to convert the data sensed by the sensor 712 from analog to digital format for the second time interval, and outputs the digital data for the second time interval. The controller of bias generator 1 receives the digital data output from the ADC of bias generator 1 for the second time interval and stores the digital data in the controller's memory device. When the pulsed preset signal 138 is received from bias generator 1, the controller of bias generator 1 accesses the digital data for the second time interval from the memory device of bias generator 1, embeds the digital data into the pulsed preset signal 138, and transmits it to TCP Match via the communication cable 704.During time intervals when the pulse of the synchronization signal 726 is not received by the bias generator 1, the controller of the bias generator 1 does not control the ADC of the bias generator 1 to convert the data sensed by the sensor 712 from analog to digital.

[0240] When the pulsed preset signal 138 is received from the bias generator 1, the TCP match controller accesses the data sensed by the sensor 402 from the match controller's memory device. The accessed data is embedded in the pulsed preset signal 138 by the TCP match and transmitted to the TCP generator via the communication cable 702.

[0241] In response to receiving the synchronization signal 724, the controller in the TCP generator controls the ADC of the TCP generator to collect data sensed by the sensor 710 in synchronization with the synchronization signal 724. The collected data is transmitted from the TCP generator to the pulse controller. For example, the synchronization signal 724 includes a series of pulses, including a first pulse and a second pulse. In response to receiving the first pulse of the synchronization signal 724 with respect to a first time interval, the TCP generator controller controls the ADC connected to the sensor 710 to convert the data sensed by the sensor 710 from analog to digital with respect to the first time interval and outputs digital data with respect to the first time interval. The TCP generator controller receives the digital data output from the ADC with respect to the first time interval and stores the digital data in the controller's memory device. When the pulsed preset signal 138 is received from the TCP generator, the TCP generator controller accesses the digital data with respect to the first time interval from the memory device. Digital data relating to the first time interval is embedded in the pulsed preset signal 138 and transmitted to the pulse controller via the communication cable 118. Similarly, in response to the reception of the second pulse of the synchronization signal 724 relating to the second time interval, the TCP generator controller controls the TCP generator's ADC to convert the data sensed by the sensor 710 from analog to digital format relating to the second time interval and outputs the digital data relating to the second time interval. The TCP generator controller receives the digital data output from the ADC relating to the second time interval and stores the digital data in the controller's memory device. When the pulsed preset signal 138 is received from the TCP match, the controller accesses the digital data relating to the second time interval from the memory device. The digital data relating to the second time interval is embedded in the pulsed preset signal 138 and transmitted to the pulse controller via the communication cable 118. During time intervals in which the pulse of the synchronization signal 724 is not received by the TCP generator, the TCP generator controller does not control the ADC to convert the data sensed by the sensor 710 from analog to digital format.

[0242] In response to receiving data sensed by one or more of sensors 710, 402, 712, 714, and 404, the pulse controller controls one or more components such as the TCP generator, bias generator 1, bias generator 2, TCP match, and bias match. For example, if the pulse controller determines that the reflected power sensed by sensor 710 is high, it controls the TCP generator to change the power level of the RF signal 102 (Figure 1) and reduces the amount of power supplied by the TCP generator.

[0243] In one embodiment, the sensor 710 is located outside the TCP generator and connected to the TCP generator's output O1.

[0244] In one embodiment, the sensor 712 is located outside the bias generator 1 and connected to the output O3 of the bias generator 1.

[0245] In one embodiment, the sensor 714 is located outside the bias generator 2 and connected to the output O4 of the bias generator 2.

[0246] In one embodiment, the functions described herein as being performed by the controller are performed by the controller's processor.

[0247] In one embodiment, the system 700 does not include one or more of the sensors 710, 712, and 714.

[0248] Figure 8 shows one embodiment of System 800 to illustrate that sensor data is transmitted from the sensor to the pulse controller via an Ethernet cable, rather than via an EtherCAT train. System 800 is structurally and functionally the same as System 300 in Figure 3, except that it includes sensors 402 and 404, a voltage sensor system 410, and an OES system 412. System 800 further includes an Ethernet cable 802 connecting the TCP match to the pulse controller, another Ethernet cable 804 connecting the bias match to the pulse controller, an Ethernet cable 806 connecting the voltage sensor system 410 to the pulse controller, and another Ethernet cable 808 connecting the OES system 412 to the pulse controller.

[0249] In response to receiving the synchronization signal 416 via the transfer cable 120, the ADC connected to the sensor 402, in synchronization with the pulses of the synchronization signal 416, converts the data sensed by the sensor 402 from analog to digital format, outputs digital measurement data, and provides the digital measurement data to the TCP match match controller. The TCP match match controller transmits the digital measurement data to the pulse controller via the Ethernet cable 802.

[0250] Similarly, upon receiving the synchronization signal 418 via the transfer cable 417, the ADC connected to the sensor 404 synchronizes with the pulses of the synchronization signal 418 to convert the data sensed by the sensor 404 from analog to digital format, outputting digital measurement data and providing it to the TCP match controller. The bias match controller transmits the digital measurement data to the pulse controller via the Ethernet cable 804.

[0251] Furthermore, in response to receiving the synchronization signal 426 via the transfer cable 420, the ADC of the voltage sensor system 410, in synchronization with the pulse of the synchronization signal 426, converts the data sensed by the voltage sensor of the voltage sensor system 410 from analog to digital format, outputs digital measurement data, and transmits the digital measurement data to the controller of the voltage sensor system 410. The controller of the voltage sensor system 410 transmits the digital measurement data to the pulse controller via the Ethernet cable 806.

[0252] Similarly, upon receiving the synchronization signal 428 via the transfer cable 422, the ADC of the OES system 412, in synchronization with the pulses of the synchronization signal 428, converts the data sensed by the OES of the OES system 412 from analog to digital format, outputs digital measurement data, and transmits the digital measurement data to the controller of the OES system 412. The controller of the OES system 412 transmits the digital measurement data to the pulse controller via the Ethernet cable 808.

[0253] In one embodiment, the TCP generator includes a sensor 710 (Figure 7) and is connected to a pulse controller via an Ethernet cable. Upon receiving multiple pulses of the synchronization signal 724 (Figure 7) via a transfer cable 716 (Figure 7), the ADC of the TCP generator, in synchronization with the pulses, converts the data sensed by the sensor 710 from analog to digital and outputs digital measurement data. The TCP generator transmits the digital measurement data to the pulse controller via the Ethernet cable.

[0254] In one embodiment, the bias generator 1 includes a sensor 712 (Figure 7) and is connected to a pulse controller via an Ethernet cable. Upon receiving multiple pulses of the synchronization signal 726 (Figure 7) via a transfer cable 718 (Figure 7), the ADC of the bias generator 1, in synchronization with the pulses, converts the data sensed by the sensor 712 from analog to digital and outputs digital measurement data. The bias generator 1 transmits the digital measurement data to the pulse controller via the Ethernet cable.

[0255] In one embodiment, the bias generator 2 includes a sensor 714 (Figure 7) and is connected to a pulse controller via an Ethernet cable. Upon receiving multiple pulses of the synchronization signal 728 via the transfer cable 720 (Figure 7), the ADC of the bias generator 2, in synchronization with the pulses, converts the data sensed by the sensor 714 from analog to digital and outputs digital measurement data. The bias generator 2 transmits the digital measurement data to the pulse controller via the Ethernet cable.

[0256] In one embodiment, a connecting cable is used instead of each of the Ethernet cables 802 and 804.

[0257] In one embodiment, instead of Ethernet cables for each sensor of the RF generator described herein, a connecting cable is used to transfer digital measurement data from the RF generator to the pulse controller.

[0258] Figure 9 is a diagram of one embodiment of the RF generator 900 to illustrate the components of the RF generator 900. The RF generator 900 is an example of a TCP generator, bias generator 1, or bias generator 2 (Figure 1). The RF generator 900 includes a communication controller 902 and a digital signal processor (DSP) 904. The RF generator 900 further includes several parameter controllers. For example, the RF generator 900 includes a parameter controller for each state. For example, the RF generator 900 includes a parameter controller PCS0 for state S0 of the RF signal 906 generated by the RF generator 900 and a parameter controller PCSn for state Sn of the RF signal 906, where n is a positive integer. Examples of parameters include power and voltage. In another example, the RF generator 900 includes a frequency controller for each state. For example, the RF generator 900 includes a frequency controller FCS0 for state S0 of the RF signal 906 and a parameter controller FCSn for state Sn of the RF signal 906.

[0259] RF signal 906 is an example of RF signals 102, 104, or 106 (Figure 1). For example, if RF generator 900 is a TCP generator, RF signal 906 is an example of RF signal 102, and if RF generator 900 is bias generator 1, RF signal 906 is an example of RF signal 104.

[0260] The RF generator 900 includes a driver system 908, which includes one or more drivers connected to each other. An example of each driver is a transistor. The RF generator 900 includes a power supply 910, such as an electronic oscillator or RF oscillator, which generates a sinusoidal RF signal or sinusoidal RF waveform. The RF generator 900 further includes a sensor 912 and an ADC 904. Sensor 912 is an example of sensor 710, sensor 712, or sensor 714 (Figure 7).

[0261] The DSP904 is connected to the communication controller 902, the parameter controllers PCS0 to PCSn, and the frequency controllers FCS0 to FCSn. The DSP904 is connected to the transfer cable 916. Transfer cable 916 is an example of transfer cable 120, transfer cable 122, or transfer cable 124 (Figure 1). The DSP904 is connected to another transfer cable 918, which is an example of transfer cable 716 (Figure 7), transfer cable 718 (Figure 7), or transfer cable 720 (Figure 7).

[0262] Controllers PRS0 to PRSn and frequency controllers FCS0 to FCSn are connected to driver system 908, which is connected to power supply 910. The output of power supply 910 is connected to sensor 912. Sensor 912 is connected to ADC 914, which is connected to DSP 904.

[0263] The communication controller 902 includes ports 920 and 922. Port 920 is connected to communication cable 924, and port 922 is connected to communication cable 926. If the RF generator 900 is a TCP generator, communication cable 924 is an example of communication cable 118 (Figure 1), and communication cable 926 is an example of communication cable 126 (Figure 1). Also, if the RF generator 900 is bias generator 1, communication cable 924 is an example of communication cable 126 (Figure 1), and communication cable 926 is an example of communication cable 128 (Figure 1). Furthermore, if the RF generator 900 is bias generator 1, communication cable 924 is an example of communication cable 704 (Figure 7), and communication cable 926 is an example of communication cable 128 (Figure 7). When RF generator 900 is bias generator 2, communication controller 902 does not include port 926, and communication cable 924 is an example of communication cable 128 (Figures 1 and 7).

[0264] The communication controller 902 receives the pulsed preset signal 138 via port 920 and determines whether the address in the pulsed preset signal 138 matches a pre-stored address of the RF generator 900. The pre-stored address is stored in one or more memory devices of the communication controller 902. The module controller or pulse controller (Figure 1) embeds the address of the RF generator 900 in the pulsed preset signal 138. If the communication controller 902 determines that the address in the pulsed preset signal 138 matches a pre-stored address of the RF generator 900, it extracts information about the duty cycle and variables of the RF signal 906 and transmits this information to the DSP 904. The communication controller 902 also extracts information about a portion of the cycle of the master clock signal 141 that generates multiple states of the RF signal 906 and provides this information to the DSP 904.

[0265] The DSP904 identifies information regarding the duty cycle and parameter level for each state of the RF signal 906 parameters from the duty cycle and variable information, and further identifies information regarding the duty cycle and frequency level for each state of the RF signal 906 frequency. The DSP904 transmits the duty cycle and parameter level for state S0 to the parameter controller PRS0 for storage in one or more memory devices of the parameter controller PRS0, and transmits the duty cycle 0 and parameter level for state Sn to the parameter controller PRSn for storage in one or more memory devices of the parameter controller PRSn. The DSP904 also transmits the duty cycle 0 and frequency level for state S0 to the frequency controller FCS0 for storage in one or more memory devices of the frequency controller FCSn, and transmits the duty cycle and frequency level for state Sn to the frequency controller FCSn for storage in one or more memory devices of the frequency controller FCSn.

[0266] When a pulse of synchronization signal 928 is received via the transfer cable 916, the DSP 904 transmits the pulse to the parameter controllers PRS0~PCSn and frequency controllers FCS0~FCSn. Synchronization signal 928 is an example of synchronization signals 140, 142, or 144 (Figure 1). Upon receiving a pulse of synchronization signal 928, the parameter controller PRS0 generates a current signal based on the parameter level of RF signal 906 relating to state S0, with respect to the duty cycle time interval of state S0, and transmits the current signal to the driver system 908. Also upon receiving a pulse of synchronization signal 928, the frequency controller FCS0 generates a current signal based on the frequency level of RF signal 906 relating to state S0, with respect to the duty cycle time interval of state S0, and transmits the current signal to the driver system 908. Upon receiving current signals relating to state S0 from controllers PCS0 and FCS0, the driver system 908 generates a current signal relating to state S0 and transmits the current signal to the power supply 910. Upon receiving the current signal, the power supply 910 generates the parameter and frequency state S0 of the RF signal 906.

[0267] Similarly, upon receiving a pulse of the synchronization signal 928, the parameter controller PRSn generates a current signal for the duty cycle time interval of state Sn based on the parameter level for state Sn of the RF signal 906 and transmits the current signal to the driver system 908. Also upon receiving a pulse of the synchronization signal 928, the frequency controller FCSn generates a current signal for the duty cycle time interval of state S0 based on the frequency level for state Sn of the RF signal 906 and transmits the current signal to the driver system 908. Upon receiving the current signals for state Sn from controllers PCSn and FCSn, the driver system 908 generates a current signal for state Sn and transmits the current signal to the power supply 910. Upon receiving the current signal, the power supply 910 generates the parameter and frequency state Sn of the RF signal 906. Similarly, for each additional pulse of the synchronization signal 928, the parameter and frequency states S0 to Sn of the RF signal 906 are generated by the power supply 910.

[0268] It should be noted that during time intervals in which the synchronization signal 928 pulses are not received by the DSP 904, the variable state of the RF signal 906 is not generated by the power supply 910. For example, during time intervals in which the synchronization signal 928 does not contain pulses, the DSP 904 does not control the controllers PCS0~PCSn and frequency controllers FCS0~FCSn to generate the variable states S0~Sn of the RF signal 906. For example, the RF signal 902 has a power level of 0 during time intervals in which the synchronization signal 928 does not contain pulses.

[0269] Based on information about a portion of the cycle of the master clock signal 141, which generates multiple states of the RF signal 906, the DSP 904 transmits different variable levels and different duty cycles to controllers PCS0~PCSn and FCS0~FCSn. For example, if the DSP 904 determines that the pulse count of the synchronization signal 928 has been exceeded, it transmits different variables and different duty cycles to controllers PCS0~PCSn and FCS0~FCSn than those transmitted before the count was exceeded. As another example, if the DSP 904 determines that the time interval of cycle 1 has elapsed since receiving a pulse of the synchronization signal 928, it transmits different variables and different duty cycles to controllers PCS0~PCSn and FCS0~FCSn than those transmitted before the time interval elapsed.

[0270] When the RF signal 906 is generated, the sensor 912 senses data such as voltage, current, complex voltage / current sensor, or power at the output of the power supply 910 and provides the measurement data to the ADC 914. The DSP 904 receives the synchronization signal 930 via the transfer cable 918 and transmits the synchronization signal 930 to the ADC 914. During the time intervals in which pulses of the synchronization signal 930 are received, the ADC 914 converts the measurement data from analog to digital format and outputs digital measurement data, which is then transmitted to one or more memory devices of the DSP 904. During the time intervals in which the synchronization signal 930 does not pulse, the ADC 914 does not convert the measurement data from analog to digital format, and no digital measurement data is output from the ADC 914. The synchronization signal 930 is an example of the synchronization signals 724, 726, or 728 (Figure 7).

[0271] The pulsed preset signal 138 is received by the communication controller 902 at port 926. While the pulsed preset signal 138 is being transferred from port 926 to port 920, the communication controller 902 sends a request to the DSP 904 for digital measurement data stored in one or more memory devices of the DSP 904. Upon receiving the request, the DSP 904 accesses the digital measurement data from one or more memory devices of the DSP 904 and sends the digital measurement data to the communication controller 902. The communication controller 902 embeds the digital measurement data within the pulsed preset signal 138 and transmits the pulsed preset signal 138 to the communication cable 924 via port 920.

[0272] In one embodiment, where the communication controller 902 includes port 920 but does not include port 922, the pulsed preset signal 138 is received at port 920 and routed back to port 920 via the communication controller 902. While the pulsed preset signal 138 is routed back to port 920, a request for digital measurement data is generated by the communication controller 902, and the received digital measurement data is embedded within the pulsed preset signal 138.

[0273] In one embodiment, the functions described herein as being performed by a communication controller are performed by the processor of the communication controller.

[0274] In embodiments where one or more Ethernet cables are used for point-to-point communication, one or more Ethernet cables are connected to the DSP 904. In this embodiment, the RF generator 900 does not include a communication controller 902 used to generate EtherCAT trains, but includes a communication controller for generating Ethernet packets and for extracting information from Ethernet packets.

[0275] In one embodiment, the DSP904 is an example of a controller.

[0276] In one embodiment, the functions described herein as being performed by the DSP904, controllers PCS0 to PCSn, and controllers FCS0 to FCSn are performed by one or more controllers.

[0277] In one embodiment, there is a switch connected to the DSP904, such as one or more transistors connected to each other. The switch connects the ADC914 to the sensor912. Upon receiving a pulse of the synchronization signal 928, the DSP904 controls the switch to turn it on. By turning the switch on, the ADC914 can acquire data from the sensor912 and convert the data from analog to digital format. For example, the DSP904 controls the switch to turn on for a certain period of time, starting from the time the pulse of the synchronization signal 928 is received by the DSP904. After the period of time, the DSP904 controls the switch to turn it off. By turning the switch off, the ADC914 can no longer receive data sensed by the sensor912 and convert the data from analog to digital format. In another example, the DSP904 controls the switch to turn on for a time interval in which the pulse of the synchronization signal 928 has logic level 1. During the time in which the pulse transitions to logic level 0, the DSP904 controls the switch to turn it off.

[0278] Figure 10 shows an embodiment of controller 1000, which is an example of a pulse controller or module controller (Figure 1). Controller 1000 includes a processor 1002, a memory device 1004, and a communication controller 1006. The processor 1002 is connected to the memory device 1004 and the communication controller 1006. The communication controller 1006 includes port 1008 and another port 1010.

[0279] Port 1008 is connected to communication cable 1012, and port 1010 is connected to another communication cable 1014. Note that if controller 1000 is a module controller, communication controller 1006 does not include port 1008. Also, if communication controller 1006 is a module controller, communication cable 1014 is an example of communication cable 116 (Figure 1). If communication controller 1006 is a pulse controller, communication cable 1012 is an example of communication cable 116, and communication cable 1014 is an example of communication cable 118 (Figure 1). Processor 1002 is connected to transfer cable 1016, which is an example of transfer cables 120, 122, 124, 414, 417, 420, or 422 (Figure 4), or 716, 718, or 720 (Figure 7).

[0280] If controller 1000 is a modular controller, communication controller 1002 generates a preset signal 1020, such as a pulsed preset signal 138 (Figure 1) or a factor control signal 415 (Figure 4), and transmits the preset signal 1020 to the pulse controller via communication cable 1014. For example, processor 1002 receives information from the user via an input device regarding the duty cycle and variables of RF signals 102, 104, and 106, and provides the information to communication controller 1006. Communication controller 1006 embeds the information received from processor 1002 into the EtherCAT train and transmits the EtherCAT train to the pulse controller via communication cable 1014. Communication controller 1002 further embeds the addresses of one or more components of system 400 to which the EtherCAT train is transmitted. Examples of components of system 400 include a TCP generator, bias generator 1, bias generator 2, TCP match, and bias match. Examples of input devices include a mouse, keyboard, touchscreen, and stylus. The input devices are connected to processor 1002.

[0281] As another example, the processor 1002 receives a predetermined factor related to the TCP match and a preset factor related to the bias match from the input device, and changes the factors to generate commands for the match controller in the TCP match to realize the predetermined factor and commands for the match controller in the bias match to change the factor of the bias match to realize the preset factor. The processor 1002 provides the commands for the match controller in the TCP match to change the factors to realize the predetermined factor and the commands for the match controller in the bias match to change the factor of the bias match to realize the preset factor to the communication controller 1006. The communication controller 1006 embeds the commands received from the processor 1002 and the addresses of the components of the system 400 in the EtherCAT train. Examples of the components of the system 400 to which the EtherCAT train such as the factor control signal 415 is transmitted include the TCP match and the bias match. The communication controller 1006 transmits the EtherCAT train to the pulse controller via the communication cable 1014.

[0282] When the communication controller 1000 is the pulse controller, the communication controller 1000 receives the pulsed preset signal 138 or the factor control signal 415 from the module controller via the communication cable 1012 at the port 1012. The communication controller 1000 transmits the pulsed preset signal 138 or the factor control signal 415 via the port 1010 and the communication cable 1014.

[0283] In an embodiment where the controller 1000 is the pulse controller and one or more Ethernet cables are used for point-to-point communication, the Ethernet cable is connected to the processor 1002. Also, in this embodiment, the controller 1000 does not include the communication controller 1006 used to generate the EtherCAT train, but includes a communication controller for generating Ethernet packets and extracting information from the Ethernet packets.

[0284] When the controller 1000 is a pulse controller, the processor 1002 generates a synchronization signal 1018 and transmits the synchronization signal 1018 via the transfer cable 1016. The synchronization signal 1018 is an example of the synchronization signals 140, 142, 144, 416, 418, 426, or 428 (FIG. 4), or 724, 726, or 728 (FIG. 7).

[0285] In one embodiment, the communication controller 1000 includes a third port connected to a third communication cable. The factor control signal 415 is transmitted via the third communication cable.

[0286] In one embodiment, the controller 1000 includes any number of processors and any number of memory devices, and the processors are connected to the memory devices. The processors perform the same functions as those performed by the processor 1002.

[0287] FIG. 11 is a diagram of one embodiment of a match 1100, and the match 1100 is an example of a TCP match or a bias match (FIG. 1). The match 1100 includes a communication controller 1102, a processor 1104, a memory device 1106, a driver system 1108, a motor system 1110, a network 1112 of circuit components, an ADC 1114, and a sensor 1116. The processor 1104 and the memory device 1106 are components of the match controller 1117 of the match 1100. The sensor 1116 is an example of the sensors 402 or 404 (FIG. 4). The communication controller 1102 includes a port 1118 and another port 1120.

[0288] The driver system 1108 includes one or more drivers connected to each other. The motor system 1110 includes one or more electric motors. Each motor is connected to circuit components such as a variable inductor or a variable capacitor of the match 1100. The network 1112 includes circuit components such as resistors, capacitors, or inductors, or combinations thereof.

[0289] The processor 1104 is connected to the memory device 1106 and the communication controller 1102. The processor 1104 is also connected to the driver system 1108, which in turn is connected to the motor system 1110. The ADC 1114 is connected to the sensor 1116 and the processor 1104.

[0290] The processor 1104 is connected to the transfer cable 1126. Transfer cable 1126 is an example of transfer cable 414 or 417 (Figure 4). Port 1118 is connected to communication cable 1122, and port 1120 is connected to communication cable 1124. If match 1100 is a TCP match, communication cable 1122 is an example of communication cable 406, and communication cable 1124 is an example of communication cable 408 (Figure 4). If match 1100 is a bias match, the communication controller 1102 does not include port 1120. Also, if match 1100 is a bias match, communication cable 1122 is an example of communication cable 408.

[0291] Sensor 1116 is connected to network 1112. For example, sensor 1116 is connected to the input or output of network 1112. For example, if network 1112 includes a single branch circuit connected to a single RF generator such as a TCP generator, sensor 1116 is connected to the input of the signal branch circuit, and the input is between the RF generator and the single branch circuit. As another example, if network 1112 includes a single branch circuit connected to a single RF generator such as a TCP generator, sensor 1116 is connected to the output of the signal branch circuit, and the output is between the single branch circuit and the plasma chamber 108 (Figure 1). As yet another example, if network 1112 includes a first branch circuit connected to bias generator 1 and a second branch circuit connected to bias generator 2, sensor 1116 is connected to the outputs of the first and second branch circuits, or to the input of the first branch circuit, or to the input of the second branch circuit. The input of the first branch circuit is located between the first branch circuit and bias generator 1, and the input of the second branch circuit is located between the second branch circuit and bias generator 2. The first and second branch circuits are connected to each other at their outputs, which are connected to the substrate support 110 (Figure 1) via RF transmission line 139 (Figure 1).

[0292] The communication controller 1102 receives a preset signal 1128, such as a pulsed preset signal 138 or a factor control signal 415, via the communication cable 1122 and port 1118, and determines whether the address in the preset signal 1128 matches a pre-stored address of the match 1100. The pre-stored address is stored in one or more memory devices of the communication controller 1102. The module controller or pulse controller (Figure 1) embeds the address of the match 1100 in the preset signal 1128. If the communication controller 1102 determines that the address in the preset signal 1128 matches a pre-stored address of the match 1100, it extracts an instruction to realize a pre-fixed factor, such as an instruction to realize a predetermined factor or an instruction to realize a pre-set factor, from the preset signal 1128 and sends the instruction to the processor 1104.

[0293] The processor 1104 identifies pre-fixed factors from the instructions. The processor 1104 generates and transmits a control signal to execute the instructions to realize the pre-fixed factors and transmits the control signal to the driver system 1108. Upon receiving the control signal, the driver system 1108 generates a drive signal and transmits the drive signal to the motor system 1110. The motor of the motor system 1110 operates based on the drive signal. When the motor operates, the circuit components of the network 1112 are controlled to realize the pre-fixed factors. For example, when the motor operates, the plate of a variable capacitor moves relative to another plate of the variable capacitor to realize the pre-fixed capacitance.

[0294] If match 1100 is a TCP match, the communication controller 1102 decides to send a preset signal 1128 to the bias match. The decision is based on a comparison between the bias match's address in the preset signal 1128 and the bias match's pre-stored address. The bias match's pre-stored address is stored in one or more memory devices of the communication controller 1102. The communication controller 1102 sends the preset signal 1128 to the bias match via port 1120 and communication cable 1124.

[0295] Sensor 1116 senses data such as voltage, current, complex voltage / current sensor, or power, and provides the measurement data to ADC 1114. Processor 1126 receives a synchronization signal 1130 via transfer cable 1126 and transmits the synchronization signal 1130 to ADC 1114. During the time intervals in which pulses of the synchronization signal 1130 are received, ADC 1114 converts the measurement data from analog to digital format and outputs digital measurement data, and transmits the digital measurement data to processor 1104 for storage in memory device 1106. For example, processor 1104 collects the digital measurement data received from ADC 1114 into memory device 1106, for example, by storing or writing it. Also, during time intervals in which there are no pulses of the synchronization signal 1130, ADC 1114 does not convert the measurement data from analog to digital format, and no digital measurement data is output from ADC 1114. Synchronization signal 1130 is an example of synchronization signal 416 or 418 (Figure 4).

[0296] The pulsed preset signal 1128 is received by the communication controller 1102 at port 1120. While the pulsed preset signal 1128 is being transferred from port 1120 to port 1118, the communication controller 1102 sends a request to the processor 1104 for digital measurement data stored in the memory device 1106. Upon receiving the request, the processor 1104 accesses the digital measurement data from the memory device 1106 and sends the digital measurement data back to the communication controller 1102. The communication controller 1102 embeds the digital measurement data within the pulsed preset signal 1128 and sends the pulsed preset signal 1124 to the communication cable 1122 via port 1118.

[0297] In one embodiment, where the communication controller 1102 includes port 1118 but does not include port 1120, the pulsed preset signal 1128 is received at port 1118 and routed back to port 1118 via the communication controller 1102. While the pulsed preset signal 1128 is routed back to port 1118, a request for digital measurement data stored in the memory device 1106 is generated by the communication controller 1102. The digital measurement data is received by the communication controller 1102 and embedded in the pulsed preset signal 1128.

[0298] In embodiments where one or more Ethernet cables are used for point-to-point communication, the Ethernet cables are connected to the processor 1104. In this embodiment, the match 1100 does not include the communication controller 1102 used to generate the EtherCAT train, but includes a communication controller for generating Ethernet packets and for extracting information from the Ethernet packets.

[0299] In one embodiment, the sensor 1116 is positioned outside the match 1110.

[0300] In one embodiment, the processor 1104, memory device 1106, ADC 1114, and sensor 1116 are components of a sensor system.

[0301] In one embodiment, there is a switch connected to the processor 1104, such as one or more transistors connected to each other. The switch connects the processor 1104 to the sensor 1116. Upon receiving a pulse of the synchronization signal 1130, the processor 1104 controls the switch to turn it on. Turning the switch on enables the ADC 1114 to acquire data from the sensor 1116 and convert the data from analog to digital format. For example, the processor 1104 controls the switch to turn it on for a certain period of time, starting from the time the pulse of the synchronization signal 1130 is received by the processor 1104. After the period of time, the processor 1104 controls the switch to turn it off. Turning the switch off prevents the ADC 1114 from receiving data sensed by the sensor 1116 and converting the data from analog to digital format. In another example, the processor 1104 controls the switch to turn it on with respect to a time interval in which the pulse of the synchronization signal 1130 has a logic level of 1. During the time it takes for the pulse to transition to logic level 0, the processor 1104 controls the switch to turn it off.

[0302] Figure 12 shows an embodiment of the sensor system 1200, which is an example of an OES system 412 (Figure 4) or a voltage sensor system 414 (Figure 4). The sensor system 1200 includes a processor 1202, a memory device 1204, an ADC 1206, and a sensor 1208. The sensor 1208 is an example of an OES in the OES system 412 or a voltage sensor in the voltage sensor system 414. The processor 1202 and the memory device 1204 are components of the controller 1203 of the sensor system 1200.

[0303] Processor 1202 is connected to transfer cable 1210, which is an example of transfer cable 420 or 422 (FIG. 4). Processor 1202 is connected to memory device 1204 and ADC 1206, and ADC 1206 is connected to sensor 1208.

[0304] Sensor 1208 senses data such as voltage or intensity and provides measurement data to ADC 1206. Processor 1202 receives synchronization signal 1212 via transfer cable 1210 and transmits synchronization signal 1212 to ADC 1206. During the time interval when the pulse of synchronization signal 1212 is received, ADC 1206 converts the measurement data from analog format to digital format, outputs digital measurement data, and transmits the digital measurement data to processor 1202. Processor 1202 transmits the measurement data regarding the time interval via transfer cable 1212. Also, during the time interval when synchronization signal 1212 has no pulse, ADC 1206 does not convert the measurement data from analog format to digital format, and digital measurement data is not output from ADC 1206. Synchronization signal 1212 is an example of synchronization signal 426 or 428 (FIG. 4).

[0305] In one embodiment, there is a switch connected to the processor 1202, such as one or more transistors connected to each other. The switch connects the processor 1202 to the sensor 1208. Upon receiving a pulse of the synchronization signal 1212, the processor 1202 controls the switch to turn it on. Turning the switch on enables the ADC 1206 to acquire data from the sensor 1208 and convert the data from analog to digital format. For example, the processor 1202 controls the switch to turn it on for a certain period of time, starting from the time the pulse of the synchronization signal 1212 is received by the processor 1202. After the period of time, the processor 1202 controls the switch to turn it off. Turning the switch off prevents the ADC 1206 from receiving data sensed by the sensor 1208 and converting the data from analog to digital format. In another example, the processor 1202 controls the switch to turn it on for a time interval in which the pulse of the synchronization signal 1212 has logic level 1. During the time it takes for the pulse to transition to logic level 0, the processor 1202 controls the switch to turn it off.

[0306] Figure 13 shows graph 1300 illustrating the clock signal 1302. The clock signal 1302 is an example of the master clock signal 141 (Figure 1). Graph 1300 plots the logic level of the clock signal 1302 on the y-axis and time t on the x-axis. The clock signal 1302 pulses from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t10. For cycle 1 of the clock signal 1302, the clock signal 1302 pulses from logic level 1 to logic level 0 at time t10 and remains at logic level 0 from time t10 to time t20. The clock signal 1302 pulses during cycle 2 of the clock signal 1302, similar to the behavior during cycle 1 of the clock signal 1302. For example, the clock signal 1302 pulses from logic level 0 to logic level 1 at time t20, and remains at logic level 1 from time t20 to time t30. The clock signal 1302 pulses from logic level 1 to logic level 0 at time t30. The clock signal 1302 remains at logic level 0 from time t30 to time t40, forming cycle 2 of the clock signal 1302.

[0307] It should be noted that the clock signal 1302 is different from the synchronization signal described herein. For example, the synchronization signal 202 (Figure 2A) is periodic for one or more time intervals of each cycle of the clock signal 130, but not periodic for one or more remaining time intervals of the cycle. For example, the synchronization signal 202 is periodically pulsed with respect to the time interval between times t0 and t16 of each cycle of the clock signal 1302, and then the pulsed state stops for the remaining time interval between times t16 and t20 of the cycle. The clock signal 1302 is periodic in that it has one pulse during each cycle of the clock signal 1302.

[0308] The embodiments described herein may be implemented in a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable home appliances, minicomputers, and mainframe computers. These embodiments can also be implemented in a distributed computing environment in which tasks are performed by remote processing hardware units linked over a network.

[0309] In some embodiments, the controller is part of a system, and the system may be part of the examples described above. Such a system includes a semiconductor processing apparatus comprising one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal, gas flow system, etc.). These systems are integrated with electronics to control their operation before, during, and after processing of semiconductor wafers or substrates. The electronics may also be referred to as “controllers” and may control various components or sub-components of one or more systems. Depending on the processing requirements and / or the type of system, the controller is programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, liquid delivery settings, position and operation settings, loading and unloading of wafers into and out of tools, and loading and unloading of wafers into and out of other transport tools and / or load locks connected to or interlocked with the system.

[0310] Broadly speaking, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive and issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, chips defined as digital signal processors (DSPs), ASICs, PLDs, and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that define variables, factors, etc. for performing a particular process on a semiconductor wafer, for a semiconductor wafer, or for a system. In some embodiments, program instructions are part of a recipe defined by a process engineer to achieve one or more processing steps during the manufacturing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0311] In some embodiments, the controller is part of a computer that is integrated into the system, connected to the system, otherwise networked to the system, or a combination thereof, or connected to such a computer. For example, the controller is the “cloud,” i.e., the entirety or part of the fab host computer system, which enables remote access to wafer processing. The computer enables remote access to the system to monitor the current progress of a manufacturing operation, investigate the history of past manufacturing operations, investigate trends or performance criteria from multiple manufacturing operations, change variables in the current process, set processing steps to track the current process, or start a new process.

[0312] In some embodiments, a remote computer (e.g., a server) provides process recipes to the system via a network, which includes a local network or the Internet. The remote computer includes a user interface that allows input or programming of variables and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying each variable, factor, and / or variable of processing steps performed during one or more operations. It should be understood that the variables, factors, and / or variables are specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller is distributed, for example, by including one or more individual controllers that are networked together and operate toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber that are located remotely (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits that collaboratively control the process in the chamber.

[0313] Examples of systems to which the methods described herein are applied in various embodiments include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing systems related to or used in the fabrication and / or manufacture of semiconductor wafers.

[0314] It should be further noted that in some embodiments, the above-described operation applies to various types of plasma chambers, such as plasma chambers containing inductively coupled plasma (ICP) reactors, capacitively coupled plasma (CCP) chambers, transformer-coupled plasma chambers, conductor tools, dielectric tools, and plasma chambers containing electron cyclotron resonance (ECR) reactors. For example, one or more RF generators are connected to inductors within the ICP reactor. Examples of inductor shapes include solenoids, dome coils, and flat coils. In a CCP plasma chamber, the top plate is used as the upper electrode instead of one or more RF coils.

[0315] As described above, depending on one or more process steps performed by the tool, the host computer communicates with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, the main computer, another controller, or tools used for material handling to load and unload wafer containers to and from tool locations and / or load ports within the semiconductor manufacturing plant.

[0316] With the embodiments described above in mind, it should be understood that some of these embodiments employ various computer implementation operations, including data stored in a computer system. These operations physically manipulate physical quantities. Any of the operations described herein that form part of these embodiments are useful mechanical operations.

[0317] Furthermore, some of these embodiments relate to hardware units or devices for performing these operations. These devices are specifically designed for a dedicated computer. When defined as a dedicated computer, the computer is capable of operating for a special purpose, but also performs other processes, program executions, or routines that do not belong to that special purpose.

[0318] In some embodiments, the operation may be processed by a computer selectively launched or configured by one or more computer programs stored in computer memory or cache, or retrieved via a computer network. If the data is retrieved via a computer network, the data may be processed by other computers on the computer network, for example, in a cloud of computing resources.

[0319] One or more embodiments may also be constructed as computer-readable code on a non-temporary computer-readable medium. A non-temporary computer-readable medium is any data storage hardware unit that stores data, such as a memory device, which is later read by a computer system. Examples of non-temporary computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disk ROMs (CD-ROMs), CD recordables (CD-Rs), CD rewritables (CD-RWs), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-temporary computer-readable medium includes computer-readable tangible media distributed on a network-connected computer system so that the computer-readable code is stored and executed in a distributed manner.

[0320] Although the method operations described above were presented in a specific order, it should be understood that in various embodiments, other housekeeping operations may be performed between operations, the method operations may be timed to occur at slightly different times, they may be distributed in a system that allows the method operations to occur at various intervals, or they may be performed in a different order than described above.

[0321] It should be further noted that in one embodiment, without departing from the scope described in the various embodiments described herein, one or more features from any of the embodiments described above may be combined with one or more features from any other embodiments.

[0322] While the embodiments described above have been explained in some detail for the purpose of clarifying understanding, it will be apparent that certain modifications and variations can be implemented within the scope of the appended claims. Therefore, these embodiments are considered illustrative and not restrictive, and are not limited to the details given herein.

Claims

1. It is a method, A radio frequency (RF) generator receives a first set of one or more variable levels and one or more duty cycles of an RF signal. The RF generator receives a synchronization signal having multiple pulses from the pulse controller, During the clock cycle of the clock signal, multiple instances of the first multiple states of the RF signal are generated in synchronization with the multiple pulses of the synchronization signal. Includes, Each of the first plurality of states of the RF signal has a corresponding one of the one or more variable levels of the first set and a corresponding one of the one or more duty cycles of the first set. method.

2. The method according to claim 1, During the time interval between two consecutive pulses of the aforementioned synchronization signal, no pulse of the synchronization signal is received. The method further comprises generating a single-state instance of the RF signal during the time interval.

3. A method according to claim 1, wherein the synchronization signal is different from the clock signal.

4. The method according to claim 1, Receiving a second set of one or more variable levels and one or more duty cycles of the RF signal, Receiving a count of the number of pulses in the synchronization signal, wherein the RF signal subsequently includes the second set of one or more variable levels and one or more duty cycles, To determine whether the aforementioned count has been exceeded, During the clock cycle of the clock signal, in response to determining that the count has been exceeded, a first instance of a second plurality of states of the RF signal is generated. It further includes, Each of the second plurality of states of the RF signal has a corresponding one of the one or more variable levels of the second set and a corresponding one of the one or more duty cycles of the second set. method.

5. A method according to claim 1, wherein the first set of one or more variable levels and one or more duty cycles is received before the reception of the synchronization signal.

6. A method according to claim 1, wherein the frequencies of the plurality of pulse generation can be changed by the pulse controller.

7. A method according to claim 1, wherein the plurality of states includes two states, three states, or four states.

8. A method according to claim 1, wherein the one or more variable levels are one or more power levels.

9. A method according to claim 1, wherein each of the one or more duty cycles is the corresponding one of the one or more variable levels.

10. It is a pulse controller, A processor configured to transmit a first set of one or more variable levels and one or more duty cycles of a high-frequency (RF) signal to an RF generator, The processor is configured to transmit a synchronization signal having multiple pulses to the RF generator. When the synchronization signal is transmitted to the RF generator, the RF generator is able to generate multiple instances of the first multiple states of the RF signal in synchronization with the multiple pulses of the synchronization signal during the clock cycle of the clock signal, each of the first multiple states of the RF signal having one corresponding to one or more variable levels of the first set and one corresponding to one or more duty cycles of the first set. Processor and The memory device connected to the aforementioned processor and A pulse controller, including one.

11. A pulse controller according to claim 10, wherein the processor is configured to generate a single logic level of the synchronization signal during a time interval between two consecutive pulses of the plurality of pulses of the synchronization signal, the single logic level enabling the RF generator to generate a single state instance of the RF signal.

12. A pulse controller according to claim 10, wherein the synchronization signal is different from the clock signal.

13. A pulse controller according to claim 10, wherein the one or more variable levels are one or more power levels.

14. It is a method, The sensor system measures sensor data, and The sensor system receives a synchronization signal having multiple pulses, The sensor system collects portions of the sensor data in synchronization with the plurality of pulses of the synchronization signal during the clock cycle of the clock signal, The aforementioned portion of the sensor data is transmitted to the pulse controller. Methods that include...

15. A method according to claim 14, wherein each of the plurality of pulses is generated during one corresponding period of a plurality of periods, and each of the portions of the sensor data is converted from analog to digital format with respect to the one corresponding period of the plurality of periods.

16. A method according to claim 15, wherein during the time interval between two consecutive pulses, a portion of the sensor data is not converted from analog to digital format.

17. A method according to claim 14, wherein a portion of the sensor data is not collected during the time interval between two consecutive pulses.

18. A method according to claim 14, wherein the sensor system is located within an impedance matching circuit.

19. A method according to claim 14, wherein the sensor system is located outside the impedance matching circuit.

20. A method according to claim 14, wherein the sensor data is a voltage value, or an intensity value, or a current value.

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