Imaging device

Abstract

We provide a three-dimensionally integrated imaging device. [Solution] A first structure including a transistor having silicon as the active layer or active region A second structure, which includes a transistor with an oxide semiconductor as the active layer, and were fabricated respectively. Later, by joining the first structure and the second structure together, the characteristics of each An imaging device is constructed by joining metal layers to create a three-dimensionally integrated system.

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field relates to a product, method, or method of manufacture. Or, the present invention. One aspect of this is a process, machine, manufacture, or composition. This relates to matter. Therefore, the invention disclosed more specifically in this specification One aspect of the technical field is semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, and lighting devices. A device, an energy storage device, a memory device, an imaging device, a method of operating them, or a method of manufacturing them. This can be given as an example.

[0003] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to the general term. Transistors and semiconductor circuits are forms of semiconductor devices. Also, memory devices, Display devices, imaging devices, and electronic devices may include semiconductor devices. [Background technology]

[0004] Oxide semiconductors are attracting attention as semiconductor materials applicable to transistors. For example, acid Using zinc oxide or In-Ga-Zn oxide semiconductors as the oxide semiconductor, the transient A technique for producing the material has been disclosed (see Patent Documents 1 and 2).

[0005] Furthermore, an imaging device that uses an oxide semiconductor transistor as part of the pixel circuit is particularly useful. This is disclosed in Document 3.

[0006] Furthermore, transistors containing silicon, transistors containing oxide semiconductors, and crystals Patent Document 4 discloses an imaging device having a configuration in which photodiodes having a silicon layer are stacked. It is being done. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Patent Document 3] Japanese Patent Publication No. 2011-119711 [Patent Document 4] Japanese Patent Publication No. 2013-243355 [Overview of the project] [Problems that the invention aims to solve]

[0008] In semiconductor integrated circuits, while density and capacity are increasing, there is also a demand for miniaturization, and two-dimensional The transition from integration to three-dimensional integration is progressing.

[0009] While 3D integration can make the manufacturing process complex, the materials and design rules for each layer are important. This increased degree of freedom allows for the creation of high-performance semiconductor integrations that are difficult to fabricate with two-dimensional integration. It is possible to fabricate circuits.

[0010] Therefore, one aspect of the present invention aims to provide a three-dimensional integrated imaging device. One of the objectives is to provide an imaging device that can drive pixels in a divided manner. To do so. One of the objectives is to provide an imaging device that can be miniaturized. Or, to reduce noise. One of the objectives is to provide an imaging device that can capture images that do not exist. One of the objectives is to provide an imaging device suitable for high-speed operation. Alternatively, to provide high-resolution imaging. One of the objectives is to provide an imaging device, or an imaging device that can take images in low light conditions. One of the objectives is to provide an imaging device, or an imaging device that can be used over a wide temperature range. One of the objectives is to provide an imaging device, or to provide an imaging device with a high aperture ratio. One of its objectives is to provide a highly reliable imaging device. Alternatively, one of the objectives is to provide a novel imaging device or the like.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention relates to an imaging device having a stacked structure.

[0013] One aspect of the present invention is an imaging device having a first layer, a second layer, and a third layer, The second layer is provided between the first layer and the third layer, and the first layer has a photoelectric conversion element. The second layer consists of a first transistor with an oxide semiconductor as the active layer, a first insulating layer, and The first metal layer is a second transistor having silicon as the active layer or active region. It has a zista, a second insulating layer, and a second metal layer, and the first metal layer and the second metal layer are The main component is the same metal element, and the first metal layer has a region embedded in the first insulating layer. Furthermore, the second metal layer has a region embedded in the second insulating layer, and the first metal layer is the second metal The first insulating layer has a region bonded to the subordinate layer, and the first insulating layer has a region bonded to the second insulating layer. The first and second transistors have their gate electrodes facing each other. The photoelectric conversion element is arranged in such a way that it is electrically connected to the first transistor, and the first transistor The transistor is electrically connected to the first metal layer, and the second transistor is connected to the second metal layer. This imaging device is characterized by being electrically connected.

[0014] Furthermore, the second layer is an n-ch type third transistor with an oxide semiconductor as the active layer, and It has a third metal layer, and the third layer is a p-ch type with silicon as the active layer or active region. It has a fourth transistor and a fourth metal layer, and the third metal layer and the fourth metal layer are The main component is the same metal element, and the third metal layer has a region embedded in the first insulating layer. The fourth metal layer has a region embedded in the second insulating layer, and the third metal layer is the fourth metal Having a region junctioned with the layer, the third and fourth transistors are connected to each other. The top surfaces of the gate electrodes are facing each other, and the third transistor is connected to the third metal layer. The fourth transistor is electrically connected to the fourth metal layer. It can also be done this way.

[0015] Another aspect of the present invention is an imaging device having a first layer, a second layer, and a third layer. The second layer is provided between the first layer and the third layer, and the first layer is a photoelectric conversion The device has an element, a third insulating layer, and a fifth metal layer, and the second layer is an oxide semiconductor as the active layer. It has a first transistor, a fourth insulating layer, and a sixth metal layer, and the third layer is silicon It has a second transistor with a capacitor as the active layer or active region, a fifth metal layer and a sixth The metal layer has the same main component metal element, and the fifth metal layer is embedded in the third insulating layer. The sixth metal layer has a region embedded in the fourth insulating layer, and the fifth metal layer is The third insulating layer has a region bonded to the fourth insulating layer. The photoelectric conversion element has a region, and is electrically connected to the fifth metal layer, and the first transistor is The second transistor is electrically connected to the first transistor, and is electrically connected to the fifth metal layer. This imaging device is characterized by being connected to [a specific device].

[0016] The above metal element is preferably Cu, Al, W, or Au.

[0017] Oxide semiconductors have In, Zn, and M (where M is Al, Ga, Y, or Sn). This is preferable. [Effects of the Invention]

[0018] By using one aspect of the present invention, a three-dimensional integrated imaging device can be provided. It is possible to provide an imaging device that can drive pixels in a segmented manner. We can provide an imaging device, or a device that can capture images with low noise. We can provide an imaging device. Or, we can provide an imaging device suitable for high-speed operation. It is possible to provide an imaging device with high resolution. Alternatively, imaging under low light conditions is possible. An imaging device can be provided that can be used over a wide temperature range. It is possible to provide an imaging device that can achieve this. Or, it is possible to provide an imaging device with a high aperture ratio. Yes, it is possible. Or, it is possible to provide a highly reliable imaging device. Or, a novel imaging device We can provide things like storage.

[0019] Furthermore, one aspect of the present invention is not limited to these effects. For example, one aspect of the present invention In some cases, or depending on the circumstances, it may have effects other than those listed above. Yes. Or, for example, one aspect of the present invention may, depending on the circumstances, These effects may not always be present. [Brief explanation of the drawing]

[0020] [Figure 1] Diagrams and circuit diagrams illustrating the pixels of an imaging device. [Figure 2] A diagram illustrating the pixels of an imaging device. [Figure 3] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 4] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 5] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 6] A cross-sectional diagram illustrating the connection configuration of a photoelectric conversion element. [Figure 7] A cross-sectional diagram illustrating the connection configuration of a photoelectric conversion element. [Figure 8] A cross-sectional diagram illustrating the configuration of the imaging device and a cross-sectional diagram illustrating the connection configuration of the photoelectric conversion elements. [Figure 9] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 10] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 11] A diagram illustrating the manufacturing process of an imaging device. [Figure 12] A diagram illustrating the manufacturing process of an imaging device. [Figure 13] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 14] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 15]Block diagrams illustrating the imaging device, circuit diagrams of the CDS circuit, and block diagrams of the A / D conversion circuit. [Figure 16] A top view and perspective view illustrating the configuration of the imaging device. [Figure 17] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 18] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 19] A cross-sectional diagram illustrating the configuration of the imaging device. [Figure 20] A circuit diagram explaining pixels. [Figure 21] A circuit diagram explaining pixels. [Figure 22] A timing chart explaining the operation of the imaging device. [Figure 23] A circuit diagram explaining pixels. [Figure 24] A diagram illustrating a curved imaging device. [Figure 25] Top view and cross-sectional view illustrating a transistor. [Figure 26] Top view and cross-sectional view illustrating a transistor. [Figure 27] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 28] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 29] Top view and cross-sectional view illustrating the semiconductor layer. [Figure 30] Top view and cross-sectional view illustrating a transistor. [Figure 31] Top view and cross-sectional view illustrating a transistor. [Figure 32] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 33] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 34] Top view and cross-sectional view illustrating a transistor. [Figure 35] A top view illustrating a transistor. [Figure 36] A diagram illustrating the range of atomic ratios in oxide semiconductors. [Figure 37] A diagram illustrating the crystal structure of InMZnO4. [Figure 38] Band diagram of a stacked oxide semiconductor structure. [Figure 39] Figures illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors, as well as a figure showing the limited-field electron diffraction pattern of CAAC-OS. [Figure 40] Cross-sectional TEM images of CAAC-OS, as well as planar TEM images and their image analysis results. [Figure 41] Figure showing the electron diffraction pattern of nc-OS, and a cross-sectional TEM image of nc-OS. [Figure 42] Cross-sectional TEM image of an a-like OS. [Figure 43] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 44] Perspective and cross-sectional views of the package containing the imaging device. [Figure 45] Perspective and cross-sectional views of the package containing the imaging device. [Figure 46] A diagram illustrating electronic devices. [Figure 47] External view and X-ray image of the X-ray imaging panel. [Modes for carrying out the invention]

[0021] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted. Note that the same elements that make up the figure Matching may be omitted or modified as appropriate between different drawings.

[0022] The ordinal numbers "1st" and "2nd" are used for convenience only and do not necessarily indicate the order of processes or layering. It does not indicate order. Therefore, for example, "the first" could be "the second" or "the third." It can be explained by substituting it as appropriate. Also, ordinal numbers as described in this specification, etc. The ordinal numbers used to specify one aspect of the present invention may not always coincide.

[0023] For example, in this specification, etc., if it is explicitly stated that X and Y are connected The cases are when X and Y are electrically connected and when X and Y are functionally connected. The cases disclosed in this specification, etc., include the case where X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the diagram or text. In addition to the connection relationships shown in the diagram or text, other connections may also be included as described in the diagram or text. do.

[0024] Here, X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer). (etc.)

[0025] One example of a case where X and Y are directly connected is when an electrical connection between X and Y is possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. If the diode, display element, light-emitting element, load, etc. are not connected between X and Y and elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitors). Without the need for elements such as components, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. This is the case when X and Y are connected.

[0026] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between them. Furthermore, if X and Y are electrically connected, then X and This includes cases where Y is directly connected to it.

[0027] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (D / A conversion circuits, A / D conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (Power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.) (etc.), voltage source, current source, switching circuit, amplification circuit (to increase signal amplitude or current amount, etc.) (Incoming circuits, operational amplifiers, differential amplifiers, source follower circuits, buffer circuits, etc.), signal One or more generation circuits, memory circuits, control circuits, etc., can be connected between X and Y. As an example, even if another circuit is placed between X and Y, the output from X If a signal is transmitted to Y, then X and Y are assumed to be functionally connected. When X and Y are functionally connected, the situation is different from when X and Y are directly connected. This includes the case where and Y are electrically connected.

[0028] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y and When they are electrically connected (i.e., when there is another element or circuit between X and Y) (when connected by) and when X and Y are functionally connected (i.e., X and Y and (When they are functionally connected with another circuit in between) and when X and Y are directly connected In the case where (that is, when X and Y are connected without another element or circuit in between) ) and are disclosed in this specification, etc. That is, electrically connected and If explicitly stated, simply explicitly stated as connected. The same information as in this case is disclosed in this specification, etc.

[0029] For example, the source (or first terminal, etc.) of the transistor is connected via Z1 (and (Without intervening), electrically connected to X, and the drain of the transistor (or second terminal, etc.) However, if Y is electrically connected via (or without) Z2, or if a transistor The source (or first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 It is directly connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z2. If one part is directly connected to Z2, and another part of Z2 is directly connected to Y, then: It can be expressed as follows.

[0030] For example, "X and Y and the source (or first terminal, etc.) and drain (or The second terminal, etc., is electrically connected to each other, and X is the source of the transistor ( (or the first terminal, etc.), the transistor's drain (or the second terminal, etc.), and Y in that order. It can be expressed as, "It is electrically connected." Or, "The source of the transistor." (or the first terminal, etc.) is electrically connected to X and the drain of the transistor (or The second terminal (or other terminal) is electrically connected to Y, and X is the source of the transistor (or the first terminal). Y is electrically connected to the drain (or second terminal, etc.) of the transistor in this order. It can be expressed as "X is connected to the source of the transistor ( or via the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.), Y is electrically connected. Connected, X, the source of the transistor (or the first terminal, etc.), the slave of the transistor It can be expressed as "N (or the second terminal, etc.), Y are provided in this connection order." Yes, it is possible. Using similar notation to these examples, the order of connections in a circuit configuration can be specified. By defining the source (or first terminal, etc.) and drain (and The technical scope can be determined by distinguishing between (for example, a second terminal) and other components.

[0031] Alternatively, another way to express it is, for example, "the source (or first terminal, etc.) of the transistor." ) is electrically connected to X via at least a first connection path, and the first connection path It does not have a second connection path, and the second connection path is via a transistor. The source of the transistor (or the first terminal, etc.) and the drain of the transistor (or the second terminal) The first connection path is a path via Z1, and the terminal is a path between terminals, etc. The drain of the inverter (or a second terminal, etc.) is connected via at least a third connection path. Electrically connected to Y, the third connection path does not have the second connection path, The third connection route is the route via Z2. This can be expressed as: The source (or first terminal, etc.) of the transistor is connected by at least the first connection path. , electrically connected to X via Z1, the first connection path has a second connection path The second connection path has a connection path via a transistor, The drain (or second terminal, etc.) is connected via at least a third connection path through Z2. The third connection path is electrically connected to Y, and the third connection path does not have the second connection path. It can be expressed as, "The source (or first terminal) of the transistor." (d) is electrically connected to X via Z1 by at least a first electrical path, The first electrical path does not have a second electrical path, and the second electrical path does not have a second electrical path. From the source (or first terminal, etc.) of the transistor to the drain (or second terminal, etc.) of the transistor This is an electrical path to the transistor's drain (or second terminal, etc.), and the drain of the transistor (or second terminal, etc.). ) is electrically connected to Y via Z2 by at least a third electrical path, and The third electrical path does not have a fourth electrical path, and the fourth electrical path is From the drain of the transistor (or the second terminal, etc.) to the source of the transistor (or the first terminal) It is an electrical path to terminals, etc. This can be expressed as "a table similar to these examples." By using the current method to define the connection paths in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.). This allows us to determine the technical scope.

[0032] Note that these methods of expression are just examples and are not limited to these methods. Here, X Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.) Let's assume it is a layer, etc.

[0033] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0034] Note that the words "membrane" and "layer" may differ in some cases or depending on the situation. Therefore, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive film." In some cases, it may be possible to change the term to "insulating film". Alternatively, for example, the term "insulating film" may be used. In some cases, it may be possible to change the term to "insulating layer."

[0035] Generally speaking, electric potential (voltage) is relative, and its relative magnitude from a reference potential is... The size is determined by the degree. Therefore, terms such as "grounding," "GND," and "earth" are used. Even if it is stated, the potential is not necessarily 0 volts. For example, when defining "ground" or "GND" based on the lowest potential in a circuit, Yes, it exists. Alternatively, in a circuit, an intermediate potential can be used as a reference to define "ground" or "GND". In some cases, positive and negative potentials are defined based on that potential. And so it becomes.

[0036] (Embodiment 1) In this embodiment, an imaging device, which is one aspect of the present invention, will be described with reference to the drawings.

[0037] One aspect of the present invention involves fabricating a first structure and a second structure, and then the first The metal layers of the first and second structures are joined together by bonding them together. This describes the configuration and fabrication method of a three-dimensionally integrated imaging device.

[0038] The first structure comprises a transistor having silicon as the active layer or active region, and the transistor The configuration may include a first metal layer electrically connected to the sta, and a first insulating layer.

[0039] The second structure comprises a photoelectric conversion element, a transistor with an oxide semiconductor as the active layer, and the The configuration includes a second metal layer electrically connected to the transistor and a second insulating layer. Cut.

[0040] Alternatively, the first structure is a first transistor having silicon as the active layer or active region. a second transistor having an oxide semiconductor as its active layer, and electrically connected to the second transistor The second structure includes a third metal layer and a third insulating layer, and the second structure is a photoelectric conversion element. The configuration includes a fourth metal layer electrically connected to the photoelectric conversion element and a fourth insulating layer. That's good too.

[0041] Furthermore, the structure can also be constructed by joining together the first structure, the second structure, and the third structure. can.

[0042] In this case, the first structure is a transistor with silicon as the active layer or active region, The configuration includes a first metal layer electrically connected to the transistor and a first insulating layer. This can be done. The second structure is a transistor with an oxide semiconductor as the active layer, and the transistor A second metal layer electrically connected to the sta, a third metal layer, a second insulating layer, and a third insulating layer The configuration may include layers. The third structure includes a photoelectric conversion element and the photoelectric conversion element The configuration may include a fourth metal layer that is electrically connected to the third layer, and a fourth insulating layer.

[0043] The transistor with the above oxide semiconductor as the active layer has a low off-current and is located within the pixels of the imaging device. The memory used to store data can be easily configured.

[0044] Figure 1(A) is a schematic diagram of a cross-section of a pixel 20 in an imaging device according to one aspect of the present invention. (B) is the circuit diagram of pixel 20. Note that in Figures 1(A), (B), etc., the transistors An example is shown where the type is n-ch, but one aspect of the present invention is not limited thereto. The transistor can be replaced with a p-channel transistor.

[0045] In pixel 20, one electrode of the photoelectric conversion element PD is the source or of transistor 41 It is electrically connected to one side of the drain. The other side of the source or drain of transistor 41. It is electrically connected to either the source or drain of transistor 42. The source or drain of transistor 41 is electrically connected to the gate of transistor 43. The source or drain of transistor 43 is connected to the source of transistor 44. It is electrically connected to one of the drains.

[0046] Here, the source or drain of transistor 41, and the source of transistor 42 Alternatively, the drain is connected to node FD, to which the gate of transistor 43 is connected, and the charge detection unit is connected. In addition, as shown in Figure 20(A), the configuration is such that a capacitive element is connected to node FD. That's fine.

[0047] In Figures 1(A) and (B), the other electrode of the photoelectric conversion element PD is connected to the wiring 71 (VPD). Electrically connected. The source or drain of transistor 42 is connected to the other wire 72 (V It is electrically connected to RS). The source or drain of transistor 43 is wired to the other end. Electrically connected to 73 (VPI). The other side of the source or drain of transistor 44. This is electrically connected to wiring 91 (OUT1).

[0048] Furthermore, the elements shown in Figures 1(A) and (B) (transistors, photoelectric conversion elements, etc.) and the wiring The connection configuration is just one example; each element may be electrically connected to different wiring, or multiple elements may be connected. These elements may also be electrically connected to the same wiring.

[0049] Wiring 71 (VPD), wiring 72 (VRS), and wiring 73 (VPI) are power lines. It can have a function. For example, wiring 71 (VPD) can function as a low-potential power line. It can be done. Wiring 72 (VRS) and wiring 73 (VPI) are high-potential power lines. It can be made to function.

[0050] The gate of transistor 41 is electrically connected to wiring 61 (TX). Transistor 4 The gate of transistor 2 is electrically connected to wiring 62 (RS). The gate of transistor 44 is It is electrically connected to wiring 63(SE).

[0051] Wires 61 (TX), 62 (RS), and 63 (SE) are connected to each other. It can function as a signal line to control the conduction of a transistor.

[0052] Transistor 41 is for transferring the cathode potential of the photoelectric conversion element PD to node FD. It can function as a transistor. Transistor 42 controls the potential of node FD. It can function as a transistor for resetting. Transistor 43 is It can function as a transistor to produce an output corresponding to the potential of node FD. Transistor 44 is used to function as a transistor for selecting pixel 20. It is possible.

[0053] Note that the above-described configuration of pixel 20 is just one example, and some circuits, some transistors, and some Capacitive elements or some wiring may not be included. Or, they may not be included in the above-mentioned configuration. It may also include circuits, transistors, capacitive elements, wiring, etc. The connection configuration may differ from the one described above.

[0054] An imaging device according to one aspect of the present invention, as shown in Figure 1(A), has layers 1100, 1200 and It has 1300 layers.

[0055] The layer 1100 can be configured to have a photoelectric conversion element PD. For example, a two-terminal photodiode can be used. For example, pn-type photodiodes using single-crystal silicon substrates, amorphous silicon thin films, and micro PIN-type photodiode using crystalline silicon thin film or polycrystalline silicon thin film, selenium Alternatively, photodiodes using selenium compounds or organic compounds may be used. can.

[0056] The layer 1200 can be configured to have transistors 41 and 42. Transistors 41 and 42 are transistors with an oxide semiconductor as the active layer (hereinafter It is preferable to use an OS transistor. Also, layer 1200 is a transistor 41 The source or drain of one of the transistors and the source or drain of transistor 42 It has an electrically connected metal layer 401b.

[0057] OS transistors have extremely low off-current characteristics. Therefore, transistor 41 Furthermore, the low off-current characteristics of transistor 42 allow for a longer period of charge retention at node FD. This allows for extremely long durations. Therefore, without complicating the circuit configuration or operating method, A global shutter method can be applied, in which charge accumulation operations are performed simultaneously at all pixels. Furthermore, an imaging device according to one embodiment of the present invention can also be operated using a rolling shutter method. .

[0058] OS transistors are transistors that use silicon in the active region or active layer (hereinafter referred to as S Because the temperature dependence of electrical characteristics is smaller than that of a transistor, it can be used over an extremely wide temperature range. It can be used. Therefore, imaging devices and semiconductor devices having OS transistors The device is also suitable for installation in automobiles, aircraft, spacecraft, and other similar applications.

[0059] Furthermore, OS transistors have a higher drain breakdown voltage than Si transistors. In photoelectric devices using selenium-based materials as the photoelectric conversion layer, avalanche multiplication is utilized to It is preferable to operate it by applying a relatively high voltage (for example, 10V or higher). By combining an OS transistor with a photoelectric conversion element that uses a selenium-based material as the photoelectric conversion layer... This makes it possible to create a highly reliable imaging device.

[0060] The layer 1300 can be configured to have transistors 43 and 44. Transistors 43 and 44 are transistors that use silicon as the active layer or active region. It is preferable to use a transistor. Transistors in which silicon is the active layer or active region are of The current is large, and the potential of node FD can be efficiently amplified. Also, layer 1200 It has a metal layer 401a that is electrically connected to the gate of transistor 44.

[0061] As shown in Figure 1(A), metal layer 401a and metal layer 401b are in direct contact with each other. The metal layers 401a and 401b are provided in a position where they have an electrically conductive connection portion 401. The configuration will be as follows.

[0062] Furthermore, an imaging device according to one embodiment of the present invention may have the configuration shown in Figure 2(A).

[0063] In the configuration shown in Figure 2(A), layer 1100 consists of a photoelectric conversion element PD and one of the photoelectric conversion elements PD. One electrode is electrically connected to the metal layer 402b, and the other electrode of the photoelectric conversion element PD is electrically connected to it. It has a metal layer 403b connected to layer 1100. It's not necessary.

[0064] Layer 1200 contains transistor 41, transistor 42, and the source of transistor 41. Alternatively, there is a metal layer 402a that is electrically connected to one side of the drain, and a wire 71 that is electrically connected to the other side. It has a metal layer 403a. Note that the wiring 71 and the metal layer 403a are provided in layer 1200. It's not necessary.

[0065] Layer 1300 has transistors 43 and 44.

[0066] As shown in Figure 2(A), metal layer 402a and metal layer 402b are in direct contact with each other. The metal layers 402a and 402b are provided in a position where they have an electrically conductive connection portion 402. The configuration is as follows. Furthermore, the metal layer 403a and the metal layer 403b are in direct contact with each other. It is provided in a position where the metal layer 403a and metal layer 403b have an electrically conductive connection portion 403. The configuration will be as follows.

[0067] Furthermore, an imaging device according to one embodiment of the present invention may have the configuration shown in Figure 2(B).

[0068] In the configuration shown in Figure 2(B), layer 1100 consists of a photoelectric conversion element PD and one of the photoelectric conversion elements PD. One electrode is electrically connected to the metal layer 402b, and the other electrode of the photoelectric conversion element PD is electrically connected to it. It has a metal layer 403b connected to layer 1100. It's not necessary.

[0069] Layer 1200 contains transistor 41, transistor 42, and the source of transistor 41. Alternatively, there is a metal layer 402a that is electrically connected to one side of the drain, and a wire 71 that is electrically connected to the other side. The metal layer 403a and one of the source or drain of the transistor 41 and the transistor It has a metal layer 401b that is electrically connected to either the source or the drain of 42. The wiring 71 and the metal layer 403a do not necessarily have to be provided in layer 1200.

[0070] Layer 1300 has transistor 43, transistor 44, and the gate of transistor 43. It has an electrically connected metal layer 401a.

[0071] As shown in Figure 2(B), metal layer 402a and metal layer 402b are in direct contact with each other. The metal layers 402a and 402b are provided in a position where they have an electrically conductive connection portion 402. The configuration is as follows. Furthermore, the metal layer 403a and the metal layer 403b are in direct contact with each other. It is provided in a position where the metal layer 403a and metal layer 403b have an electrically conductive connection portion 403. The configuration is such that the metal layer 401a and the metal layer 401b are in direct contact with each other. The metal layers 401a and 401b are provided in a position and have a conductive connection portion 401. This will be the structure.

[0072] Figures 3(A), (B), and (C) illustrate the specific configuration of pixel 20 corresponding to Figure 1(A). This is a diagram. Figure 3(A) shows the channel length direction of transistors 41, 42, 43, and 44. This is a cross-sectional view. Figure 3(B) is a cross-sectional view of the dashed line X1-X2 shown in Figure 3(A), and the tra This shows a cross-section of the channel width of the inverter 41. Figure 3(C) is a single point shown in Figure 3(A). This is a cross-sectional view along the dashed line Y1-Y2, representing the cross-section of transistor 42 in the channel width direction. .

[0073] In the cross-sectional view described in this embodiment, the wiring, electrodes, metal layer and contact plug ( Although the conductors 82) are shown as individual elements, when they are electrically connected... In some cases, they may be provided as the same element. Also, wiring, electrodes, and metal layers, etc. The configuration in which the elements are connected via the conductor 82 is just one example; each element is connected without the conductor 82. It may also be connected directly.

[0074] Each element, such as a transistor, has a protective film, an interlayer insulating film, or a planarizing film. An insulating layer 81a to 81j is provided. For example, the insulating layer 81a to 81j is made of an oxide Inorganic insulating films such as acrylic film and silicon oxidnitride film can be used. Alternatively, acrylic Organic insulating films such as resins and polyimide resins may be used. Insulating layers 81a to 81j The top surfaces of these areas may be treated with CMP (Chemical Mechanical Polish) as needed. It is preferable to perform a planarization treatment using methods such as the shing method.

[0075] Please note that some of the wiring shown in the drawings may not be provided, or there may be wiring or traffic not shown in the drawings. In some cases, components such as inverters may be included in each layer. Also, layers not shown in the drawings may be included. Also, some of the layers shown in the drawings may not be included.

[0076] The region where the OS transistor is formed, and the Si device (Si transistor or Si film) Insulating layers 80a and 80b are provided between the region where the diode is formed and the surrounding region.

[0077] Hydrogen in the insulating layer located near the active region of transistors 43 and 44 is in the silicon dung. The ring bond is terminated. Therefore, the hydrogen improves the reliability of transistors 43 and 44. It has the effect of raising the temperature. On the other hand, the oxide semiconductor layer which is the active layer of transistors 41 and 42 Hydrogen in the insulating layer placed nearby is one of the factors that generate carriers in the oxide semiconductor layer. Therefore, the hydrogen in question can be a factor that reduces the reliability of transistors 41 and 42. There is a combination. Therefore, one layer has Si transistors and the other has OS transistors. When the other layer is laminated, an insulating layer 80 has the function of preventing hydrogen diffusion between them. It is preferable to provide b. By trapping hydrogen in one layer with the insulating layer 80b, The reliability of transistors 43 and 44 can be improved. Also, from one layer to the other By suppressing the diffusion of hydrogen, the reliability of transistors 41 and 42 can also be improved. It is possible. Also, for the same reasons as above, one layer having a Si photodiode and OS trace An insulating layer 80a is provided between the other layer containing the inverter and the insulating layer, which has the function of preventing hydrogen diffusion. It is preferable to do so.

[0078] Examples of insulating layers 80a and 80b include aluminum oxide, aluminum oxide nitride, and acid Gallium oxide, gallium nitride oxide, yttrium oxide, yttrium nitride oxide, hafni oxide It is possible to use materials such as um, hafnium oxidizride, and yttria-stabilized zirconia (YSZ). Cut.

[0079] In Figure 3(A), the photoelectric conversion element PD in layer 1100 uses a single-crystal silicon substrate. This shows a pn-type photodiode. The photoelectric conversion element PD is p + area 620, p - region 630, n-type region 640, p + The configuration can include a region 650.

[0080] n-type region 640 is electrically connected to the metal layer 405. Also, p + Region 650 is metal layer 4 It is electrically connected to 06. Metal layers 405 and 406 penetrate the insulating layer 81g. It is established.

[0081] Layer 1200 is provided with transistors 41 and 42, which are OS transistors. Transistors 41 and 42 both show a configuration with a back gate, Even if the transistors in a section, for example, transistor 41, have a back gate, Good. The back gate is provided opposite to the transistor as shown in Figure 3(B). It may be electrically connected to the front gate. Alternatively, the back gate may be connected to the front gate. A configuration that can supply a fixed potential different from the target is also acceptable.

[0082] The metal layer 401b is provided such that it has a region embedded in the insulating layer 81d, and the conductive layer and The other side of the source or drain of transistor 41 and the transistor via the conductor 82 etc. It is electrically connected to either the source or drain of transistor 42. Also, transistor 41 Either the source or the drain has electrical connections with the metal layer 405 via the conductor 82 and the conductive layer, etc. They are connected precisely. In addition, the wiring 71 is electrically connected to the metal layer 406 via the conductor 82. ru.

[0083] Layer 1300 contains transistors 43 and 44, which are Si transistors. It can be kicked. In Figure 3(A), transistors 43 and 44 illustrate a fin-type configuration. However, it may also be a planar type as shown in Figure 4(A). Or, as shown in Figure 4(B) Alternatively, it may be a transistor having an active layer 660 made of a silicon thin film. This is polycrystalline silicon and single-crystal silicon of SOI (Silicon on Insulator). It can be reconciled.

[0084] The metal layer 401a is provided to have a region embedded in the insulating layer 81c, and the conductive layer and It is electrically connected to the gate of transistor 43 via a conductor 82, etc.

[0085] Here, it is preferable that metal layer 401a and metal layer 401b have the same main component metal element. Furthermore, the insulating layer 81c and insulating layer 81d are composed of the same components. preferable.

[0086] For example, metal layers 401a and 401b contain Cu, Al, Sn, Zn, W, and Ag. Pt or Au can be used. Cu, A is preferred due to its ease of bonding. l, W, or Au is used. In addition, the insulating layer 81c and insulating layer 81d are made of silicone oxide. Using silicon oxide nitride, silicon nitride, silicon nitride, titanium nitride, etc. It is possible.

[0087] The same metal material as described above is used for each of the metal layers 401a and 401b. The same insulating material as described above is used for both the insulating layer 81c and the insulating layer 81d. Then, the bonding process can be performed at the bonding position a shown in Figure 3. Therefore, electrical connection between metal layer 401a and metal layer 401b can be obtained. This allows for a connection with mechanical strength between the insulating layer 81c and the insulating layer 81d.

[0088] For joining metal layers, sputtering is used to remove surface oxide films and impurity adsorption layers. Surface activation bonding is a method that involves removing contaminants, cleaning and activating surfaces, and then bringing them into contact to bond them together. It can be used. Alternatively, diffusion bonding methods that use temperature and pressure in combination to join surfaces together can be used. Both can be used. Since bonding occurs at the atomic level in both cases, it is not only electrical but also mechanical. Mechanically superior bonding can also be achieved.

[0089] Furthermore, for bonding the insulating layers, high flatness is achieved by polishing, etc., followed by oxygen plasma, etc. The hydrophilic treated surfaces are brought into contact to create a temporary bond, and then dewatered by heat treatment to create the permanent bond. Aqueous bonding methods can be used. Hydrophilic bonding methods also involve bonding at the atomic level. This allows for mechanically superior bonding.

[0090] When layer 1300 and layer 1200 are bonded together, each bonding surface has an insulating layer and a metal layer. Since they coexist, for example, a combination of surface activation bonding and hydrophilic bonding methods can be used. .

[0091] For example, after polishing, the surface is cleaned, an anti-oxidation treatment is applied to the surface of the metal layer, and then a hydrophilic treatment is applied. Methods such as performing a process to join the metal layers can be used. An oxidizing metal may be used, and hydrophilic treatment may be performed. Furthermore, a joining method other than the one described above may be used. That's fine.

[0092] The bonding method involves bonding each device after it is completed, so OS transitions Both silicon and silicon transistors can be fabricated using processes optimized for each. Therefore, the electrical characteristics and reliability of each transistor can be improved. Since the top-gate type transistors are completed and then bonded together, OS The front gate electrode of the transistor and the gate electrode of the Si transistor are on the upper surface of each other. They are arranged so that they face each other.

[0093] Furthermore, the pixel 20 can also have the stacked configuration shown in Figure 5. The pixel 20 shown in Figure 5 is... Only pixel 20 and layer 1100, as shown in 3(A), are different; the rest of the configuration is the same.

[0094] In Figure 5, the photoelectric conversion element PD in layer 1100 uses selenium in the photoelectric conversion layer. This shows a photodiode. The photoelectric conversion element PD consists of a photoelectric conversion layer 561 and a light-transmitting conductive material. The configuration may include a layer 562, an electrode 566, a partition wall 567, and wiring 571.

[0095] The electrode 566 is electrically connected to the metal layer 405. The light-transmitting conductive layer 562 is connected to the wiring 57. It is electrically connected to the metal layer 406 via 1. Metal layer 405 and metal layer 406 are insulated It is installed by penetrating the marginal layer 81g.

[0096] Figure 5 illustrates a configuration in which a selenium-based material is used in the photoelectric conversion layer 561. Photoelectric converters (PDs) using this technology have the characteristic of high external quantum efficiency for visible light. Selenium-based materials have a high light absorption coefficient, which has the advantage of making it easier to thin the photoelectric conversion layer 561. In photoelectric conversion elements (PDs) using selenium-based materials, avalanche doubling results in high sensitivity with large amplification. It can be used as a sensor. In other words, by using a selenium-based material in the photoelectric conversion layer 561. Therefore, even if the pixel area is reduced, a sufficient photocurrent can be obtained. Photoelectric converters (PDs) using this technology are also suitable for imaging in low-light environments.

[0097] As selenium-based materials, amorphous selenium or crystalline selenium can be used. For example, crystalline selenium can be obtained by heat-treating amorphous selenium after film formation. By making the crystal grain size smaller than the pixel pitch, the characteristic variation between pixels can be reduced. In addition, crystalline selenium has characteristics such as higher spectral sensitivity and light absorption coefficient for visible light than amorphous selenium.

[0098] In FIG. 5, the photoelectric conversion layer 561 is shown as a single layer. However, as shown in FIG. 6(A), gallium oxide, cerium oxide, or In-Ga-Zn oxide or the like may be provided as a hole injection blocking layer 568 on the light receiving surface side. Alternatively, as shown in FIG. 6(B), nickel oxide, antimony sulfide, or the like may be provided as an electron injection blocking layer 569 on the electrode 566 side. Alternatively, as shown in FIG. 6(C), a configuration in which a hole injection blocking layer 568 and an electron injection blocking layer 569 are provided may also be used.

[0099] The photoelectric conversion layer 561 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, it may be a layer containing a compound of copper, indium, gallium, and selenium (CIGS). In CIS and CIGS, a photoelectric conversion element utilizing avalanche multiplication can be formed in the same manner as a single layer of selenium.

[0100] The photoelectric conversion element PD using a selenium-based material can be configured to have a photoelectric conversion layer 561 between an electrode 56 formed of a metal material or the like and a transparent conductive layer 562. Also, CIS and CIGS are p-type semiconductors, and cadmium sulfide, zinc sulfide, or the like of an n-type semiconductor may be provided in contact with them to form a junction.

[0101] In FIG. 5, the transparent conductive layer 562 and the wiring 571 are directly in contact. However, as shown in FIG. 6(D), they may be configured to be in contact via a wiring 588. Also, in FIG. 5, the photoelectric conversion Although layer 561 and the light-transmitting conductive layer 562 are not separated between pixel circuits, as shown in Figure 6 ( As shown in E), the circuit may be separated. In the region that does not have 66, an insulating partition 567 is provided, and a photoelectric conversion layer 561 and a light-transmitting conductive layer are provided. It is preferable to prevent cracks from forming in layer 562, as shown in Figures 7(A) and (B). A configuration without a partition wall 567 is also possible.

[0102] Furthermore, electrodes 566 and wiring 571, etc., may be multilayered. For example, as shown in Figure 7(C) Therefore, the electrode 566 is made of two layers, conductive layer 566a and conductive layer 566b, and the wiring 571 is conductive It can consist of two layers, layer 571a and conductive layer 571b. In the configuration shown in Figure 7(C) For example, conductive layers 566a and 571a are formed by selecting a low-resistance metal or the like. The conductive layer 566b and conductive layer 571b are made of a metal or other material with good contact characteristics with the photoelectric conversion layer 561. It is preferable to select and form such a configuration. By adopting this configuration, the electrical characteristics of the photoelectric conversion element PD This can improve the performance. Also, some metals come into contact with the light-transmitting conductive layer 562. This can cause electrolytic corrosion. Even if such a metal is used in the conductive layer 571a, the conductive layer 5 By using 71b, electrolytic corrosion can be prevented.

[0103] For example, the conductive layers 566b and 571b may be made of molybdenum or tungsten. It is possible to have it. Also, conductive layers 566a and 571a are, for example, made of aluminum. Laminations can be used in which um, titanium, or aluminum are sandwiched between layers of titanium.

[0104] Furthermore, as shown in Figure 7(D), the translucent conductive layer 562 and the wiring 571 are conductor 82 and wiring You may also connect via port 588.

[0105] The partition wall 567 can be formed using an inorganic insulator or an insulating organic resin. Wall 567 provides light shielding for transistors, etc., and / or the area of ​​the light-receiving part per pixel. It may be colored black or other colors to confirm its identity.

[0106] Furthermore, the pixel 20 can also be configured in the stacked structure shown in Figure 8(A). Element 20 differs only from pixel 20 and layer 1100 shown in Figure 3(A), with the rest of its configuration being the same. be.

[0107] In Figure 8(A), the photoelectric conversion element PD in layer 1100 has amorphous silicon in the photoelectric conversion layer This shows a pin-type photodiode using a condenser film or a microcrystalline silicon film. The power conversion element PD consists of an n-type semiconductor layer 565, an i-type semiconductor layer 564, and a p-type semiconductor layer 56 3. The configuration may include electrodes 566, wiring 571, and wiring 588.

[0108] Electrode 566 is electrically connected to metal layer 405. Also, p-type semiconductor layer 563 is wiring 588 and wiring 571 are electrically connected to the metal layer 406. The metal layer 406 is provided penetrating the insulating layer 81g.

[0109] It is preferable to use amorphous silicon for the i-type semiconductor layer 564. Layer 563 and n-type semiconductor layer 565 contain dopants that impart their respective conductivity types. Amorphous silicon or microcrystalline silicon can be used. The photodiode used as the power conversion layer has high sensitivity in the wavelength range of visible light, and weak visible light is easy to detect.

[0110] Further, the configuration of the photoelectric conversion element PD having the form of a pin-type thin film photodiode, and the connection form of the photoelectric conversion element PD and the wiring may be the examples shown in FIGS. 8(B), (C), and (D). Note that the configuration of the photoelectric conversion element PD and the connection form between the photoelectric conversion element PD and the wiring are not limited to this, and other forms may be used.

[0111] FIG. 8(B) shows a configuration in which a translucent conductive layer 562 in contact with the p-type semiconductor layer 563 of the photoelectric conversion element PD is provided. The translucent conductive layer 562 acts as an electrode and can increase the output current of the photoelectric conversion element PD.

[0112] For the translucent conductive layer 562, for example, indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, tin oxide containing fluorine, tin oxide containing antimony, graphene or graphene oxide, etc. can be used. Further, the translucent conductive layer 562 is not limited to a single layer, and it may be a laminate of different films.

[0113] FIG. 8(C) shows a configuration in which the translucent conductive layer 562 and the wiring 571 are connected via a conductor 82 and a wiring 588. Note that the p-type semiconductor layer 563 of the photoelectric conversion element PD and the wiring 571 may be connected via a conductor 82 and a wiring 588. In FIG. 8(C), a configuration in which the translucent conductive layer 562 is not provided may also be used.

[0114] FIG. 8(D) shows an insulating layer 81k covering the photoelectric conversion element PD with the p-type semiconductor layer 563 exposed. ​​​​​An opening is provided, and a translucent conductive layer 562 covering the opening and wiring 571 are electrically connected. It has the following configuration.

[0115] The photoelectric conversion element PD formed using the aforementioned selenium-based material or amorphous silicon is a thin film. It is manufactured using common semiconductor fabrication processes such as lithography and etching. It is possible to do so. Also, selenium-based materials have high resistance, and as shown in Figure 5, the photoelectric conversion layer 5 It is also possible to configure 61 without separating it between circuits. Therefore, the yield is high and the cost is low. It can be manufactured using [a specific method / tool].

[0116] The photoelectric conversion element PD in the pixel 20 shown in Figures 5 and 8(A) is a stack of thin films. Therefore, it is preferable to form it after the bonding process.

[0117] Furthermore, the pixel 20 can also have a stacked configuration as shown in Figure 9. The pixel 20 shown in Figure 9 is layered A layer 1200 is formed on 1300, and the layer 1200 and the separately formed layer 1100 are joined at joint position b. It is a bonded structure. That is, in the laminated structure of Figure 3(A), the joint of the metal layers is layer 13 It is provided between layer 00 and layer 1200, but in the laminated configuration shown in Figure 9, layer 1200 and layer 110 It is placed between 0 and 0.

[0118] In Figure 9, the photoelectric conversion element PD in layer 1100 is a p using a single-crystal silicon substrate. This shows an n-type photodiode. The photoelectric conversion element PD is p + area 620, p - territory area 630, n-type area 640, p + The configuration can include a region 650.

[0119] n-type region 640 is electrically connected to the metal layer 402b. Also, p+ Region 650 is a metal layer and is electrically connected to 403b. The metal layer 405 and the metal layer 406 are provided through the insulating layer 81g .

[0120] In layer 1200, a metal layer 402a and a metal layer 403a are provided. The metal layer 402a is provided so as to have a region embedded in the insulating layer 81h, and is electrically connected to one of the source or drain of the transistor 41 through a conductive layer, a conductor 82, etc. Also, the metal layer 4 03a is provided so as to have a region embedded in the insulating layer 81h, and is electrically connected to the wiring 71 through the conductor 82 .

[0121] In layer 1300, a transistor 43 and a transistor 44 which are Si transistors are provided . The gate of the transistor 43 is electrically connected to the other of the source or drain of the transistor 41 and one of the source or drain of the transistor 42 through a conductive layer, a conductor 82, etc .

[0122] Also, the pixel 20 can have a stacked structure shown in FIG. 10. The pixel 20 shown in FIG. 10 is configured by separately forming the layer 1300, the layer 1200, and the layer 1100, and bonding the layer 1300 and the layer 1200 at the bonding position a and bonding the layer 1200 and the layer 1100 at the bonding position b . That is, the joint portion of the metal layers is provided between the layer 1300 and the layer 1200 and between the layer 1200 and the layer 1 1100

[0123] .

[0123] In FIG. 10, the photoelectric conversion element PD included in the layer 1100 shows a pn-type photodiode using a single crystal silicon substrate. The photoelectric conversion element PD has a p region 620, a p + region 620, a p - region 630, n-type region 640, p + The configuration can include a region 650.

[0124] n-type region 640 is electrically connected to the metal layer 402b. Also, p + Region 650 is a metal layer It is electrically connected to 403b. Metal layers 402a and 403b are connected to insulating layer 81g. It is installed by penetrating it.

[0125] Layer 1200 is provided with metal layer 401b, metal layer 402a, and metal layer 403a. Layer 401b is provided to have a region embedded in the insulating layer 81d, and the conductive layer and conductive The other side of the source or drain of transistor 41 and transistor 4 via body 82 etc. It is electrically connected to either the source or drain of 2. Metal layer 402a is insulated layer 81g It is provided to have an embedded region, and a transient is transmitted via the conductive layer and the conductor 82, etc. It is electrically connected to either the source or drain of sta 41. Also, the metal layer 403a It is provided so as to have a region embedded in the insulating layer 81g, and the wiring 71 is connected via the conductor 82. It is electrically connected.

[0126] A metal layer 401a is provided in layer 1300. The metal layer 401a is embedded in the insulating layer 81c. It is provided to have a region, and via the conductive layer and conductor 82 etc., the transistor 41 It is electrically connected to either the source or the drain of the device.

[0127] An example of a method for fabricating the laminated structure shown in Figure 3(A) will be explained using Figures 11(A1) to (A3). do.

[0128] First, a layer 1300 having an insulating layer 81c and a metal layer 401a as the uppermost layer is fabricated (Figure 1). See 1(A1). The metal layer 401a is, for example, the gateway of the transistor 43 to the insulating layer 81c. A through-hole is formed that reaches the wiring layer to which the electrode is electrically connected, and CVD, plating, etc. are used. Then, a metal layer is provided to fill the through hole, and the surface is polished to remove the excess metal layer. Alternatively, the metal layer 401a can be fabricated using a film deposition method such as CVD or sputtering. First, the metal layer 401a is formed, then an insulating layer 81c is formed to cover it, and the surface is polished. The upper surface of the metal layer 401a may be exposed. In either method, polishing is performed using CMP (C The entire surface is polished using methods such as chemical mechanical polishing. The surface is flattened to minimize any step difference between the metal layer 401a and the insulating layer 81c. It is preferable.

[0129] Furthermore, a photoelectric conversion element PD was fabricated, and an insulating layer 81d and gold were placed on top of the photoelectric conversion element PD. A layer 1200 having a related layer 401b is prepared.

[0130] Photoelectric conversion elements (PDs) are, for example, made by doping a single-crystal silicon substrate 670 using methods such as diffusion or doping. It is fabricated by forming an impurity region using this method. Then, an OS transient is placed on the photoelectric conversion element PD. Each element, such as a star, is electrically connected to form the structure, with an insulating layer 81d and a metal layer 40 on top. Form 1b. Metal layer 401b can be formed in the same way as metal layer 401a, CMP The surfaces of the insulating layer 81d and the metal layer 401b are planarized using methods such as the above.

[0131] Next, the planarized surface of layer 1300 and the planarized surface of layer 1200 are subjected to the aforementioned The following pre-bonding treatment is performed. After that, the metal layer 401a and the metal layer 401b come into contact. Align the parts and bond them together, then perform appropriate processing on both parts and the insulating layer 8 Join 1c and the insulating layer 81d (see Figure 11(A2)).

[0132] After bonding is complete, the unnecessary areas of the single-crystal silicon substrate 670 are polished, and the photoelectric conversion The light-receiving surface of the PD element is exposed, and a protective film such as an insulating layer is formed as needed (Figure 11(A See 3). The layered structure shown in Figure 3(A) is thus completed.

[0133] Note that the polishing of the single-crystal silicon substrate 670 is performed before the bonding process or the OS transistor This may be done before forming the substrate. In that case, use a removable adhesive or the like, and a suitable support substrate. It is preferable to carry out the process by providing a [specific component / feature].

[0134] Figures 11(B1) to (B4) show an example of a method for fabricating the laminated structure shown in Figures 5 and 8(A). This will be explained using the following. Furthermore, the method for manufacturing layer 1300 and the bonding of layer 1300 and layer 1200 will be explained. The blending process can refer to the method for producing the pixel 20 shown in Figure 3(A) above.

[0135] First, a layer 1300 having an insulating layer 81c and a metal layer 401a as the uppermost layer is fabricated (Figure 1). 1(B1)).

[0136] Furthermore, a release layer 1800 is applied to a flat support substrate 1700 such as a glass substrate or a semiconductor substrate. A layer 120 is provided on the release layer 1800, with an insulating layer 81d and a metal layer 401b as the uppermost layer. Create 0.

[0137] The release layer 1800 is formed, for example, by laminating a tungsten film and a silicon oxide film. This is possible. The laminate is thermally stable, and after the transistor fabrication process is completed... By applying physical force, delamination occurs near the interface between the tungsten film and the silicon oxide film. This can be done. Alternatively, a polyimide film may be used as the release layer 1800. When a film is used, it is preferable to use a light-transmitting substrate, and the transistor fabrication process is completed. Afterward, light such as laser light is irradiated from the translucent substrate side to weaken the polyimide film and peel it off. This can be done. Alternatively, a thermally stable, peelable adhesive, etc., can be used as the release layer 1800. You may use it.

[0138] Next, layer 1300 and layer 1200 are bonded together (see Figure 11(B2)).

[0139] After bonding is complete, the laminate of layers 1300 and 1200 is formed from the support substrate 1700. Remove the peeled layer. If any part of the peeled layer remains on the surface of layer 1200, clean it or remove it. Remove by chipping or other means to expose the surfaces of metal layer 405 and metal layer 406. See Figures 11(B3) and 3(A).

[0140] Then, a layer 1100 having a photoelectric conversion element PD is formed on layer 1200 (Figure 11(B4) (See reference). This completes the layered structure shown in Figure 5 or Figure 8(A).

[0141] An example of a method for fabricating the laminated structure shown in Figure 9 will be explained using Figures 12(A1) to (A4). Furthermore, the method for fabricating and bonding the metal layers at the joint is as shown in Figure 3(A) for the laminated structure. The manufacturing method can be referenced.

[0142] First, layer 1300 is fabricated (see Figure 12(A1)), and an insulating layer 81 is placed on top of layer 1300 as the uppermost layer. h. A layer 1200 having metal layer 402a and metal layer 403a is fabricated (Figure 12(A2 )). At this time, the elements of layer 1300 and the elements of layer 1200 are electrically charged as needed. Establish a connection.

[0143] Next, the single-crystal silicon substrate 670 on which layer 1200 and the photoelectric conversion element PD are bonded together. The process involves metal layers 402a and 402b, metal layers 403a and 403b, Next, the insulating layer 81h and insulating layer 81g are joined together (see Figure 12(A3)).

[0144] After bonding is complete, the unnecessary areas of the single-crystal silicon substrate 670 are polished, and the photoelectric conversion The light-receiving surface of the PD element is exposed, and a protective film such as an insulating layer is formed as needed (Figure 12(A See 4). As a result, layer 1100 can be formed, and the laminated structure shown in Figure 9 is completed. do.

[0145] The polishing of the single-crystal silicon substrate 670 may be performed before the bonding process. In this process, it is preferable to use a removable adhesive and provide a support substrate as appropriate.

[0146] An example of a method for fabricating the laminated structure shown in Figure 10 will be explained using Figures 12(B1) to (B5). The method for fabricating and bonding the metal layers at the joint is as shown in Figure 3(A) for the laminated structure. The manufacturing method can be referenced.

[0147] First, a layer 1300 having an insulating layer 81c and a metal layer 401a as the uppermost layer is fabricated (Figure 1). 2(B1)).

[0148] Furthermore, a release layer 1800 is applied to a flat support substrate 1700 such as a glass substrate or a semiconductor substrate. A layer is provided, with an insulating layer 81g, a metal layer 402a and a metal layer 403a as the bottom layer on top of the release layer 1800. A layer 1200 is fabricated having an insulating layer 81d and a metal layer 401b as the uppermost layer.

[0149] Next, layer 1300 and layer 1200 are bonded together (see Figure 12(B2)).

[0150] After bonding is complete, the laminate of layers 1300 and 1200 is formed from the support substrate 1700. Remove the peeled layer. If any part of the peeled layer remains on the surface of layer 1200, clean it or remove it. Remove by chipping or other means to expose the surfaces of metal layer 402a and metal layer 403a. (See Figure 12 (B3)).

[0151] Next, the single-crystal silicon substrate 670 on which layer 1200 and the photoelectric conversion element PD are bonded together. The process involves metal layers 402a and 402b, metal layers 403a and 403b, Next, the insulating layer 81h and insulating layer 81g are joined together (see Figure 12 (B4)).

[0152] After bonding is complete, the unnecessary areas of the single-crystal silicon substrate 670 are polished, and the photoelectric conversion The light-receiving surface of the PD element is exposed, and a protective film such as an insulating layer is formed as needed (Figure 12(B) See 5). As a result, layer 1100 can be formed, and the laminated structure shown in Figure 10 is complete. To accomplish.

[0153] The polishing of the single-crystal silicon substrate 670 may be performed before the bonding process. In this process, it is preferable to use a removable adhesive and provide a support substrate as appropriate.

[0154] Furthermore, in an imaging device according to one aspect of the present invention, a Si transistor formed in layer 1300 is used to rotate the pixels. A circuit different from the main path can be provided. For example, such a circuit could be a column driver. Drive circuits such as low drivers, data conversion circuits such as A / D converters, CDS(C Noise reduction circuits such as (or related) Double Sampling circuits, This includes the control circuit for the entire imaging device.

[0155] Transistors 46 and 47 included in any of the above circuits are shown in Figure 13. Transistors 46 and 47 can be formed in a region that overlaps with the photoelectric conversion element PD. Also, one or both of transistors 46 and 47 may be connected to one or both of transistors 41 and 42. It may be formed in a region that overlaps with both. That is, the above circuit is formed in a region that overlaps with pixel 20. This is achieved. Note that in Figure 13, transistor 46 is a p-channel type, and transistor 47 is an n-channel type. The example shown is a CMOS inverter configured as a channel type, but other circuit configurations are also available. That's good too.

[0156] Furthermore, as shown in Figure 14, transistor 47 is an OS transistor provided in layer 1200. It may be present. In the configuration shown in Figure 14, transistors 46 and 47 overlap each other. It can be formed in a specific area through a bonding process, thereby reducing the circuit area. Furthermore, when the transistors 44 and 45 of the pixel 20 are formed in the p-channel type, single crystal All transistors on the recon board 600 can be p-channel type, or n-channel type The process of forming the Si transistor can be omitted.

[0157] Figures 13 and 14 show the pixel 20 shown in Figure 3(A) with transistors 46 and 47 attached. The stacked configuration is shown, but in Figure 5, Figure 9, or Figure 10, pixel 20 contains transistor 4 You can also add 6 and 47.

[0158] Figure 15(A) is a block diagram illustrating the circuit configuration of an imaging device according to one embodiment of the present invention. The imaging device includes a pixel array 21 having pixels 20 arranged in a matrix, and a pixel array A circuit 22 (low driver) has the function of selecting row I21, and the output signal of pixel 20 In contrast, there is circuit 23 (CDS circuit) for performing CDS operation, and the output from circuit 23 A circuit 24 (such as an A / D conversion circuit) that has the function of converting log data into digital data, Circuit 25 (column driver) has the function of selecting and reading the data converted by circuit 24. ) and . It is also possible to have a configuration without circuit 23. The circuits leading to 25 are combined and designated as circuit 30.

[0159] Figure 15(B) shows the schematic of circuit 23 connected to one row of the pixel array 21 and circuit 24 This is a block diagram. Circuit 23 consists of transistor 51, transistor 52, and capacitive element C3. The configuration can also include a capacitive element C4. Furthermore, the circuit 24 is a comparator circuit. The configuration may include a path 27 and a counter circuit 29.

[0160] Transistor 53 functions as a current source circuit. The source of transistor 53 or Wiring 91 (OUT1) is electrically connected to one side of the drain, and the other side of the source or drain A power line is connected to this side. This power line can be, for example, a low-voltage power line (VSS). Yes, it is possible. Also, a bias voltage is constantly applied to the gate of transistor 53. Let's assume that.

[0161] In circuit 23, either the source or drain of transistor 51 is connected to transistor 52 It is electrically connected to either the source or the drain of transistor 51. One side of the drain is electrically connected to one electrode of the capacitive element C3. Transistor 52 The source or the other drain is electrically connected to one electrode of the capacitive element C4. The source or drain of ZISTA 52 is electrically connected to wiring 92 (OUT2). The source or drain of transistor 51 is supplied with, for example, a high reference potential. It is electrically connected to the potential power line (CDSVDD). The other electrode of the capacitive element C4 is, for example It is electrically connected to the low-voltage power line (CDSVSS).

[0162] An example of the operation of circuit 23 when connected to pixel 20 shown in Figure 1(B) will be explained. First, Connect transistors 51 and 52. Next, connect the wiring 91 from pixel 20. The potential of the imaging data is output to OUT1), and the reference potential (CDSVD) is output to wiring 92 (OUT2). Hold D). Then, make transistor 51 non-conductive and wire 91 (OU) from pixel 20. T1) Reset potential (here, a potential higher than the potential of the imaging data, for example, VDD potential and It outputs (the result). At this time, wiring 92 (OUT2) is connected to the potential of the imaging data and the reset power. The absolute value of the difference in positions is added to the reference potential (CDSVDD) to obtain the potential. Therefore, the reference A low-noise potential signal obtained by adding the net imaging data potential to the potential (CDSVDD). It can be supplied to circuit 24.

[0163] Note that the reset potential is lower than the potential of the imaging data (for example, the GND potential). In this case, wiring 92 (OUT2) uses the absolute value of the difference between the potential of the imaging data and the reset potential as the reference voltage. This is the potential obtained by subtracting from the position (CDSVDD).

[0164] In circuit 24, the signal potential input from circuit 23 to comparator circuit 27 is compared with an upward or downward or It is compared to a reference potential (RAMP) that is swept downwards. Then, the comparator... The counter circuit 29 operates according to the output of circuit 27, and a digital signal is sent to wiring 93 (OUT3). A signal is output.

[0165] Furthermore, an imaging device according to one aspect of the present invention includes a pixel array 21 and a circuit section 35 having a circuit 30. A stacked structure can be formed. For example, Figure 16(A) is a top view of the pixel array 21, and Figure 1 When 6(B1) and (B2) are top views of the circuit section 35, the perspective view is shown in Figure 16(C). The pixel array 21 and the circuit section 35 can be stacked. Therefore, transistors suitable for each element can be used, and the area of ​​the imaging device can be reduced. It can be cut. Note that the circuit layout in Figures 16(B1) and (B2) is the same. This is an example, and other layouts are also possible. Furthermore, the circuit section 35 may be configured to include a control circuit 26. Although this is an example, the control circuit 26 may be located outside the circuit section 35.

[0166] Circuits 22 and 30 shown in Figure 16(B1) are divided into two, and the ends are located near the center. The configuration to be arranged is shown. The shift register circuits of circuits 22 and 30 are 2 The divided regions can operate independently, or they can operate as a series of shift register circuits. You may allow it.

[0167] Circuits 22 and 30 shown in Figure 16(B2) are divided into two parts, similar to Figure 16(B1). However, the circuit is arranged diagonally.

[0168] By using the configuration shown in Figures 16(B1) and (B2), circuits 22 and 30 are provided at the ends. This reduces the load on each wire connected to the pixel 20. The load on the wiring is not uniform, but if the wiring capacitance and resistance are small, the unevenness will not be a problem. do not have.

[0169] Circuits 22 and 30 are designed to achieve both high-speed operation and a CMOS circuit configuration, using silico It is preferable to fabricate it using a transistor made of silicon (hereinafter referred to as a Si transistor). For example, the circuit section 35 can be formed on the silicon substrate. Also, the pixel array 21 is It can be fabricated using an oxide semiconductor transistor (hereinafter referred to as an OS transistor). Preferred. Note that some of the transistors constituting circuits 22 and 30 are OS transistors. It may be formed with a sta.

[0170] Figure 17(A) is a cross-sectional view of an example of an imaging device with a color filter and the like added. The cross-sectional view shows a portion of the region having a pixel circuit for 3 pixels. The photoelectric conversion element PD is An insulating layer 2500 is formed on the formed layer 1100. The insulating layer 2500 is visible light In contrast, highly light-transmitting silicon oxide films can be used. Also, passivation A configuration in which silicon nitride films are laminated as the film may also be used. Alternatively, as the anti-reflective film, A configuration in which dielectric films such as humic acid are stacked may also be used.

[0171] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 is on top It has the function of preventing the mixing of colors of light passing through the color filter. The light-shielding layer 2510 is made of aluminum Metal layers such as um and tungsten, or dielectrics that function as an anti-reflective coating with the said metal layers. A configuration in which multiple films are stacked can be used.

[0172] An organic resin layer 2520 is provided on the insulating layer 2500 and the light-shielding layer 2510 as a planarizing film. It can be configured as follows. Also, a color filter 2530 (color filter 25 30a, color filter 2530b, color filter 2530c) are formed. , color filter 2530a, color filter 2530b and color filter 2530 c can represent R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By assigning colors, a color image can be obtained.

[0173] A light-transmitting insulating layer 2560 or the like can be provided on the color filter 2530. ru.

[0174] Also, as shown in Figure 17(B), instead of the color filter 2530, the optical conversion layer 255 You may also use 0. With this configuration, images can be obtained in various wavelength ranges. It can be used as an imaging device.

[0175] For example, if a filter that blocks light with wavelengths below visible light is used in the optical conversion layer 2550, infrared It can be used as an imaging device. Furthermore, the optical conversion layer 2550 blocks light with wavelengths below near-infrared. By using a filter, it can be made into a far-infrared imaging device. Also, the optical conversion layer 2550 By using a filter that blocks light with wavelengths greater than visible light, it can be converted into an ultraviolet imaging device. .

[0176] Furthermore, if a scintillator is used in the optical conversion layer 2550, radiation can be used in X-ray imaging devices, etc. It can be used as an imaging device to obtain an image that visualizes the strength of the lines. When radiation enters a scintillator, the photoluminescence phenomenon causes visible light and purple light to be emitted. It is converted into light (fluorescence) such as ambient light. Then, this light is detected by a photoelectric converter element (PD). Image data is acquired by using the imaging device with the above configuration as a radiation detector or the like. That's good too.

[0177] When a scintillator is irradiated with radiation such as X-rays or gamma rays, it absorbs that energy. It contains substances that emit visible light and ultraviolet light. For example, Gd2O2S:Tb, Gd2O2S:P r, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, C It is possible to use materials in which eF3, LiF, LiI, and ZnO are dispersed in resin or ceramics. Cut.

[0178] Figure 47(A) is a photograph of an X-ray imaging panel fabricated using an OS transistor. The dimensions are 100.5mm x 139mm, the number of pixels is 384 x 512, and the pixel size is 120 The dimensions are μm × 120 μm, the resolution is 106 ppi, and the photodiode is made of amorphous silicon. It uses a low driver for selecting pixels and a control for the output signal. It has a built-in multiplexer.

[0179] Figure 47(B) shows the above X-ray imaging panel with a scintillator (Gd2O2S:Tb) added. This is an X-ray image taken. A lead plate, a copper coin, and a resin casing were placed on the panel. A sensor is placed, and X-rays are shone from above to take images. Underneath the lead plate that shields the X-rays, Because the intiler does not emit light, the resulting image is black. Made of copper, which transmits X-rays more easily than lead. Images taken under a coin will appear gray. Also, X-rays penetrate watches with resin casings, so the inside The metal parts of the section are imaged.

[0180] Furthermore, in photoelectric converters (PDs) using selenium-based materials, radiation such as X-rays is directly converted into electric charge. Because it can be converted, a configuration that does not require a scintillator can also be implemented.

[0181] Also, as shown in Figure 17(C), color filter 2530a, color filter 2530 A microlens array 2540 may be provided on b and the color filter 2530c. The light passing through each lens of the microlens array 2540 passes through the color filter directly below. As a result, the light is irradiated onto the photoelectric conversion element PD. Also, as shown in Figure 17(D), A microlens array 2540 may be provided on the light conversion layer 2550. See Figure 17(A The region other than layer 1100 shown in (B), (C), and (D) is defined as layer 1600.

[0182] Figure 18 shows a pixel 20 according to one aspect of the present invention and the microlens array 2 shown in Figure 17(C). This figure illustrates specific stacking configurations such as 540. Figure 18 shows pixel 20 as shown in Figure 3(A) This is an example using the configuration shown in Figure 9. Figure 19 also shows an example using the pixel configuration shown in Figure 9.

[0183] Thus, the circuits of the photoelectric conversion element PD and the pixel 20 have overlapping regions. Because it can be configured in this way, the imaging device can be miniaturized.

[0184] Furthermore, as shown in Figures 18 and 19, a diffraction grating is located above the microlens array 2540. A configuration with 1500 is also possible. Image of the subject through the diffraction grating 1500 (diffraction image) The image is captured into a pixel, and the input image (image of the subject) is calculated from the captured image at the pixel. It can be configured. Also, by using a diffraction grating 1500 instead of a lens, the imaging device This can reduce the cost of electronic devices and other equipment that have a built-in storage space.

[0185] The diffraction grating 1500 can be formed from a translucent material. For example, silicone oxide Inorganic insulating films such as silicon oxide nitride films can be used. Alternatively, acrylic resin can be used. Organic insulating films such as lipids and polyimide resins may be used. Alternatively, the above inorganic insulating film and It may also be laminated with an insulating film.

[0186] Furthermore, the diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. Yes, it is possible. It can also be formed using lithography and etching processes. Furthermore, it can also be formed using nanoimprint lithography or laser scribing. ru.

[0187] A gap X may be provided between the diffraction grating 1500 and the microlens array 2540. X can be 1 mm or less, preferably 100 μm or less. This spacing can also be empty space. Alternatively, a light-transmitting material may be provided as a sealing layer or adhesive layer. For example, nitrogen or Inert gases such as noble gases can be contained within that space. Alternatively, acrylic resin, Epoxy resin or polyimide resin may be provided at the intervals. Alternatively, silicone resin may be used. A liquid such as oil may be provided. Note that if the microlens array 2540 is not provided... Alternatively, a gap X may be provided between the color filter 2530 and the diffraction grating 1500.

[0188] Pixel 20 may have the circuit configuration shown in Figure 20(B). Pixel 20 shown in Figure 20(B) In this case, the orientation in which the photoelectric conversion element PD is connected is different from that of pixel 20 shown in Figure 1(A). The potentials of wiring 71 (VPD) and wiring 72 (VRS) are reversed compared to the circuit description in Figure 1(B). This can be used to make it work.

[0189] Furthermore, the transistor used for pixel 20 is transistor 41, as shown in Figure 21(A). Alternatively, a configuration in which a back gate is provided on transistor 44 may also be used. Figure 21(A) shows a back gate. This configuration applies a constant potential to the gate, allowing for control of the threshold voltage.

[0190] The wiring 75 to 78 connected to each back gate is supplied with a different potential individually. It is possible to do so. Alternatively, as shown in Figure 21(B), transistor 41 and transistor The wiring connected to the tailgate of the STA42 may be electrically connected. The wiring connected to the back gates of transistors 43 and 44 is electrically It may be connected electrically.

[0191] In an n-channel transistor, when a potential lower than the source potential is applied to the back gate... The threshold voltage shifts in the positive direction. Conversely, if the back gate is higher than the source potential, When an electric potential is applied, the threshold voltage shifts in the negative direction. Therefore, a predetermined... When controlling the on / off state of each transistor with a set gate voltage, the source voltage is applied to the back gate. Applying a potential lower than the specified value can reduce the off-current. Also, backgain Applying a potential higher than the source potential to the tortoise can reduce the on-current.

[0192] In the circuits shown in Figures 1, 20(A), (B), and 21(A), (B), the potential of node FD is Since high retention capacity is desired, as mentioned above, transistors 41 and 42 are set to OFF-voltage. It is preferable to use low-current OS transistors. Backgear of transistors 41 and 42 By applying a potential lower than the source potential to the circuit, the off-current can be reduced. Therefore, the potential retention capability of node FD can be increased.

[0193] Furthermore, as mentioned above, transistors 43 and 44 are Si transistors with high on-current. It is preferable to use a source potential higher than the source potential at the back gates of transistors 43 and 44. By applying an electric potential, the on-current can be increased. Therefore, wiring 91 The readout potential output to (OUT1) can be quickly determined, that is, high It can be operated at high frequencies.

[0194] Furthermore, as shown in Figure 21(C), transistor 44 has the same potential as the front gate. It may also be configured to be applied to the gate. Also, transistors 43 and 44 are Si transistors It can be an OS transistor instead of a ZISTA. The on-current of an OS transistor is comparative Although the target is small, the on-current can be increased by providing a back gate, and high frequency It will be possible to operate it in this way.

[0195] Furthermore, within the imaging device, in addition to the power supply potentials, the signal potential and the potential applied to the back gate are also considered. Multiple potentials are used, such as a specific potential. When multiple potentials are supplied from outside the imaging device, the number of terminals... Because factors such as these increase, the imaging device has a power supply circuit that generates multiple potentials inside. It is preferable.

[0196] The operation of the pixel circuit shown in Figure 21(A) will be explained using the timing chart shown in Figure 22. In a timing chart, "V1" is a potential higher than the reference potential, for example, high This can be the power supply potential (VDD). "V0" is the reference potential, i.e., the source potential. For example, it can be 0V, GND potential, or low power supply potential (VSS).

[0197] First, at time T1, the potential of wiring 75 (RS) and wiring 61 (TX) is set to "V1". Then, transistors 41 and 42 conduct, and node FD reaches the reset potential (e.g., VDD). It is reset (reset operation). At this time, wires 75 and 76 are connected to “V0”. By setting a high potential (>"V0"), the on-current of transistors 41 and 42 is increased. A reset operation can be performed quickly.

[0198] If the potential of wiring 75(RS) at time T2 is set to "V0", then transistor 42 becomes non-conductive. Then, the reset operation is completed and the storage operation begins. At this time, wire 76 is connected to “V0”. By setting a low potential, the off-current of transistor 42 can be reduced, and the leakage current... This prevents the supply of charge to node FD. Note that at time T2, The potential of line 75 may be defined as "V0".

[0199] If the potential of wiring 61 (TX) is set to "V0" at time T3, then transistor 41 will be non-conductive. Then, the potential of node FD is determined and held (holding operation). At this time, wiring 75 is set to “V0 By setting a lower potential (<"V0"), the off-current of transistor 41 is reduced. This allows for the prevention of charge outflow from the node FD due to leakage current.

[0200] If the potential of wiring 63(SE) at time T4 is set to "V1", then transistor 44 will conduct, The potential of wiring 91 (OUT1) changes according to the current flowing through transistor 43 (readout). Operation). At this time, wires 77 and 78 are set to a potential higher than "V0" (> "V0"). This increases the on-current of transistors 43 and 44, allowing for quick connection of the wiring 91 (OUT1 The potential of ) can be determined.

[0201] If the potential of wiring 63(SE) is set to "V0" at time T5, then transistor 44 will be non-conductive. The read operation is then completed. Note that the potential of node FD remains constant until the read operation is finished. To prevent changes, keep the potential of wires 75 and 76 at a potential lower than "V0" (<"V0"). It is preferable to do so. In the above description, wiring 76 is done at the same timing as wiring 75. The potential may be changed.

[0202] As a result, a signal corresponding to the potential of node FD can be read out. (See Figure 1(A)) The pixel 20 shown is controlled by omitting the control of wiring 75 to 78 in the timing chart shown in Figure 22. Simply run it. Pixel 20 shown in Figure 21(B) corresponds to the timing chart shown in Figure 22. You can operate it by omitting the control of wiring 76 and 78.

[0203] Furthermore, a pixel circuit according to one aspect of the present invention has multiple pixels as shown in Figures 23(A) and (B). A configuration that shares the transistors is also acceptable.

[0204] In the transistor-shared pixel shown in Figure 23(A), pixels 20a to 20d are each photoelectric It has a conversion element PD and a transistor 41 separately, and transistors 42, 43, 44 and The configuration shares a capacitance element C1. The transistors of pixels 20a to 20d Each of the 41 is controlled by wiring 61a to 61d. In this configuration, each pixel It can sequentially perform reset, storage, hold, and read operations, mainly for low-power storage. It is suitable for imaging using a long-shutter method.

[0205] In the transistor-shared pixel shown in Figure 23(B), pixels 20a to 20d are each photoelectric It has a conversion element PD and transistors 41, 45 individually, and transistors 42, 43, 4 This configuration shares 4 and the capacitive element C1. It operates based on the potential of wiring 65 (GPD). A transistor 45, which controls the function, is provided between the photoelectric conversion element PD and the wiring 71 (VPD). This allows the potential to be maintained at the cathode of the photoelectric conversion element PD. Therefore, all Simultaneously, reset, storage, and hold operations are performed sequentially for each pixel, followed by a read operation for each pixel. It is suitable for imaging using a global shutter method.

[0206] The pixel circuits shown in Figures 23(A) and (B) are in the direction in which the wiring 91 (OUT1) extends (hereinafter, Multiple pixels (pixels 20a, 20b, 20c, 20d) arranged vertically form a transistor The configuration shows a shared wiring, but in the direction in which wiring 63(SE) extends (hereinafter referred to as the horizontal direction) A configuration in which multiple pixels arranged in a row share a transistor is also possible. Alternatively, in the horizontal and vertical directions. It may also be a configuration in which multiple pixels arranged in a row share a transistor.

[0207] Furthermore, the number of pixels sharing a transistor is not limited to 4 pixels; it can be 2, 3, or 5 pixels. That's fine too.

[0208] In Figures 23(A) and (B), wiring 72 (VRS) and wiring 73 (VPI) shown in Figure 1 are The diagram shows a configuration that integrates and omits wiring 72 (VRS), but wiring 72 (VRS) is present. This configuration is also possible. Furthermore, the other electrode of the capacitive element C1 is in contact with the wiring 73 (VPI). The example shown is a continuation, but it may also be connected to wiring 71 (VPD).

[0209] Furthermore, the imaging device may be curved as shown in Figures 24(A1) and 24(B1). Figure 24(A1) shows the imaging device curved along the dashed line Y1-Y2 in the figure. This is shown. Figure 24(A2) shows the area indicated by the dashed line X1-X2 in Figure 24(A1). This is a cross-sectional view. Figure 24(A3) shows the area indicated by the dashed line Y1-Y2 in Figure 24(A1). This is a cross-section.

[0210] Figure 24(B1) shows the imaging device curved along the dashed line X3-X4 in the figure, and The diagram shows the curved state along the dashed line Y3-Y4. Figure 24(B2) is a diagram. This is a cross-sectional view of the area indicated by the dashed line X3-X4 in 24(B1). Figure 24(B3) is This is a cross-sectional view of the area indicated by the dashed line Y3-Y4 in Figure 24(B1).

[0211] By curving the imaging device, image field curvature and astigmatism can be reduced. This facilitates the optical design of lenses and other components used in combination with imaging devices. For example, Because the number of lenses required for aberration correction can be reduced, semiconductor devices using imaging devices can be miniaturized. It can be easily made lighter and more compact. Furthermore, it can improve the quality of captured images. Cut.

[0212] In this embodiment, one aspect of the present invention has been described. Or, other embodiments may be described. In this section, one aspect of the present invention will be described. However, this aspect of the present invention is not limited to these. It is not possible. In other words, various aspects of the invention are described in this embodiment and other embodiments. Therefore, one aspect of the present invention is not limited to a specific aspect. For example, one aspect of the present invention and An example of its application to an imaging device has been shown, but one aspect of the present invention is not limited thereto. In some cases, or depending on the circumstances, one aspect of the present invention may not be applied to an imaging device. This is also possible. For example, one aspect of the present invention may be applied to a semiconductor device having a different function. Example For example, in one aspect of the present invention, the channel formation region and source-drain region of a transistor Although examples of cases having oxide semiconductors have been shown, one aspect of the present invention is not limited thereto. In some cases, or depending on the circumstances, various transitions in one aspect of the present invention The channel formation region of a transistor, or the source-drain region of a transistor, etc. The present invention may have various semiconductors. Depending on the circumstances, the present invention may be used in some cases or situations. Various transistors, channel formation regions of transistors, or transistors in one embodiment The source and drain regions of a converter are, for example, made of silicon, germanium, or silicon gel. Manium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphate, It may have at least one of the following: gallium nitride, or an organic semiconductor. Or, for example... For example, depending on the circumstances, or depending on the situation, various transitions in one aspect of the present invention The channel formation region of a transistor, or the source-drain region of a transistor. These do not necessarily have oxide semiconductors. For example, in one aspect of the present invention, global An example of the Ru-Shatta method has been shown, but one aspect of the present invention is not limited thereto. Depending on the circumstances, one aspect of the present invention may be expressed in another manner, for example, rolling A shutter method may be used. Alternatively, depending on the circumstances, or depending on the situation, a global The Lushatter method does not need to be used.

[0213] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0214] (Embodiment 2) In this embodiment, the OS transistor that can be used in one aspect of the present invention is shown in the drawings. This will be explained using [the following]. Note that in the drawings of this embodiment, some elements are [the following] for clarity. The illustrations are enlarged, reduced, or abbreviated.

[0215] Figures 25(A) and (B) show a top view and a cross-sectional view of a transistor 101 according to one embodiment of the present invention. Yes. Figure 25(A) is a top view, and the cross section is in the direction of the dashed line B1-B2 shown in Figure 25(A). This corresponds to Figure 25(B). Also, the cross-section in the direction of the dashed line B3-B4 shown in Figure 25(A) is This corresponds to Figure 27(A). Also, the direction of the dashed line B1-B2 is the channel length direction, and the dashed line B The 3-B4 direction is referred to as the channel width direction.

[0216] The transistor 101 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 140 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 150, oxide semiconductor layer 130, conductive layer 140, and insulating layer 1 in contact with conductive layer 150 60, conductive layer 170 in contact with insulating layer 160, conductive layer 140, conductive layer 150, insulating layer 1 60 and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175 , and also, if necessary, the insulating layer 180 may be given the function of a planarizing film. .

[0217] The conductive layer 140 is the source electrode layer, the conductive layer 150 is the drain electrode layer, and the insulating layer 160 is the gate insulating layer. The edge film and the conductive layer 170 can each function as gate electrode layers.

[0218] In Figure 25(B), region 231 is the source region, region 232 is the drain region, and region 233 is It can function as a channel-forming region. Regions 231 and 232 are conductive layer 1 40 and conductive layer 150 are in contact with each other, and conductive layer 140 and conductive layer 150 are Using a conductive material that readily bonds with oxygen will reduce the resistance of regions 231 and 232. It is possible.

[0219] Specifically, the oxide semiconductor layer 130 and the conductive layer 140 and conductive layer 150 come into contact with each other. Oxygen vacancies occur within the oxide semiconductor layer 130, and these oxygen vacancies remain within the oxide semiconductor layer 130. Due to interactions with hydrogen that is either distilled or diffused from the outside, regions 231 and 232 have low resistance. It becomes an n-type resistance.

[0220] Furthermore, the "source" and "drain" functions of a transistor are related to transistors with different polarities. When adopting a circuit, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are interchangeable. It may be used in this manner. Also, "electrode layer" can be replaced with "wiring." can.

[0221] The diagram shows an example where the conductive layer 170 is formed by two layers: conductive layer 171 and conductive layer 172. However, it may be a single layer or a stack of three or more layers. This configuration is similar to the other configurations described in this embodiment. It can also be applied to transistors.

[0222] The diagram shows examples where conductive layers 140 and 150 are formed as single layers, but two or more layers are also shown. It may also be a layer. This configuration can be applied to other transistors described in this embodiment. .

[0223] A transistor according to one aspect of the present invention may have the configuration shown in Figures 25(C) and (D). Figure 25(C) is a top view of transistor 102, and the dashed line C1-C shown in Figure 25(C) The cross-sections in two directions correspond to Figure 25(D). Also, the dashed line C3-C4 shown in Figure 25(C) The cross-section in the direction corresponds to Figure 27(B). Also, the direction of the dashed line C1-C2 is the length of the channel. The direction of the dashed line C3-C4 is referred to as the channel width direction.

[0224] The transistor 102 has an insulating layer 160 that acts as a gate insulating film and a gate electrode layer. Except for the fact that it does not coincide with the edge of the conductive layer 170 which acts as a transistor, it is the same as transistor 101. It has the following configuration. The structure of transistor 102 is such that conductive layer 140 and conductive layer 150 are insulated Because it is broadly covered by the edge layer 160, the conductive layer 140 and conductive layer 150 and conductive layer 170 It has the characteristic of high resistance between the terminals and low gate leakage current.

[0225] Transistors 101 and 102 have conductive layers 170 and 140 and This is a top gate structure having a region where the electrochemical layer 150 overlaps. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacity. In this configuration, since no offset region is formed in the oxide semiconductor layer 130, the on-current is high It is easy to form transistors.

[0226] A transistor according to one aspect of the present invention may have the configuration shown in Figures 25(E) and (F). Figure 25(E) is a top view of transistor 103, and the dashed line D1-D shown in Figure 25(E) The cross-sections in two directions correspond to Figure 25(F). Also, the dashed line D3-D4 shown in Figure 25(E) The cross-section in the direction corresponds to Figure 27(A). Also, the direction of the dashed line D1-D2 is the length of the channel. The direction indicated by the dashed line D3-D4 is referred to as the channel width direction.

[0227] Transistor 103 has an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A material semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, and an insulating layer 160 in contact with The conductive layer 170, the oxide semiconductor layer 130, the insulating layer 160, and the insulating layer covering the conductive layer 170 are all connected. Edge layer 175, insulating layer 180 in contact with insulating layer 175, insulating layer 175 and insulating layer 180 A conductive layer 140 is electrically connected to the oxide semiconductor layer 130 through an opening provided therein. It also has a conductive layer 150. Furthermore, an insulating layer 180, a conductive layer 140, and a conductive layer may be added as needed. It may have an insulating layer (planarized film) in contact with 150.

[0228] The conductive layer 140 is the source electrode layer, the conductive layer 150 is the drain electrode layer, and the insulating layer 160 is the gate insulating layer. The edge film and the conductive layer 170 can each function as gate electrode layers.

[0229] In Figure 25(F), region 231 is the source region, region 232 is the drain region, and region 233 is It can function as a channel-forming region. Regions 231 and 232 are insulating layer 1 It is in contact with 75, and if, for example, an insulating material containing hydrogen is used as the insulating layer 175, then region 231 Furthermore, the resistance of region 232 can be reduced.

[0230] Specifically, the process up to forming the insulating layer 175 generates in regions 231 and 232 The interaction between the oxygen deficiency and the hydrogen diffusing from the insulating layer 175 to regions 231 and 232 As a result of this action, regions 231 and 232 become low-resistance n-type. Note that this is an insulating material containing hydrogen. Materials such as silicon nitride and aluminum nitride can be used.

[0231] A transistor according to one aspect of the present invention may have the configuration shown in Figures 26(A) and (B). Figure 26(A) is a top view of transistor 104, and the dashed line E1-E shown in Figure 26(A) The cross-section in two directions corresponds to Figure 26(B). Also, the dashed line E3-E4 shown in Figure 26(A) The cross-section in the direction corresponds to Figure 27(A). Also, the direction of the dashed line E1-E2 is the length of the channel. The direction indicated by the dashed line E3-E4 is referred to as the channel width direction.

[0232] Transistor 104 has conductive layers 140 and 150 at the edges of oxide semiconductor layer 130. Except for the fact that it is in contact with the other element in a way that covers it, it has the same configuration as transistor 103.

[0233] Regions 331 and 334 shown in Figure 26(B) are the source region, region 332 and region 3 Region 35 can function as a drain region, and region 333 can function as a channel-forming region.

[0234] Regions 331 and 332 correspond to regions 231 and 23 in transistor 101. Similar to method 2, the resistance can be reduced.

[0235] Regions 334 and 335 correspond to regions 231 and 23 in transistor 103. Similar to 2, the resistance can be reduced. Note that region 334 and in the channel length direction When the length of region 335 is 100 nm or less, preferably 50 nm or less, the gate electric field The ON current does not decrease significantly due to the contribution. Therefore, the low of regions 334 and 335 Resistance training may not always be performed.

[0236] Transistors 103 and 104 have conductive layers 170 and 140 and It is a self-aligned structure in which the electrolytic layer 150 does not have any overlapping regions. The lampistor has extremely low parasitic capacitance between the gate electrode layer and the source and drain electrode layers. Therefore, it is suitable for high-speed operation applications.

[0237] A transistor according to one aspect of the present invention may have the configuration shown in Figures 26(C) and (D). Figure 26(C) is a top view of transistor 105, and the dashed line F1-F shown in Figure 26(C) The cross-sections in two directions correspond to Figure 26(D). Also, the dashed line F3-F4 shown in Figure 26(C) The cross-section in the direction corresponds to Figure 27(A). Also, the dashed line F1-F2 direction is the length of the channel. The direction indicated by the dashed line F3-F4 is referred to as the channel width direction.

[0238] Transistor 105 has an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 141 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 151, oxide semiconductor layer 130, conductive layer 141, insulating layer 160 in contact with conductive layer 151 And, a conductive layer 170 in contact with the insulating layer 160, an oxide semiconductor layer 130, a conductive layer 141, and a conductive layer. An insulating layer 175 that is in contact with layer 151, insulating layer 160 and conductive layer 170, and an insulating layer 175 that is in contact with The insulating layer 180 and the insulating layer 175 and the insulating layer 180 are conductive through openings provided in them. Conductive layers 142 and 15 are electrically connected to layer 141 and conductive layer 151, respectively. It has 2. It also comes into contact with the insulating layer 180, the conductive layer 142 and the conductive layer 152 as needed. It may have an insulating layer or the like.

[0239] The conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and the side surface. It has no such configuration.

[0240] The transistor 105 has conductive layers 141 and 151, and insulating layers 175 and The insulating layer 180 has an opening, and the conductive layer 14 is accessible through the opening. It has conductive layers 142 and 152 that are electrically connected to conductive layer 151 and conductive layer 151, respectively. It has the same configuration as transistor 101, except for the following point. Conductive layer 140 (conductive layer 141 The conductive layer 142) can be used as a source electrode layer, and the conductive layer 150 (conductive Layer 151 and conductive layer 152 can be used as drain electrode layers.

[0241] A transistor according to one aspect of the present invention may have the configuration shown in Figures 26(E) and (F). Figure 26(E) is a top view of transistor 106, and the dashed line G1-G shown in Figure 26(E) The cross-sections in two directions correspond to Figure 26(F). Also, the dashed line G3-G4 shown in Figure 26(E) The cross-section in the direction corresponds to Figure 27(A). Also, the dashed line G1-G2 direction is the length of the channel. The direction of the dashed line G3-G4 is referred to as the channel width direction.

[0242] Transistor 106 has an insulating layer 120 that is in contact with the substrate 115 and an oxide layer that is in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 141 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer in contact with the insulating layer 160. Layer 170, insulating layer 120, oxide semiconductor layer 130, conductive layer 141, conductive layer 151, insulating An insulating layer 175 in contact with layer 160, conductive layer 170, and an insulating layer 180 in contact with insulating layer 175. Through openings provided in the insulating layer 175 and the insulating layer 180, the conductive layer 141 and the conductive It has conductive layers 142 and 152 that are electrically connected to layer 151, respectively. If necessary, an insulating layer (planarized film) in contact with the insulating layer 180, conductive layer 142, and conductive layer 152. They may also have, etc.

[0243] The conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and the side surface. It has no such configuration.

[0244] Transistor 106 has conductive layers 141 and 151, except that the transistor It has the same configuration as Ta 103. The conductive layer 140 (conductive layer 141 and conductive layer 142) is - It can be used as an electrode layer, conductive layer 150 (conductive layer 151 and conductive layer 15 2) can be used as a drain electrode layer.

[0245] In the configuration of transistors 105 and 106, conductive layer 140 and conductive layer 1 Since 50 is not in contact with the insulating layer 120, oxygen in the insulating layer 120 enters the conductive layer 140. Furthermore, it becomes less likely for the conductive layer 150 to absorb acid, and acid from the insulating layer 120 into the oxide semiconductor layer 130 This makes it easier to supply raw materials.

[0246] Regions 231 and 232 in transistor 103, transistor 104 and Regions 334 and 335 in the lampistor 106 form oxygen vacancies and improve conductivity. Impurities may be added to enhance the properties. These impurities may form oxygen vacancies in the oxide semiconductor layer. For example, phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helical Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more elements selected from zinc and carbon may be used. Methods of adding include plasma treatment, ion implantation, ion doping, and plasma treatment. Methods such as Merjohn ion implantation can be used.

[0247] When the above elements are added to the oxide semiconductor layer as impurity elements, the metal in the oxide semiconductor layer The bonds between elements and oxygen are broken, and an oxygen vacancy is formed. Due to the interaction between elementary defects and hydrogen remaining in or later added in the oxide semiconductor layer, The conductivity of the semiconductor layer can be increased.

[0248] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by the addition of impurity elements, oxygen vacancies are formed. Hydrogen enters the loss site and a donor level is formed near the conduction band. As a result, the oxide conductor It can be formed. Here, an oxide semiconductor that has been made conductive is called an oxide conductor. Furthermore, oxide conductors, like oxide semiconductors, are translucent.

[0249] Oxide conductors are degenerate semiconductors in which the conduction band edge and the Fermi level coincide or nearly coincide. It is presumed that there is an oxide conductor layer, a source electrode layer and a drain electrode layer. The contact with the conductive layer that functions is ohmic contact, and the oxide conductive layer and the source electrode layer This reduces the contact resistance with the conductive layer that functions as the drain electrode layer.

[0250] A transistor according to one aspect of the present invention is shown in Figure 28(A), (B), (C), (D), (E), ( F) shows a cross-sectional view in the length direction of the channel, and Figures 27(C) and (D) show the cross-sectional view in the width direction of the channel. As shown in the cross-sectional view, a conductive layer 173 is provided between the oxide semiconductor layer 130 and the substrate 115. It is also possible to use the conductive layer as a second gate electrode layer (back gate). It is possible to increase the current and control the threshold voltage. (See Figures 28(A), (B)) In the cross-sectional views shown in (C), (D), (E), and (F), the width of the conductive layer 173 is the oxide semiconductor. The width of the conductive layer 173 may be shorter than the width of the conductive layer 170. It can also be shortened.

[0251] To increase the ON current, for example, the conductive layer 170 and conductive layer 173 are set to the same potential, double It can be driven as a gate transistor. Also, to control the threshold voltage, A constant potential different from that of the conductive layer 170 should be supplied to the conductive layer 173. To make 73 at the same potential, for example, as shown in Figure 27(D), conductive layer 170 and conductive layer 1 73 can be electrically connected via the contact hole.

[0252] In transistors 101 to 106 in Figures 25 and 26, the oxide semiconductor Although an example where the conductive layer 130 is a single layer is shown, the oxide semiconductor layer 130 may be a stacked layer. The oxide semiconductor layer 130 of transistors 101 to 106 is shown in Figure 29(B). It can be replaced with the oxide semiconductor layer 130 shown in (C) or Figure 29(D), (E). Cut.

[0253] Figure 29(A) is a top view of the oxide semiconductor layer 130, and Figures 29(B) and (C) show the two-layer structure. This is a cross-sectional view of the oxide semiconductor layer 130, which is constructed in a three-layer structure. Figures 29(D) and (E) show the three-layer structure. This is a cross-sectional view of the oxide semiconductor layer 130.

[0254] In oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c, Oxide semiconductor layers with different compositions can be used.

[0255] A transistor according to one aspect of the present invention may have the configuration shown in Figures 30(A) and (B). Figure 30(A) is a top view of transistor 107, and the dashed line H1-H shown in Figure 30(A) The cross-sections in two directions correspond to Figure 30(B). Also, the dashed line H3-H4 shown in Figure 30(A) The cross-section in that direction corresponds to Figure 32(A). Also, the dashed line H1-H2 direction is the channel length direction. The direction of the dashed line H3-H4 is referred to as the channel width direction.

[0256] Transistor 107 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and electrically connected to the stack Connecting conductive layer 140 and conductive layer 150, and the laminate, conductive layer 140 and conductive layer 15 The oxide semiconductor layer 130c in contact with 0, and the insulating layer 160 in contact with the oxide semiconductor layer 130c , conductive layer 170 in contact with insulating layer 160, conductive layer 140, conductive layer 150, oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170, and an insulating layer 175 in contact with It has an insulating layer 180 and, if necessary, a planarizing film as a functional You may add the ability.

[0257] In transistor 107, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The point is that it is a semiconductor layer 130c), and conductive layer 140 and conductive layer 150 and insulating layer 160 Except for the fact that a portion of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between them, It has the same configuration as the Ranjista 101.

[0258] A transistor according to one aspect of the present invention may have the configuration shown in Figures 30(C) and (D). Figure 30(C) is a top view of transistor 108, and the dashed line I1-I shown in Figure 30(C) The cross-sections in two directions correspond to Figure 30(D). Also, the dashed line I3-I4 shown in Figure 30(C) The cross-section in that direction corresponds to Figure 32(B). Also, the dashed line I1-I2 direction is the channel length direction. The direction from the dashed line I3 to I4 is referred to as the channel width direction.

[0259] The transistor 108 has an insulating layer 160 and an oxide semiconductor layer 130c, with the edges connected to the conductive layer 17. It differs from transistor 107 in that its terminals do not coincide with the zero point.

[0260] A transistor according to one aspect of the present invention may have the configuration shown in Figures 30(E) and (F). Figure 30(E) is a top view of transistor 109, and the dashed line J1-J shown in Figure 30(E) The cross-sections in two directions correspond to Figure 30(F). Also, the dashed line J3-J4 shown in Figure 30(E) The cross-section in that direction corresponds to Figure 32(A). Also, the dashed line J1-J2 direction is the channel length direction. The direction from the dashed line J3 to J4 is referred to as the channel width direction.

[0261] The transistor 109 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and an acid in contact with the stack. A oxide semiconductor layer 130c, an insulating layer 160 in contact with the oxide semiconductor layer 130c, and an insulating layer 16 A conductive layer 170 in contact with 0, the laminate, oxide semiconductor layer 130c, insulating layer 160 and conductive An insulating layer 175 covering the electrical layer 170, an insulating layer 180 in contact with the insulating layer 175, and the insulating layer 175 and conductive layer 14 which is electrically connected to the laminate through an opening provided in the insulating layer 180. It has a conductive layer 150 and an insulating layer 180, conductive layer 140 and as needed. The conductive layer 150 may have an insulating layer (planarized film) or the like in contact with it.

[0262] In transistor 109, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide It has the same configuration as transistor 103, except that it is a physical semiconductor layer 130c.

[0263] A transistor according to one aspect of the present invention may have the configuration shown in Figures 31(A) and (B). Figure 31(A) is a top view of transistor 110, and the dashed line K1-K shown in Figure 31(A) The cross-section in two directions corresponds to Figure 31(B). Also, the dashed line K3-K4 shown in Figure 31(A) The cross-section in that direction corresponds to Figure 32(A). Also, the dashed line K1-K2 direction is the channel length direction. The direction of the dashed line K3-K4 is referred to as the channel width direction.

[0264] In transistor 110, the oxide semiconductor layer 130 is divided into two regions 331 and 332. In region 333, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide It has the same configuration as transistor 104, except that it is a solid semiconductor layer (130c).

[0265] A transistor according to one aspect of the present invention may have the configuration shown in Figures 31(C) and (D). Figure 31(C) is a top view of transistor 111, and the dashed line L1-L shown in Figure 31(C) The cross-sections in two directions correspond to Figure 31(D). Also, the dashed line L3-L4 shown in Figure 31(C) The cross-section in that direction corresponds to Figure 32(A). Also, the direction of the dashed line L1-L2 is the channel length direction. The direction of the dashed line L3-L4 is referred to as the channel width direction.

[0266] The transistor 111 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and electrically connected to the stack Connecting conductive layers 141 and 151, and the laminate, conductive layer 141 and conductive layer 15 A 1 oxide semiconductor layer 130c in contact with 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , conductive layer 170 in contact with insulating layer 160, said lamination, conductive layer 141, conductive layer 151, oxidation A semiconductor layer 130c, an insulating layer 160, and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer The insulating layer 180 is in contact with 175, and the openings provided in the insulating layer 175 and the insulating layer 180 Conductive layers 142 and 151 are electrically connected through conductive layer 141 and conductive layer 151, respectively. It has a conductive layer 152. Additionally, an insulating layer 180, a conductive layer 142, and a conductive layer 1 may be provided as needed. It may have an insulating layer (planarized film) or the like in contact with 52.

[0267] In transistor 111, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The fact that it is a semiconductor layer 130c), and that it is a conductive layer 141 and a conductive layer 151 and an insulating layer 16 Except for the fact that a portion of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between it and 0, It has the same configuration as transistor 105.

[0268] A transistor according to one aspect of the present invention may have the configuration shown in Figures 31(E) and (F). Figure 31(E) is a top view of transistor 112, and the dashed line M1-M shown in Figure 31(E) The cross-section in two directions corresponds to Figure 31(F). Also, the dashed line M3-M4 shown in Figure 31(E) The cross-section in that direction corresponds to Figure 32(A). Also, the direction of the dashed line M1-M2 is the channel length direction. The direction of the dashed line M3-M4 is referred to as the channel width direction.

[0269] Transistor 112 is located in regions 331, 332, 334, and 335. The oxide semiconductor layer 130 consists of two layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b). At point 333, the oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide Except for the fact that it is a monocrystalline semiconductor layer 130b and an oxide semiconductor layer 130c, transistor 106 and They have a similar configuration.

[0270] A transistor according to one aspect of the present invention is shown in Figures 33(A), (B), (C), (D), (E), ( F) shows a cross-sectional view in the length direction of the channel, and 32(C) and (D) shows a cross-sectional view in the width direction of the channel. As shown in the cross-sectional view, a conductive layer 173 is provided between the oxide semiconductor layer 130 and the substrate 115. It may be used as a second gate electrode layer (back gate). This allows for an increase in on-current and control of the threshold voltage. Note that, as shown in Figure 33(A), In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is acid The width of the conductive layer 173 may be shorter than that of the conductive layer 170. It can be made shorter than the width.

[0271] A transistor according to one aspect of the present invention has the configuration shown in Figures 34(A) and 34(B). It is also possible to do so. Figure 34(A) is a top view, and Figure 34(B) is a single-point chain shown in Figure 34(A). This is a cross-sectional view corresponding to lines N1-N2 and dashed lines N3-N4. See Figure 34(A). In the top view, some elements have been omitted for clarity.

[0272] The transistor 113 shown in Figures 34(A) and 34(B) is connected to substrate 115 and substrate 11 5. An insulating layer 120 on top of the insulating layer 120, and an oxide semiconductor layer 130 on top of the insulating layer 120 (oxide semiconductor layer 130 a) oxide semiconductor layer 130b, oxide semiconductor layer 130c) and oxide semiconductor layer 130 in contact And conductive layers 140 and 150 are arranged with a gap between them, and an oxide semiconductor layer 130 It has an insulating layer 160 in contact with c and a conductive layer 170 in contact with the insulating layer 160. The semiconductor layer 130, the insulating layer 160, and the conductive layer 170 are located on the insulating layer 1 of the transistor 113. Oxide semiconductor layer 130a, oxide semiconductor layer 130b, and insulating layer 120 provided on 90 It is provided in the opening that reaches [the end].

[0273] The configuration of transistor 113 is, compared to the configurations of the other transistors mentioned above, source Alternatively, because the overlapping region between the drain conductor and the gate electrode conductor is small, parasitic The capacitance can be reduced. Therefore, transistor 113 does not require high-speed operation. It is suitable as an element of the circuit. The top surface of transistor 113 is as shown in Figure 34(B). Using methods such as CMP (Chemical Mechanical Polishing) for sea urchins It is preferable to flatten the surface, but a configuration that does not flatten the surface is also possible.

[0274] Conductive layer 140 (source electrode layer) and conductive layer 15 in a transistor according to one aspect of the present invention 0 (drain electrode layer) is shown in the top view in Figures 35(A) and (B) (oxide semiconductor layer 130, The width (W) of the oxide semiconductor layer 130 is shown as shown in the figure (only conductive layers 140 and 150 are shown). O S The width of conductive layer 140 and conductive layer 150 is greater than (W SD Even if a long gap is formed And it may be formed in a short form. OS ≥W SD (W SD is W OS By doing the following, The gate electric field is more easily applied to the entire oxide semiconductor layer 130, affecting the electrical characteristics of the transistor. It can be improved. Also, as shown in Figure 35(C), the conductive layer 140 and the conductive layer 150 may be formed only in the region that overlaps with the oxide semiconductor layer 130.

[0275] In one embodiment of the present invention, a transistor (transistors 101 to 113) is Even in the misaligned configuration, the conductive layer 170, which is the gate electrode layer, is an insulating layer, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via 160, and the on current is This can be improved. Such a transistor structure is called a surrounded channel This is called an (s-channel) structure.

[0276] A transistor having an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, and It has an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. In the transistor, the two or three layers of material constituting the oxide semiconductor layer 130 are suitable. By selecting this option, current can be passed through the oxide semiconductor layer 130b. By allowing current to flow through 130b, the effects of interfacial scattering are reduced, and a high on-current can be obtained. Therefore, increasing the thickness of the oxide semiconductor layer 130b improves the on-current. There is a match.

[0277] By using the above configuration, the electrical characteristics of the transistor can be improved.

[0278] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0279] (Embodiment 3) In this embodiment, the components of the transistor shown in Embodiment 2 will be described in detail. ru.

[0280] The substrate 115 includes a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, and a surface that is insulated. Processed metal substrates can be used. Alternatively, transistors and photodiodes can be used. A silicon substrate on which a silicon layer is formed, and an insulating layer, wiring, and contact plastics are placed on the silicon substrate. Materials that have a conductive or similar material forming a component that functions as a conductor can be used. When forming a p-channel transistor on a substrate, n - Silicon group having a conductive type It is preferable to use a plate. Alternatively, n - SOI substrate having a type or i-type silicon layer This is also acceptable. Furthermore, if the transistor provided on the silicon substrate is of the p-channel type, The plane orientation of the surface forming the transistor is (110) plane when using a silicon substrate. Preferred. By forming a p-channel transistor on the (110) plane, mobility can be increased. It is possible.

[0281] The insulating layer 120 has the role of preventing the diffusion of impurities from elements contained in the substrate 115. In addition, it can play a role in supplying oxygen to the oxide semiconductor layer 130. Therefore, The margin layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. It is more preferable that the insulating layer is an insulating film. The insulating layer 120 is converted to oxygen atoms as measured by the TDS method. The calculated amount of oxygen released is 1.0 × 10 19 atoms / cm 3 It is preferable that the above conditions are met. Note that the surface temperature of the film during the above TDS analysis should be between 100°C and 700°C, or 10 The temperature range is 0°C to 500°C. Also, the substrate 115 is a substrate on which other devices are formed. In this case, the insulating layer 120 also functions as an interlayer insulating film. In that case, the surface is flat. It is preferable to perform a planarization treatment using methods such as CMP to make the surface flat.

[0282] For example, the insulating layer 120 contains aluminum oxide, magnesium oxide, silicon oxide, and oxide Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide oxide insulating films such as lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. , nitrous oxide such as silicon nitride, silicon nitride, aluminum nitride, aluminum nitride A dielectric insulating film or a mixture thereof can be used. Furthermore, a lamination of the above materials is also possible. That's fine.

[0283] The oxide semiconductor layer 130 consists of oxide semiconductor layer 130a, oxide semiconductor layer 130b and oxide A three-layer structure can be formed by stacking the semiconductor layer 130c sequentially from the insulating layer 120 side.

[0284] In the case of a single layer oxide semiconductor layer 130, the oxide semiconductor layer 13 shown in this embodiment You can use the layer corresponding to 0b.

[0285] If the oxide semiconductor layer 130 consists of two layers, then the layer corresponding to oxide semiconductor layer 130a and the oxide layer are considered to be two layers. A laminated structure can be used in which layers corresponding to the material semiconductor layer 130b are stacked sequentially from the insulating layer 120 side. In this configuration, the oxide semiconductor layer 130a and the oxide semiconductor layer 130b are swapped. It's also possible.

[0286] For example, the oxide semiconductor layer 130b contains the oxide semiconductor layer 130a and the oxide semiconductor layer Acids with a higher electron affinity (energy from the vacuum level to the bottom of the conduction band) than body layer 130c. Ion semiconductors are used.

[0287] In such a structure, when an electric field is applied to the conductive layer 170, the oxide semiconductor layer 130 A channel is formed in the oxide semiconductor layer 130b, which has the lowest energy at the lower end of the conduction band. Therefore, it can be said that the oxide semiconductor layer 130b has a region that functions as a semiconductor. However, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are insulators or semi-insulators. It could also be said that it has an area in which it functions.

[0288] The oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c are used. The oxide semiconductor that can be used preferably contains at least In or Zn. i. Alternatively, it is preferable to include both In and Zn. Also, a to To reduce variations in the electrical properties of transistors, along with them, Al, Ga, Y, or It is preferable to include a stabilizer such as Sn.

[0289] The oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c contain: It is preferable that the crystalline portion is included. In particular, using a crystal oriented along the c-axis allows for the creation of transistors. It can impart stable electrical properties. Furthermore, crystals oriented along the c-axis are resistant to distortion. This can improve the reliability of semiconductor devices using flexible substrates.

[0290] Conductive layer 140 acting as source electrode layer and conductive layer 1 acting as drain electrode layer 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc , and a single layer or laminate of a material selected from alloys or conductive nitrides of the said metallic material. This can be used. In addition, lamination of low-resistance alloys such as Cu or Cu-Mn with the above materials is possible. You may also use: Transistor 105, Transistor 106, Transistor 111, Transistor In the converter 112, for example, W is used in conductive layer 141 and conductive layer 151, and conductive layer 14 A multilayer film of Ti and Al can be used for layer 2 and the conductive layer 152.

[0291] The above material has the property of extracting oxygen from oxide semiconductor films. Therefore, when in contact with the above material... In some regions of the oxide semiconductor film, oxygen is desorbed from the oxide semiconductor film, forming an oxygen vacancy. The region becomes noticeably affected when the small amount of hydrogen contained in the membrane combines with the oxygen deficiency. It is converted to n-type. Therefore, the n-type region is the source or drain of the transistor. It can be made to work in this way.

[0292] When W is used in conductive layers 140 and 150, nitrogen doping may be performed. By doping with nitrogen, the property of extracting oxygen can be moderately weakened, resulting in an n-type compound. This prevents the region from expanding into the channel region. Also, the conductive layer 140 and the conductive The electrode layer 150 is stacked with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are in contact. This also prevents the n-type region from expanding into the channel region. Examples of n-type semiconductor layers include nitrogen-doped In-Ga-Zn oxide, zinc oxide, and zinc oxide. Indium, tin oxide, indium tin oxide, etc., can be used.

[0293] The insulating layer 160, which acts as a gate insulating film, contains aluminum oxide, magnesium oxide, Silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, gallium oxide, acid Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing one or more hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. These may be included as impurities.

[0294] Furthermore, an example of the laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, oxygen It contains nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide, and oxide It is preferable that the material contains silicon or silicon oxide nitride.

[0295] Hafnium oxide and aluminum oxide are compared to silicon oxide and silicon oxide-nitride. It has a high dielectric constant. Therefore, compared to the case where silicon oxide is used, the thickness of the insulating layer 160 is Because it can be made larger, the leakage current due to tunnel current can be reduced. That is, This makes it possible to realize transistors with low current. Furthermore, a crystalline oxide can be used. Hafnium has a higher dielectric constant compared to hafnium oxide, which has an amorphous structure. Therefore, in order to create a transistor with a small off-current, hafnium oxide, which has a crystalline structure, is used. It is preferable to use [this]. Examples of crystal structures include monoclinic and cubic systems. However, one aspect of the present invention is not limited to these.

[0296] Furthermore, the insulating layer 120 and insulating layer 160 that are in contact with the oxide semiconductor layer 130 are made of nitrogen oxide It is preferable to use a film with low emission levels. An insulating layer and an oxide semiconductor with high nitrogen oxide emission levels are preferable. When conductors come into contact, the energy level density may increase due to nitrogen oxides. Insulating layer 120 And the insulating layer 160 is, for example, a silicon oxide nitride film that emits a small amount of nitrogen oxides. An oxide insulating layer such as an aluminum oxide nitride film can be used.

[0297] Silicon oxiditride films with low nitrogen oxide emissions are used in the TDS method. This is a membrane where the amount of ammonia released is greater than the amount of ammonia discharged, typically when the amount of ammonia released is 1 × 10⁻⁶. 18 cm -3 The above 5 x 10 19 cm -3 The following applies. Note that the amount of ammonia released is from the membrane. By heat treatment to a surface temperature of 50°C to 650°C, preferably 50°C to 550°C This shall be the amount of release.

[0298] By using the above oxide insulating layer as the insulating layer 120 and insulating layer 160, the transient This makes it possible to reduce the threshold voltage shift of the transistor and the variation in the transistor's electrical characteristics. This can be reduced.

[0299] The conductive layer 170 acting as the gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni Conductive films such as Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, and W It can be used. Furthermore, alloys of the above materials or conductive nitrides of the above materials may also be used. Furthermore, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials Layers of materials are also possible. Typical examples include tungsten and tungsten and titanium nitride layers. Laminated layers of tungsten and tantalum nitride can be used. Also, low-resistance Cu can be used. Alternatively, using alloys such as Cu-Mn or laminates of the above materials with alloys such as Cu or Cu-Mn. This may also be the case. In this embodiment, the conductive layer 171 is made of tantalum nitride, and the conductive layer 172 is made of tungsten A conductive layer 170 is formed using [a specific method / tool].

[0300] Furthermore, the conductive layer 170 contains In-Ga-Zn oxide, zinc oxide, indium oxide, and tin oxide. Alternatively, an oxide conductive layer such as indium tin oxide may be used.

[0301] The insulating layer 175 may be made of a silicon nitride film or an aluminum nitride film containing hydrogen. This is possible. Transistors 103, 104, and 2 shown in Embodiment 2 In transistors 106, 109, 110, and 112: By using a hydrogen-containing insulating film as the insulating layer 175, a portion of the oxide semiconductor layer is converted to n-type. It is possible. In addition, the nitride insulating film also acts as a blocking film for moisture, etc. This can improve the reliability of the transistor.

[0302] Furthermore, an aluminum oxide film can also be used as the insulating layer 175. In particular, the embodiment Transistors 101, 102, 105, and 2 shown in state 2 In transistors 107, 108, and 111, the insulating layer 175 contains oxide It is preferable to use a luminium film. The aluminum oxide film contains impurities such as hydrogen and water. It has a high barrier effect that prevents both aluminum oxide and oxygen from permeating the membrane. The nium film contains impurities such as hydrogen and water during and after the transistor fabrication process. Prevention of contamination into the oxide semiconductor layer 130, prevention of oxygen release from the oxide semiconductor layer, insulating layer 1 It is suitable for use as a protective film that prevents the unnecessary release of oxygen from 20°C. .

[0303] Preferably, an insulating layer 180 is formed on the insulating layer 175. Magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Using an insulating film containing one or more neodymium oxide, hafnium oxide, and tantalum oxide. This is possible. Furthermore, the insulating layer may be a laminate of the above-mentioned materials.

[0304] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than its stoichiometric composition. This is preferable. Oxygen released from the insulating layer 180 passes through the insulating layer 160 to the oxide semiconductor Since it can diffuse into the channel-forming region of layer 130, it can form a shape in the channel-forming region. The oxygen deficiency that has occurred can be compensated for by oxygen. Therefore, a stable transistor Electrical properties can be obtained.

[0305] Miniaturization of transistors is essential for highly integrating semiconductor devices. Miniaturization tends to worsen the electrical characteristics of transistors, for example, by reducing the channel width. Doing so will reduce the on-current.

[0306] In transistors 107 to 112 of one aspect of the present invention, a channel is formed An oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b, The channel-forming layer and the gate insulating film are not in contact. This suppresses carrier scattering at the interface with the insulating film, thus reducing the on-voltage of the transistor. The flow can be made larger.

[0307] In one embodiment of the present invention, the channel width of the oxide semiconductor layer 130 is as described above. Because the gate electrode layer (conductive layer 170) is formed so as to electrically surround the direction, acid For the ionized semiconductor layer 130, in addition to the gate electric field from a direction perpendicular to the top surface, there is also a gate electric field perpendicular to the side surface. A gate electric field is applied from an angle. That is, a gate electric field is applied to the entire channel formation layer. As an electric field is applied, the effective channel width is expanded, further increasing the on-current. It can be done.

[0308] The various films described in this embodiment, such as metal films, semiconductor films, and inorganic insulating films, are typically spalled. It can be formed by the condensate method or plasma CVD, but other methods, such as thermal CVD, can also be used. It may also be formed by law. An example of the thermal CVD method is MOCVD (Metal Organic Compounds). nic Chemical Vapor Deposition (NIC) method and ALD (Atom Examples include the IC Layer Deposition method.

[0309] Thermal CVD is a film deposition method that does not use plasma, so defects are generated by plasma damage. It has the advantage of not being affected.

[0310] Furthermore, in the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the contents of the chamber are processed By using atmospheric pressure or reduced pressure, the reaction is carried out near or on the substrate, causing the deposit to be deposited on the substrate. Film deposition may be performed.

[0311] The ALD method involves maintaining atmospheric pressure or reduced pressure inside the chamber and supplying the raw material gas for the reaction to the chamber. - The material is introduced and reacted with, and this process is repeated to form a film. Along with the raw material gas, an inert gas is also used. Argon or nitrogen may be introduced as a carrier gas. For example, two or more types The raw material gases may be supplied to the chamber in sequence. In this case, multiple types of raw material gases must not be mixed. As described above, after the reaction of the first raw material gas, an inert gas is introduced, and then the second raw material gas is introduced. Instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation, and then the A second raw material gas may be introduced. The first raw material gas is adsorbed and reacts with the surface of the substrate to form the first layer. A film is formed, and a second raw material gas introduced later is adsorbed and reacts, causing the second layer to form on top of the first layer. The layers are stacked to form a thin film. This process is repeated while controlling the gas introduction sequence until the desired thickness is achieved. By repeating the process several times, a thin film with excellent step coverage can be formed. The thickness of the thin film is Because it can be adjusted by the number of times the injection is repeated, precise film thickness adjustment is possible. It is suitable for fabricating miniature FETs.

[0312] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It can form various films such as metal films, semiconductor films, and inorganic insulating films, for example, In-Ga -When forming a Zn-O film, trimethylindium (In(CH3)3), trimethyl Tilgarium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) are used. This is possible. It is not limited to these combinations, and trimethylgallium can be substituted with triethyl Lugarium (Ga(C2H5)3) can also be used, and diethyl can be used instead of dimethylzinc. Zinc (Zn(C2H5)2) can also be used.

[0313] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes ALD, the solvent and Liquids containing hafnium precursors (such as hafnium alkoxide or tetrakisdimethylamide) Fnium (TDMAH, Hf[N(CH3)2]4) and tetrakis (ethylmethylamide) (The raw material gas is a vaporized hafnium amide such as hafnium, and ozone is used as an oxidizer.) Two types of gases (O3) are used.

[0314] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, the solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3) Two types of gases are used: a raw material gas obtained by vaporizing (such as) and H2O as an oxidizing agent. The materials include tris(dimethylamide)aluminum, triisobutylaluminum, and Luminium tris(2,2,6,6-tetramethyl-3,5-heptanedione), etc. There is.

[0315] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Roloticilane is adsorbed onto the film-forming surface, and radicals of oxidizing gases (O2, nitrous oxide) are supplied. It is supplied and reacted with the adsorbed material.

[0316] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 gas The initial tungsten film is formed by sequentially introducing S and B2H6 gas, and then WF6 gas and H Two gases are introduced sequentially to form a tungsten film. Note that SiH4 gas is used instead of B2H6 gas. Gas may be used.

[0317] For example, oxide semiconductor films, such as In-Ga-Zn-O, can be deposited using an ALD (Advanced Laser Deposition) system. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are sequentially introduced to form a GaO layer, and further Subsequently, Zn(CH3)2 gas and O3 gas are introduced sequentially to form a ZnO layer. The order of these layers is not limited to this example. These gases can be used to create In-Ga-O layers and In-Zn layers. A mixed compound layer such as an O layer or a Ga-Zn-O layer may be formed. Alternatively, instead of O3 gas... H2O gas obtained by bubbling with an inert gas such as Ar may be used, but it does not contain H. It is preferable to use O3 gas, which does not contain oxygen.

[0318] A counter-target sputtering system can also be used to deposit oxide semiconductor layers. The film deposition method using a counter-target sputtering system is called VDSP (vapor deposition). It can also be called tion SP.

[0319] By depositing an oxide semiconductor layer using a counter-target sputtering apparatus, Plasma damage during semiconductor layer deposition can be reduced. Therefore, oxygen in the film Defects can be reduced. Also, by using a counter-target sputtering device, low pressure Since film formation becomes possible, the impurity concentration in the formed oxide semiconductor layer (e.g., hydrogen, dilute) It can reduce gases (such as argon and water).

[0320] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0321] (Embodiment 4) This embodiment describes an oxide semiconductor material that can be used in one aspect of the present invention. I will reveal it.

[0322] The oxide semiconductor preferably contains at least indium or zinc. In particular, indium It is preferable to include aluminum and zinc. In addition to these, aluminum is preferred as element M. Preferably, it contains gallium, yttrium, or tin. Also, element M Examples include boron, silicon, titanium, iron, nickel, germanium, zirconium, and Ribdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and This may include one or more elements selected from magnesium, etc.

[0323] Now, let's consider the case where the oxide semiconductor contains indium, element M, and zinc.

[0324] First, using Figures 36(A), 36(B), and 36(C), the oxide according to the present invention is described. This section describes the preferred range of atomic ratios of indium, element M, and zinc in semiconductors. The atomic ratio of oxygen is not described. Also, the indigenous properties of oxide semiconductors are not described. The terms representing the atomic ratios of element M and zinc are [In], [M], and [Zn], respectively. Let's assume that.

[0325] In Figures 36(A), 36(B), and 36(C), the dashed line represents [In]:[M] The line where the atomic ratio of Zn is (-1≦α≦1) is [ ] In]:[M]:[Zn]=(1+α):(1-α):2 is the line where the atomic ratio is [I The line [In]:[M]:[Zn]=(1+α):(1-α):3 represents the atomic ratio. The line where the atomic ratio of ]:[M]:[Zn]=(1+α):(1-α):4, and [ This represents a line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):5. .

[0326] Furthermore, the dashed line represents the atomic ratio [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio is [In]:[M]:[Zn]=1:2:β, [In] The line where the atomic ratio of :[M]:[Zn]=1:3:β is [In]:[M]:[Zn] The line with an atomic ratio of 1:4:β, where [In]:[M]:[Zn]=2:1:β atoms. Lines that represent numerical ratios, and lines that represent atomic ratios of [In]:[M]:[Zn]=5:1:β. It represents "in".

[0327] Furthermore, as shown in Figure 36, the atomic ratio of [In]:[M]:[Zn]=0:2:1 or a near-percentage of this ratio is used. Oxide semiconductors with lateral values ​​tend to adopt a spinel-type crystal structure.

[0328] Figures 36(A) and 36(B) show the indicators of an oxide semiconductor according to one embodiment of the present invention. An example of a preferred range for the atomic ratio of um, element M, and zinc is shown.

[0329] As an example, Figure 37 shows InMZnO, where [In]:[M]:[Zn]=1:1:1. Figure 4 shows the crystal structure. Figure 37 also shows InMZn when observed from a direction parallel to the b-axis. This is the crystal structure of O4. Note that the layer containing M, Zn, and oxygen shown in Figure 37 (hereinafter referred to as (M,Z) In layer n), the metallic element represents either element M or zinc. In this case, element M and zinc. Assume that the proportions are equal. Element M and zinc are substituted for each other, and their arrangement is irregular. .

[0330] InMZnO4 has a layered crystalline structure (also called a layered structure), as shown in Figure 37. One layer contains indium and oxygen (hereinafter referred to as the In layer), while the other layer contains elements M, zinc, and The (M,Zn) layer containing oxygen is 2.

[0331] Furthermore, indium and element M are mutually substitutable. Therefore, the elements in the (M,Zn) layer... It can also be represented as an (In,M,Zn) layer, where M is substituted with indium. In that case, the In layer... It has a layered structure where there is 1 layer and 2 (In,M,Zn) layers.

[0332] In an oxide semiconductor with an atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer is 1 In contrast, it has a layered structure with 3 (M,Zn) layers. That is, in contrast to [In] and [M] When [Zn] becomes large, if the oxide semiconductor crystallizes, (M,Zn) relative to the In layer The proportion of the ) layer increases.

[0333] However, in oxide semiconductors, the number of (M,Zn) layers relative to the number of In layers is a non-integer. In this case, there are multiple layered structures in which the number of (M,Zn) layers is an integer for every one In layer. It may have. For example, if [In]:[M]:[Zn]=1:1:1.5, A layered structure with 1 In layer and 2 (M,Zn) layers, and a layered structure with 3 (M,Zn) layers. In some cases, a layered structure may be formed, which is a mixture of crystalline and crystalline structures.

[0334] For example, when depositing an oxide semiconductor film using a sputtering system, the atomic ratio of the target deviates. A film with a specific atomic ratio is formed. In particular, depending on the substrate temperature during film formation, the target [Zn In some cases, the [Zn] of the film may be smaller than [ ].

[0335] Furthermore, multiple phases may coexist within an oxide semiconductor (e.g., two-phase coexistence, three-phase coexistence). Example For example, in the atomic ratios that are close to the atomic ratio [In]:[M]:[Zn]=0:2:1 Furthermore, two phases, a spinel-type crystal structure and a layered crystal structure, tend to coexist. In atomic ratios that are close to the atomic ratio that shows M]:[Zn]=1:0:0, the Bixby Two phases, such as a T-shaped crystal structure and a layered crystal structure, can easily coexist. Multiple phases exist in oxide semiconductors. When they coexist, grain boundaries (also called grain boundaries) exist between different crystal structures. It may form.

[0336] Furthermore, by increasing the indium content, the carrier mobility (electron mobility) of oxide semiconductors can be improved. The degree can be increased. This is an oxide semiconducting indium, element M and zinc. In conductors, the s orbitals of heavy metals primarily contribute to carrier conduction, and the indium content... By increasing the s orbital, the region where the s orbitals overlap becomes larger, thus increasing the indium content. Oxide semiconductors with a high indium content have higher carrier mobility compared to oxide semiconductors with a low indium content. This is because it will increase.

[0337] On the other hand, when the content of indium and zinc in oxide semiconductors decreases, the carrier mobility decreases. It becomes lower. Therefore, the atomic ratio that shows [In]:[M]:[Zn]=0:1:0, and In the vicinity of that value, the atomic ratio (for example, region C shown in Figure 36(C)), the insulating properties are high. ru.

[0338] Therefore, an oxide semiconductor according to one aspect of the present invention has high carrier mobility and few grain boundaries. It is preferable to have the atomic ratio shown in region A of Figure 36(A), which tends to result in a layered structure. It seems so.

[0339] Furthermore, region B shown in Figure 36(B) is 4 from [In]:[M]:[Zn]=4:2:3. 1 and its neighboring values ​​are shown. Neighboring values ​​include, for example, atomic ratios [In]:[M]. [Zn]=5:3:4 is included. Oxide semiconductors having the atomic ratio shown in region B are In particular, it is an excellent oxide semiconductor with high crystallinity and high carrier mobility.

[0340] Furthermore, the conditions under which oxide semiconductors form a layered structure are not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. On the other hand, with the same atomic ratio... Even if present, depending on the formation conditions, it may or may not form a layered structure. Therefore, the region shown in the illustration is the region where the oxide semiconductor has a layered structure and exhibits an atomic ratio. The boundaries between region A and region C are not strictly defined.

[0341] Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0342] Furthermore, by using the above oxide semiconductor in a transistor, carrier scattering at grain boundaries can be improved. Because it can be reduced, it is possible to realize transistors with high field-effect mobility. Furthermore, it enables the creation of highly reliable transistors.

[0343] Furthermore, it is preferable to use an oxide semiconductor with a low carrier density for the transistor. Example For example, oxide semiconductors have a carrier density of 8 × 10⁻¹⁰ 11 / cm 3 Less than 1 × 10 11 / cm 3 Less than 1 × 10 10 / cm 3 It is less than 1 × 10 -9 / cm 3 That should suffice.

[0344] Furthermore, oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic have fewer carrier sources. Therefore, carrier density can be lowered. Also, high-purity intrinsic or substantially high-purity In highly intrinsic oxide semiconductors, the defect level density is low, and therefore the trap level density is also low. There is a match.

[0345] Furthermore, the time required for charges trapped in the trap levels of oxide semiconductors to disappear is long. Furthermore, it can behave as if it were a fixed charge. Therefore, it can behave as if it were a fixed charge. In transistors where a channel region is formed in an oxide semiconductor, the electrical properties can become unstable. There is.

[0346] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor must be reduced. Reducing the degree is effective. Also, in order to reduce the impurity concentration in oxide semiconductors Furthermore, it is preferable to reduce the concentration of impurities in the adjacent membrane. Examples of impurities include hydrogen, nitrogen, Examples include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0347] Here, we will explain the effects of various impurities in oxide semiconductors.

[0348] In oxide semiconductors, if silicon or carbon, which are among the Group 14 elements, are present, the oxide Defect levels are formed in semiconductors. Therefore, oxide semiconductors or contact with oxide semiconductors Near the interface with the layer, the concentrations of silicon and carbon (by secondary ion mass spectrometry (SIM)) Obtained by S: Secondary Ion Mass Spectrometry) The concentration is 2 × 10 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The system is controlled to have the following regions:

[0349] Furthermore, if alkali metals or alkaline earth metals are present in the oxide semiconductor, defect levels are formed. This can result in the generation of carriers. Therefore, alkali metals or alkaline earth metals Transistors using oxide semiconductors containing this group tend to exhibit normally-on characteristics. Therefore, reducing the concentration of alkali metals or alkaline earth metals in oxide semiconductors is necessary. This is preferable. Specifically, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor. The degree (concentration obtained by SIMS analysis) is 1 × 10 18 atoms / cm 3 The following are preferred Or 2 x 10 16 atoms / cm 3 The system is controlled to have the following regions:

[0350] Furthermore, in oxide semiconductors, when nitrogen is present, electrons, which are carriers, are generated. The density increases, making it easier to convert to n-type. As a result, oxide semiconductors containing nitrogen can be converted into semiconductors. The transistor used tends to exhibit normally-on characteristics. Therefore, the oxide semiconductor In this context, it is preferable that nitrogen is reduced as much as possible, specifically in oxide semiconductors. The nitrogen concentration (concentration obtained by SIMS analysis) is 5 × 10 19 atoms / cm 3 Not yet Full, preferably 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 at oms / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following areas Control it so that it has.

[0351] Furthermore, the hydrogen contained in oxide semiconductors reacts with the oxygen bonded to the metal atoms to form water. This can sometimes form an oxygen vacancy. When hydrogen enters this oxygen vacancy, the electrons, which are carriers, In some cases, this can be generated. Also, some of the hydrogen combines with oxygen that is bonded to a metal atom, resulting in a It can generate electrons, which are rear electrons. Therefore, an oxide semiconductor containing hydrogen The transistor used tends to exhibit normally-on characteristics. Therefore, water in oxide semiconductors It is preferable that the element is reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor. (Concentration obtained by SIMS analysis) is 1 × 10 20 atoms / cm 3 Less than, preferred ku is 1 x 10 19 atoms / cm 3 Less than 5x10 18 ate / c m 3 Less than 1 × 10 18 atoms / cm 3 It has a region that is less than Control it.

[0352] Using oxide semiconductors with sufficiently reduced impurities in the channel formation region of transistors. This allows for the imparting of stable electrical properties. Furthermore, as mentioned above, highly purified oxide The off-current of a transistor using a monocrystalline semiconductor in the channel formation region is extremely small. For example, When the voltage between the source and drain is set to approximately 0.1V, 5V, or 10V, Reduce the off-current per channel width of the transistor to several yA / μm to several zA / μm. This becomes possible.

[0353] Next, we will discuss the case where the oxide semiconductor has a two-layer or three-layer structure. The insulator in contact with the stacked structure of semiconductor S1, oxide semiconductor S2, and oxide semiconductor S3 The diagram shows the band of the insulator in contact with the layered structure of oxide semiconductor S2 and oxide semiconductor S3. Figure and will be explained using Figure 38. Note that oxide semiconductor S1 is oxide semiconductor layer 1 30a, oxide semiconductor S2 is oxide semiconductor layer 130b, oxide semiconductor S3 is oxide semiconductor This corresponds to layer 130c.

[0354] Figure 38(A) shows insulator I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S3 Figure 38 is an example of a band diagram in the film thickness direction of a laminated structure having an insulator I2. (B) comprises an insulator I1, an oxide semiconductor S2, an oxide semiconductor S3, and an insulator I2. This is an example of a band diagram in the film thickness direction of a laminated structure. Note that the band diagram is intended to facilitate understanding. Insulator I1, oxide semiconductor S1, oxide semiconductor S2, oxide semiconductor S3, and insulator This shows the energy level (Ec) at the lower end of the conduction band of I2.

[0355] Oxide semiconductors S1 and S3 have a lower energy at the bottom of the conduction band than oxide semiconductor S2. - The energy level is close to the vacuum level, and typically corresponds to the energy level at the lower end of the conduction band in oxide semiconductors S2. The difference between the energy levels of the lower end of the conduction band of oxide semiconductor S1 and oxide semiconductor S3 is 0. The voltage must be 15 eV or higher, or 0.5 eV or higher and 2 eV or lower, or 1 eV or lower. Preferably. That is, the electron affinity of oxide semiconductor S1 and oxide semiconductor S3 is greater than that of oxide semiconductor S1. The electron affinity of semiconductor S2 is high, and the electron affinity of oxide semiconductors S1 and S3 is... The difference from the electron affinity of the oxide semiconductor S2 is 0.15 eV or more, or 0.5 eV or more. Furthermore, it is preferable that the voltage is 2 eV or less, or 1 eV or less.

[0356] As shown in Figures 38(A) and 38(B), oxide semiconductor S1, oxide semiconductor S2 In oxide semiconductors S3, the energy levels at the lower end of the conduction band change gradually. In other words... Therefore, it can be said that it changes continuously or is continuously joined. Such a band diagram In order to have it, the interface between oxide semiconductor S1 and oxide semiconductor S2, or oxide semiconductor S By lowering the defect level density of the mixed layer formed at the interface between 2 and the oxide semiconductor S3, stomach.

[0357] Specifically, oxide semiconductor S1 and oxide semiconductor S2, oxide semiconductor S2 and oxide semiconductor S Mixture 3 has a low defect level density because it contains a common element other than oxygen (it is the main component). A layer can be formed. For example, if the oxide semiconductor S2 is an In-Ga-Zn oxide semiconductor In this case, the oxide semiconductor S1 and oxide semiconductor S3 are In-Ga-Zn oxide semiconductors. Ga-Zn oxide semiconductors, gallium oxide, etc., are suitable materials to use.

[0358] In this case, the main carrier pathway is through the oxide semiconductor S2. Oxide semiconductor S1 and oxide Defects at the interface with semiconductor S2, and at the interface between oxide semiconductor S2 and oxide semiconductor S3. Because the level density can be lowered, the influence of interfacial scattering on carrier conduction is small. High on-current can be obtained.

[0359] When an electron is trapped in a trap level, the trapped electron behaves like a fixed charge. Therefore, the transistor's threshold voltage shifts in the positive direction. Oxide semiconductor S1, By providing the oxide semiconductor S3, the trap level is moved further away from the oxide semiconductor S2. This configuration allows the transistor's threshold voltage to shift in the positive direction. This can prevent that from happening.

[0360] Oxide semiconductors S1 and S3 have significantly better conductivity compared to oxide semiconductor S2. Low-cost materials are used. In this case, oxide semiconductor S2, oxide semiconductor S2 and oxide semiconductor S1 The interface with and the interface between oxide semiconductor S2 and oxide semiconductor S3 are mainly the channel region and It functions in this way. For example, in oxide semiconductor S1 and oxide semiconductor S3, as shown in Figure 36(C) Therefore, an oxide semiconductor with an atomic ratio shown in region C, where insulation is high, should be used.

[0361] In particular, when using an oxide semiconductor with the atomic ratio shown in region A for the oxide semiconductor S2, The monocrystalline semiconductor S1 and the oxide semiconductor S3 have a [M] / [In] ratio of 1 or more, preferably 2 or more. It is preferable to use an oxide semiconductor with the above atomic ratio. Also, as oxide semiconductor S3 Therefore, if the ratio [M] / ([Zn]+[In]) is 1 or greater, a sufficiently high insulating property can be obtained. It is preferable to use an oxide semiconductor with such an atomic ratio.

[0362] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0363] (Embodiment 5) The following describes the structure of an oxide semiconductor that can be used in one aspect of the present invention.

[0364] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Perpendicular" refers to a state where two lines are positioned at an angle between 80° and 100°. Therefore, this also includes cases where the angle is between 85° and 95°.

[0365] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0366] <Oxide semiconductor structure> The structure of oxide semiconductors will be described below.

[0367] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned (crystalline oxide semiconductor), polycrystalline oxide Semiconductors, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l Examples include oxide semiconductors and amorphous oxide semiconductors. ru.

[0368] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. It can be divided into conductors and crystalline oxide semiconductors. As for crystalline oxide semiconductors, there are single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductors, and nc-OS.

[0369] Amorphous structures are generally isotropic and lack heterogeneous structures, representing a metastable state of atomic arrangement. It is not fixed, the bonding angle is flexible, and it has short-range order but not long-range order. It is said that...

[0370] Conversely, stable oxide semiconductors can be made into completely amorphous (completely amorphous) materials. It cannot be called an oxide semiconductor (rphous). Also, it is not isotropic (for example, in a minute region) Oxide semiconductors that have a periodic structure cannot be called perfectly amorphous oxide semiconductors. On the other hand, a-like OS is not isotropic but has an unstable structure with voids (also called porous structures). It is a structure. In terms of instability, a-like OS is an amorphous oxide in terms of its physical properties. It's similar to a semiconductor.

[0371] <caac-os> First, let me explain CAAC-OS.

[0372] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0373] CAAC-OS can be analyzed by X-ray diffraction (XRD). Let's explain the case of analysis. For example, InGaZnO4, which is classified as space group R-3m Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in Figure 39(A), a peak appears near 31° at the diffraction angle (2θ). Since the 'k' is attributed to the (009) plane of the InGaZnO4 crystal, CAAC-OS The crystal has c-axis orientation, and the c-axis is the surface that forms the CAAC-OS film (also called the surface to be formed). It can be confirmed that it is facing in a direction approximately perpendicular to the top surface. Note that 2θ is 31° In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak is due to a crystal structure classified as space group Fd-3m. Therefore, CAAC -OS preferably does not show the peak.

[0374] On the other hand, in CAAC-OS, X-rays are incident from a direction parallel to the surface being formed. Structural analysis using the ne method reveals a peak near 2θ = 56°. This peak corresponds to I It is attributed to the (110) plane of the nGaZnO4 crystal. Then, 2θ is fixed near 56°. The analysis (φ-scan) is performed while rotating the sample around the normal vector of the sample surface as the axis (φ-axis). Even when this is done, no clear peak appears, as shown in Figure 39(B). On the other hand, single crystal InGaZ When φ scanning is performed on nO4 with 2θ fixed near 56°, the result is shown in Figure 39(C). Six peaks are observed that belong to a crystal plane equivalent to the (110) plane. Therefore, X Structural analysis using RD revealed that CAAC-OS has irregular orientations in its a-axis and b-axis. This can be confirmed.

[0375] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe is applied parallel to the surface of the CAAC-OS being formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern like the one shown in Figure 39(D) (control) is observed. This is also called a limited-field electron diffraction pattern. A diffraction pattern may appear. This diffraction pattern includes In The spot contains a location originating from the (009) plane of the GaZnO4 crystal. Therefore, the electron rotation Depending on the circumstances, the pellets contained in CAAC-OS may have c-axis orientation, and the c-axis may be the surface to be formed. Alternatively, it can be seen that it is oriented in a direction approximately perpendicular to the upper surface. On the other hand, for the same sample, on the sample surface Figure 39(E) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly. As shown in Figure 39(E), a ring-shaped diffraction pattern can be observed. Therefore, the probe Electron diffraction using an electron beam with a diameter of 300 nm also revealed the presence of peridotites in CAAC-OS. It can be seen that the a-axis and b-axis of the net do not have orientation. Note that in Figure 39(E) The ring is caused by the (010) and (100) planes of the InGaZnO4 crystal, among other things. It is thought that the second ring in Figure 39(E) is caused by the (110) plane, etc. It's possible.

[0376] Furthermore, a transmission electron microscope (TEM) A composite image of the bright-field image and diffraction pattern of CAAC-OS obtained by (croscope) analysis. When observing a high-resolution TEM image (also known as a TEM image), multiple pellets can be identified. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are not visible. Also called "Nandaly." ) There are cases where it is not possible to clearly confirm this. Therefore, CAAC -OS can be said to be less prone to the decrease in electron mobility caused by grain boundaries.

[0377] Figure 40(A) shows a high-resolution T-scale cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The EM image is shown. For observing high-resolution TEM images, spherical aberration correction is required. The aberration correction function was used. High-resolution analysis was performed using the spherical aberration correction function. High-resolution TEM images are specifically called Cs-corrected high-resolution TEM images. For example, using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. This can be observed.

[0378] From Figure 40(A), we can see the pellet, which is a region in which metal atoms are arranged in layers. Yes, it is possible. It has been found that the size of a single pellet can be 1 nm or larger, or even 3 nm or larger. Therefore, pellets are called nanocrystals (nc). It is also possible to use CAAC-OS with CANC(C-Axis Aligned nan It can also be called an oxide semiconductor containing ocrystals. The pellet is CAAC -Reflects the unevenness of the surface or top surface of the OS, and the surface or top surface of the CAAC-OS It becomes parallel to the plane.

[0379] Furthermore, Figures 40(B) and 40(C) show CAAC observed from a direction approximately perpendicular to the sample surface. -Shows a Cs-corrected high-resolution TEM image of the OS plane. Figures 40(D) ​​and 40(E) are shown. These are images obtained by image processing Figure 40(B) and Figure 40(C), respectively. The following describes the image processing. Let's explain the method. First, Figure 40(B) is converted to the Fast Fourier Transform (FFT). The FFT image is obtained by performing a Fourier Transform (FFT) process. Next, the acquisition In the resulting FFT image, with the origin as the reference point, 2.8 nm -1 from 5.0nm -1 Leave the range between Next, the masked FFT image is subjected to the inverse Fast Fourier Transform (IFFT: By processing the image (Inverse Fast Fourier Transform), The processed image is obtained. The image obtained in this way is called an FFT filtered image. The filtered image is an image obtained by extracting the periodic component from the Cs-corrected high-resolution TEM image, and is a grid image. This shows the array.

[0380] In Figure 40(D), areas where the grid arrangement is disordered are indicated by dashed lines. The area enclosed by the dashed lines is It is a single pellet. The dotted line indicates the connection point between the pellets. The dashed line indicates a hexagonal shape, showing that the pellet is hexagonal. The shape of the net is not always a regular hexagon; it is often a non-regular hexagon.

[0381] In Figure 40(E), a dotted line is drawn between one region with a aligned grid arrangement and another region with a aligned grid arrangement. As shown, even near the dotted line, a clear grain boundary cannot be confirmed. Connecting the surrounding grid points to a central grid point creates a distorted hexagon, or a pentagon and / or heptagon. Shapes and other features can be formed. That is, by distorting the lattice arrangement, the formation of grain boundaries can be suppressed. It can be seen that CAAC-OS has interatomic bond distance in the ab-plane direction. This is due to factors such as the material not being dense, and the change in interatomic bond distances caused by the substitution of metallic elements. Therefore, it is thought that this is because distortion can be tolerated.

[0382] As described above, CAAC-OS has c-axis orientation and multiple properties in the ab-plane direction. A number of pellets (nanocrystals) are linked together, forming a distorted crystalline structure. Therefore, CA AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an anchored crystal. ru.

[0383] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors depends on the presence of impurities. Because it can decrease due to the generation of defects or other factors, from the opposite perspective, CAAC-OS It can also be described as an oxide semiconductor with few impurities or defects (such as oxygen vacancies).

[0384] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0385] <nc-os> Next, I will explain nc-OS.

[0386] This section describes the case of analyzing nc-OS using XRD. For example, for nc-OS When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. In other words, nc-OS crystals do not have orientation.

[0387] Furthermore, for example, nc-OS having an InGaZnO4 crystal is thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region parallel to the surface to be formed, Figure 41 A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. Furthermore, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample (na The beam electron diffraction pattern is shown in Figure 41(B). From Figure 41(B), a ring-shaped region is visible. Multiple spots are observed within. Therefore, nc-OS has a probe diameter of 50 nm. Order is not confirmed by irradiating with an electron beam, but when an electron beam with a probe diameter of 1 nm is irradiated... Order can be confirmed by having them shoot.

[0388] Furthermore, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, As shown in Figure 41(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. This may occur. Therefore, in the range of thickness less than 10 nm, nc-OS is ordered. It can be seen that there is a region with high fissure, i.e., a crystal. Furthermore, the crystals are oriented in various directions. Therefore, there are also regions where a regular electron diffraction pattern is not observed.

[0389] Figure 41(D) shows the Cs-corrected elevation of the cross-section of nc-OS observed from a direction approximately parallel to the surface being formed. High-resolution TEM images are shown. nc-OS refers to areas indicated by auxiliary lines in the high-resolution TEM image. As shown, there are regions where the crystalline structure can be observed and regions where the crystalline structure cannot be clearly observed. It has a region and a crystal portion contained in nc-OS, with a size of 1 nm to 10 nm. Yes, and they are often between 1 nm and 3 nm in size. Oxide semiconductors with a wavelength greater than 0 nm and less than or equal to 100 nm are called microcrystalline oxide semiconductors (micro It is sometimes called a crystalline oxide semiconductor. nc-OS is useful, for example, when grain boundaries cannot be clearly identified in high-resolution TEM images. There is a possibility that the nanocrystals share the same origin as the pellets in CAAC-OS. Therefore, the crystalline portion of nc-OS may be referred to as a pellet in the following text.

[0390] Thus, nc-OS is suitable for minute regions (for example, regions between 1 nm and 10 nm, particularly The atomic arrangement has periodicity in the region between 1 nm and 3 nm. Furthermore, nc-OS is Furthermore, no regularity is observed in the crystal orientation between different pellets. Therefore, orientation is not observed throughout the entire film. Therefore, nc-OS can be analyzed using methods that produce a-like OS or amorphous OS. It can sometimes be indistinguishable from oxide semiconductors.

[0391] Furthermore, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc-OS is used. Oxides containing RANC (Random Aligned nanocrystals) semiconductors, or containing NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0392] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. nc-OS has a higher defect level density compared to CAAC-OS.

[0393] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor.

[0394] Figure 42 shows a high-resolution cross-sectional TEM image of an a-like OS. Here, Figure 42(A) is This is a high-resolution cross-sectional TEM image of a-like OS at the start of electron irradiation. Figure 42(B ) is 4.3 × 10 8 e - / nm 2 electrons (e - ) High a-like OS after irradiation These are high-resolution cross-sectional TEM images. From Figures 42(A) and 42(B), a-like OS It can be seen that, from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. The bright regions show a change in shape after electron irradiation. Furthermore, the bright regions are either porous or low-density. It is presumed to be in the degree range.

[0395] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0396] As samples, prepare a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0397] First, high-resolution cross-sectional TEM images are obtained for each sample. All of them have a crystalline portion.

[0398] Furthermore, the unit cell of the InGaZnO4 crystal has three In-O layers, and Ga-Zn- It is known to have a structure in which a total of nine layers, including six O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the spacing between the grid planes of the (009) plane (also called the d value). It is approximately [value], and from crystal structure analysis, its value has been determined to be 0.29 nm. Therefore, Below, areas where the spacing of the grid stripes is between 0.28 nm and 0.30 nm are represented as InGaZn. This was considered to be the crystalline portion of O4. Note that the lattice fringes correspond to the ab-plane of the InGaZnO4 crystal. ru.

[0399] Figure 43 shows an example of investigating the average size of the crystalline regions (22 to 30 locations) in each sample. The length of the lattice fringes mentioned above is used to define the size of the crystal portion. From Figure 42, a-like The crystalline portion of the OS grows larger in proportion to the cumulative amount of electrons irradiated during TEM image acquisition, etc. It can be seen that, as shown in Figure 42, the size is about 1.2 nm in the initial stages of TEM observation. The crystal region (also called the initial nucleus) is then transformed into an electron (e - The cumulative radiation dose was 4.2 × 10⁻⁶ 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 1.9 nm. On the other hand, nc -OS and CAAC-OS are defined as the cumulative electron dose from the start of electron irradiation being 4.2 × 10⁻⁶. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. (Figure 42) Furthermore, regardless of the cumulative electron irradiation dose, the size of the crystal region in nc-OS and CAAC-OS is, It can be seen that they are approximately 1.3 nm and 1.8 nm, respectively. TEM observations were performed using a Hitachi transmission electron microscope H-9000NAR. Electron beam irradiation conditions The acceleration voltage is 300kV and the current density is 6.7 × 10⁻⁶. 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0400] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It cannot be seen. In other words, a-like OS is different from nc-OS and CAAC-OS. It is clear that the structure is unstable.

[0401] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density of oxide semiconductors is between 78.6% and 92.3%. The density of CAAC-OS is 92.3% or more of the density of a single-crystal oxide semiconductor of the same composition. It is less than 00%. Oxide semiconductors with a density of less than 78% of that of single-crystal oxide semiconductors are thin films. Doing so is difficult in itself.

[0402] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's right. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of nc-OS and CAAC-OS is 5.9 g / cm³. 3 More than 6.3g / cm 3 It is less than.

[0403] If single crystals with the same composition do not exist, single crystals with different compositions can be combined in any proportion. By doing so, the density equivalent to a single crystal at the desired composition can be estimated. The density corresponding to a single crystal of the desired composition is, with respect to the ratio of single crystals with different compositions combined, The density can be estimated using a weighted average. However, the density should be calculated using as few types of single crystals as possible. It is preferable to estimate by combining the costs.

[0404] As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, nc-OS, The multilayer film may have two or more types of CAAC-OS.

[0405] <Carrier density of oxide semiconductors> Next, the carrier density of oxide semiconductors will be explained below.

[0406] Factors that affect the carrier density of oxide semiconductors include oxygen vacancies in oxide semiconductors. Examples include vo, or impurities in oxide semiconductors.

[0407] When the number of oxygen vacancies in an oxide semiconductor increases, hydrogen atoms bond to these oxygen vacancies (this state is called VoH). When this occurs, the defect level density increases. Alternatively, when there are many impurities in the oxide semiconductor... Consequently, the defect level density increases due to the impurity. By controlling the carrier density, the carrier density of oxide semiconductors can be controlled.

[0408] Now, let's consider a transistor that uses an oxide semiconductor in the channel region.

[0409] Suppression of negative shift in the transistor threshold voltage, or the transistor off-current When the goal is reduction, it is preferable to lower the carrier density of the oxide semiconductor. When lowering the carrier density of an oxide semiconductor, the impurity concentration in the oxide semiconductor is The defect level density should be reduced by lowering the impurity concentration. In this specification, the impurity concentration is low and the defect level density is low. A low void density is referred to as high-purity intrinsic or substantially high-purity intrinsic. Oxidation of high-purity intrinsic The carrier density of a semiconductor is 8 × 10⁻¹⁰ 15 cm -3 Less than 1 × 10 11 cm -3 Less than 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm - 3 That should suffice.

[0410] On the other hand, improving the on-current of the transistor, or improving the field-effect mobility of the transistor When this is the objective, it is preferable to increase the carrier density of the oxide semiconductor. When increasing the carrier density of a semiconductor, the impurity concentration of the oxide semiconductor is slightly reduced. To increase it, or to slightly increase the defect level density of the oxide semiconductor, It is preferable to make the band gap of the oxide semiconductor smaller. For example, in the range where the on / off ratio of the Id-Vg characteristics of a transistor can be obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect levels can be regarded as substantially intrinsic. Also, an oxide semiconductor with a large electron affinity, and accordingly a small band gap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that when an oxide semiconductor with a larger electron affinity is used, the threshold voltage of the transistor becomes lower. Among the ranges where the on / off ratio of the Id-Vg characteristics of a transistor can be obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect levels can be regarded as substantially intrinsic. Among the ranges where the on / off ratio of the Id-Vg characteristics of a transistor can be obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect levels can be regarded as substantially intrinsic. Also, an oxide semiconductor with a large electron affinity, and accordingly a small band gap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Among the ranges where the on / off ratio of the Id-Vg characteristics of a transistor can be obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect levels can be regarded as substantially intrinsic. Also, an oxide semiconductor with a large electron affinity, and accordingly a small band gap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Among the ranges where the on / off ratio of the Id-Vg characteristics of a transistor can be obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect levels can be regarded as substantially intrinsic. Also, an oxide semiconductor with a large electron affinity, and accordingly a small band gap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that when an oxide semiconductor with a larger electron affinity is used, the threshold voltage of the transistor becomes lower. Among the ranges where the on / off ratio of the Id-Vg characteristics of a transistor can be obtained, an oxide semiconductor with a slightly higher impurity concentration or a slightly higher density of defect levels can be regarded as substantially intrinsic. Also, an oxide semiconductor with a large electron affinity, and accordingly a small band gap, and as a result, an increased density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that when an oxide semiconductor with a larger electron affinity is used, the threshold voltage of the transistor becomes lower.

[0411] The carrier density of the above-described oxide semiconductor with an increased carrier density is slightly n-type. Therefore, the oxide semiconductor with an increased carrier density may be referred to as "Slightly-n". The carrier density of the above-described oxide semiconductor with an increased carrier density is slightly n-type. Therefore, the oxide semiconductor with an increased carrier density may be referred to as "Slightly-n".

[0412] The carrier density of a substantially intrinsic oxide semiconductor is preferably 1×10 5 cm -3 or more and less than 1×10 18 c m -3 It is more preferably 1×10 7 cm -3 or more and 1×10 17 cm -3 or less, even more preferably 1×10 It is more preferably 1×10 9 cm -3 or more and 5×10 16 cm -3 or less, even more preferably 1×10 10 cm -3 or more and 1×10 16 cm -3 or less, even more preferably 1×10 11 cm -3 or more and 1 ×10 15 cm -3 or less.

[0413] ​​The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0414] (Embodiment 6) In this embodiment, an example of a package containing an image sensor chip and a camera module will be described. The image sensor chip can use the configuration of the imaging device according to one aspect of the present invention. The configuration of the imaging device according to one aspect of the present invention can be used. It is possible.

[0415] FIG. 44(A) is an external perspective view of the upper surface side of a package containing an image sensor chip. The package includes a package substrate 810 for fixing the image sensor chip 850, a cover glass 820, an adhesive 830 for bonding the two, and the like. It has a cover glass 820 and an adhesive 830 for bonding the two.

[0416] FIG. 44(B) is an external perspective view of the lower surface side of the package. The lower surface of the package has a BGA (Ball grid array) configuration with solder balls as bumps 840. It has a BGA (Ball grid array) configuration with solder balls as bumps 840. Note that it is not limited to BGA, and it may be LGA (Land grid array), PGA (Pin Grid Array), or the like. It may be LGA (Land grid array), PGA (Pin Grid Array), or the like.

[0417] FIG. 44(C) is a perspective view of the package shown with a part of the cover glass 820 and the adhesive 830 omitted, and FIG. 44(D) is a cross-sectional view of the package. Electrode pads 860 are formed on the package substrate 810, and the electrode pads 860 and the bumps 840 are electrically connected via through-holes 880 and lands 885. The electrode pads 860 are electrically connected to the electrodes of the image sensor chip 850 by wires 870. The electrode pads 860 are electrically connected to the electrodes of the image sensor chip 850 by wires 870. The electrode pads 860 are electrically connected to the electrodes of the image sensor chip 850 by wires 870. It is connected.

[0418] Furthermore, Figure 45(A) shows a camera with an image sensor chip housed in a lens-integrated package. This is a perspective view of the top side of the camera module. The camera module is an image sensor. Package substrate 811, lens cover 821, and lens 835 for fixing the top 851 It has the following features. Also, between the package substrate 811 and the image sensor chip 851 An IC chip 890 is also provided, which has functions such as a drive circuit and a signal conversion circuit for the image device. It has a configuration as a SiP (System in Package).

[0419] Figure 45(B) is a perspective view of the lower side of the camera module. Package substrate 8 The bottom and four sides of 11 are provided with mounting lands 841 for the QFN (Quad f It has a lat no-lead package configuration. Note that this configuration is just one example. Yes, it can be a QFP (Quad flat package) or the aforementioned BGA, etc. stomach.

[0420] Figure 45(C) shows the module with the lens cover 821 and part of the lens 835 omitted. This is a perspective view of the frame, and Figure 45(D) is a cross-sectional view of the camera module. A portion of 41 is used as an electrode pad 861, and the electrode pad 861 is an image sensor chip The electrodes of the pin 851 and IC chip 890 are electrically connected by wire 871. It is.

[0421] By housing the image sensor chip in the type of package described above, implementation becomes easier. It can be incorporated into various semiconductor devices and electronic equipment.

[0422] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0423] (Embodiment 7) An imaging device, a display device, and a semiconductor device including both according to one aspect of the present invention can be used. As an electronic device, it includes a display device, a personal computer, and an image storage device equipped with a recording medium. Devices or image playback devices, mobile phones, game consoles including portable models, mobile data terminals, e-book terminals In addition, cameras such as video cameras and digital still cameras, goggle-type displays (head Mounted display), navigation system, sound playback device (car audio, de Digital audio players, etc.), photocopiers, fax machines, printers, multifunction printers, Examples include automated teller machines (ATMs) and vending machines. These electronic devices An example is shown in Figure 46.

[0424] Figure 46(A) shows a surveillance camera, which has a housing 951, a lens 952, a support part 953, etc. One component for acquiring images in the said surveillance camera is an imaging device according to one aspect of the present invention. The device can be equipped with such equipment. Note that "surveillance camera" is a common term and does not specify its intended use. It's not a camera. For example, a device that functions as a surveillance camera is a camera, or a video camera. It is also called Ra.

[0425] Figure 46(B) shows a video camera, comprising a first housing 971, a second housing 972, a display unit 973, It has an operation key 974, a lens 975, a connecting part 976, etc. Operation key 974 and lens 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. It exists. One aspect of the present invention is a component for acquiring images in the video camera. It can be equipped with an imaging device.

[0426] Figure 46(C) shows a digital camera, consisting of a housing 961, a shutter button 962, and a microphone 9 It has components 63, a light-emitting unit 967, a lens 965, etc. Images are acquired with this digital camera. One component for this purpose may be an imaging device according to one embodiment of the present invention.

[0427] Figure 46(D) shows a wristwatch-type information terminal, comprising a housing 931, a display unit 932, and a wristband 9 33, it has operating buttons 935, a crown 936, a camera 939, etc. The display unit 932 is It may be a touch panel. It is one of the components for acquiring images on the information terminal. The present invention may be provided with an imaging device according to one embodiment of the present invention.

[0428] Figure 46(E) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display unit. 904, Microphone 905, Speaker 906, Control keys 907, Stylus 908, Camera It has 909, etc. Note that the portable game console shown in Figure 46(E) has two display units 903 It has a display unit 904, but the number of display units that a portable game console has is not limited to this. It is not possible. The present invention is one of the components for acquiring images in the portable game console. The device can be equipped with an imaging device of the form.

[0429] Figure 46(F) shows a portable data terminal, which includes a housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows for the input and output of information. One aspect of the present invention is a component for acquiring images in the mobile data terminal. It can be equipped with an imaging device.

[0430] This embodiment can be appropriately combined with other embodiments shown herein. . [Explanation of symbols]

[0431] 20 pixels 20a pixels 20b pixels 20c pixels 20d pixels 21-pixel array 22 circuits 23 circuits 24 circuits 25 circuits 26 Control circuits 27 Comparator Circuit 29 Counter Circuit 30 circuits 35 Circuit section 41 Transistors 42 transistors 43 transistors 44 transistors 45 transistors 46 transistors 47 transistors 51 Transistors 52 transistors 53 Transistors 61 Wiring 61a Wiring 61d Wiring 62 Wiring 63 Wiring 65 Wiring 71 Wiring 72 Wiring 73 Wiring 75 Wiring 76 Wiring 77 Wiring 78 Wiring 80a insulating layer 80b Insulating layer 81a Insulating layer 81c insulating layer 81d insulating layer 81g insulating layer 81h insulating layer 81j insulating layer 81k insulating layer 82 Conductors 91 Wiring 92 Wiring 93 Wiring 101 Transistors 102 transistors 103 Transistors 104 transistors 105 transistors 106 transistors 107 transistors 108 transistors 109 transistors 110 transistors 111 transistors 112 transistors 113 Transistors 115 circuit boards 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide Semiconductor Layer 130c oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive layer 150 conductive layer 151 Conductive layer 152 Conductive layer 160 Insulating layer 170 Conductive layer 171 Conductive layer 172 Conductive layer 173 Conductive layer 175 Insulating layer 180 Insulating layer 190 Insulating layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 401 Connection section 401a metal layer 401b Metal layer 402 Connection section 402a metal layer 402b metal layer 403 Connection section 403a metal layer 403b metal layer 405 Metal layer 406 Metal layer 561 Photoelectric conversion layer 562 Transparent conductive layer 563 Semiconductor layer 564 Semiconductor layer 565 Semiconductor layer 566 Electrode 566a conductive layer 566b Conductive layer 567 Bulkhead 568 Hole injection blockage layer 569 Electron injection blocking layer 571 Wiring 571a Conductive layer 571b Conductive layer 588 Wiring 600 Single-crystal silicon substrate 620p + region 630 p - region 640 n-type region 650 p + region 660 Active layer 670 Single-crystal silicon substrate 810 Package Substrate 811 Package substrate 820 Cover Glass 821 Lens Cover 830 Adhesive 835 lens 840 Bump 841 Land 850 Image Sensor Chips 851 Image Sensor Chip 860 Electrode Pads 861 Electrode Pads 870 wire 871 Wire 880 Through Hole 885 Rand 890 IC chip 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 909 Camera 911 cabinet 912 Display section 919 Camera 931 cabinet 932 Display section 933 Wristband 935 buttons 936 Crown 939 Camera 951 cabinet 952 Lens 953 Support part 961 cabinet 962 Shutter button 963 Mike 965 lens 967 Light-emitting part 971 cabinet 972 cabinets 973 Display section 974 Operation Keys 975 lens 976 Connection part 1100 layers 1200 layers 1300 layers 1500 diffraction grating 1600 layers 1700 Support board 1800 Delamination layer 2500 Insulating layer 2510 Light blocking layer 2520 Organic resin layer 2530 Color Filters 2530a color filter 2530b color filter 2530c color filter 2540 Microlens Array 2550 Optical Conversion Layer 2560 Insulating layer

Claims

1. It comprises a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a first metal part, a second metal part, an insulating layer, and a light-shielding layer. The first metal part is joined to the second metal part which is located in a lower layer of the first metal part. The first transistor and the second transistor are arranged on the upper layer of the first metal part. The photoelectric conversion element is arranged on the upper layer of the first metal part. The third transistor is placed in the lower layer of the second metal part. The insulating layer is positioned above the photoelectric conversion element. The light-shielding layer is positioned above the insulating layer. The first transistor and the second transistor have a shared region where one of the source and the drain is integrated. The shared region functions as an FD node and is arranged to overlap with the joining region between the first metal part and the second metal part. The gate of the first transistor is electrically connected to the first wiring, The first transistor has the function of transferring the charge generated in the photoelectric conversion element to the FD node according to the signal of the first wiring. The gate of the third transistor is electrically connected to the FD node, The anode of the aforementioned photoelectric conversion element is positioned on the light-receiving surface side. An imaging device in which the anode of the photoelectric conversion element is electrically connected to a second wiring arranged in the same layer as the first wiring.

2. It comprises a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a first metal part, a second metal part, an insulating layer, and a light-shielding layer. The first metal part is joined to the second metal part which is located in a lower layer of the first metal part. The first transistor and the second transistor are arranged on the upper layer of the first metal part. The photoelectric conversion element is arranged on the upper layer of the first metal part. The third transistor is placed in the lower layer of the second metal part. The insulating layer is positioned above the photoelectric conversion element. The light-shielding layer is positioned above the insulating layer. The first transistor and the second transistor have a shared region where one of the source and the drain is integrated. The shared region functions as an FD node and is arranged to overlap with the joining region between the first metal part and the second metal part. The gate of the first transistor is electrically connected to the first wiring, The first transistor has the function of transferring the charge generated in the photoelectric conversion element to the FD node according to the signal of the first wiring. The gate of the third transistor is electrically connected to the FD node, The anode of the photoelectric conversion element is positioned on the light-receiving surface side and has a recessed region on the light-receiving surface side. An imaging device wherein the anode of the photoelectric conversion element is electrically connected to a second wiring arranged in the same layer as the first wiring via the recessed region.

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