Manufacturing method for semiconductor devices

Abstract

In a method for manufacturing semiconductor devices using semiconductor materials harder than silicon, the residual stress in the semiconductor device caused by the dicing process is reduced. [Solution] One surface of a semiconductor wafer 30 made of a semiconductor material harder than silicon is ground to form a fractured layer 32 with a surface roughness greater than that of the surface before grinding. Then, a crack C is formed on the semiconductor wafer 30 with the fractured layer 32 formed on it, via the fractured layer 32. As a result, a crack C can be formed with less force compared to a mirror-finish semiconductor wafer, and residual stress generated in the semiconductor wafer 30 can be reduced.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device.

Background Art

[0002] Conventional semiconductor devices are formed by forming a plurality of element regions each having a semiconductor element on a semiconductor wafer, and then cutting the semiconductor wafer with a blade to divide the plurality of element regions into individual pieces. In the dicing process of dividing the semiconductor wafer into individual pieces, cracks may occur in the semiconductor chip, or burrs may occur on the back electrode where the blade abuts.

[0003] As a method for manufacturing a semiconductor device that suppresses the occurrence of cracks in the semiconductor chip and burrs on the back electrode in such a dicing process, for example, the method described in Patent Document 1 below has been proposed. In this method for manufacturing a semiconductor device, after forming a V-shaped V-groove and a back electrode on the back surface of the semiconductor wafer in this order, a V-groove is formed in a portion of the front surface of the semiconductor wafer that is located above the V-groove on the back surface. Then, the semiconductor wafer is irradiated with laser light to form a modified layer inside the semiconductor wafer between the V-grooves on the front and back surfaces. Thereafter, a dicing tape is attached to the semiconductor wafer, and the semiconductor wafer is stretched together with the dicing tape to split and divide the wafer starting from the V-grooves and the modified layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, development of power semiconductor devices such as IGBTs and MOSFETs using silicon carbide (SiC) as a semiconductor material has been progressing. Because SiC has lower on-resistance and higher breakdown voltage than silicon (Si), it is expected to improve the performance of power semiconductor devices. IGBT stands for Insulated Gate Bipolar Transistor, and MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor.

[0006] However, semiconductor devices using SiC experience a greater load on the blade during the dicing process because SiC is harder than silicon. Therefore, a dicing process consisting of a scribe process and a break process has been proposed as a method for manufacturing semiconductor devices using semiconductor materials harder than Si. The scribe process involves pressing a blade against a semiconductor wafer to form vertical cracks on the surface. The break process involves pressing a plate or the like against the side of the semiconductor wafer opposite to the side where the vertical cracks were formed, and cleaving and dividing the semiconductor wafer using a three-point bending technique, starting from the vertical cracks. Hereafter, for the sake of simplicity, the dicing process consisting of the scribe process and the break process may be referred to as the "scribe-break process."

[0007] As a result of the inventors' diligent research into manufacturing methods for this type of semiconductor device, it was found that semiconductor chips separated by the scribe-break process exhibit greater residual stress near the end faces compared to those cut by a blade. Furthermore, it was found that this high residual stress can cause cracks to form due to thermal stress in semiconductor chips mounted on other components using solder or the like.

[0008] On the other hand, when the manufacturing method described in Patent Document 1 is applied to this type of semiconductor device, the blade is subjected to a large load because it cuts the hard surface layer of the semiconductor wafer. Furthermore, the process requires forming V-grooves on the surface of the semiconductor wafer in addition to the back surface with the blade, and forming a modified layer by laser irradiation, which increases the number of steps and thus the manufacturing cost. Moreover, there is concern that the process of forming a modified layer by laser irradiation will increase residual stress inside the semiconductor wafer.

[0009] In view of the above, the present invention aims to reduce residual stress in a semiconductor device caused by the dicing process in a method for manufacturing a semiconductor device using a semiconductor material harder than silicon. [Means for solving the problem]

[0010] To achieve the above objective, the method for manufacturing a semiconductor device described in claim 1 includes: preparing a semiconductor wafer (30) made of a semiconductor material harder than silicon; grinding one surface (30b) of the semiconductor wafer to form a fractured layer (32) with a surface roughness greater than that before grinding the surface; forming a crack (C) on the surface layer of the semiconductor wafer through the fractured layer; forming a back electrode (33) on the back surface (30c) of the semiconductor wafer where the crack was formed after the crack was formed; and pressing the surface of the semiconductor wafer opposite to the back surface after the back electrode was formed to cleave the semiconductor wafer into individual pieces starting from the crack.

[0011] This semiconductor device manufacturing method involves forming a fractured layer by grinding a hard semiconductor wafer, and then forming cracks in the semiconductor wafer through the fractured layer before forming the back electrode. This allows for crack formation at lower pressure compared to forming cracks on a mirror-finished surface, making it possible to manufacture semiconductor devices with reduced residual stress caused by the crack shaping process after fragmentation.

[0012] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0013] [Figure 1] This is a top layout diagram showing an example of a semiconductor module using a semiconductor device according to the embodiment. [Figure 2] This is a cross-sectional view showing the cross-sectional configuration between II-II in Figure 1. [Figure 3] This is a diagram illustrating the conventional scribe-break process. [Figure 4] This figure shows the measurement results of residual stress in semiconductor devices obtained by conventional cutting methods and scribe-break processes. [Figure 5] This corresponds to an enlarged view of region V in Figure 2, and is an explanatory diagram of crack generation due to residual stress in semiconductor devices caused by the conventional scribe-break process. [Figure 6A] This is a cross-sectional view showing the bonding process to a support substrate, which is part of the dicing process of a semiconductor device according to the embodiment. [Figure 6B] This is a cross-sectional view showing the process following Figure 6A. [Figure 6C] This is a cross-sectional view showing the process following Figure 6B. [Figure 6D] This is a cross-sectional view showing the process following Figure 6C. [Figure 6E] This is a cross-sectional view showing the process following Figure 6D. [Figure 6F] This is a cross-sectional view showing the process following Figure 6E. [Figure 6G] This is a cross-sectional view showing the process that follows Figure 6F. [Figure 6H] This is a cross-sectional view showing the process following Figure 6G. [Figure 6I] This is a cross-sectional view showing the process following Figure 6H. [Figure 7] This figure shows the results of observing the cross-section of the back side formed by the process shown in Figure 6B using a transmission electron microscope (TEM). [Figure 8]It is a diagram showing the result of observing the cross-section of the back electrode after the process shown in FIG. 6E by TEM. [Figure 9A] It is a cross-sectional view showing another example of the process following FIG. 6C. [Figure 9B] It is a cross-sectional view showing the process following FIG. 9A. **[Embodiment for Carrying Out the Invention]**

[0014] Hereinafter, embodiments of the present invention will be described based on the drawings. In each of the following embodiments, parts that are identical or equivalent to each other will be described with the same reference numerals.

[0015] (Embodiment) A semiconductor module using a semiconductor device according to an embodiment will be described with reference to the drawings. This semiconductor device is, for example, a power semiconductor element mainly composed of a semiconductor material harder than silicon such as SiC, and can be applied to an inverter or the like. In this specification, the case where the semiconductor device is applied to a semiconductor module constituting an inverter will be described as a representative example, but it is not limited to this example and can also be applied to other uses.

[0016] In FIG. 1, in order to make the configuration of the semiconductor module 100 easy to understand, the outline of the encapsulation resin 8 described later is shown by a two-dot chain line, and the portion of the outline of the constituent members of the semiconductor module 100 that overlaps with other constituent members other than the encapsulation resin 8 is shown by a broken line.

[0017] Hereinafter, for the sake of convenience of explanation, as shown by arrows and the like in FIG. 1, the direction along the left-right direction of the paper plane of FIG. 1 will be referred to as the "x direction", the direction perpendicular to the x direction on the same plane will be referred to as the "y direction", and the direction orthogonal to the same plane, that is, the xy plane, will be referred to as the "z direction". The x, y, and z directions indicated by arrows and the like in the figures after FIG. 1 respectively correspond to the x, y, and z directions of FIG. 1.

[0018] **[Semiconductor Module]** As shown in Figure 1, for example, the semiconductor module 100 comprises a first lead frame 1, a second lead frame 2, a semiconductor device 3, a conductor block 4 and connecting members 6 and 7 arranged between the lead frames 1 and 2 in the z direction, a wire 5, and a sealing resin 8.

[0019] The first lead frame 1 is made of a conductive material such as copper and includes a positive electrode plate 11 with a positive electrode terminal P, an output plate 12 with an output terminal O, a negative electrode plate 13 with a negative electrode terminal N, and a plurality of signal terminals 14. The first lead frame 1 is formed when the plate material, which was connected by busbars (not shown) or the like (not shown), is separated during the manufacturing process of the semiconductor module 100 by removing the connecting portion.

[0020] The positive electrode plate 11 has, for example, a positive electrode terminal P that protrudes from the sealing resin 8 along the y-direction, is positioned away from the output plate 12 in the x-direction, and the first semiconductor device 3a is mounted on it via a bonding material (not shown). The positive electrode plate 11 is electrically connected to the first connecting plate 21 (described later) via a first conductor block 4a positioned on the first semiconductor device 3a. The island portion of the positive electrode plate 11 on which the first semiconductor device 3a is mounted has an exposed surface from the sealing resin 8 opposite to the surface facing the first semiconductor device 3a, allowing for cooling by contact with a cooler (not shown). At this time, an insulating member (not shown) is placed between the cooler (not shown) and the exposed portion of the island portion to ensure electrical insulation between the cooler and the semiconductor module 100.

[0021] The output plate 12 has, for example, an output terminal O that is arranged parallel to the positive terminal P and protrudes from the sealing resin 8 in the same direction as the positive terminal P, and the second semiconductor device 3b is mounted on it. The output plate 12 has, for example, a projection 121 that extends toward the positive plate 11 and toward the first connecting plate 21 (described later) in the z direction, and is electrically connected to the first connecting plate 21 via a first connecting member 6 arranged on the projection 121. The output plate 12 is electrically connected to the second connecting plate 22 (described later) via a second conductor block 4b arranged on the second semiconductor device 3b. Similar to the positive plate 11, the side of the output plate 12 opposite to the second semiconductor device 3b side of the island portion on which the second semiconductor device 3b is mounted is exposed from the sealing resin 8, allowing cooling by a cooler (not shown).

[0022] The negative electrode plate 13 is positioned between the positive electrode plate 11 and the output plate 12, but at a distance from them. The negative electrode plate 13 has a negative electrode terminal N that is positioned parallel to the positive electrode terminal P and the output terminal O and protrudes from the sealing resin 8 in the same direction as them. The negative electrode plate 13 has an extension portion 131 that extends in the gap between the positive electrode plate 11 and the output plate 12 in the direction opposite to the negative electrode terminal N, and is electrically connected to the second connecting plate 22 via a second connecting member 7 positioned on the extension portion 131.

[0023] The plurality of signal terminals 14 include a plurality of first signal terminals 14a connected to the first semiconductor device 3a via wires 5, and a plurality of second signal terminals 14b connected to the second semiconductor device 3b via wires 5. The plurality of signal terminals 14 are located between the positive electrode plate 11 and the output plate 12, on the opposite side from terminals P, O, and N, and away from other components.

[0024] The second lead frame 2, for example, comprises a first connecting plate 21 and a second connecting plate 22, and is positioned opposite the first lead frame 1 in the z-direction, separated by the semiconductor device 3 and the conductor block 4. The first connecting plate 21 is positioned opposite the positive electrode plate 11 and is positioned away from the second connecting plate 22. The first connecting plate 21 has, for example, a protruding portion 211 that projects toward the second connecting plate 22 and is partially bent toward the output plate 12. When the first semiconductor device 3a is turned on, the first connecting plate 21 constitutes a current path connecting the positive electrode plate 11, the first semiconductor device 3a, the first conductor block 4a, and the output plate 12. The second connecting plate 22 has, for example, the same shape as the first connecting plate 21 and has a protruding portion 221 that projects toward the first connecting plate 21. The second connecting plate 22 is electrically connected to the negative electrode plate 13 via the protruding portion 221 and a second connecting member 7 positioned directly beneath it. The second connecting plate 22 constitutes a current path connecting the output plate 12, the second semiconductor device 3b, the second conductor block 4b, and the negative electrode plate 13 when the second semiconductor device 3b is turned on. The first connecting plate 21 and the second connecting plate 22 have portions of their surfaces opposite to the conductor block 4 side, excluding the protrusions 211 and 221, that are exposed from the sealing resin 8, and like the positive electrode plate 11 and the output plate 12, they can be cooled by a cooler (not shown).

[0025] The semiconductor device 3 is constructed using a semiconductor substrate made of a semiconductor material harder than silicon, such as SiC, gallium nitride (GaN), or gallium oxide (Ga2O3). For convenience of explanation, semiconductor materials harder than silicon will be referred to as "hard semiconductor materials" below. The semiconductor device 3 constitutes a power semiconductor element on which switching elements such as IGBTs and MOSFETs and freewheeling diodes (FWDs) are formed. In this specification, the case in which the semiconductor device 3 has IGBTs and FWDs is described as a representative example, but it is not limited to this example. The semiconductor device 3 has a structure in which the anode and cathode of the FWD are electrically connected to the emitter, which is the surface electrode of the switching element, and the collector, which is the back electrode, respectively. In the semiconductor device 3, a wire 5 is connected to the gate electrode (not shown) of the switching element, and on / off control is performed via the signal terminal 14.

[0026] The semiconductor device 3 is mounted on the positive electrode plate 11 or output plate 12 via a bonding material 9, such as solder, as shown in Figure 2, for example. Multiple semiconductor devices 3 are formed on a semiconductor wafer made of a high-rigidity hard semiconductor material, and then diced into individual pieces through a scribe-break process described later, resulting in a state where residual stress caused by dicing is reduced. Details of this reduction in residual stress and its effects will be described later.

[0027] The conductor block 4 is made of a conductive material such as copper and is positioned on the opposite side of the semiconductor device 3 from the positive electrode plate 11 or the output plate 12, and is joined to the semiconductor device 3 by a bonding material 9. The conductor block 4 has a planar size smaller than the semiconductor device 3, as shown in Figure 1, for example, and is connected to the part of the semiconductor device 3 other than the part to which the wires 5 are connected. The conductor block 4 is positioned between the positive electrode plate 11 and the first connecting plate 21, and between the output plate 12 and the second connecting plate 22, respectively, and plays a role in ensuring these gaps and preventing the wires 5 from coming into contact with the connecting plates 21 and 22.

[0028] Wire 5 is made of a conductive material such as gold or aluminum, and is connected to the signal terminal 14 and the semiconductor device 3, respectively, by wire bonding.

[0029] The first connecting member 6 and the second connecting member 7 are made of a conductive material such as copper, and are positioned between the protrusion 121 and the protrusion 211, and between the extension 131 and the protrusion 221, respectively, to electrically connect them.

[0030] The sealing resin 8 is composed of a thermosetting resin material such as epoxy resin, and is formed by any resin molding method.

[0031] The above describes the basic configuration of the semiconductor module 100 when used as an inverter. The semiconductor device 3 used in the semiconductor module 100 is made by framing a semiconductor wafer composed of hard semiconductor material using an improved scribe-break process, resulting in reduced residual stress compared to the conventional scribe-break process.

[0032] [Residual stress in semiconductor devices] As a result of our diligent research, we found that when a semiconductor wafer made of hard semiconductor material such as SiC is fragmented using a conventional scribe-break process, the residual stress of the fragmented semiconductor chips is high.

[0033] Here, the conventional scribe-break process will be explained with reference to Figure 3. The conventional scribe-break process consists of a scribe process in which a vertical crack C of a predetermined depth is formed in the semiconductor wafer W, and a break process in which the semiconductor wafer W is cleaved open using a three-point bending method starting from the vertical crack C. In the scribe process, for example, the surface Wa of the semiconductor wafer W is temporarily fixed to an adsorption table or the like, and a blade B is pressed against the back surface Wb to form a vertical crack C on the surface layer of the back surface Wb. In the break process, for example, a tape T is attached to the surface Wa of the semiconductor wafer W and a protective film PF is attached to the back surface Wb, and the wafer is placed on a base, and the position on the vertical crack C on the surface Wa is pressed with a break plate BP. At this time, the semiconductor wafer W is in a hollow state where the part where the vertical crack C is formed is separated from the base, and both ends on either side of the pressing point by the break plate BP are supported by the base, and the wafer is cleaved open and divided using a three-point bending method starting from the vertical crack C. In conventional scribing processes, the back surface Wb of a semiconductor wafer W is polished to a mirror-like state with very low surface roughness using processes such as CMP, and a back electrode made of a metallic material is formed on this back surface Wb. CMP stands for Chemical Mechanical Polishing.

[0034] Through diligent research by the inventors, it has been found that when the semiconductor wafer W is composed of a hard semiconductor material, the blade pressure during the scribing process, i.e., the scribe pressure, increases, and the residual stress in the semiconductor chip after it has been separated into individual pieces increases.

[0035] Specifically, as shown in Figure 4, for example, sample S1, a semiconductor chip formed by cutting a semiconductor wafer W made of SiC with a blade B, had a maximum residual stress of approximately 23 MPa in the dicing region. The maximum residual stress in sample S1 was observed at a distance of approximately 2 μm from the chip edge formed by dicing.

[0036] In contrast, sample S2, a semiconductor chip formed by dicing a SiC semiconductor wafer W using the conventional scribe-break process described above, exhibited a maximum residual stress of approximately 68 MPa in the dicing region. This is thought to be due to the fact that, during the formation of vertical cracks, the back surface Wb of the semiconductor wafer W is covered with a mirror-like back electrode made of metallic material, requiring a large scribe pressure of approximately 6 N, which remains as strain near the scribe line of the semiconductor wafer W. The residual stress in sample S2 was maximum at a distance of approximately 6 μm from the chip edge formed by dicing. The residual stress of the semiconductor chip shown in Figure 4 was measured by Raman scattering spectroscopy.

[0037] When a semiconductor chip has high residual stress, it is subjected to thermal stress due to the difference in thermal expansion coefficients between it and the surrounding components, especially when mounted on other components. If the semiconductor module 100 described above is constructed using a semiconductor chip SC (corresponding to semiconductor device 3) with high residual stress, cracks may develop in the semiconductor chip SC, starting from areas with high residual stress due to thermal stress, as shown in Figure 5, for example. When such cracks occur, they propagate toward the element regions such as IGBTs, reducing the reliability of the semiconductor module 100.

[0038] To reduce residual stress in semiconductor chips after they have been separated into individual pieces, a cutting method using blades can be considered. However, when the semiconductor wafer W is made of a hard semiconductor material, the cutting method using blades places a large load on the blades, and the time required for separation is longer than that of the scribe-break process, thus increasing manufacturing costs. Therefore, the inventors have devised a method to reduce residual stress in semiconductor chips after separation while separating them using the scribe-break process.

[0039] [Scribing and Breaking Process] Next, we will describe a scrib-break process, which is part of the manufacturing process of the semiconductor device 3 according to the embodiment, that separates the semiconductor wafer into individual pieces and can reduce the residual stress described above. Note that the process for forming the element region 31 on the semiconductor wafer 30, which will be described later, can be done by known semiconductor processes, so a detailed explanation of this process is omitted in this specification.

[0040] First, as shown in Figure 6A, the semiconductor wafer 30 made of a hard semiconductor material such as SiC is protected by covering the other side 30a on which the element region 31 is formed with adhesive 201, and is temporarily fixed to the support substrate 200. The support substrate 200 is, for example, a glass substrate having an adhesive film (not shown) made of LTHC manufactured by 3M, but any substrate capable of supporting the semiconductor wafer 30 is acceptable, and may also be a protective tape. It is preferable that the support substrate 200 be made of a material with higher rigidity than a resin material, such as a glass substrate. This is because, in the subsequent scribing process, the pressing force of the blade applied to the semiconductor wafer 30 is less likely to escape, and the scribing pressure can be reduced. The adhesive 201 is made of, for example, any resin material that is UV curable and thermoplastic.

[0041] Next, as shown in Figure 6B, one side 30b of the semiconductor wafer 30 opposite to the support substrate 200 is ground using a grinding device (not shown), such as a grinder, to thin the semiconductor wafer 30. This grinding process is a step in which the semiconductor wafer 30 is roughly ground with a grinding wheel to thin it, and is different from a polishing process to form a mirror surface. Therefore, the surface layer of the back surface 30c obtained by grinding one side 30b is a fractured layer 32 with a greater surface roughness than the surface 30b before grinding. Specifically, when the cross-section of the back surface 30c of the semiconductor wafer 30 after this grinding process was observed using a transmission electron microscope (TEM), it was found to be a fractured layer 32 with an uneven shape of about 50 nm in the thickness direction of the wafer from the surface layer, as shown in Figure 7, for example.

[0042] Next, as shown in Figure 6C, the semiconductor wafer 30 attached to the support substrate 200 is placed on the base 300, and the blade B is pressed against the crushing layer 32 to form a vertical crack C in the dicing region located between the element regions 31. At this time, the blade B and the dicing region of the semiconductor wafer 30 are aligned using, for example, an alignment camera (not shown). The vertical crack C is formed on the surface layer on the back surface 30c side of the semiconductor wafer 30 and is a crack along the thickness direction of the semiconductor wafer 30.

[0043] Furthermore, when performing a similar scribing process on a SiC wafer in a mirror-finish state before the formation of the back electrode, the required scribing pressure was approximately 2N. In contrast, the semiconductor wafer 30 having the crushed layer 32 is more brittle than the base made of SiC, so the required scribing pressure in the scribing process is at least less than 2N. As a result, the strain generated in the semiconductor wafer 30 during vertical crack formation is reduced, and the residual stress near the scribe line becomes smaller.

[0044] Then, as shown in Figure 6D, a back electrode 33 is formed on the back surface 30c of the semiconductor wafer 30 by sputtering or the like. The back electrode 33 is mainly composed of at least one conductive metal material that is silicided, such as Ni (nickel), Ti (titanium), Mo (molybdenum), Ta (tantalum), Pt (platinum), or Co (cobalt), at least in the portion that is in contact with the crushed layer 32. Here, "main component" means a component that exceeds 50 vol%. For example, the back electrode 33 has a layered structure such as Ni / Ti / Ni / Au (gold) from the crushed layer 32 side, and at least the region in contact with the crushed layer 32 is silicided by the next thermal oxidation process. The back electrode 33 is at least thicker than the crushed layer 32, for example, if the depth of the crushed layer 32 is 50 nm, the back electrode 33 has a thickness of 100 nm. This is to remove the crushed layer 32 by silicideing the entire crushed layer 32 with the back electrode 33 in the next step, thereby suppressing an excessive decrease in flexural strength caused by the crushed layer 32. Note that if the back electrode 33 formed in the process shown in Figure 6D has a Ni / Ti / Ni / Au configuration from the crushed layer 32 side, it will become NiSi / Ti / Ni / Au after thermal oxidation.

[0045] Subsequently, as shown in Figure 6E, the semiconductor wafer 30 is heat-treated to silicide the fractured layer 32 with the back electrode 33. This heat treatment may be performed by heating the entire semiconductor wafer 30 using a heating furnace or by laser annealing, in which laser light is irradiated onto the back electrode 33 to locally heat the back surface 30c, and can be carried out by known methods. After this heat treatment, as shown in Figure 8, for example, the semiconductor wafer 30 has a thickness of approximately 150 nm with the back electrode 33 silicided with the fractured layer 32, and the fractured layer 32 has been removed. This suppresses an excessive decrease in the flexural strength of the semiconductor wafer 30 due to the remaining fractured layer 32, resulting in improved reliability.

[0046] Next, as shown in Figure 6F, the dicing tape DT is attached to the back electrode 33 side of the semiconductor wafer 30. Then, for example, by irradiating with laser light, the semiconductor wafer 30 is separated from the adhesive 201 and the support substrate 200, as shown in Figure 6G, exposing the other side 30a.

[0047] Next, as shown in Figure 6H, protective tape PT is attached to the other side 30a of the semiconductor wafer 30, and the semiconductor wafer 30 is placed on the stage 400. At this time, the semiconductor wafer 30 is aligned using an alignment camera (not shown) or the like so that the location where the vertical crack C is formed is positioned over a gap provided in the stage 400. Then, the portion of the other side 30a located above the location where the vertical crack C is formed is pressed with a break plate BP, and the vertical crack C is propagated in the thickness direction of the semiconductor wafer 30 in a three-point bending manner, thereby cleaving the semiconductor wafer 30. By repeating this breaking process for the number of scribe lines in which the vertical crack C is formed, the semiconductor wafer 30 is divided into multiple semiconductor devices 3.

[0048] After the break-up process described above, the protective tape PT is peeled off, and the adhesive strength of the dicing tape DT is reduced by, for example, ultraviolet irradiation, and the divided semiconductor device 3 (semiconductor chip) is picked up by a pickup device (not shown) as shown in Figure 6I.

[0049] By separating the semiconductor wafer 30, which is made of a hard semiconductor material, into individual pieces using the scribe-break process described above, the scribe pressure is reduced compared to conventional methods, and a semiconductor device 3 can be obtained in which residual stress near the edges obtained by the individual pieces is reduced. Compared to the cutting method using a blade B, this method suppresses the load on the blade B and shortens the time required for individual pieces. In addition, the formation of a modified layer by laser irradiation is unnecessary, and the manufacturing cost of the semiconductor device 3 can also be reduced.

[0050] In the above, silicide formation with the back electrode 33 was given as an example of a process for removing the crushed layer 32, but this is not the only example. For example, after the scribing process shown in Figure 6C, the crushed layer 32 may be removed by a mechanical polishing process such as CMP, as shown in Figure 9A. In this case, the back electrode 33 is then formed on the back surface 30c of the polished semiconductor wafer 30, as shown in Figure 9B, and heat treatment is performed. The subsequent steps are the same as described above. Even after going through such a process, the scribe pressure in the scribe process is reduced, and the crushed layer 32 is removed, so a semiconductor device 3 is obtained that is in the same state as when the dicing process shown in Figures 6A to 6I is performed.

[0051] (Other embodiments) This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence range. In addition, various combinations and forms, as well as other combinations and forms including one, more, or less of those elements, fall within the scope and concept of this disclosure.

[0052] It goes without saying that, in each of the above embodiments, the elements constituting the embodiment are not necessarily essential unless explicitly stated to be particularly essential or unless they are clearly considered essential in principle. Furthermore, in each of the above embodiments, when numerical values ​​such as the number, numerical values, quantities, or ranges of the components of the embodiment are mentioned, the embodiment is not limited to those specific numbers unless explicitly stated to be particularly essential or unless it is clearly limited to a specific number in principle. Furthermore, in each of the above embodiments, when the shape, positional relationship, etc., of the components are mentioned, the embodiment is not limited to those shapes, positional relationships, etc., unless explicitly stated or unless it is clearly limited to a specific shape, positional relationship, etc., in principle. [Explanation of Symbols]

[0053] 30 semiconductor wafers 30a Other side of semiconductor wafer 30b One side of a semiconductor wafer 30c semiconductor wafer back surface 32 Fractured layer 33 Backside electrode C Vertical crack

Claims

[Claim 1] The process involves preparing a semiconductor wafer (30) using a semiconductor material harder than silicon, Grinding one side (30b) of the semiconductor wafer to form a fractured layer (32) with a surface roughness greater than that before grinding, To form a crack (C) on the surface layer of the semiconductor wafer via the fractured layer, After forming the aforementioned crack, a back electrode (33) is formed on the back surface (30c) of the semiconductor wafer where the crack was formed. A method for manufacturing a semiconductor device, comprising forming the back electrode, pressing the surface of the semiconductor wafer opposite to the back surface, and cleaving the semiconductor wafer into individual pieces starting from the crack.

Images