Performance control device, control method, and control program

Abstract

The control circuit for the performance effects will be able to recover quickly from any malfunctions. [Solution] The performance control unit 10, which is capable of reading and writing data to the storage device 43, outputs a data write request and a specification of the number of data to be written to the storage device 43 via the input / output control unit 20, or outputs a data read request and a specification of the number of data to be read to the storage device 43 via the input / output control unit 20. The input / output control unit 20 writes the specified number of data to the storage device 43 if the performance control unit 10 is initialized before the writing to the storage device 43 is completed, and reads the specified number of data from the storage device 43 if the performance control unit 10 is initialized before the reading of data from the storage device 43 is completed.

Description

Technical Field

[0001] The present invention relates to a production control device, a control method, and a control program.

Background Art

[0002] There are known gaming machines such as pachinko gaming machines that play games using game balls as game media. In a game hall, game balls are supplied from island facilities to gaming machines, but static electricity is generated when the game balls rub against each other while circulating between the island facilities and the gaming machines. This static electricity noise may cause interference and affect the operation of the production control device and its external storage device. In addition, noise generated by other gaming machines arranged facing each other may cause interference and affect the operation of the production control device and storage device arranged on the back side of the gaming machine. Therefore, various techniques for reducing the influence of static electricity noise are used in gaming machines. As a related technique, for example, electromagnetic wave noise that has invaded control boards such as a peripheral control board, a peripheral data ROM board, and a liquid crystal output board flows from the ground (GND) line of the control boards such as the peripheral control board, the peripheral data ROM board, and the liquid crystal output board to the GND line of the power supply board. A technique for removing this electromagnetic wave noise by flowing it to the ground of the island facilities in the game hall via a frame ground board is disclosed (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, even if measures are taken to reduce the influence of noise, it is difficult to completely eliminate the influence of interference on the production control device and storage device provided in the gaming machine. One aspect of this invention is to enable the rapid recovery of a performance control device that has malfunctioned due to external disturbances or other factors, and to allow it to operate normally. [Means for solving the problem]

[0005] In one aspect, the present invention is a performance control device that includes a first control unit and a second control unit and performs synchronous communication with a storage device, wherein the first control unit comprises a request unit that outputs a write request to the storage device including a specification of write data to the storage device and the number of write data, and an initialization unit that initializes the first control unit, and the second control unit comprises a monitoring unit that monitors whether or not the first control unit has been initialized, and a writing unit that, after outputting the write request but before the first control unit is initialized and before it outputs the specified number of write data to the storage device, writes dummy data to the storage device in an amount that is less than the specified number of write data already output by the first control unit. Furthermore, the present invention also features a performance control device that includes a first control unit and a second control unit and performs synchronous communication with a storage device, wherein the first control unit includes a request unit that outputs a read request to the storage device including a specification of read data and the number of read data items, and an initialization unit that initializes the first control unit, and the second control unit includes a monitoring unit that monitors whether or not the first control unit has been initialized, and an acquisition unit that, if the first control unit is initialized after outputting the read request but before it acquires the specified number of read data items, acquires from the storage device an amount of read data from which the number of acquired read data items is insufficient to reach the specified number. [Effects of the Invention]

[0006] One aspect of the present invention is that a malfunctioning performance control device can be quickly restored and made to normal operation. [Brief explanation of the drawing]

[0007] [Figure 1] This figure shows a schematic configuration of a gaming machine according to this embodiment. [Figure 2] This figure shows an example of the hardware configuration of a gaming machine including the performance control device of this embodiment. [Figure 3] This diagram shows the functional configuration of the performance control device of this embodiment. [Figure 4] This diagram illustrates the communication between the performance control unit and the memory unit during the write process when the performance control unit is not reset. [Figure 5] This diagram illustrates the communication between the performance control unit and the memory unit or external storage device during the read operation when the performance control unit is not reset. [Figure 6] This diagram illustrates the communication between the performance control unit and the memory unit during the write process when the performance control unit is reset. [Figure 7] This diagram illustrates the communication between the performance control unit and the memory unit or external storage device during the read operation when the performance control unit is reset. [Figure 8] This flowchart shows the processes performed by the input / output control unit when writing data. [Figure 9] This flowchart shows the processing performed by the input / output control unit when reading data. [Figure 10] This is a block diagram showing an embodiment of a computer device. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described in detail below with reference to the drawings. Figure 1 is a diagram showing the schematic configuration of a gaming machine according to this embodiment. As shown in Figure 1, the gaming machine 100 comprises a main control board 1, a performance control board 2A, an external storage device 3, a display device 4, a sound emitter 5, and a lighting device 6. The main control board 1 is equipped with the main control unit (main CPU). The performance control board (sub-board) 2A is equipped with the performance control device 2 (sub-CPU). The gaming machine 100 is, for example, a pachinko gaming machine that uses game balls as the game medium. In this embodiment, the performance control device 2 and the external storage device 3 are collectively referred to as the performance control system. The main control board 1 and the performance control board 2A, the performance control board 2A and the external storage device 3, and the performance control board 2A, the display device 4, the sound emitter 5, and the lighting device 6 are all connected to each other in a communicative manner. However, communication between the main control board 1 and the performance control board 2A is one-way communication, and only the input of commands from the main control board 1 to the performance control device 2 is permitted. Data and commands cannot be input from the performance control device 2 to the main control board 1.

[0009] If the gaming machine 100 is a pachinko gaming machine, when a game medium launched into the game area by the launching device enters the starting prize entry point provided in the game area, the main control device performs a random number drawing for symbols, and determines whether it is a jackpot based on the result of this drawing. The main control board 1 outputs a command to the performance control device 2 that specifies the timing and pattern of the symbol changes based on the jackpot determination result. Alternatively, if no start-up win occurs for a certain period of time, the main control board 1 puts the gaming machine 100 into a customer-waiting state (standby state) and inputs a command to the performance control device 2 indicating that it has entered a customer-waiting state. If a jackpot is determined during the jackpot determination process, after the symbols have finished changing, the game ball enters the opened attacker, and a jackpot is awarded, with prize balls being paid out.

[0010] The performance control device 2 is a sub-CPU to the main CPU of the main control board 1 and has the function of a VDP (Video Display Processor). The term VDP originally refers to a processor that controls video output. However, the performance control device 2 in this embodiment is a SoC (System on Chip) that integrates the image control circuit, audio control circuit, lamp control circuit, and control device (performance control CPU) shown in Figure 2. The performance control device 2 selects a performance to be performed using performance devices such as the display device 4, the sound playback device 5, the lighting device 6, etc. based on the commands input from the main control board 1, and performs control to execute the selected performance or the performance during customer waiting within the specified variation time. The display device 4 is, for example, a display device such as an LCD (Liquid Crystal Display), a PDP (Plasma Display Panel), and an OLED (Organic Light Emitting Diode). The sound playback device 5 is, for example, a speaker. The lighting device 6 is, for example, a light emitting device such as an LED (Light Emitting Diode).

[0011] The external storage device 3 is an external storage device connected to the memory I / F 204 (Fig. 2) provided in the performance control device 2. The external storage device 3 stores image data, audio data, and lighting data used for game performances, customer waiting performances (waiting performances), and performances during a big win. The image data includes moving image data. The performance control board 2A can output a performance with rich expressions using images and sounds by reading performance data from the external storage device 3 according to the progress of the game.

[0012] The performance control device 2 reads performance data from the external storage device 3 and the internal storage device 203 (Fig. 2) described later based on the commands input from the main control board 1, and performs various processes on the read performance data. The performance control device 2 outputs the data obtained by performing drawing processing on the read image data to the display device 4 to display an image (image processing). Also, the performance control device 2 outputs the data obtained by performing reproduction processing on the read audio data to the sound playback device 5 to output sound (audio processing). Further, the performance control device 2 outputs the read lighting data to the lighting device 6 to light the lamp (lighting processing). In the present embodiment, the request by each performance control circuit 201 (Fig. 2) provided in the performance control device 2 to read performance data from the external storage device 3 or the internal storage device is referred to as a "read request".

[0013] The performance control device 2 also writes the performance data, which has been processed (for example, image processing) by each performance control circuit 201, to the internal storage device 203 based on commands input from the main control board 1. In this embodiment, only data is read from the external storage device 3, and no data is written to the external storage device 3. In this embodiment, when each performance control circuit 201 requests data to be written to the internal storage device 203, this is referred to as a "write request".

[0014] A "read request" includes, in addition to specifying the data to be read, the address of the data to be read and the size of the data to be read. The size of the data to be read is expressed by the burst size and burst length in the AXI (Advanced eXtensible Interface) bus specification described later. Burst size refers to the number of bytes output during a single burst transfer operation. Burst length refers to the number of burst transfer operations required for a read operation. In other words, burst length is the number of burst-sized data units (unit data) to be read. Therefore, the size of the read data is specifically burst size × burst length. The size of the read data is information for sending and receiving data via the AXI bus included in the performance control device 2. In other words, a "read request" includes the specification of the data to be read and the number of units of data. The data to be read can be specified as the address where the desired data is located in the storage area of ​​the external storage device 3 or the internal storage device 203.

[0015] A "write request" includes, in addition to specifying the data to be written, the address of the data to be written in the internal storage device 203 and the size of the data to be written. The size of the data to be written is expressed in terms of burst size and burst length, similar to the case of the read data described above. Similar to read data, the burst size is the number of bytes output during a single burst transfer process, and the burst length is the number of burst transfer processes required for a write operation. In other words, the burst length is the number of burst-sized data units (unit data) to be written. Therefore, the size of the written data is specifically the burst size multiplied by the burst length. The size of the data to be written is information used for sending and receiving data on the AXI bus. In other words, a "write request" includes the specification of the data to be written and the number of units of data. The data to be written can be specified as the address where the desired data is located in the internal storage device 203.

[0016] Figure 2 is a diagram showing an example of the hardware configuration of a gaming machine including the performance control device of this embodiment, and is a diagram showing the performance control device of Figure 1 in detail. In Figure 2, the performance control device 2 comprises an image control circuit 201a, an audio control circuit 201b, and a lamp control circuit 201c. The image control circuit 201a is a circuit that performs image processing using data acquired from the external storage device 3 or the internal storage device 203, and is connected to the display device 4. In Figure 3, the image control circuit 201a functions as the image control unit 10a. The audio control circuit 201b is a circuit that performs audio processing using data acquired from the external storage device 3 or the internal storage device 203, and is connected to the sound emission device 5. In Figure 3, the audio control circuit 201b functions as the audio control unit 10b. The lamp control circuit 201c is a circuit that performs the lighting process using data acquired from the external storage device 3 or the internal storage device 203, and is connected to the lighting device 6. In Figure 3, the lamp control circuit 201c functions as the lamp control unit 10c.

[0017] Furthermore, the performance control device 2 may include a motor control circuit 201 as a performance control circuit, which controls the motors that drive the movable parts, attackers, electric tulips, etc. used in the performance. In this case, the motor control circuit is connected to the bus 207 and performs motor drive processing using data acquired from the external storage device 3. In the following explanation, when the image control circuit 201a, the audio control circuit 201b, and the lamp control circuit 201c are not specifically distinguished, they will also simply be referred to as the performance control circuit 201.

[0018] Furthermore, the performance control device 2 includes an input / output control circuit 202a for images, an input / output control circuit 202b for audio, and an input / output control circuit 202c for lamps, corresponding to the image control circuit 201a, the audio control circuit 201b, and the lamp control circuit 201c, respectively. Furthermore, the input / output control circuit 202a for images, the input / output control circuit 202b for audio, and the input / output control circuit 202c for lamps are also simply referred to as the input / output control circuit 202. The input / output control circuit 202 is a circuit that controls the transfer of data between each performance control circuit 201, the internal storage device 203, and the external storage device 3. In Figure 3, the input / output control circuit 202 functions as the input / output control unit 20. As explained below, the input / output control circuit 202 has the function of quickly restoring the entire performance control device 2 without resetting it by writing necessary data to the internal storage device 203 or reading it from the internal storage device 203 or external storage device 3 when the performance control circuit 201 is reset due to a malfunction.

[0019] The performance control device 2 also includes an internal memory device 203, a memory interface 204, a control unit 205, and an arbitration circuit 206. The internal memory device 203 is a VRAM or DRAM provided internally by the performance control device 2. The internal memory device 203 may also be a DRAM provided on the performance control board 2A on which the performance control device 2 is mounted. In Figure 3, the internal memory device 203 functions as the storage unit 43. The memory I / F204 is an interface that connects the performance control device 2 and the external storage device 3, and is an input / output interface used for data communication between the performance control device 2 and the external storage device 3.

[0020] The performance control device 2 is connected to the external storage device 3 via the memory I / F 204. The memory interface 204 performs the initialization and link-up process for communication with the external storage device 3, and controls communication between the performance control device 2 and the external storage device 3. In Figure 3, the memory interface 204 functions as the input / output unit 41. The overall control unit 205 is a processor that controls the entire performance control unit 2, and in Figure 3, it functions as the overall control unit 40. The arbitration circuit 206 is a circuit that processes the assignment of usage rights of bus 207 (AXI bus) to multiple masters (in this case, each performance control circuit 201) based on the AXI protocol, and functions as the arbitration unit 42 in Figure 3. The arbitration circuit 206 monitors whether the number of data specified in the "write request" has been written, and once the writing is complete, it releases bus 207 and accepts requests for the allocation of usage rights for bus 207. The arbitration circuit 206 also monitors whether the number of data specified in the "read request" has been read from bus 207, and once the read is complete, it releases bus 207 and accepts requests for the allocation of usage rights to bus 207.

[0021] The input / output control circuit 202, memory I / F 204, overall control unit 205, and arbitration circuit 206 are connected by bus 207. Bus 207 is an AXI bus conforming to the AXI specification, and within the performance control device 2, it connects various components such as the performance control circuit 201, the input / output control circuit 202, and the overall control device 205 in a communicative manner. Each performance control circuit 201 is not directly connected to bus 207, but rather connected to bus 207 via its respective input / output control circuit 202.

[0022] Figure 3 shows the functional configuration of the performance control device of this embodiment. Figure 3 shows the functional configuration of the performance control device corresponding to the hardware configuration in Figure 2. As shown in Figure 3, the performance control device 2 comprises an image control unit 10a, an audio control unit 10b, and a lamp control unit 10c. The performance control device 2 also includes an input / output control unit 20a, an input / output control unit 20b, an input / output control unit 20c, an overall control unit 40, an input / output unit 41, an arbitration unit 42, and a storage unit 43. The image control unit 10a corresponds to the image control circuit 201a in Figure 2, the audio control unit 10b corresponds to the audio control circuit 201b in Figure 2, and the lamp control unit 10c corresponds to the lamp control circuit 201c in Figure 2. The input / output control unit 20a corresponds to the input / output control circuit 202a in Figure 2, the input / output control unit 20b corresponds to the input / output control circuit 202b in Figure 2, and the input / output control unit 20c corresponds to the input / output control circuit 202c in Figure 2. In the following description, when the image control unit 10a, the sound control unit 10b, and the lamp control unit 10c are not specifically distinguished, they will simply be referred to as the performance control unit 10. When the input / output control unit 20a for images, the input / output control unit 20b for sound, and the input / output control unit 20c for lamps are not specifically distinguished, they will simply be referred to as the input / output control unit 20.

[0023] The central control unit 40 corresponds to the central control device 205 in Figure 2 and controls the entire performance control device 2. The central control unit 40 also determines the performance in response to commands input from the main control board 1 and requests the necessary control from each performance control unit 10. The input / output unit 41 corresponds to the memory I / F 204 in Figure 2, and performs the process of initializing communication with the external storage device 3 and linking up, and controls communication with the external storage device 3. The memory unit 43 corresponds to the internal memory device 203 in Figure 2, and is either a DRAM or VRAM located inside the performance control device 2, or a DRAM on the performance control board 2A. The arbitration unit 42 corresponds to the arbitration circuit 206 in Figure 2 and arbitrates the allocation of bus 50.

[0024] The input / output control unit 20 controls the input and output of data between the performance control unit 10 and the external storage device 3 or the internal storage device 203 (storage unit 43). The input / output control unit 20 has a characteristic configuration in the performance control device 2 of this embodiment. The performance control unit 10 is an example of the first control unit. The input / output control unit 20 is an example of the second control unit.

[0025] Each of the performance control units 10 will be described below. The image control unit 10a includes a request unit 11a, an image processing unit 12a, an initialization unit 13a, and an input / output unit 14a. The image control unit 10a controls the image processing in the performance control device 2 in response to requests from the overall control unit 40. The request unit 11a outputs a "read request" to the input / output control unit 20a, which requests the reading of image data for performance from the external storage device 3 or the storage unit 43, or a "write request" to write data to the storage unit 43. The image processing unit 12a performs image processing to draw an image using image data acquired from the external storage device 3 or storage unit 43 via the input / output control unit 20a. The initialization unit 13a performs initialization processing for the image control unit 10a when a malfunction occurs in the operation of the image control unit 10a. The input / output unit 14a processes data input and output with the external storage device 3 and the storage unit 43 via the input / output control unit 20a. More specifically, the input / output unit 14a receives the number of data inputs specified in the "read request" from the external storage device 3 and the storage unit 43, and outputs the number of data inputs specified in the "write request" to the storage unit 43.

[0026] The audio control unit 10b includes a request unit 11b, an audio processing unit 12b, an initialization unit 13b, and an input / output unit 14b. The audio control unit 10b controls the audio processing in the performance control device 2 in response to requests from the overall control unit 40. The request unit 11b outputs a "read request" to the input / output control unit 20b, which requests the reading of audio data for performance from the external storage device 3 or the storage unit 43, and a "write request" to request the writing of data to the storage unit 43. The audio processing unit 12b performs image processing to reproduce audio using audio data acquired from the external storage device 3 or storage unit 43 via the input / output control unit 20b. The initialization unit 13b performs initialization processing for the voice control unit 10b when a malfunction occurs in the operation of the voice control unit 10b. The input / output unit 14b processes data input and output with the external storage device 3 and the storage unit 43 via the input / output control unit 20b. More specifically, the input / output unit 14b receives the number of data inputs specified in the "read request" from the external storage device 3 and the storage unit 43, and outputs the number of data inputs specified in the "write request" to the storage unit 43.

[0027] The lamp control unit 10c includes a request unit 11c, a lighting processing unit 12c, an initialization unit 13c, and an input / output unit 14c. The lamp control unit 10c controls the lighting process in the performance control device 2 in response to a request from the overall control unit 40. The request unit 11c outputs a "read request" to the input / output control unit 20c, which requests the reading of lighting data for effects from the external storage device 3 or the storage unit 43, and a "write request" to request the writing of data to the storage unit 43. The lighting processing unit 12c uses lighting data obtained from the external storage device 3 or storage unit 43 via the input / output control unit 20c to perform a lighting process to light up the lamp. The initialization unit 13c performs initialization processing for the lamp control unit 10c when a malfunction occurs in the operation of the lamp control unit 10c. The input / output unit 14c processes data input and output with the external storage device 3 and the storage unit 43 via the input / output control unit 20c. More specifically, the input / output unit 14c receives the number of data inputs specified in the "read request" from the external storage device 3 and the storage unit 43, and outputs the number of data inputs specified in the "write request" to the storage unit 43. In the following explanation, the performance control unit 10 that sends a request to the external storage device 3 is assumed to be the image control unit 10a. However, the same control can be performed on the sound control unit 10b and the lamp control unit 10c.

[0028] The input / output control unit 20 will now be described. The input / output control unit 20a comprises an input / output unit 21, a monitoring unit 22, a writing unit 23, a discard unit 24, and a storage unit 25. When the input / output unit 21 receives a "write request" from the image control unit 10a, which includes specifying the data to be written and the number of data to be written, and a "read request" that includes specifying the data to be read and the number of data to be read, it stores the request in the storage unit 25. The input / output unit 21 also outputs the "write request" and "read request" to the external storage device 3 and the storage unit 43.

[0029] The monitoring unit 22 monitors whether the image control unit 10a has started the initialization process. When the monitoring unit 22 detects that the image control unit 10a has been initialized, the writing unit 23 determines whether the image control unit 10a is currently writing data to the storage unit 43. If the image control unit 10a is writing data to the storage unit 43 by outputting a "write request," but has not yet written the number of data specified in the "write request," the writing unit 23 writes dummy data to the storage unit 43 for the number of data items that have not yet been written to the storage unit 43. For example, dummy data stored in the storage unit 25 can be used. The written data includes data that has already been output from the image control unit 10a to the bus 50 and has not yet been written to the storage unit 43. If a "write request" specifies the writing of 8 data items, and 2 data items have already been written to the storage unit 43, and 2 data items are waiting to be written to the bus 50, then the write unit 23 will write 4 dummy data items to the storage unit 43. The number of dummy data items, which are the number of data items that have not yet been output to the bus 50, can be determined by counting them each time data is written to the bus 50.

[0030] When the monitoring unit 22 detects that the image control unit 10a has been initialized, the discard unit 24 determines whether data is being read from the external storage device 3 or the storage unit 43. If data is being read by outputting a "read request," but the number of data specified in the "read request" has not yet been transferred to the image control unit 10a, the discard unit 24 retrieves the remaining data from the external storage device 3, storage unit 43, or bus 50 to the number of data that the image control unit 10a has read that is insufficient to reach the specified number, and discards them. The case where the specified number of data has not been transferred includes cases where the specified number of data has not been output from the external storage device 3 or the storage unit 43, or where data being transferred is stuck on the bus 50. In other words, the discard unit 24 acquires all the data stuck on the bus 50 and all the data that the external storage device 3 or the storage unit 43 will output to the bus 50, and then discards them. The last data retrieved from bus 50 has a flag such as LAST set, and by referring to this, you can determine that there is one last piece of data to read from bus 50. Once the last piece of data has been read, you can discard the data that has been read.

[0031] The memory unit 25 comprises a memory area 25a and a memory area 25b. The memory unit 25 stores the dummy data in the memory area 25a and stores the "write request" and "read request" input from the image control unit 10a in the memory area 25b. The input / output control units 20b and 20c have the same configuration as the input / output control unit 20a, except that the monitoring unit 22 monitors the audio control unit 10b and the lamp control unit 10c, and the targeted "read requests" and "write requests" originate from the audio control unit 10b and the lamp control unit 10c. Therefore, their explanation is omitted.

[0032] Dummy data can be any data that can be identified as dummy data, such as random values ​​or fixed values. For example, dummy data can be all zeros. The dummy data itself is indeed sent to and stored in the storage unit 43, but no actual information is written to the storage unit 43 by the dummy data. What is important is the number of dummy data outputs to the storage unit 43 and bus 50 in order to establish the AXI protocol. If the required number of dummy data are generated randomly, there is no need to provide a storage area 25a in the storage unit 25.

[0033] When there is no malfunction in the performance control unit 10, the input / output control unit 20 stores the "read requests" and "write requests" output from the performance control unit 10 in the memory area 25b and then relays them to the bus 50. Data input and output between the external storage device 3 and the memory unit 43 resulting from "read requests" and "write requests" are controlled by the performance control unit 10 itself, and the writing unit 23 and discard unit 24 are bypassed and rendered inoperable. However, the relay of data between the performance control unit 10 and the external storage device 3 and the memory unit 43 can be controlled by the input / output unit 21 of the input / output control unit 20. On the other hand, if the performance control unit 10 is initialized due to a malfunction, the input / output control unit 20 (write unit 23, discard unit 24) takes over and controls the input and output of data to and from the external storage device 3 and the memory unit 43. After the initialization of the performance control unit 10 is completed, the input / output control unit 20 processes the unprocessed data (acquires data from the external storage device 3 and the memory unit 43 from the bus 50 and discards it, and outputs dummy data to the memory unit 43) to establish the AXI protocol, and the performance control device 2 returns to its normal state. Furthermore, the input / output control unit 20 may process unprocessed data in parallel with the initialization of the performance control unit 10 and establish the AXI protocol. In this case, since the bus 50 is released when the AXI protocol is established, communication between other components other than the performance control unit 10 is possible even while the performance control unit 10 is being initialized. After the initialization of the performance control unit 10 is completed, the performance control device 2 returns to its normal state. In other words, since the performance control device 2 can establish the AXI protocol and release the bus 50 even while the performance control unit 10 is being initialized, communication between other components other than the performance control unit 10 is possible to continue. The following explanation will be given in more detail using Figures 2 and 3, but basically, the explanation will be based on the configuration of the functional unit shown in Figure 3, except when referring to the circuit configuration of the performance control device.

[0034] [Communication method between the performance control device and the external storage device] Here, we will explain the communication method between the performance control device 2 and the external storage device 3. The performance control device 2 includes an input / output control unit 20 that controls communication between the performance control device 2 and the external storage device 3, and relays communication between each performance control unit 10 and the external storage device 3. External storage device 3 is a storage device that performs synchronous communication with the performance control device 2, and is, for example, an SSD (Solid State Drive). In the following explanation, we will assume that external storage device 3 is an SSD. The external storage device 3 comprises a storage area 3a, for example, made of NAND flash memory, and a controller 3b that controls reading and writing to the storage area 3a and communication between the display control device 2 and the external storage device 3. If the handshake is successful, the controller 3b of the external storage device 3 reads the data requested by the input / output control unit 20 from the storage area 3a and transfers it to the input / output control unit 20.

[0035] The handshake communication between the input / output control unit 20 and the external storage device 3 will now be described. If the handshake is successful and unaffected by disturbances, the input / output control unit 20 can receive the requested data normally. However, if the handshake fails due to disturbances or other reasons, the input / output control unit 20 will not be able to receive the requested data normally. A successful handshake means that the receiver successfully receives a signal from the sender indicating that data is being transmitted, and the sender successfully receives a signal from the receiver indicating that data has been received. A handshake failure occurs when the sender and receiver fail to receive either a signal indicating that data is being sent, a signal indicating that data has been received, or the data itself. The external storage device 3 employs SATA (Serial ATA) as its communication interface. Like other high-speed serial communication methods, SATA requires communication negotiation to establish communication. Communication negotiation is a process to ensure the reliability of communication.

[0036] In this embodiment, communication negotiation is performed between the performance control device 2 and the external storage device 3. Communication negotiation is a process that includes communication initialization and adjustment of the communication speed. Communication initialization is the process by which the performance control device 2 and the external storage device 3 establish communication with each other. Communication initialization is performed when the power to the gaming machine 100 is turned on, or when at least one of the performance control device 2 and the external storage device 3 is restarted. During the communication initialization process, the performance control device 2 and the external storage device 3 each independently begin transmitting initialization signals. Then, when the performance control device 2 and the external storage device 3 receive the other's initialization signal, they transition to the next state and transmit another signal, repeating this process multiple times to establish communication (for example, the OOB sequence of SATA communication). Initialization signals include, for example, COMINIT, COMORESET, and COMWAKE, which are OOB sequences used to establish communication. The communication speed adjustment is a process that adjusts the communication speed between the performance control device 2 and the external storage device 3 after communication has been established (for example, Speed ​​Negotiation for SATA communication).

[0037] In this embodiment, the gaming machine 100 performs SATA communication between the performance control device 2 and the external storage device 3. Therefore, after the power is turned on, or when at least one of the performance control device 2 and the external storage device 3 is restarted, the gaming machine 100 performs communication negotiation between the performance control device 2 and the external storage device 3. Furthermore, the communication, including communication negotiation, between the performance control device 2 and the external storage device 3 is controlled by the input / output unit 21 of the performance control device 2 and the controller 3b of the external storage device 3.

[0038] This section describes the communication negotiation that takes place when the gaming machine 100 is powered on, or when at least one of the performance control device 2 and the external storage device 3 is restarted. When power is turned on to the gaming machine 100, or when the performance control device 2 restarts, once the voltage input to the performance control device 2 rises and its operation stabilizes, the performance control device 2 performs a reset process. Then, once the reset is released, the performance control device 2 starts the initialization process for communication with the external storage device 3. The reset of the performance control device 2 refers to the initialization of, for example, flip-flops (FFs) and registers. Furthermore, when the power to the gaming machine 100 is turned on, or when the external storage device 3 restarts, the external storage device 3 performs a reset process once the voltage input to the external storage device 3 increases and its operation stabilizes. Then, when the reset is released, the external storage device 3 starts the initialization process for communication with the performance control device 2. During the initialization process, the input / output control unit 20 of the performance control device 2 transmits a COMRESET signal to the external storage device 3. Upon receiving this COMRESET signal, the external storage device 3 transmits a COMINIT signal to the performance control device 2. When the performance control device 2 receives the COMINIT signal, it transmits a COMWAKE signal to the external storage device 3. When the performance control device 2 receives a COMWAKE signal, it transmits the COMWAKE signal to the external storage device 3. Once these negotiations are successfully completed, the communication initialization is finished, communication between the performance control device 2 and the external storage device 3 is established, and communication between the two devices becomes possible. Subsequently, the performance control device 2 and the external storage device 3 perform Speed ​​Negotiation to adjust the communication speed between them.

[0039] After the gaming machine 100 is powered on, or after the performance control device 2 restarts, once communication negotiation with the external storage device 3 is complete, the performance control device 2 reads the performance control program from the external storage device 3. The performance control device 2 completes its startup by executing the read program. As a result, the performance control device 2 completes its initialization for receiving commands from the main control board 1 and enters a waiting state where it can receive commands from the main control board 1. The performance control device 2 starts performance control in response to commands from the main control board 1. In this embodiment, the series of processes that occur after the performance control device 2 restarts and then starts performance control is referred to as a system reset.

[0040] [Data transfer method within the performance control system] The communication method between the input / output control unit 20, the external storage device 3, and the storage unit 43 using the bus 207 (bus 50) shown in Figures 2 and 3 will be explained. Bus 207 (Bus 50) employs the AXI protocol as its communication protocol. The AXI protocol is based on a handshake between devices. The AXI protocol defines five channels between the master and the slave. Two of these channels are used for read transactions, containing the read address and the read data, while the remaining three channels are used for write transactions, containing the write address, the write data, and the write response. In this embodiment, the performance control unit 10 of the performance control device 2 reads performance data from the external storage device 3 and the storage unit 43 via the input / output control unit 20 and writes the data to the storage unit 43. In a read transaction, the master sends the read address and burst length (LENGTH) to the slave. This is the "read request" in this embodiment. In a write transaction, the master sends the write address and burst length (LENGTH) to the slave. This is the "write request" in this embodiment.

[0041] The burst length is a value in the AXI protocol that indicates how many units of data to request the slave to transfer, assuming that the burst size data specified is one unit of data. For example, when the master requests 128 bits of data from the slave, if the unit data is 32 bits, the master requests to read 128 / 32=4 units of data. In this case, the requested data is transferred when the 4 units of data have been transferred from the slave to the master. For example, when the master requests 140 bits of data from the slave, if the unit data is 32 bits, it will request five unit data sets: four corresponding to 128 bits, plus one unit data set containing the remaining 18 bits. In this case, the requested data is transferred when the five unit data sets have been transferred from the slave to the master. Furthermore, the number of unit data items is specified in the request using the value LENGTH. LENGTH should be set to burst length minus 1. Therefore, to request 4 unit data items, you would specify LENGTH=3. The master determines that it has successfully received the requested data when it receives the number of unit data specified in the request.

[0042] In the AXI protocol, read transactions are performed using the following steps (1) to (5). (1) The master outputs a VALID signal to the slave to indicate that it is requesting a read (by setting the signal HIGH). (2) The slave outputs a READY signal to the master to indicate that it is ready to accept a read request (by setting the signal LOW). (3) The target data is sent to the master while the slave is outputting a VALID signal to the master indicating that the read data is valid (the signal is turned ON). (4) The master can accept data while the master has the READY signal, which indicates that the data is ready to be accepted, turned ON. (5) The slave outputs a signal to the master indicating that it has finished sending the data that was requested to be read. In the AXI protocol, this handshake procedure, using READY and VALID signals, allows the master to read data from the slave. Write transactions can also be performed using the following procedure. (1) The master outputs a VALID signal to the slave to indicate that it is requesting a write (by setting the signal HIGH). (2) The slave outputs a READY signal to the master to indicate that it is ready to accept the write request (by setting the signal LOW). (3) The target data is sent to the master while the slave is outputting a VALID signal to the master indicating that the data to be written is valid (the signal is turned ON). (4) The master can accept data while the master has the READY signal, which indicates that the data is ready to be accepted, turned ON. (5) The slave outputs a signal to the master indicating that it has finished sending the data that was requested to be written.

[0043] In Figure 3, the input / output control unit 20 corresponds to the master of the AXI protocol, the external storage device 3 and the storage unit 43 correspond to slaves, and the input / output control unit 20 and the external storage device 3 communicate with each other via the bus 50 according to the AXI protocol. Figure 3 shows a many-to-many configuration with multiple masters for multiple slaves. However, it is not limited to this; a one-to-many configuration is also possible, where multiple masters are connected to a single slave via bus 50. In a many-to-many configuration, for example, the image control unit 10a and the external storage device 3, and the audio control unit 10b and the storage unit 43 can share the bus 50 and communicate simultaneously in accordance with the AXI protocol. By providing an input / output control unit 20 for each performance control unit 10, the processing of the input / output control unit 20 of this embodiment can be performed independently and in parallel for each performance control unit 10. In that case, even if the image control unit 10a, the audio control unit 10b, or the lamp control unit 10c is reset, the other performance control units 10 can continue to communicate in accordance with the AXI protocol without being affected by communication with their corresponding slaves.

[0044] The above describes the basic configuration of the performance control device 2 of this embodiment, which will be explained in more detail below. The external storage device 3, memory unit 43, and performance control device 2 of the gaming machine 100 may be affected by electrostatic noise caused by static electricity generated on the game balls, noise generated by other gaming machines located opposite, and other disturbances. The external storage device 3 has a long signal line between it and the performance control device 2 on the performance control board 2A, and is connected to the performance control board 2A via a connector. As a result, data transfer between the performance control board 2A and the external storage device 3 is susceptible to disturbances such as electrostatic noise. Similar problems can occur with the DRAM on the performance control board 2A and the performance control device 2. Therefore, if electrostatic noise is applied to the transmission path between the performance control device 2 and the external storage device 3 while acquiring data to be used by the performance control unit 20 from the external storage device 3 or memory unit 43 (DRAM on the performance control board 2A), the data being transferred may be corrupted.

[0045] Even when data is transferred from the memory unit 43 (DRAM or VRAM) within the performance control device 2, strong electrostatic noise may not always have any effect on the data being transferred, and the data may become corrupted during the transfer. As a result, the reading of the number of data items requested in the "read request" from the external storage device 3 or storage unit 43 may not be completed. The writing of the number of data items requested in the "write request" to storage unit 43 may not be completed. In that case, when reading data from the external storage device 3 or the memory unit 43, there is a problem in that the performance control unit 10 that requested the data continues to wait for the data. This is because, under the AXI protocol, a request cannot be canceled once it has been made. When such a situation occurs, it is necessary to restart (reset) the entire performance control system, which includes the performance control device 2 and the external storage device 3.

[0046] During the restart of the performance control system, the external storage device 3 is restarted, the performance control device 2 is restarted, and communication negotiation between the restarted performance control device 2 and the external storage device 3 is performed. Subsequently, the performance control device 2 reads the performance control program from the external storage device 3. Then, the performance control device 2 completes its startup by executing the read program and enters a state where it can receive commands from the main control board 1. This completes the restart of the performance control system. During the restart of the performance control system, the display device 4 will either black out or display a blue screen without displaying any performance images. No sound will be output from the sound emitter 5, and the LEDs on the lighting device 6 will not light up. As described above, restarting the performance control system takes a relatively long time because it involves restarting the external storage device 3 and communication negotiation, as well as processing until the performance control device 2 enters a state where it can receive commands from the main control board 1. Therefore, after restarting the performance control system, it takes time to restore the performance control system and resume screen display and sound output. In the gaming machine 100, impressive effects are sometimes performed for the player by dimming the screen or muting the sound effects. A blackout caused by restarting the effect control system may give the player false information and is therefore undesirable.

[0047] In contrast, by inputting dummy data into the performance control unit 10, the request is completed without any problems according to the protocol. Therefore, the performance control unit 10 that made the request does not have to wait indefinitely for data. In the case of data transfer from the external storage device 3, the performance control system can be restored and the performance requested by the main control board 1 can be performed simply by restarting the external storage device 3 and performing communication negotiation between the performance control device 2 and the external storage device 3. In the case of data transfer from the memory unit 43, the problem can be solved simply by inputting dummy data into the performance control unit 10. A restart of the entire performance control device 2 is not required, and each performance control unit can continue processing. The time required to restart the entire performance control device 2 is eliminated, and the time it takes for the performance control system to return to normal operation can be reduced. However, inputting dummy data into the performance control unit 10 could potentially cause the performance control unit 10 to malfunction.

[0048] Even after the requested number of data items have been read, corrupted data (program or content data) due to electrostatic noise may be input to the performance control unit 10, potentially causing malfunctions in its operation. In such cases, the entire performance control system needs to be initialized. Furthermore, regardless of electrostatic noise, malfunctions in the performance control unit 10 may occur due to defects in the performance control program. In such cases, it is necessary to initialize the entire performance control system. Initializing the entire performance control system will take time to restore normal operation, including the communication negotiations mentioned above.

[0049] To facilitate a quick recovery, it is conceivable to initialize (reset) only the malfunctioning performance control unit 10, avoiding the initialization of the entire performance control system. However, if the initialized performance control unit 10 is executing a read request and has not yet finished reading the number of data specified in the "read request," the arbitration unit 42 cannot release the bus 50 and accept the next request (read request, write request). The external storage device 3 and the storage unit 43 also cannot accept the next request (read request, write request) because the specified number of data has not yet been read.

[0050] Furthermore, if the initialized performance control unit 10 is executing a write request and the number of data specified in the "write request" has not been written, the data will remain on the bus, and the arbitration unit 42 will not be able to release the bus 50 and accept the next request. Also, the storage unit 43 will not be able to accept the next request (read request, write request) because the specified number of data has not been written. If the performance control unit 10 is reset, the handshake (the read transaction and write transaction described above) in the AXI protocol between the performance control unit 10 and the input / output control unit 20 will not be completed. In the AXI protocol, the master waits until all the requested number of unit data have been transferred to the slave and the handshake is complete. In the AXI protocol, the transfer cannot be terminated before the specified number of unit data has been transferred. The performance control unit 10, while transferring data, continues to occupy communication with the external storage device 3 or memory unit 43 on the bus 50. As a result, other performance control units 10 cannot read or write data to the external storage device 3 or memory unit 43 that is in use. It becomes difficult for the performance control unit 2 to control the performance normally. In this case as well, since a process to restart the entire performance control system is executed, the time it takes to return to normal operation will be longer compared to the case where only the initialization of the malfunctioning performance control unit 10 is performed.

[0051] In contrast, the configuration of this embodiment satisfies the constraints of the AXI protocol, putting the storage unit 43 into a state where it can accept the next request and releasing the bus 50. Therefore, regardless of the state of the write operation of the image control unit 10a, for example, the initialization unit 13a immediately executes the initialization process as soon as a malfunction occurs in the image control unit 10a, and the entire performance control system can be restored to normal operation. Thus, the time it takes for the system to restore to normal operation can be reduced. The arbitration unit 42 and the storage unit 43 do not have to wait indefinitely for data transmission because a specified number of data items are input. Furthermore, the AXI protocol constraints are met, and the memory unit 43 or external memory device 3 is put into a state to accept the next request, and the bus 50 is released. Therefore, regardless of the read operation status of the image control unit 10a, the initialization unit 13a immediately executes initialization processing when a malfunction occurs in the image control unit 10a, and the entire performance control system can be restored to normal operation. Thus, the time it takes for the system to return to normal operation can be reduced. The arbitration unit 42 determines that a specified number of data has been transferred and does not continue to wait for the image control unit 10a to acquire the data. Therefore, even if a malfunction occurs in the image control unit 10a, the entire performance control system can be quickly restored simply by initializing the image control unit 10a, without having to initialize the entire performance control system.

[0052] Figure 4 illustrates the communication between the performance control unit and the memory unit during the write process when the performance control unit is not reset. The input / output control unit 20 acts as a host for AXI protocol communication with the memory unit 43 and SATA communication with the external storage device 3, and acts as a slave for AXI protocol communication with the performance control unit 10. Please refer to Figure 4 for further explanation. When power is turned on to the gaming machine 100 and communication negotiation between the performance control device 2 and the external storage device 3 is completed, the performance control device 2 reads the performance control program from the external storage device 3. Then, the performance control device 2 completes its startup by executing the read program and enters a reception waiting state in which it can receive commands from the main control board 1.

[0053] When the performance control device 2 receives a command from the main control board 1, the performance control unit 10 makes a "write request" to the input / output control unit 20, specifying the number of performance data to be written (4) in accordance with the AXI protocol (S11). The input / output control unit 20 requests the storage unit 43 to write the specified number of data (4) to the address specified in the "write request" (S21). The performance control unit 10 outputs the first data to the input / output control unit 20 (S12), and the input / output control unit 20 outputs the requested data to the storage unit 43 (S22). The performance control unit 10 outputs the second data to the input / output control unit 20 (S13), and the input / output control unit 20 outputs the requested data to the storage unit 43 (S23). The performance control unit 10 outputs the third data to the input / output control unit 20 (S14), and the input / output control unit 20 outputs the requested data to the storage unit 43 (S24). The performance control unit 10 outputs the fourth data to the input / output control unit 20 (S15), and the input / output control unit 20 outputs the requested data to the storage unit 43 (S25). The AXI protocol terminates successfully once the writing (data transfer to the storage unit 43) of the specified number of data (4 items) in the "write request" is complete, and the performance control unit 10 can execute write requests and read requests again.

[0054] Figure 5 illustrates the communication between the performance control unit and the memory unit or external memory device (not shown) during the read operation when the performance control unit is not reset. Please refer to Figure 5 for further explanation. As in Figure 4, when the performance control device 2, which is in a waiting state, receives a command from the main control board 1, the performance control unit 10 makes a "read request" to the input / output control unit 20 specifying the number of performance data to read or write (4) according to the AXI protocol (S31). The input / output control unit 20 requests the storage unit 43 or external storage device 3 to read the specified number (4) of data from the address specified in the "read request" (S41).

[0055] The memory unit 43 or external storage device 3 outputs the first data to the input / output control unit 20 (S51), and the input / output control unit 20 outputs the requested first data to the performance control unit 10 (S32). The memory unit 43 or external storage device 3 outputs the second data to the input / output control unit 20 (S52), and the input / output control unit 20 outputs the requested second data to the performance control unit 10 (S33). The memory unit 43 or external storage device 3 outputs the third data to the input / output control unit 20 (S53), and the input / output control unit 20 outputs the requested third data to the performance control unit 10 (S34). The memory unit 43 or external storage device 3 outputs the fourth data to the input / output control unit 20 (S54), and the input / output control unit 20 outputs the requested fourth data to the performance control unit 10 (S35). Once the reading of the specified number of data items (4) in the "read request" (data transfer from the storage unit 43) is complete, the AXI protocol terminates successfully, and the performance control unit 10 can execute write requests and read requests again.

[0056] Figure 6 illustrates the communication between the performance control unit and the memory unit during the write process when the performance control unit is reset. As in Figure 4, when the performance control device 2, which is in a waiting state, receives a command from the main control board 1, the performance control unit 10 makes a "write request" to the input / output control unit 20, specifying the number of performance data to be written (4) according to the AXI protocol (S11). The input / output control unit 20 requests the storage unit 43 to write the specified number of data (4) to the address specified in the "write request" (S21). The performance control unit 10 outputs the first data to the input / output control unit 20 (S12), and the input / output control unit 20 outputs the requested first data to the storage unit 43 (S22). The performance control unit 10 outputs the second data to the input / output control unit 20 (S13), and the input / output control unit 20 outputs the requested second data to the storage unit 43 (S23). Now, let's assume that the performance control unit 10 has been reset (S16). The input / output control unit 20 outputs two dummy data items to the storage unit 43 until the number specified in the "write request" is reached (S26, S27). As a result, the writing of the number of data items specified in the "write request" (data transfer to the storage unit 43) is completed. Therefore, the handshake in the AXI protocol between the performance control unit 10 and the storage unit 43 (steps (1) to (5) of the above write transaction) is completed. As a result, the AXI protocol terminates successfully, and the performance control unit 10 can execute write requests and read requests again.

[0057] Figure 7 illustrates the communication between the performance control unit and the memory unit or external storage device during the read operation when the performance control unit is reset. Please refer to Figure 7 for further explanation. As in Figure 4, when the performance control device 2, which is in a waiting state, receives a command from the main control board 1, the performance control unit 10 makes a "read request" to the input / output control unit 20 specifying the number of performance data to read or write (4) according to the AXI protocol (S31). The input / output control unit 20 requests the storage unit 43 or external storage device 3 to read the specified number (4) of data from the address specified in the "read request" (S41).

[0058] The memory unit 43 or external storage device 3 outputs the first data to the input / output control unit 20 (S51), and the input / output control unit 20 outputs (transfers) the requested first data to the performance control unit 10 (S32). The memory unit 43 or external storage device 3 outputs the second data to the input / output control unit 20 (S52), and the input / output control unit 20 outputs the requested second data to the performance control unit 10 (S33). Now, let's assume that the performance control unit 10 has been reset (S16). The memory unit 43 or external storage device 3 outputs the third data to the input / output control unit 20 (S53), and the input / output control unit 20 acquires the data and discards it without outputting it to the performance control unit 10 (S42). The memory unit 43 or external storage device 3 outputs the fourth data to the input / output control unit 20 (S54), and the input / output control unit 20 acquires the data and discards it without outputting it to the performance control unit 10 (S43). As a result, the reading of the number of data items (4) specified in the "read request" (data transfer from the storage unit 43 or external storage device 3) is completed. Therefore, the handshake in the AXI protocol between the performance control unit 10 and the storage unit 43 or external storage device 3 (steps (1) to (5) of the read transaction described above) is completed. As a result, the AXI protocol terminates successfully, and the performance control unit 10 can execute write requests and read requests again.

[0059] Figure 8 is a flowchart showing the input / output control process performed by the input / output control unit when writing data. The processing of the input / output control unit can be performed by the input / output control circuit 202, or by software processing by a processor provided in the performance control device 2 instead of the input / output control circuit 202. In the following explanation with reference to Figure 8, it will be assumed that a "write request" for image data has been made from the image control unit 10a. In step S101, the input / output control unit 20 determines whether or not an input request for writing image data has been received, for example, from the request unit 11a of the image control unit 10a. When the input / output control unit 20 determines that a write request has been received (Yes in step S101), it stores the write request (S102). Then, in step S103, the input / output control unit 20 starts outputting a request to write image data to the storage unit 43 (transferring the write request).

[0060] In step S104, the input / output control unit 20 outputs one data to the storage unit 43 (to the bus 50). In step S105, the input / output control unit 20 determines whether it has finished outputting the specified number of data items. If the system determines that it has finished outputting the specified number of data (Yes in step S105), the input / output control unit 20 proceeds to step S106 and terminates the input / output control process. If it is determined that the specified number of data items have not been output (there is remaining data to be output) (No in step S105), the input / output control unit 20 determines in step S107 whether or not the image control unit 10a has been reset (initialized). If the image control unit 10a determines that it has not been reset (No in step S107), the input / output control unit 20 returns to step S104 and outputs the following data to the storage unit 43. If the image control unit 10a determines that a reset has occurred (Yes in step S107), the input / output control unit 20 outputs the number of dummy data points that are insufficient to reach the specified number to the storage unit 43 in step S108. Once this is complete, the process proceeds to step S106 and terminates the input / output control process.

[0061] Figure 9 is a flowchart showing the input / output control process performed by the input / output control unit when reading data. The processing of the input / output control unit can be performed by the input / output control circuit 202, or by software processing by a processor provided in the performance control device 2 instead of the input / output control circuit 202. In the following explanation with reference to Figure 9, it will be assumed that an image data read request has been made from the image control unit 10a. In step S201, the input / output unit 21 of the input / output control unit 20 determines whether or not an image data read request has been received, for example, from the request unit 11a of the image control unit 10a. When the input / output control unit 20 determines that a read request has been received (Yes in step S201), it stores the read request (S202). Then, in step S203, the input / output control unit 20 starts outputting a request to read image data from the storage unit 43 or the external storage device 3 (transferring the read request). In step S204, the input / output control unit 20 reads one data from the storage unit 43 or the external storage device 3. In step S205, the input / output control unit 20 inputs the read data to the image control unit 10a. In step S206, the input / output control unit 20 determines whether it has finished reading the specified number of data items. If the input / output control unit 20 determines that it has finished reading the specified number of data (Yes in step S206), it proceeds to step S207 and terminates the input / output control process. The image control unit 10a draws an image using image data acquired from the storage unit 43 or the external storage device 3 and displays it on the display device 4.

[0062] If the input / output control unit 20 determines that it has not finished reading the specified number of data (there is remaining data to be read) (No in step S206), it determines in step S208 whether the image control unit 10a has been reset (initialized). If the input / output control unit 20 determines that the image control unit 10a has not been reset (No in step S208), it returns to step S204 and reads the next data from the storage unit 43 or the external storage device 3 (bus 50). If the image control unit 10a determines that it has been reset (Yes in step S208), the input / output control unit 20 acquires the next data from the bus 50 in step S209 and discards the data read in step S210. In step S211, the input / output control unit 20 determines whether it has completed reading the specified number of data, including the discarded data. If it is determined that the specified number of data items have not been read (there is still data to be read) (No in step S211), the process returns to step S209 to obtain the next data from bus 50, discard the data read in step S210, and then perform the determination in step S211. If the input / output control unit 20 determines that it has finished reading the specified number of data (Yes in step S211), it proceeds to step S212 and terminates the input / output control process. The image control unit 10a does not perform drawing using the image data obtained from the current read request, but instead outputs, for example, an image that has been drawn up to that point (for example, the previous frame) stored in the frame buffer to the display device 4.

[0063] According to this embodiment, even if the performance control unit 10 is reset while data is being written to or read from the external storage device 3 and the memory unit 43, all the data output by the external storage device 3 and the memory unit 43 to the bus 50 is acquired, and dummy data is also output to the memory unit 43. As a result, the number of data specified by the "read request" and "write request" from the performance control unit 10 is correctly transferred within the bus. Consequently, the arbitration unit 42, which manages the bus 50, releases the bus 50. As a result, a reset of the entire output control unit 2 and communication negotiation with the external storage device 3 are not required, and another performance control unit 10 can communicate with the external storage device 3 and the memory unit 43, allowing for the continuous execution of normal performances.

[0064] Figure 10 is a block diagram showing one embodiment of a computer device. Referring to Figure 10, the configuration of the computer device 300 will be described. In Figure 10, the computer device 300 includes a control circuit 301, a storage device 302, a reading device 303, a recording medium 304, a communication interface 305, an input / output interface 306, an input device 307, and a display device 308. The communication interface 305 is connected to a network 309. Each component is connected by a bus 310. The main control board 1, the performance control device 2, and the external storage device 3 can be configured by appropriately selecting some or all of the components described in the computer device 300. The control circuit 301 controls the entire computer device 300. The control circuit 301 is a processor such as a CPU (Central Processing Unit), a multi-core CPU, an FPGA (Field Programmable Gate Array), or a PLD (Programmable Logic Device). The control circuit 301 functions, for example, as the performance control unit 10 and the input / output control unit 20 in Figure 3.

[0065] The storage device 302 stores various types of data. The storage device 302 is, for example, a memory such as ROM (Read Only Memory) and RAM (Random Access Memory), or a non-temporary recording medium such as HD (Hard Disk) and SSD (Solid State Drive). The storage device 302 functions as, for example, storage unit 25 and storage unit 43 in Figure 3. The ROM stores programs such as the boot program. The RAM is used as the work area for the control circuit 301. The HD stores programs such as the OS, application programs, firmware, and various data. When performing various processes, the performance control device 2 reads the performance control program stored in the memory device 302 into RAM. By executing the performance control program read into RAM with the control circuit 301, the performance control device 2 performs a process that includes one or more of the following: request processing, image processing, sound processing, lighting processing, and input / output processing. Alternatively, the performance control device 2 may also perform a process that includes one or more of the following: request processing, image processing, sound processing, lighting processing, and input / output processing by reading and executing the performance control program from the external memory device 3. Furthermore, each of the above-mentioned programs may be stored in a memory device on a server on the network 309, provided that the control circuit 301 can access it via the communication interface 305.

[0066] The reading device 303 is controlled by the control circuit 301 and performs read / write operations on the removable recording medium 304. The reading device 303 communicates with, for example, the performance control device 2 and the external storage device 3. The reading device 303 is, for example, an FDD (Floppy Disk Drive), CDD (Compact Disc Drive), DVDD (Digital Versatile Disk Drive), BDD (Blu-ray® Disk Drive), USB (Universal Serial Bus), SATA, etc. The recording medium 304 stores various types of data. The recording medium 304 may, for example, store a processing program for the performance control device. The performance control program includes one or more of the following: request processing, image processing, sound processing, lighting processing, and input / output processing. The recording medium 304 is connected to the bus 310 via the reading device 303, and data is read / written by the control circuit 301 controlling the reading device 303. Furthermore, the recording medium 304 is a non-temporary recording medium such as an SD memory card, floppy disk, compact disc, digital versatile disc, Blu-ray disc, hard disk drive, solid state drive, and flash memory. The recording medium 304 functions as an external storage device 3, for example, in Figures 2 and 3.

[0067] The communication interface 305 connects the computer device 300 to other devices via the network 309, enabling communication between them. The communication interface 305 may also include an interface with wireless LAN functionality and an interface with short-range wireless communication functionality. The wireless LAN interface may support, for example, Wi-Fi® as the wireless LAN standard. The short-range wireless interface may support, for example, Bluetooth® as the short-range wireless communication standard. LAN stands for Local Area Network.

[0068] The input / output interface 306 is connected to, for example, an input device 307. When signals indicating various information are input from the connected input device 307, the input / output interface 306 outputs the input signals to the control circuit 301 via the bus 310. Conversely, when signals indicating various information output from the control circuit 301 are input to the input / output interface 306 via the bus 310, the input / output interface 306 outputs those signals to the connected devices. The input device 307 may be, for example, a keyboard, mouse, or touch panel. The display device 308 displays various information. For example, the display device 308 displays an image drawn by the performance control device 2. The display device 308 may also display information for accepting input via the touch panel. For example, in Figure 1, the display device 308 functions as the display device 4. Furthermore, the input / output interface 306, input device 307, and display device 308 may function as a GUI (Graphical User Interface). This allows the computer device 300 to accept intuitive operation via a touch panel, mouse, or the like. The network 309 is, for example, a LAN, wireless communication, or the Internet, and connects the computer device 300 with other devices for communication.

[0069] This embodiment is not limited to the embodiments described above, and various configurations or embodiments can be taken without departing from the spirit of this embodiment. [Explanation of Symbols]

[0070] 1 Main control board, 2 Performance control device, 2A Performance control board, 3 External storage device, 4 Display device, 5 Sound emitter, 6 Lighting device, 10 Performance control unit, 10a Image control unit, 10b Sound control unit, 10c Lamp control unit, 20 Input / output control unit, 20a Input / output control unit, 20b Input / output control unit, 20c Input / output control unit, 21 Input / output unit, 22 Monitoring unit, 23 Writing unit, 24 Discard unit, 25 Memory unit, 40 Overall control unit, 41 Input / output unit, 42 Arbitration unit, 43 Memory unit, 50 Bus, 100 Gaming machine, 201 Performance control circuit, 201a Image control circuit, 201b Sound control circuit, 201c Lamp control circuit, 202 Input / output control circuit, 202a Image input / output control circuit, 202b Sound input / output control circuit, 202c Lamp input / output control circuit, 203 Internal storage device, 204 Memory I / F, 205 Integrated Control Unit, 206 Arbitration Circuit, 207 Bus

Claims

1. A performance control device including a first control unit and a second control unit, which performs synchronous communication with a storage device, The first control unit is, A request unit that outputs a write request to the storage device, including the data to be written to the storage device and the number of data to be written. The system comprises an initialization unit that performs initialization of the first control unit, The second control unit is, A monitoring unit that monitors whether the first control unit has been initialized, After the output of the write request, if the first control unit is initialized before it outputs the specified number of write data to the storage device, the write unit writes dummy data to the storage device in an amount that is less than the specified number of write data already output by the first control unit. Equipped with, A performance control device characterized by the following features.

2. In the performance control device according to claim 1, The second control unit stores pre-created dummy data in the storage unit, and writes the dummy data stored in the storage unit to the memory device. A performance control device characterized by the following features.

3. A performance control device including a first control unit and a second control unit, which performs synchronous communication with a storage device, The first control unit is, A request unit outputs a read request to the storage device that includes the data to be read from the storage device and a specification of the number of data to be read. The system comprises an initialization unit that performs initialization of the first control unit, The second control unit is, A monitoring unit that monitors whether the first control unit has been initialized, If the first control unit is initialized after the output of the read request but before it acquires the specified number of read data, the system includes an acquisition unit that acquires from the storage device the number of read data that are insufficient to reach the specified number of read data already acquired. A performance control device characterized by the following features.

4. The performance control device according to claim 3, The second control unit discards the read data acquired by the acquisition unit. A performance control device characterized by the following features.

5. In the performance control device according to any one of claims 1 to 4, The aforementioned number is information indicating how many data units across the bus width connecting the first control unit and the storage device. A performance control device characterized by the following features.

6. A control method for a performance control device that performs synchronous communication with a storage device, If the control unit outputs a write request to the storage device, including the data to be written to the storage device and the number of data items to be written, but the control unit is initialized before it outputs the specified number of data items to the storage device, the control unit writes dummy data to the storage device in an amount that is less than the specified number of data items that have already been output. A control method characterized by the following:

7. A control method for a performance control device that performs synchronous communication with a storage device, After the control unit outputs a read request to the storage device, which includes the data to be read from the storage device and a specification of the number of data to be read, if the control unit is initialized before it acquires the specified number of data to be read, the control unit acquires from the storage device the number of data to be read that is less than the specified number of data already acquired. A control method characterized by the following:

8. A control program executed by a processor in a performance control device that performs synchronous communication with a memory device, The processor, after the control unit outputs a write request to the storage device including the data to be written to the storage device and the number of data to be written, if the control unit is initialized before it outputs the specified number of data to the storage device, writes to the storage device a number of dummy data equal to the number of data to be written that the control unit has already output is less than the specified number. A control program characterized by the following features.

9. A control program executed by a processor in a performance control device that performs synchronous communication with a memory device, A control program characterized in that, after the control unit outputs a read request to the storage device including read data from the storage device and a specification of the number of read data items, if the control unit is initialized before it acquires the specified number of read data items, the control unit acquires from the storage device an amount of read data from which the number of read data items already acquired is less than the specified number.

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