Semiconductor packages

Abstract

This semiconductor package improves the optical communication speed with external devices and reduces signal loss. [Solution] The semiconductor package 100 includes a substrate 110, a logic die 10 located on the substrate, a base insulating layer 120 located on the side and top surfaces of the logic die, insulating layer through-vias 125 penetrating the base insulating layer on both sides of the logic die, a high-bandwidth memory 20 located on the top surface of the base insulating layer, and an optical connector 40 including an optical fiber 42 for transmitting optical signals between the optical structure and an external device. The high-bandwidth memory 20 includes a plurality of memory dies 21, 22, 23, 24 stacked perpendicular to the top surface of the base insulating layer 120, and the optical structure is connected to the logic die 10 perpendicular to the top surface of the logic die.

Description

Technical Field

[0001] The present invention relates to a semiconductor package.

Background Art

[0002] With the development of technologies such as biohealth, AI (artificial intelligence), VR (virtual reality), autonomous driving, and robots, data traffic has been increasing exponentially. As a result, ultra-high-speed data communication is required, and the demand for optical transceivers that communicate using optical signals rather than electrical signals is increasing.

[0003] Silicon photonics technology is a technology for implementing a photonic integrated circuit capable of processing optical signals on a silicon chip. Silicon photonics technology features low optical propagation loss, low power consumption, high bandwidth, and compatibility with a mature commercial CMOS (complementary metal-oxide-semiconductor) process. Along with such silicon photonics technology, packaging technology based on silicon photonics for integrating a photonics module with an existing semiconductor package has also been developed.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor package capable of improving the optical communication speed with an external device and reducing signal loss.

Means for Solving the Problems

[0005] A semiconductor package according to one aspect of the present invention, made to achieve the above objective, includes a substrate, a logic die located on the substrate, a base insulating layer located on the side and top surfaces of the logic die, insulating layer through-vias penetrating the base insulating layer on both sides of the logic die, a high-bandwidth memory and an optical structure located on the top surface of the base insulating layer, and an optical connector including an optical fiber for transmitting optical signals between the optical structure and an external device, wherein the high-bandwidth memory includes a plurality of memory dies stacked in a direction perpendicular to the top surface of the base insulating layer, and the optical structure is connected to the logic die in a direction perpendicular to the top surface of the logic die.

[0006] To achieve the above objective, another aspect of the present invention provides a semiconductor package comprising: a substrate; a logic die located on the substrate; a base insulating layer located on the side and top surfaces of the logic die; insulating layer through-vias penetrating the base insulating layer on both sides of the logic die; a high-bandwidth memory and optical structure located on the top surface of the base insulating layer; and an optical connector including an optical fiber for transmitting optical signals between the optical structure and an external device, wherein the high-bandwidth memory includes a plurality of memory dies stacked perpendicular to the top surface of the base insulating layer; the optical structure in a planar plane overlaps with at least a portion of the logic die; and the optical structure is connected to the logic die in a direction perpendicular to the top surface of the logic die.

[0007] A semiconductor package according to yet another aspect of the present invention made to achieve the above objectives includes a substrate and a plurality of chiplets mounted on the substrate, each of the plurality of chiplets including a logic die located on the substrate, a base insulating layer located on the side and top surface of the logic die, insulating layer through-vias penetrating the base insulating layer on both sides of the logic die, a high-bandwidth memory and optical structure located on the top surface of the base insulating layer, and an optical connector including an optical fiber for transmitting optical signals between the optical structure and an external device, wherein the high-bandwidth memory includes a plurality of memory dies stacked in a direction perpendicular to the top surface of the base insulating layer, and the optical structure is connected to the logic die in a direction perpendicular to the top surface of the logic die. [Effects of the Invention]

[0008] According to the present invention, the communication speed of a semiconductor package that communicates with an external device using optical signals can be improved and signal loss can be reduced. Furthermore, it can reduce the size of semiconductor packages. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view of a semiconductor package according to one embodiment. [Figure 2] This is a cross-sectional view of a semiconductor package according to one embodiment, taken along the line A-A' in Figure 1. [Figure 3] This is a schematic block diagram showing the components of an optical structure according to one embodiment. [Figure 4] This is a schematic cross-sectional view showing a photon integrated circuit according to one embodiment. [Figure 5] This is a cross-sectional view of a semiconductor package according to one embodiment. [Figure 6] This is a cross-sectional view of a semiconductor package according to one embodiment. [Figure 7] This is a cross-sectional view of a semiconductor package according to one embodiment. [Figure 8]This is a cross-sectional view of a semiconductor package according to one embodiment. [Figure 9] This is a cross-sectional view of a semiconductor package according to one embodiment. [Figure 10] This is a plan view of a semiconductor package according to one embodiment. [Figure 11] This is a cross-sectional view of a semiconductor package according to one embodiment, and is a cross-sectional view taken along the line B-B' in Figure 10. [Figure 12] This is a cross-sectional view of a semiconductor package according to one embodiment, and is a cross-sectional view taken along the line B-B' in Figure 10. [Figure 13] This is a cross-sectional view showing the manufacturing process of a semiconductor package according to one embodiment, in sequence. [Figure 14] This is a cross-sectional view showing the manufacturing process of a semiconductor package according to one embodiment, in sequence. [Figure 15] This is a cross-sectional view showing the manufacturing process of a semiconductor package according to one embodiment, in sequence. [Figure 16] This is a cross-sectional view showing the manufacturing process of a semiconductor package according to one embodiment, in sequence. [Figure 17] This is a cross-sectional view showing the manufacturing process of a semiconductor package according to one embodiment, in sequence. [Figure 18] This is a cross-sectional view showing the manufacturing process of a semiconductor package according to one embodiment, in sequence. [Figure 19] This is a cross-sectional view showing the manufacturing process of a semiconductor package according to one embodiment, in sequence. [Modes for carrying out the invention]

[0010] Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings, so that those with ordinary skill in the art to which the present invention pertains can easily implement them. The present invention can be implemented in a variety of different forms and is not limited to the embodiments described herein.

[0011] In order to clearly describe the present invention, parts not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0012] In addition, the sizes and thicknesses of the respective configurations shown in the drawings are arbitrarily shown for the sake of convenience of explanation, and the invention is not necessarily limited to those shown in the drawings. In the drawings, the thickness is enlarged to clearly represent some layers and regions. And, in the drawings, for the sake of convenience of explanation, the thicknesses of some layers and regions are exaggeratedly shown.

[0013] Also, when a part such as a layer, film, region, plate, etc. is "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there are other parts in between. Conversely, when a part is "directly above" another part, it means that there are no other parts in between. Also, being "above" the reference part means being located above or below the reference part, and does not necessarily mean being located "above" in the direction opposite to gravity.

[0014] Also, throughout the specification, when a part "includes" a certain component, this means that, unless otherwise stated to the contrary, it does not exclude other components, but may further include other components.

[0015] Also, throughout the specification, when it is said "on a plane", this means when the target part is viewed from above, and when it is said "in a cross-section", this means when the cross-section obtained by vertically cutting the target part is viewed from the side.

[0016] Hereinafter, a semiconductor package according to an embodiment will be described with reference to FIGS. 1 and 2.

[0017] FIG. 1 is a plan view of a semiconductor package according to an embodiment, and FIG. 2 is a cross-sectional view of a semiconductor package according to an embodiment. FIG. 2 is a cross-sectional view taken along the line A-A' of FIG. 1.

[0018] Referring to Figures 1 and 2, a semiconductor package 100 according to one embodiment includes a substrate 110, a logic die 10 located on the substrate 110, a base insulating layer 120 located on the side and top surfaces of the logic die 10, insulating layer through-vias 125 penetrating the base insulating layer 120 on both sides of the logic die 10, a high-bandwidth memory (HBM) 20 and an optical structure 30 located on the top surface of the base insulating layer 120, and an optical connector 40 including an optical fiber for transmitting optical signals between the optical structure 30 and an external device.

[0019] The substrate 110 is a packaging substrate, such as a printed circuit board (PCB) or a ceramic substrate. If the substrate 110 is a printed circuit board, it is made of at least one material selected from phenolic resin, epoxy resin, and polyimide. The substrate 110 includes an integrated circuit. The substrate 110 includes one or more routing lines.

[0020] The substrate 110 includes a first surface and a second surface that face each other. The first surface and the second surface are aligned in a first direction DR1 and a second direction DR2, respectively. The second direction DR2 intersects with the first direction DR1. For example, the second direction DR2 is perpendicular to the first direction DR1. The first surface and the second surface face each other along a third direction DR3. The third direction DR3 is perpendicular to the first direction DR1 and the second direction DR2.

[0021] Multiple first connection pads 118 are located on the first surface of the substrate 110, and multiple external connection members 111 are located on the second surface of the substrate 110. The multiple external connection members 111 electrically connect the semiconductor package 100 to an external device (for example, a motherboard).

[0022] The external connecting member 111 contains a conductive material. For example, the external connecting member 111 contains a metal such as copper or aluminum, or an alloy thereof. For example, the external connecting member 111 is a solder ball.

[0023] Multiple first connection pads 118 electrically connect components located on the first surface of the substrate 110 to the substrate 110. The logic die 10 and the base insulating layer 120 are located on the first surface of the substrate 110. Multiple second connection pads 122 are located on the lower surface of the logic die 10 and the lower surface of the base insulating layer 120. Some of the multiple second connection pads 122 are located on the lower surface of the logic die 10, and some are located on the lower surface of the base insulating layer 120. Multiple second connection pads 122 are connected to multiple first connection pads 118. For example, multiple second connection pads 122 are connected to multiple first connection pads 118 by multiple first connection members 121. Each of the multiple first connection members 121 is located between the respective lower surfaces of the multiple second connection pads 122 and the respective upper surfaces of the multiple first connection pads 118.

[0024] Each of the first connecting pad 118, the second connecting pad 122, and the first connecting member 121 contains a conductive material. For example, each of the first connecting pad 118, the second connecting pad 122, and the first connecting member 121 contains a metal such as copper or aluminum, or an alloy thereof. For example, the first connecting member 121 is a solder ball.

[0025] The logic die 10 is covered on its top and sides by a base insulating layer 120. The bottom surface of the logic die 10 is at substantially the same level as the bottom surface of the base insulating layer 120. On a plane, the logic die 10 is located in the center of the base insulating layer 120. The logic die 10 is surrounded by the base insulating layer 120.

[0026] The logic die 10 is connected to the high-bandwidth memory 20 and the optical structure 30. The logic die 10 generates and transmits electrical signals to the high-bandwidth memory 20 to control it. The logic die 10 reads data from the high-bandwidth memory 20 and writes data to the high-bandwidth memory 20. The logic die 10 processes the data read from the high-bandwidth memory 20. The logic die 10 generates and transmits electrical signals to the optical structure 30 to control it. The logic die 10 processes the electrical signals received from the optical structure 30.

[0027] For example, logic die 10 includes an ASIC (application-specific integrated circuit), a CPU (central processing unit), a GPU (graphic processing unit), or an FPGA (field-programmable gate array).

[0028] Multiple third connection pads 124 are located on the upper surface of the logic die 10. Some of the multiple third connection pads 124 are connected to the high-bandwidth memory 20, and others are connected to the optical structure 30.

[0029] Multiple through-logic vias 105 are provided that penetrate the logic die 10. The through-logic vias 105 extend through the logic die 10 in a third direction DR3. Signals are transmitted between the high-bandwidth memory 20 and the substrate 110, and between the optical structure 30 and the substrate 110, via the through-logic vias 105.

[0030] The logic through-via 105 contains a conductive material. For example, the logic through-via 105 contains a metal such as copper or aluminum, or an alloy thereof.

[0031] The base insulating layer 120 covers the side and top surfaces of the logic die 10. In cross-section, the base insulating layer 120 is located on both sides of the logic die 10. Multiple insulating layer through-vias 125 are provided that penetrate the base insulating layer 120. The insulating layer through-vias 125 penetrate the base insulating layer 120 on both sides of the logic die 10. The insulating layer through-vias 125 extend in a third direction DR3. Signals are transmitted between the optical structure 30 and the substrate 110 via the insulating layer through-vias 125.

[0032] The base insulating layer 120 is located on the upper surfaces of the multiple insulating layer through vias 125 and the multiple third connection pads 124. Multiple fourth connection pads 128 are located on the upper surface of the base insulating layer 120. The side and bottom surfaces of the fourth connection pads 128 are covered by the base insulating layer 120. The upper surface of the fourth connection pads 128 is located at substantially the same level as the upper surface of the base insulating layer 120. The fourth connection pads 128 are embedded in the upper surface of the base insulating layer 120.

[0033] The base insulating layer 120 contains an insulating material. For example, the base insulating layer 120 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The insulating layer through-vias 125 contain a conductive material. For example, the insulating layer through-vias 125 may include a metal such as copper or aluminum, or an alloy thereof.

[0034] Some of the multiple fourth connection pads 128 are connected to multiple insulating layer through vias 125, and other parts are connected to multiple third connection pads 124. The multiple fourth connection pads 128 are connected to the multiple insulating layer through vias 125 and the multiple third connection pads 124 by multiple connecting vias 127. The connecting vias 127 extend in the third direction DR3. The sides of the connecting vias 127 are surrounded by the base insulating layer 120. Some of the multiple connecting vias 127 connect the lower surface of the fourth connection pad 128 and the upper surface of the insulating layer through vias 125 in the third direction DR3. Other parts of the multiple connecting vias 127 connect the lower surface of the fourth connection pad 128 and the upper surface of the third connection pad 124 in the third direction DR3.

[0035] Each of the third connecting pad 124, the fourth connecting pad 128, and the connecting via 127 contains a conductive material. For example, each of the third connecting pad 124, the fourth connecting pad 128, and the connecting via 127 contains a metal such as copper or aluminum, or an alloy thereof.

[0036] The high-bandwidth memory 20 is located on the upper surface of the base insulating layer 120 and on the upper surfaces of the multiple fourth connection pads 128. The high-bandwidth memory 20 is electrically connected to some of the multiple fourth connection pads 128 that are connected to the logic die 10. The high-bandwidth memory 20 and the logic die 10 are electrically connected via the fourth connection pads 128. In a plane, the high-bandwidth memory 20 is located on the center of the base insulating layer 120. The high-bandwidth memory 20 overlaps the logic die 10 in the third direction DR3. In a plane, the high-bandwidth memory 20 is located on the center of the logic die 10.

[0037] The high-bandwidth memory 20 includes a plurality of memory dies 21, 22, 23, and 24. The plurality of memory dies 21, 22, 23, and 24 are stacked in a direction perpendicular to the upper surface of the base insulating layer 120 (for example, the third direction DR3). For example, each of the plurality of memory dies 21, 22, 23, and 24 is a DRAM (dynamic random access memory), but is not necessarily limited to this.

[0038] In one embodiment, the high-bandwidth memory 20 includes a memory die but does not include a buffer die. That is, the high-bandwidth memory 20 in one embodiment is a bufferless HBM. Since the high-bandwidth memory 20 is electrically connected to the logic die 10, the logic die 10 can be used as a buffer die without including another buffer die.

[0039] Multiple memory through-vias 205 are provided that penetrate multiple memory dies 21, 22, 23, and 24. The memory through-vias 205 penetrate multiple memory dies 21, 22, 23, and 24 and extend in a third direction DR3. Signals are transmitted between the multiple memory dies 21, 22, 23, and 24, and between the multiple memory dies 21, 22, 23, and 24 and the logic die 10 via the memory through-vias 205. The memory through-vias 205 allow multiple memory dies 21, 22, 23, and 24 to transmit data simultaneously, thereby improving bandwidth. The memory through-vias 205 shorten the signal transmission distance, thereby reducing power consumption.

[0040] Multiple memory dies 21, 22, 23, and 24 are connected via multiple solder bumps and molded by a molding member. For example, the MR (mass reflow)-MUF (molded underfill) method can be used, but is not limited to this, in which the memory dies are bonded by melting the solder via a reflow process before molding, and then underfilling and molding are performed in one step. As another example, the TC (thermo compression)-NCF method can also be used, in which a non-conductive film (NCF) is inserted between the memory dies, then heat and pressure are applied to bond them, and then molding is performed.

[0041] The optical structure 30 is located on the upper surface of the base insulating layer 120 and on the upper surfaces of the plurality of fourth connection pads 128. The optical structure 30 is electrically connected to some of the plurality of fourth connection pads 128 which are connected to the insulating layer through via 125. The optical structure 30 is electrically connected to the insulating layer through via 125 via the fourth connection pads 128. A plurality of fifth connection pads 322 are located on the lower surface of the optical structure 30. A first insulating layer 324 is located between the plurality of fifth connection pads 322. Each side of the plurality of fifth connection pads 322 is surrounded by the first insulating layer 324. The plurality of fifth connection pads 322 are separated by the first insulating layer 324. The lower surfaces of the fifth connection pads 322 are in contact with the upper surfaces of the fourth connection pads 128, and the lower surface of the first insulating layer 324 is in contact with the upper surface of the base insulating layer 120.

[0042] The fifth connecting pad 322 contains a conductive material. For example, the fifth connecting pad 322 contains a metal such as copper or aluminum, or an alloy thereof. The first insulating layer 324 contains an insulating material. For example, the first insulating layer 324 contains, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0043] In other words, the optical structure 30 is bonded to the base insulating layer 120 using the HCB (hybrid copperbonding) method, but is not necessarily limited to this. The method by which the optical structure 30 is bonded to the base insulating layer 120 can be changed in various ways.

[0044] The optical structure 30 on the plane is located on the edge of the base insulating layer 120. The optical structure 30 overlaps with at least a portion of the logic die 10 in the third direction DR3. The optical structure 30 on the plane is located on the edge of the logic die 10. The optical structure 30 overlaps with a plurality of insulating layer through vias 125 in the third direction DR3.

[0045] The optical structure 30 is positioned along a direction aligned with the upper surface of the high-bandwidth memory 20 and the base insulating layer 120 (e.g., a first direction DR1 or a second direction DR2). The optical structure 30 is positioned along a direction perpendicular to the upper surface of the logic die 10 and the base insulating layer 120 (e.g., a third direction DR3). The optical structure 30 is connected to the logic die 10 in a direction perpendicular to the upper surface of the logic die 10 (e.g., a third direction DR3). For example, the optical structure 30 is connected to the logic die 10 via a fourth connection pad 128, a connecting via 127, and a third connection pad 124, but is not limited to these. This shortens the signal transmission path between the optical structure 30 and the logic die 10, enabling high-speed communication and reducing signal loss, compared to the comparative example where the optical structure 30 is positioned along a direction aligned with the first surface of the logic die 10 and the substrate 110.

[0046] The optical structure 30 is separated from the first surface of the substrate 110 by the base insulating layer 120. The optical structure 30 is connected to the substrate 110 in a direction perpendicular to the first surface of the substrate 110 (e.g., a third direction DR3) via insulating layer through vias 125. For example, the optical structure 30 is connected to the substrate 110 via a fourth connecting pad 128, a connecting via 127, an insulating layer through via 125, a second connecting pad 122, a first connecting member 121, and a first connecting pad 118, but is not limited to these.

[0047] The device comprises multiple optical structures 30, which are arranged on the upper surface of the base insulating layer 120, flanking the high-bandwidth memory 20. As shown in the figure, the multiple optical structures 30 are arranged on both sides of the high-bandwidth memory 20, but are not limited to this arrangement.

[0048] The optical structure 30 includes a photonic integrated circuit 32 and an electronic integrated circuit 34. The photonic integrated circuit 32 is located on the upper surface of the base insulating layer 120. The photonic integrated circuit 32 is located on a plurality of fourth connection pads 128. The electronic integrated circuit 34 is located on at least a portion of the upper surface of the photonic integrated circuit 32. In one embodiment, the photonic integrated circuit 32 and the electronic integrated circuit 34 overlap with the logic die 10 in the third direction DR3. The photonic integrated circuit 32 and the electronic integrated circuit 34 overlap with the edge of the logic die 10 in the third direction DR3. The photonic integrated circuit 32 is located on the upper surface of the base insulating layer 120 in the region that overlaps with the edge of the logic die 10 in the third direction DR3. The electronic integrated circuit 34 is located on the upper surface of the photonic integrated circuit 32 in the region that overlaps with the edge of the logic die 10 in the third direction DR3.

[0049] The lower surface of the optical structure 30 is the lower surface of the photon integrated circuit 320. The lower surface of the photon integrated circuit 32 has the aforementioned plurality of fifth connection pads 322 and the first insulating layer 324 surrounding the plurality of fifth connection pads 322. The photon integrated circuit 32 is electrically connected to the logic die 10 and the insulating layer through-via 125 via the plurality of fifth connection pads 322. The photon integrated circuit 32 is electrically connected to the substrate 110 via the insulating layer through-via 125.

[0050] Multiple sixth connection pads 326 are located on the upper surface of the photon integrated circuit 32. A second insulating layer 328 is located between the multiple sixth connection pads 326. Each side of the multiple sixth connection pads 326 is surrounded by the second insulating layer 328. The multiple sixth connection pads 326 are separated by the second insulating layer 328.

[0051] Multiple seventh connection pads 342 are located on the lower surface of the electronic integrated circuit 34. A third insulating layer 344 is located between the multiple seventh connection pads 342. Each side of the multiple seventh connection pads 342 is surrounded by the third insulating layer 344. The multiple seventh connection pads 342 are separated by the third insulating layer 344. The lower surface of the seventh connection pad 342 is in contact with the upper surface of the sixth connection pad 326, and the lower surface of the third insulating layer 344 is in contact with the upper surface of the second insulating layer 328.

[0052] Each of the sixth connecting pad 326 and the seventh connecting pad 342 contains a conductive material. For example, each of the sixth connecting pad 326 and the seventh connecting pad 342 contains a metal such as copper or aluminum, or an alloy thereof. Each of the second insulating layer 328 and the third insulating layer 344 contains an insulating material. For example, each of the second insulating layer 328 and the third insulating layer 344 contains, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0053] In other words, the electronic integrated circuit 34 is bonded to the photon integrated circuit 32 using the HCB method, but is not necessarily limited to this. The method of bonding the electronic integrated circuit 34 to the photon integrated circuit 32 can be changed in various ways.

[0054] As described above, the photon integrated circuit 32 and the electronic integrated circuit 34 are electrically connected by bonding.

[0055] For example, the photon integrated circuit 32 converts the optical signal received from the optical fiber 42 into an electrical signal and transmits it to the electronic integrated circuit 34. The electronic integrated circuit 34 converts or amplifies the electrical signal received from the photon integrated circuit 32 and transmits it to the logic die 10. The electronic integrated circuit 34 transmits the electrical signal received from the logic die 10 to the photon integrated circuit 32. The photon integrated circuit 32 converts and modulates the electrical signal received from the electronic integrated circuit 34 into an optical signal and transmits it to the optical fiber 42. This will be explained in more detail with reference to Figures 3 and 4.

[0056] The photon integrated circuit 32 is provided with a photonic layer through-via 325 that penetrates the photon integrated circuit 32. The photon layer through-via 325 extends through the photon integrated circuit 32 in a third direction DR3. The photon layer through-via 325 is connected between a fifth connection pad 322 and a sixth connection pad 326. The electronic integrated circuit 34 is electrically connected to the logic die 10 and an insulating layer through-via 125 via the photon layer through-via 325 and the insulating layer through-via 125. The electronic integrated circuit 34 is electrically connected to the substrate 110 via the photon layer through-via 325 and the insulating layer through-via 125.

[0057] Although Figure 2 shows one through-photon layer via 325, the design is not limited to this and may include multiple through-photon layer vias 325.

[0058] The photon layer via 325 contains a conductive material. For example, the photon layer via 325 contains a metal such as copper or aluminum, or an alloy thereof.

[0059] The photon integrated circuit 32 includes a grating coupler 455 that is optically connected to the optical fiber. The grating coupler 455 plays a role in transmitting optical signals received through the optical fiber in other directions. For example, the grating coupler 455 transmits optical signals received perpendicular to the top surface of the photon integrated circuit 32 in a horizontal direction parallel to the top surface of the photon integrated circuit 32. The grating coupler 455 transmits optical signals generated by the photon integrated circuit 32 to the optical fiber.

[0060] The grid coupler 455 is covered by a second insulating layer 328. In Figure 2, the second insulating layer 328 is shown covering the sides of the grid coupler 455, but is not limited to this, and the second insulating layer 328 may further cover the top surface of the grid coupler 455. In embodiments in which the second insulating layer 328 covers the top surface of the grid coupler 455, the second insulating layer 328 comprises a light-transmitting material. For example, the second insulating layer 328 comprises silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0061] The grid coupler 455 does not overlap with the electronic integrated circuit 34 in the third direction DR3. That is, the electronic integrated circuit 34 is not located between the grid coupler 455 and the optical connector 40 in the third direction DR3.

[0062] In one embodiment, the optical structure 30 includes a light-transmitting insulating layer 36 located on the upper surface of the photon integrated circuit 32 and on the side surface of the electronic integrated circuit 34. In one embodiment, the electronic integrated circuit 34 is located on a portion of the upper surface of the photon integrated circuit 32. The light-transmitting insulating layer 36 is located on another portion of the upper surface of the photon integrated circuit 32. The light-transmitting insulating layer 36 covers the upper surface of the lattice coupler 455 and the upper surface of the second insulating layer 328. The light-transmitting insulating layer 36 contains a light-transmitting material. For example, the light-transmitting insulating layer 36 contains silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The light-transmitting insulating layer 36 consists of a single layer or multiple layers.

[0063] As shown in Figure 2, the light-transmitting insulating layer 36 is in contact with the upper surface of the second insulating layer 328. In one embodiment, the light-transmitting insulating layer 36 and the second insulating layer 328 may contain the same material. When the light-transmitting insulating layer 36 and the second insulating layer 328 contain the same material, the interface between the light-transmitting insulating layer 36 and the second insulating layer 328 is not distinguishable.

[0064] In Figure 2, the upper surface of the light-transmitting insulating layer 36 is shown to be at substantially the same level as the upper surface of the electronic integrated circuit 34, but this is not limited to this. For example, the light-transmitting insulating layer 36 may be located further above the upper surface of the electronic integrated circuit 34.

[0065] In one embodiment, the optical structure 30 includes a cover layer 38 on the upper surface of the electronic integrated circuit 34. The cover layer 38 covers the upper surface of the photon integrated circuit 32 and the upper surface of the electronic integrated circuit 34. The cover layer 38 is in contact with the upper surface of the electronic integrated circuit 34. The cover layer 38 is separated from the upper surface of the photon integrated circuit 32 in a third direction DR3. A light-transmitting insulating layer 36 is located between the cover layer 38 and the photon integrated circuit 32 in the third direction DR3. The cover layer 38 is located on the upper surface of the light-transmitting insulating layer 36. The cover layer 38 is in contact with the upper surface of the light-transmitting insulating layer 36.

[0066] The cover layer 38 contains a light-transmitting material. For example, the cover layer 38 may contain, but is not limited to, glass or silicon (Si).

[0067] The optical connector 40 is located on the upper surface of the cover layer 38. The optical connector 40 includes an optical fiber 42. In Figure 2, for convenience, the optical connector 40 is shown to include one optical fiber 42, but the optical connector 40 can include multiple optical fibers 42, and the multiple optical fibers 42 may be provided in an array configuration. The cover layer 38 is located between the end of the optical fiber 42 of the optical connector 40 and the upper surface of the photon integrated circuit 32. The cover layer 38 protects the photon integrated circuit 32 and the electronic integrated circuit 34 while allowing light to pass between the optical connector 40 and the photon integrated circuit 32.

[0068] The optical connector 40 is positioned such that the end of the optical fiber 42 faces the upper surface of the cover layer 38. The end of the optical fiber 42 is separated from the upper surface of the cover layer 38. An air gap is located between the end of the optical fiber 42 and the upper surface of the cover layer 38.

[0069] Although not shown in the diagram, the optical connector 40 is fastened through a hole in the frame covering the semiconductor package 100. For example, the optical connector 40 and the hole are coupled to each other in a male-female structure.

[0070] Multiple optical connectors 40 are provided, and each of the multiple optical connectors 40 is connected between the multiple optical structures 30 and the external device 1000. One end of each optical fiber 42 of the multiple optical connectors 40 is optically connected to each of the multiple optical structures 30, and the other end of each optical fiber 42 of the multiple optical connectors 40 is optically connected to the external device 1000.

[0071] The semiconductor package 100 includes a first molding member 190 for molding the high-bandwidth memory 20 and the optical structure 30 onto the upper surface of the base insulating layer 120. The first molding member 190 covers the upper and side surfaces of the high-bandwidth memory 20. The first molding member 190 covers the side surfaces of the optical structure 30. The first molding member 190 does not cover the upper surface of the optical structure 30. That is, the upper surface of the cover layer 38 is not covered by the first molding member 190 and is exposed. The upper surface of the first molding member 190 is at substantially the same level as the upper surface of the cover layer 38. The first molding member 190 includes, for example, an epoxy molding compound (EMC), but is not necessarily limited thereto.

[0072] The semiconductor package 100 is not limited to the components described above, but may further include other components. According to the embodiment, the semiconductor package 100 may include a front redistribution layer between the lower surface of the logic die 10 and the upper surface of the substrate 110, or a back redistribution layer between the upper surface of the logic die 10 and the lower surface of the high-bandwidth memory 20 and the lower surface of the optical structure 30, or it may include both a front redistribution layer and a back redistribution layer.

[0073] The optical and electronic components of the optical structure 30 shown in Figures 1 and 2 will be described below with reference to Figures 3 and 4.

[0074] Figure 3 is a schematic block diagram showing the components of an optical structure according to one embodiment. Figure 4 is a schematic cross-sectional view showing a photon integrated circuit according to one embodiment.

[0075] In one embodiment, the photon integrated circuit 32 includes optical components, and the electronic integrated circuit 34 includes electronic components. The electronic components of the electronic integrated circuit 34 consist of a transistor array, and the optical components of the photon integrated circuit 32 include a part of the transistor array.

[0076] For example, the photon integrated circuit 32 includes, but is not limited to, a multiplexer (MUX) 310, multiple optical modulators 315, a demultiplexer (DEMUX) 350, and multiple photodetectors 355, and may further include other components. For example, the electronic integrated circuit 34 includes, but is not limited to, a current-to-voltage converter 360, an output driver 370, an input buffer 330, a modulator driver 320, and a controller 340, and may further include other components. The current-to-voltage converter 360, the output driver 370, the input buffer 330, the modulator driver 320, and the controller 340 are classified according to the function each component performs. This is not necessarily the same as a physical distinction.

[0077] The optical connector 40 is an input / output port for optical signals between the optical fiber 42, which is connected to an external device, and the semiconductor package 100. The following describes each component separately for cases where an optical signal is received via the optical fiber 42 and cases where an optical signal is transmitted.

[0078] Referring to Figure 3, the optical signal received via the optical connector 40 reaches multiple photodetectors 355 via the demultiplexer 350. The photodetectors 355 convert the optical signal into an analog electrical signal. The current-to-voltage converter 360 converts the current signal output from the photodetectors 355 into a voltage signal. For example, the current-to-voltage converter amplifies the current output of the photodetectors 355 or other types of sensors of the photon integrated circuit 32 into a usable voltage. The converted electrical signal is output to the outside of the optical structure 30 (e.g., the logic die 10) via the output driver 370.

[0079] When an electrical signal is received by the input buffer 330, the light source element emits light based on the received electrical signal, and the modulator driver 320 drives multiple optical modulators 315 to modulate the light emitted from the light source element. The electronic components operate under the control of the controller 340. The modulated light is transmitted to the optical connector 40 via the multiplexer 310, and the optical signal is transmitted via the optical fiber 42 connected to the optical connector 40.

[0080] Referring to Figure 4, the photon integrated circuit 32 includes a buried oxide layer (BOX) 400, a silicon layer 410 located on the buried oxide layer 400, and a clad layer 420 located on the silicon layer 410.

[0081] The embedded oxide layer 400 is located on a silicon-based member. The embedded oxide layer 400 is formed over the entire upper surface of the silicon-based member, or on only a portion thereof.

[0082] The silicon layer 410 is located on the embedded oxide layer 400. The silicon layer 410 includes optical components. In one embodiment, the silicon layer 410 includes an optical waveguide 450, a grating coupler 455, an optical modulator 460, and a photodetector 465.

[0083] For example, a silicon material layer is formed on an embedded oxide layer 400, and the silicon material layer is patterned through a lithography process and an etching process to form a silicon layer 410. The patterned silicon layer 410 contains optical components. A cladding layer 420 is laminated on the patterned silicon layer 410. Although not shown, a nitride layer may be further located on the patterned silicon layer 410.

[0084] The waveguide member 450 is optically connected to other optical components. The waveguide member 450 provides an optical path that confines and transmits light within the photon integrated circuit 32. The waveguide member 450 consists of a single structure or multiple structures. For example, the waveguide member 450 includes optical fibers, silicon waveguide members, silicon nitride waveguide members, and the like.

[0085] The lattice coupler 455 is a medium for receiving optical signals transmitted from an external device via the optical fiber 42, and for transmitting optical signals to an external device via the optical fiber 42. In one embodiment, the photon integrated circuit 32 uses the lattice coupler 455 as a medium for transmitting and receiving optical signals, but it is easily understood by an ordinary engineer that an edge coupler can also be used as a medium for transmitting and receiving optical signals of the photon integrated circuit 32. When the lattice coupler 455 is used, the optical signals are transmitted and received vertically via the top surface of the photon integrated circuit 32, and when the edge coupler is used, the optical signals are transmitted and received horizontally via the side (or edge) of the photon integrated circuit 32.

[0086] The optical modulator 460 modulates the light emitted from the light source element with the signal to be transmitted, converting it into an optical signal containing information. The optical modulator 460 is, for example, a phase modulator. In some embodiments, the optical modulator 460 is, but is not limited to, one of the following: a Mach-Zehnder modulator, a micro-ring modulator, an electro-absorption modulator, and an LN / Si hybrid or TFLN (thin-film lithium niobate) modulator.

[0087] The photodetector 465 generates and outputs an electrical signal from the received optical signal. The photodetector 465 is, for example, a PIN (positive-intrinsinc-negative) structure including a germanium (Ge) region. Although not shown, the photon integrated circuit 32 may further include a ring resonator. The ring resonator is an element that filters signals of a desired wavelength in the optical signal transmitted through the waveguide member 450.

[0088] The embodiments are not limited to the optical components described above, and the photon integrated circuit 32 may further include switches, splitters, heaters, and the like, in addition to the components described above.

[0089] Optical components are classified into passive and active components. Waveguide members 450 and grid couplers 455 belong to passive components, while optical modulators 460 and photodetectors 465 belong to active components. Active components are electrically connected to contact terminals 470 and 475 that penetrate the cladding layer 420 and are exposed on the upper surface in order to electrically connect them to electronic components. The multiple sixth connection pads 326 in Figure 2 represent the connection pads of the contact terminals 470 and 475 that are exposed on the upper surface of the cladding layer 420. The second insulating layer 328 in Figure 2 represents a portion of the cladding layer 420. Various structures are used for electrically connecting the active components to the electronic components of the electronic integrated circuit 34, and are not limited to the structures of the contact terminals 470 and 475 shown in Figure 4.

[0090] Figure 4 only shows a schematic structure of an optical component as an example, and the optical component is not limited to the structure shown in Figure 4.

[0091] A semiconductor package 100 according to one embodiment includes a base insulating layer 120 covering the side and top surfaces of the logic die 10, insulating layer through-vias 125 that penetrate the base insulating layer 120 located on both sides of the logic die 10, a high-bandwidth memory 20 located on the top surface of the base insulating layer 120, and an optical structure 30. The high-bandwidth memory 20 and the optical structure 30 are connected to the logic die 10 and the top surface of the logic die 10 in a direction perpendicular to the logic die 10. As a result, the signal transmission path between the optical structure 30 and the logic die 10 is shorter than in a comparative example where the optical structure 30 is arranged along the direction aligned with the first surface on the first surface of the substrate 110, enabling high-speed communication and reducing signal loss.

[0092] In one embodiment, the optical structure 30 of the semiconductor package 100 overlaps the logic die 10 on a plane. As a result, the size of the semiconductor package 100 is reduced compared to the comparative example in which the optical structure 30 is arranged on the first surface of the logic die 10 and the substrate 110, along the direction aligned with the first surface.

[0093] The following describes modified examples of the semiconductor package 100 shown in Figures 1 to 4, with reference to Figures 5 and 6, respectively.

[0094] Figures 5 and 6 are cross-sectional views of a semiconductor package according to one embodiment, respectively. The embodiments shown in Figure 5 and Figure 6 correspond to the same parts as the embodiments shown in Figures 1 to 4, so their explanation will be omitted, and the differences will be explained in detail. In addition, the same reference numerals will be used for the same components as in the previous embodiments. In the embodiment shown in Figure 5, the molding structure of the optical structure 30 differs in part from that of the previous embodiment. In the embodiment shown in Figure 5, the bonding structure of the optical structure 30 differs in part from that of the previous embodiment.

[0095] Referring to Figure 5, the semiconductor package 100 further includes a second molding member 192 positioned between the side surface of the optical structure 30 and the first molding member 190. The second molding member 192 covers the side surface of the optical structure 30. The second molding member 192 does not cover the top surface of the optical structure 30. The top surface of the second molding member 192 is at substantially the same level as the top surface of the optical structure 30. The top surface of the second molding member 192 is at substantially the same level as the top surface of the cover layer 38.

[0096] The first molding member 190 covers the top and sides of the high-bandwidth memory 20 and the sides of the second molding member 192. The first molding member 190 is separated from the sides of the optical structure 30 by the second molding member 192. The first molding member 190 does not cover the top surface of the second molding member 192 or the top surface of the optical structure 30. The top surface of the first molding member 190 is at substantially the same level as the top surface of the second molding member 192 and the top surface of the optical structure 30. The top surface of the first molding member 190 is at substantially the same level as the top surface of the cover layer 38.

[0097] In one embodiment, the optical structure 30 is first molded with a second molding member 192, and then molded together with the high-bandwidth memory 20 with a first molding member 190. In other words, the optical structure 30 is double-molded.

[0098] The second molding member 192 contains the same material as the first molding member 190, or a different material from the first molding member 190. For example, the second molding member 192 contains, but is not limited to, EMC.

[0099] Referring to Figure 6, the semiconductor package 100 includes a first underfill member 323 located between the lower surface of the optical structure 30 and the upper surface of the base insulating layer 120. In the embodiment of Figure 6, the bonding method of the optical structure 30 differs from that of the embodiments of Figures 1 to 4, resulting in the addition of the first underfill member 323.

[0100] In the embodiments shown in Figures 1 to 4, multiple fifth connection pads 322 are in contact with multiple fourth connection pads 128, and the first insulating layer 324 is in contact with the base insulating layer 120. That is, the optical structure 30 is bonded to the base insulating layer 120 using the HCB method. In contrast, in the embodiment shown in Figure 6, multiple fifth connection pads 322 are electrically connected to multiple fourth connection pads 128 by multiple second connection members 321. The multiple second connection members 321 are, for example, solder bumps. That is, the optical structure 30 is bonded to the base insulating layer 120 using solder bumps.

[0101] In one embodiment, the semiconductor package 100 includes a plurality of second connecting members 321, each located on the lower surface of a plurality of fifth connecting pads 322. The first underfill member 323 surrounds the sides of the plurality of fifth connecting pads 322 and the sides of the plurality of second connecting members 321. The first underfill member 323 fills the remaining space between the lower surface of the photon integrated circuit 32 and the upper surface of the base insulating layer 120. The first underfill member 323 fills the space between the plurality of second connecting members 321. The first underfill member 323 prevents adjacent second connecting members 321 from short-circuiting.

[0102] In one embodiment, the semiconductor package 100 includes a plurality of third connecting members 341, each located on the lower surface of a plurality of seventh connecting pads 342. The plurality of seventh connecting pads 342 are electrically connected to a plurality of sixth connecting pads 326 by the plurality of third connecting members 341. The plurality of third connecting members 341 are, for example, solder bumps. That is, the electronic integrated circuit 34 is bonded to the photon integrated circuit 32 using solder bumps.

[0103] In one embodiment, the semiconductor package 100 includes a second underfill member 343 located between the lower surface of the electronic integrated circuit 34 and the upper surface of the photon integrated circuit 32. The second underfill member 343 surrounds the sides of a plurality of seventh connection pads 342 and the sides of a plurality of third connection members 341. The second underfill member 343 fills the remaining space between the lower surface of the electronic integrated circuit 34 and the upper surface of the photon integrated circuit 32. The second underfill member 343 fills the space between a plurality of third connection members 341. The second underfill member 343 prevents adjacent third connection members 341 from short-circuiting.

[0104] In Figure 6, bonding is shown to occur at all solder bumps between the electronic integrated circuit 34 and the photon integrated circuit 32, and between the photon integrated circuit 32 and the base insulating layer 120, but this is not necessarily the case. For example, bonding may be performed in different ways, such as bonding between the electronic integrated circuit 34 and the photon integrated circuit 32 as an HCB, and bonding between the photon integrated circuit 32 and the base insulating layer 120 as solder bumps.

[0105] The following describes modified examples of the semiconductor package 100 shown in Figures 1 to 4, with reference to Figure 7.

[0106] Figure 7 is a cross-sectional view of a semiconductor package according to one embodiment. The embodiment shown in Figure 7 corresponds to the same parts as the embodiments shown in Figures 1 to 4, so the explanation of those parts will be omitted, and the differences will be explained in detail. Also, the same reference numerals will be used for the same components as in the previous embodiments. The embodiment shown in Figure 7 differs from the previous embodiments in that a heat conduction block 50 has been added.

[0107] Referring to Figure 7, the semiconductor package 100 further includes a thermal conductive pad 52 located on the upper surface of the base insulating layer 120, and a thermal conductive block 50 located on the thermal conductive pad 52 and positioned in a direction aligned with the optical structure 30 and the upper surface of the base insulating layer 120. The thermal conductive pad 52 is connected to the insulating layer through via 125 and the logic die 10. The lower surface of the thermal conductive block 50 is in contact with the upper surface of the thermal conductive pad 52. The upper surface of the thermal conductive block 50 is not covered by the first molding member 190 and is exposed. The thermal conductive pad 52 and the thermal conductive block 50 play a role in releasing or dispersing heat generated from the logic die 10 and the substrate 110 to the outside.

[0108] In one embodiment, the thermal conductive pad 52 overlaps the insulating layer through via 125 and the logic die 10 in a direction perpendicular to the upper surface of the base insulating layer 120 (e.g., a third direction DR3). The thermal conductive pad 52 is connected to the insulating layer through via 125 and the logic die 10 in the third direction DR3. This reduces the distance between the substrate 110 and the logic die 10 and the thermal conductive pad 52, allowing heat to be transferred to the thermal conductive block 50 more quickly and improving heat dissipation performance.

[0109] The thermal conductive pad 52 includes a thermal interface material (TIM). For example, the thermal interface material (TIM) includes, but is not limited to, a metal with high thermal conductivity such as copper or aluminum.

[0110] The heat conduction block 50 contains a material with high thermal conductivity. The heat conduction block 50 includes, for example, a metal such as copper or aluminum, or a ceramic, but is not limited to these.

[0111] The following describes modified examples of the semiconductor package 100 shown in Figures 1 to 4, with reference to Figure 8.

[0112] Figure 8 is a cross-sectional view of a semiconductor package according to one embodiment. The embodiment shown in Figure 8 corresponds to the same parts as the embodiments shown in Figures 1 to 4, so the explanation of those parts will be omitted, and the differences will be explained in detail. Also, the same reference numerals will be used for the same components as in the previous embodiments. In the embodiment shown in Figure 8, the configuration of the optical structure 30 differs in part from that of the previous embodiments.

[0113] Referring to Figure 8, the optical structure 30 includes an optoelectronic integrated circuit 33 located on the upper surface of the base insulating layer 120, a cover layer 38 covering the upper surface of the optoelectronic integrated circuit 33, and a light-transmitting insulating layer 36 located between the optoelectronic integrated circuit 33 and the cover layer 38. The cover layer 38 and the light-transmitting insulating layer 36 contain a light-transmitting material.

[0114] In the embodiments shown in Figures 1 to 4, the photon integrated circuit 32 and the electronic integrated circuit 34 are functionally and structurally separated. In contrast, in the embodiment shown in Figure 8, the photon integrated circuit 32 and the electronic integrated circuit 34 from the embodiments shown in Figures 1 to 4 are functionally and structurally integrated to form an optoelectronic integrated circuit 33. The optoelectronic integrated circuit 33 converts the optical signal received from the optical fiber 42 into an electrical signal and transmits it to the logic die 10, and converts the electrical signal received from the logic die 10 into an optical signal and transmits it to the optical fiber 42. The optoelectronic integrated circuit 33 includes a lattice coupler 455 that is optically connected to the optical fiber 42. The optoelectronic integrated circuit 33 receives signals received via the optical fiber 42 via the lattice coupler 455 and transmits the optical signal generated by the optoelectronic integrated circuit 33 to the optical fiber 42 via the lattice coupler 455.

[0115] In the embodiments shown in Figures 1 to 4, the electronic integrated circuit 34 covers a portion of the upper surface of the photon integrated circuit 32, so the light-transmitting insulating layer 36 covers only the remaining portion of the photon integrated circuit 32. Conversely, in the embodiment shown in Figure 8, the light-transmitting insulating layer 36 covers the entire upper surface of the optoelectronic integrated circuit 33.

[0116] The following describes modified examples of the semiconductor package 100 shown in Figures 1 to 4, with reference to Figure 9.

[0117] Figure 9 is a cross-sectional view of a semiconductor package according to one embodiment. The embodiment shown in Figure 9 corresponds to the same parts as the embodiments shown in Figures 1 to 4, so the explanation of those parts will be omitted, and the differences will be explained in detail. Also, the same reference numerals will be used for the same components as in the previous embodiments. In the embodiment shown in Figure 9, the configuration of the high-bandwidth memory 20 differs in part from that of the previous embodiments.

[0118] Referring to Figure 9, the high-bandwidth memory 20 further includes a base die 25 beneath the multiple memory dies 21, 22, 23, and 24. The base die 25 has a larger planar area than the multiple memory dies 21, 22, 23, and 24. The base die 25 serves to support the multiple memory dies 21, 22, 23, and 24. The multiple memory dies 21, 22, 23, and 24 are stacked on the top surface of the base die 25. The multiple memory dies 21, 22, 23, and 24 are molded onto the top surface of the base die 25. The molding material of the high-bandwidth memory 20 covers the top and side surfaces of the multiple memory dies 21, 22, 23, and 24, and the top surface of the base die 25. The side surfaces of the base die 25 are not covered by the molding material of the high-bandwidth memory 20.

[0119] In one embodiment, the base die 25 is a different type of die from the multiple memory dies 21, 22, 23, and 24. For example, the base die 25 is an FPGA (field programmable gatearray) die. For example, the FPGA die includes arithmetic circuits and performs arithmetic or logical operations on data read from the multiple memory dies 21, 22, 23, and 24. In this case, the high-bandwidth memory 20 can perform some of the data processing within the memory without communicating with the logic die 10. The high-bandwidth memory 20 supports PIM (processing in memory).

[0120] As another example, the base die 25 is a cache memory die. The cache memory die has a faster data access speed than the multiple memory dies 21, 22, 23, and 24. The cache memory die stores data that is frequently used by the logic die 10. The cache memory die acts as a buffer between the logic die 10 and the multiple memory dies 21, 22, 23, and 24. For example, each of the multiple memory dies 21, 22, 23, and 24 is a dynamic random access memory (DRAM) die, and the base die 25 is a static random access memory (SRAM) die.

[0121] The following describes modified examples of the semiconductor package 100 shown in Figures 1 to 4, with reference to Figures 10 to 12.

[0122] Figure 10 is a plan view of a semiconductor package according to one embodiment. Figures 11 and 12 are cross-sectional views of the semiconductor package according to each embodiment, taken along the line B-B' in Figure 10. The embodiments shown in Figures 10 to 12 include the same parts as the embodiments shown in Figures 1 to 4, so their explanation will be omitted, and the differences will be explained. Also, the same reference numerals will be used for the same components as in the previous embodiments. The embodiments shown in Figures 10 to 12 differ from the previous embodiments in that they include multiple chiplets CL1, CL2, CL3, and CL4 having the structure of the embodiments shown in Figures 1 to 4.

[0123] First, referring to Figures 10 and 11, the semiconductor package 100 includes a substrate 110 and a plurality of chiplets CL1, CL2, CL3, and CL4 mounted on the substrate 110. In one embodiment, each of the plurality of chiplets CL1, CL2, CL3, and CL4 includes the same components and has the same structure as the semiconductor package 100 in the embodiments of Figures 1 to 4. Each of the plurality of chiplets CL1, CL2, CL3, and CL4 includes a logic die 10 located on the first surface of the substrate 110, a base insulating layer 120 located on the side and top surfaces of the logic die 10, insulating layer through-vias 125 penetrating the base insulating layer 120 on both sides of the logic die 10, a high-bandwidth memory 20 located on the top surface of the base insulating layer 120, an optical structure 30, and an optical connector 40 including an optical fiber 42 for transmitting optical signals between the optical structure 30 and an external device. The high-bandwidth memory 20 includes a plurality of memory dies 21, 22, 23, and 24 stacked perpendicularly to the upper surface of the base insulating layer 120. The optical structure 30 is connected to the logic die 10 and perpendicularly to the upper surface of the logic die 10.

[0124] In the embodiments shown in Figures 1 to 4, one module is shown in which a high-bandwidth memory 20, including multiple memory dies 21, 22, 23, and 24, is vertically stacked on a logic die 10, but the embodiment is not limited to this. As in the embodiments shown in Figures 10 and 11, the semiconductor package 100 includes multiple modules in which a high-bandwidth memory 20, including multiple memory dies 21, 22, 23, and 24, is vertically stacked on a logic die 10. In this case, each of the multiple modules is called a chiplet. Each logic die 10 of the multiple chiplets CL1, CL2, CL3, and CL4 may include different functions from the various functions of the logic die 10 in the embodiments of Figures 1 to 4. That is, the various functions of the logic die 10 in the embodiments of Figures 1 to 4 can be divided and possessed by the multiple chiplets CL1, CL2, CL3, and CL4. As a result, each logic die 10 of the multiple chiplets CL1, CL2, CL3, and CL4 is smaller in size than the logic die 10 in the embodiments of Figures 1 to 4.

[0125] In one embodiment, the semiconductor package 100 further includes a bridge layer 115 embedded on top of the substrate 110. Multiple chiplets CL1, CL2, CL3, and CL4 are connected by the bridge layer 115. The bridge layer 115 is located between the multiple chiplets CL1, CL2, CL3, and CL4 on a plane. The bridge layer 115 includes, for example, silicon and includes wiring patterned on the silicon layer. The bridge layer 115 electrically connects the multiple chiplets CL1, CL2, CL3, and CL4 to one another. Each logic die 10 of the multiple chiplets CL1, CL2, CL3, and CL4 communicates via the bridge layer 115. Each logic die 10 of the multiple chiplets CL1, CL2, CL3, and CL4 can access high-bandwidth memory 20 contained in different chiplets via the bridge layer 115.

[0126] Figure 11 shows one bridge layer 115, but is not limited to this. Multiple bridge layers 115 can be embedded in the substrate 110. For example, multiple bridge layers 115 are each located between two adjacent chiplets from among multiple chiplets CL1, CL2, CL3, and CL4.

[0127] The embodiment in Figure 12 is the same as the embodiment in Figure 11 in that it includes multiple chiplets CL1, CL2, CL3, and CL4, but the method of connecting some of the multiple chiplets CL1, CL2, CL3, and CL4 is different.

[0128] Referring to Figures 10 and 12, the semiconductor package 100 further includes a redistribution layer 130 located between the substrate 110 and the logic dies 10 of the plurality of chiplets CL1, CL2, CL3, and CL4. In one embodiment, the plurality of chiplets CL1, CL2, CL3, and CL4 are connected by the redistribution layer 130. The redistribution layer 130 includes redistributions 132, redistribution vias 134 connecting the redistributions 132 in a direction perpendicular to the first surface of the substrate 110 (e.g., a third direction DR3), and a redistribution insulating layer 136 surrounding the redistributions 132 and the redistribution vias 134. A plurality of second connection pads 122 located on the lower surface of each of the plurality of chiplets CL1, CL2, CL3, and CL4 are connected to the redistributions 132 of the uppermost layer of the redistribution layer 130 by a plurality of first connection members 121. Multiple chiplets CL1, CL2, CL3, and CL4 are electrically connected to each other by a redistribution layer 130.

[0129] In one embodiment, a plurality of eighth connection pads 142 are located on the lower surface of the redistribution layer 130, and a plurality of fourth connection members 141 are located on the lower surfaces of the plurality of eighth connection pads 142. The plurality of eighth connection pads 142 are connected to a plurality of first connection pads 118 located on the upper surface of the substrate 110 by the plurality of fourth connection members 141. Each of the plurality of chiplets CL1, CL2, CL3, and CL4 is electrically connected to the substrate 110 by the redistribution layer 130.

[0130] The manufacturing method for the semiconductor package 100 shown in Figures 1 to 4 will be described below with reference to Figures 13 to 19.

[0131] Figures 13 to 19 are cross-sectional views showing the manufacturing process of a semiconductor package according to one embodiment.

[0132] Referring to Figure 13, the logic die 10 is provided on the upper surface of the carrier substrate CR. The logic die 10 includes a plurality of logic through-vias 105 that penetrate the logic die 10 in a direction perpendicular to the upper surface of the carrier substrate CR (for example, the third direction DR3). A plurality of third connection pads 124 are located on the upper surface of the logic die 10. The plurality of logic through-vias 105 are connected to the plurality of third connection pads 124.

[0133] Each of the multiple logic through-vias 105 and the multiple third connection pads 124 may include, but is not limited to, a metal such as copper or aluminum.

[0134] Referring to Figure 14, an insulating material is deposited on the carrier substrate CR to form a base insulating layer 120 that covers the side and top surfaces of the logic die 10. The base insulating layer 120 is formed by, but is not limited to, a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. The base insulating layer 120 surrounds the sides of a plurality of third connection pads 124 located on the top surface of the logic die 10.

[0135] The base insulating layer 120 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0136] For example, after depositing an insulating material to cover the upper surfaces of multiple third connection pads 124, the upper surfaces of the multiple third connection pads 124 are exposed through a planarization process. The planarization process includes, for example, a chemical mechanical polishing (CMP) process. The upper surface of the base insulating layer 120 is located at substantially the same level as the upper surfaces of the multiple third connection pads 124.

[0137] Referring to Figure 15, multiple through-holes 125 are formed that penetrate the base insulating layer 120. For example, multiple through-holes are formed through the base insulating layer 120 in a direction perpendicular to the upper surface of the carrier substrate CR (e.g., a third direction DR3) via a photolithography process and an etching process. Subsequently, conductive material is filled into the multiple through-holes to form multiple through-holes 125. The multiple through-holes 125 may, but are not limited to, metals such as copper or aluminum. The multiple through-holes 125 are formed via a plating process or a CVD process, but are not limited to these.

[0138] Multiple insulated layer through vias 125 extend in a third direction DR3, penetrating the base insulated layer 120 on both sides of the logic die 10. The upper surfaces of the multiple insulated layer through vias 125 are at substantially the same level as the upper surfaces of the multiple third connection pads 124.

[0139] Referring to Figure 16, an additional insulating material is deposited to form a base insulating layer 120 that covers the upper surfaces of multiple third connection pads 124 and multiple insulating layer through vias 125. Subsequently, multiple connecting vias 127 and multiple fourth connection pads 128 are formed. For example, after patterning the additionally deposited base insulating layer 120 to form multiple via holes, a conductive material layer is formed to fill the inside of the multiple via holes and cover the upper surface of the base insulating layer 120, and the conductive material layer is patterned to form multiple connecting vias 127 and multiple fourth connection pads 128.

[0140] Each of the multiple connected vias 127 and the multiple fourth connecting pads 128 contains, but is not limited to, a metal such as copper or aluminum. The conductive material layer is formed by, but is not limited to, a plating process or a CVD process. The conductive material layer is patterned by a photolithography process and an etching process.

[0141] Next, an additional insulating material is deposited to form a base insulating layer 120 that covers the sides of the multiple fourth connection pads 128. For example, after additional insulating material is deposited to cover the upper surfaces of the multiple fourth connection pads 128, the upper surfaces of the multiple fourth connection pads 128 are exposed through a planarization process. The upper surface of the base insulating layer 120 is located at substantially the same level as the upper surfaces of the multiple fourth connection pads 128.

[0142] Some of the multiple connecting vias 127 are connected to multiple third connecting pads 124, and other parts are connected to multiple insulating layer through vias 125. Multiple fourth connecting pads 128 are connected to multiple third connecting pads 124 and multiple insulating layer through vias 125 by multiple connecting vias 127. Some of the multiple fourth connecting pads 128 are connected to multiple third connecting pads 124, and other parts are connected to multiple insulating layer through vias 125. Being connected to multiple third connecting pads 124 means being connected to the logic die 10.

[0143] Referring to Figure 17, the high-bandwidth memory 20 and optical structure 30 are bonded to the base insulating layer 120 and a plurality of fourth connection pads 128. For example, the high-bandwidth memory 20 and optical structure 30 are bonded using various methods, such as bonding with solder bumps or bonding without bumps using the HCB method.

[0144] In one embodiment, the high-bandwidth memory 20 and the optical structure 30 overlap with the logic die 10 and the third direction DR3. The high-bandwidth memory 20 overlaps with the center of the logic die 10 and the third direction DR3. The optical structure 30 overlaps with the edge of the logic die 10 and the third direction DR3. The optical structure 30 overlaps with the multiple insulating layer through vias 125 and the third direction DR3.

[0145] In one embodiment, the high-bandwidth memory 20 and the optical structure 30 are connected to the logic die 10 and the third direction DR3. The high-bandwidth memory 20 is connected to the third direction DR3 at the center of the upper surface of the logic die 10. The optical structure 30 is connected to the third direction DR3 at the edge of the upper surface of the logic die 10. The optical structure 30 is connected to the third direction DR3 and a plurality of insulating layer through vias 125.

[0146] According to one embodiment, the signal transmission path between the optical structure 30 and the logic die 10, and the signal transmission path between the high-bandwidth memory 20 and the logic die 10 are shorter than in a comparative example where the high-bandwidth memory 20 and the optical structure 30 are arranged horizontally with respect to the logic die 10 (for example, in the first direction DR1), thereby improving the communication speed of the semiconductor package and reducing signal loss during communication.

[0147] In one embodiment, the optical structure 30 is arranged along a direction (e.g., a first direction DR1 or a second direction DR2) aligned with the upper surface of the high-bandwidth memory 20 and the base insulating layer 120. In one embodiment, a plurality of optical structures 30 are provided, and the plurality of optical structures 30 are arranged along a direction (e.g., a first direction DR1 or a second direction DR2) aligned with the upper surface of the base insulating layer 120. For example, the plurality of optical structures 30 are located on both sides of the high-bandwidth memory 20, but are not limited thereto.

[0148] The high-bandwidth memory 20 includes a plurality of memory dies 21, 22, 23, 24 stacked vertically (e.g., in the third direction DR3). For example, each of the plurality of memory dies 21, 22, 23, 24 is a DRAM (dynamic random access memory, DRAM), but is not necessarily limited to this.

[0149] In one embodiment, the high-bandwidth memory 20 includes a memory die but does not include a buffer die. That is, the high-bandwidth memory 20 in one embodiment is a bufferless HBM. The high-bandwidth memory 20 is electrically connected to the logic die 10, and the logic die 10 is used as a buffer die.

[0150] The high-bandwidth memory 20 includes multiple memory penetration vias 205 that penetrate multiple memory dies 21, 22, 23, and 24. The multiple memory penetration vias 205 shorten the signal transmission path between the multiple memory dies 21, 22, 23, and 24 and the logic die 10, thereby increasing bandwidth.

[0151] In one embodiment, the optical structure 30 includes a photon integrated circuit 32, an electronic integrated circuit 34 located on the photon integrated circuit 32, and a cover layer located on the upper surface of the electronic integrated circuit 34. The photon integrated circuit 32 is located on the upper surface of the base insulating layer 120 and on the upper surfaces of a plurality of fourth connection pads 128. The electronic integrated circuit 34 is located on at least a portion of the upper surface of the photon integrated circuit 32. In one embodiment, the photon integrated circuit 32 and the electronic integrated circuit 34 overlap with the logic die 10 in the third direction DR3. The photon integrated circuit 32 and the electronic integrated circuit 34 overlap with the edge of the logic die 10 in the third direction DR3. The photon integrated circuit 32 is located on the upper surface of the base insulating layer 120 in the region that overlaps with the edge of the logic die 10 in the third direction DR3. The electronic integrated circuit 34 is located on the upper surface of the photon integrated circuit 32 in the region that overlaps with the edge of the logic die 10 in the third direction DR3.

[0152] The photon integrated circuit 32 includes a lattice coupler 455 in an area not covered by the electronic integrated circuit 34. The lattice coupler 455 plays a role in transmitting optical signals received through the optical fiber in other directions. For example, the lattice coupler 455 transmits optical signals received perpendicular to the top surface of the photon integrated circuit 32 in a horizontal direction parallel to the top surface of the photon integrated circuit 32. The lattice coupler 455 transmits optical signals generated by the photon integrated circuit 32 to the optical fiber.

[0153] The lower surface of the optical structure 30 is the lower surface of the photon integrated circuit 32. The photon integrated circuit 32 is electrically connected to the logic die 10 and the insulating layer through-via 125 via a plurality of fifth connection pads 322 located on the lower surface of the photon integrated circuit 32. The photon integrated circuit 32 is electrically connected to the substrate 110 via the insulating layer through-via 125.

[0154] In one embodiment, the cover layer 38 covers the upper surface of the photon integrated circuit 32 and the upper surface of the electronic integrated circuit 34. The cover layer 38 is in contact with the upper surface of the electronic integrated circuit 34. The cover layer 38 is separated from the upper surface of the photon integrated circuit 32 in a third direction DR3. The optical structure 30 includes a light-transmitting insulating layer 36 located between the cover layer 38 and the photon integrated circuit 32 in the third direction DR3. The light-transmitting insulating layer 36 is located on the upper surface of the photon integrated circuit 32 and the side surface of the electronic integrated circuit 34. The cover layer 38 is located on the upper surface of the light-transmitting insulating layer 36. The cover layer 38 is in contact with the upper surface of the light-transmitting insulating layer 36.

[0155] The cover layer 38 and the light-transmitting insulating layer 36 contain a light-transmitting material. For example, the cover layer 38 contains, but is not limited to, glass or silicon (Si). For example, the light-transmitting insulating layer 36 contains silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0156] Referring to Figure 18, the high-bandwidth memory 20 and the optical structure 30 are molded onto the upper surface of the base insulating layer 120 using a first molding member 190. The molding process using the first molding member 190 includes, but is not limited to, compression molding or transfer molding. The first molding member 190 includes, but is not necessarily limited to, an epoxy molding compound (EMC).

[0157] Next, the first molding member 190 is planarized. The planarization process includes, but is not limited to, a CMP process. The first molding member 190 covers the top and side surfaces of the high-bandwidth memory 20. The first molding member 190 covers the side surfaces of the optical structure 30. The first molding member 190 does not cover the top surface of the optical structure 30. That is, the top surface of the cover layer 38 is not covered by the first molding member 190 and is exposed. The top surface of the first molding member 190 is at substantially the same level as the top surface of the cover layer 38.

[0158] Figure 18 illustrates the optical structure 30 being molded together with the high-bandwidth memory 20 in one step with the first molding member 190 without any further molding of the optical structure 30, but is not limited to this. For example, the optical structure 30 can be primary molded alone, and then the optical structure 30 can be molded again together with the high-bandwidth memory 20. Alternatively, the optical structure 30 can be underfilled before molding by bonding the optical structure 30 to the base insulating layer 120 and a plurality of fourth connection pads 128.

[0159] Referring to Figure 19, the carrier substrate CR is removed, and a plurality of second connection pads 122 and a plurality of first connection members 121 are formed on the lower surface of the base insulating layer 120 and the lower surface of the logic die 10, after which the plurality of first connection members 121 are bonded onto the substrate 110.

[0160] Next, the optical connector 40 is optically connected to the optical structure 30. Although not shown, this may include a frame covering the semiconductor package 100. The optical connector 40 is fastened through a hole provided in the frame covering the semiconductor package 100. For example, the optical connector 40 and the hole are connected to each other in a male-female structure.

[0161] An optical connector 40 is located on the upper surface of the cover layer 38. The optical connector 40 includes an optical fiber 42. The optical connector 40 is positioned such that the end of the optical fiber 42 faces the upper surface of the cover layer 38. The end of the optical fiber 42 is spaced away from the upper surface of the cover layer 38. An air gap is located between the end of the optical fiber 42 and the upper surface of the cover layer 38.

[0162] Figure 19 shows, but is not limited to, that optical signals are transmitted and received vertically through the top surface of the photon integrated circuit 32. For example, the optical connector 40 may be fastened toward the side of the semiconductor package 100, and optical signals may be transmitted and received horizontally through the side or edge of the photon integrated circuit 32. In this case, the photon integrated circuit 32 may be equipped with an edge coupler instead of the lattice coupler 455 described above.

[0163] In one embodiment, the semiconductor package 100 includes a plurality of optical structures 30, and a plurality of optical connectors 40 that are optically connected to each of the plurality of optical structures 30. The plurality of optical connectors 40 are connected between the plurality of optical structures 30 and an external device. One end of the optical fiber 42 of each of the plurality of optical connectors 40 is optically connected to each of the plurality of optical structures 30, and the other end of the optical fiber 42 of each of the plurality of optical connectors 40 is optically connected to the external device.

[0164] The manufacturing process shown in Figures 13 to 19 allows for the formation of a semiconductor package 100 that can improve the optical communication speed with external devices and reduce signal loss.

[0165] Although embodiments of the present invention have been described in detail above, the technical scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concepts of the present invention also fall within the technical scope of the present invention. [Explanation of symbols]

[0166] 100 semiconductor packages 110 circuit boards 120 Base insulating layer 125 Insulation layer through via 10 Logic Dies 105 Logic Through Vias 20 High-bandwidth memory 205 Through-memory vias 30 Optical structure 32 Photon Integrated Circuits 325-Photon-Penetrating Via 455 Lattice Coupler 34 Electronic Integrated Circuits 36 Light-transmitting insulating layer 38 Cover layer 190 First Molding Member 192 Second Molding Member 40 Optical Connectors 42 Optical Fibers 310 Multiplexer (MUX) 315 Optical modulator 320 Modulator Drivers 330 Input Buffer 340 Controllers 350 Demultiplexer (DEMUX) 355 Photodetector 360 Current-Voltage Converter 370 Output Driver 400 Embedded oxide layer 410 Silicon layer 420 Clad layer 450 Waveguide Members 455 Lattice Coupler 460 Optical Modulator 465 Photodetector 50 Heat Conduction Blocks 52 Heat Conducting Pads 33 Optoelectronic Integrated Circuits 115 Bridge layer 130 Redistribution layer

Claims

1. circuit board and A logic die located on the aforementioned substrate, A base insulating layer located on the side and top surface of the logic die, Insulating layer penetration vias that penetrate the base insulating layer on both sides of the logic die, A high-bandwidth memory and optical structure located on the upper surface of the base insulating layer, The optical connector includes an optical fiber for transmitting optical signals between the optical structure and an external device, The high-bandwidth memory includes a plurality of memory dies stacked perpendicular to the upper surface of the base insulating layer, The semiconductor package is characterized in that the optical structure is connected to the logic die and the upper surface of the logic die in a direction perpendicular to it.

2. The semiconductor package according to claim 1, characterized in that the optical structure overlaps the logic die and the through-via of the insulating layer and the upper surface of the base insulating layer in a direction perpendicular to it.

3. The aforementioned optical structure is A photon integrated circuit located on the upper surface of the base insulating layer, The semiconductor package according to claim 1, characterized in that it includes an electronic integrated circuit located on at least a portion of the upper surface of the aforementioned photon integrated circuit.

4. The aforementioned optical structure is It includes a cover layer that covers the upper surface of the photon integrated circuit and the upper surface of the electronic integrated circuit, The semiconductor package according to claim 3, characterized in that the cover layer contains a light-transmitting material.

5. The optical connector is located on the upper surface of the cover layer, The semiconductor package according to claim 4, characterized in that the cover layer is located between the end of the optical fiber and the upper surface of the photon integrated circuit.

6. The semiconductor package according to claim 5, characterized in that the photon integrated circuit includes a grating coupler optically connected to the optical fiber.

7. Multiple connection pads are located on the upper surface of the logic die. The semiconductor package according to claim 1, characterized in that some of the plurality of connection pads are connected to the optical structure and other parts are connected to the high-bandwidth memory.

8. A plurality of optical structures located on the upper surface of the base insulating layer, It includes a plurality of optical connectors connected between the plurality of optical structures and the plurality of external devices, The semiconductor package according to claim 1, characterized in that the plurality of optical structures are arranged in a direction aligned with the upper surface of the base insulating layer.

9. circuit board and A logic die located on the aforementioned substrate, A base insulating layer located on the side and top surface of the logic die, Insulating layer penetration vias that penetrate the base insulating layer on both sides of the logic die, A high-bandwidth memory and optical structure located on the upper surface of the base insulating layer, The optical connector includes an optical fiber for transmitting optical signals between the optical structure and an external device, The high-bandwidth memory includes a plurality of memory dies stacked perpendicular to the upper surface of the base insulating layer, The optical structure on the plane overlaps with at least a portion of the logic die, The semiconductor package is characterized in that the optical structure is connected to the logic die and the upper surface of the logic die in a direction perpendicular to it.

10. circuit board and The substrate includes a plurality of chiplets mounted on the substrate, Each of the aforementioned multiple chiplets is A logic die located on the aforementioned substrate, A base insulating layer located on the side and top surface of the logic die, Insulating layer penetration vias that penetrate the base insulating layer on both sides of the logic die, A high-bandwidth memory and optical structure located on the upper surface of the base insulating layer, The optical connector includes an optical fiber for transmitting optical signals between the optical structure and an external device, The high-bandwidth memory includes a plurality of memory dies stacked perpendicular to the upper surface of the base insulating layer, The semiconductor package is characterized in that the optical structure is connected to the logic die and the upper surface of the logic die in a direction perpendicular to it.

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