Glass substrate, wiring board, and method for processing glass substrate

Abstract

The present invention provides a glass substrate in which semiconductor elements are arranged in recesses formed on the surface, wherein wiring can be appropriately formed on the bottom surface of the recesses, and the adhesion of the semiconductor elements to the bottom surface of the recesses is ensured. [Solution] The glass substrate 12 comprises a first surface 13, a second surface 14 located opposite the first surface, and at least one recess 20 located on the first surface. The recess includes a side surface 21 and a bottom surface 22. The bottom surface includes a rough region 23 that has a square shape with sides of 1 mm in a plan view. The rough region has a maximum height Sz1 of 0.1 μm or more and less than 10 μm. By using the maximum height Sz1 as an indicator of roughness, it is possible to suppress the tilting of the element 40 relative to the bottom surface 22 due to the localized presence of large peak heights Rp, and to ensure adhesion to the bottom surface.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a glass substrate, a wiring substrate, and a method for processing a glass substrate.

Background Art

[0002] Packaging technologies for densely mounting a plurality of semiconductor elements with different functions, such as CPUs and memories, on a single substrate have attracted attention. A substrate for electrically connecting a plurality of semiconductor elements is also referred to as an interposer. For example, Patent Document 1 discloses a semiconductor package including an interposer including through electrodes and semiconductor elements mounted on the interposer.

[0003] In Patent Document 1, the semiconductor element is disposed in a recess formed on the surface of the substrate. In Patent Document 1, it is proposed that the surface roughness of the bottom surface of the recess is three times or less the surface roughness of the surface of the substrate. By reducing the surface roughness of the bottom surface of the recess, wiring can be appropriately formed on the bottom surface of the recess.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When the surface roughness of the bottom surface of the recess is reduced, the adhesion of the element to the bottom surface of the recess decreases.

[0006] An embodiment of the present disclosure aims to provide a glass substrate, a wiring substrate, and a method for processing a glass substrate that can effectively solve such problems.

Means for Solving the Problems

[0007] Embodiments of this disclosure relate to the following [1] to

[24] .

[0008] [1] A glass substrate, Page 1 and, The second surface is located on the opposite side of the first surface, The first surface comprises at least one recess, The recess includes the side surface and the bottom surface, The bottom surface includes a rough region that has a square shape with sides of 1 mm in a plan view. The aforementioned coarse region is a glass substrate having a maximum height Sz1 of 0.1 μm or more and less than 10 μm.

[0009] [2] The glass substrate described in [1] may have at least one through hole that penetrates the glass substrate from the first surface to the second surface.

[0010] [3] The glass substrate described in [1] or [2] may have at least one through hole that penetrates the glass substrate from the bottom surface to the second surface.

[0011] [4] In the glass substrate described in any one of [1] to [3], the maximum height Sz1 of the rough region may be five times or more the maximum height Sz2 of the first surface.

[0012] [5] In the glass substrate described in any one of [1] to [4], the rough region may include a plurality of peaks and a plurality of valleys, and the area of ​​the plurality of peaks in a plan view may be larger than the area of ​​the plurality of valleys in a plan view.

[0013] [6] In the glass substrate described in any one of [1] to [5], the rough region may include a plurality of peaks and a plurality of valleys, and the area of ​​the plurality of peaks in a cross-sectional view may be larger than the area of ​​the plurality of valleys in a plan view.

[0014] [7] In the glass substrate according to [6], at least one of the plurality of the mountain portions may have a shape approximated to a trapezoid in a cross-sectional view.

[0015] [8] In the glass substrate according to [7], at least one of the plurality of the mountain portions may include an upper portion substantially parallel to the first surface in a cross-sectional view.

[0016] [9] In the glass substrate according to [7] or [8], the angle formed by the upper base and the leg of the trapezoid may be 100 degrees or more.

[0017]

[10] In the glass substrate according to any one of [6] to [9], the angle formed by the normal line of the first surface and the inclined portion of the mountain portion may be larger than the angle formed by the normal line of the first surface and the inclined portion of the valley portion.

[0018]

[11] In the glass substrate according to any one of [1] to

[10] , the rough region may have a central point that coincides with the central point of the bottom surface.

[0019]

[12] A wiring substrate, [2] the glass substrate according to, and a through electrode located in the through hole of the glass substrate, comprising: the through hole of the glass substrate includes a wall surface, the through electrode is a wiring substrate including at least a layer made of a metal material covering the wall surface.

[0020]

[13] In the wiring substrate according to

[12] , the through electrode may be formed over the entire area of the through hole.

[0021]

[14] The wiring substrate according to

[12] or

[13] may include at least one wiring layer located on the first surface, and the wiring layer may include an insulating layer and a conductive layer electrically connected to the through electrode.

[0022]

[15] The wiring board according to any one of

[12] to

[14] may be provided with an element including terminals and located in the recess.

[0023]

[16] The wiring board according to

[15] may be provided with at least one wiring layer located on the first surface, and the wiring layer may include an insulating layer and a conductive layer electrically connected to the through electrode and the terminal of the element.

[0024]

[17] A wiring board, [1] The glass substrate according to, An element including terminals and located in the recess, At least one wiring layer located on the first surface, and The wiring layer includes an insulating layer and a conductive layer electrically connected to the terminal of the element. A wiring board.

[0025]

[18] The wiring board according to any one of

[15] to

[17] may be provided with an adhesive layer located between the element and the bottom surface of the recess, and the adhesive layer may include a resin material and a curing agent.

[0026]

[19] In the wiring board according to

[18] , the adhesive layer may include a side surface located inside the side surface of the element in a plan view.

[0027]

[20] In the wiring board according to

[18] , the adhesive layer may include an outer peripheral portion located outside the side surface of the element in a plan view, and the outer peripheral portion may include a portion located above the lower surface of the element.

[0028]

[21] A method for processing a glass substrate, A step of preparing a glass substrate including a first surface and a second surface located on the opposite side of the first surface, A processing step of forming at least one recess on the first surface, The recess includes a side surface and a bottom surface, The bottom surface includes a rough region having a square shape with a side length of 1 mm in a plan view. A method for processing a glass substrate, wherein the rough region has a maximum height Sz1 of 0.1 μm or more and less than 10 μm.

[0029]

[22] In the method for processing a glass substrate described in

[21] , the processing step may include a first processing step of forming at least one recess on the first surface, the bottom surface of the recess formed by the first processing step may include a plurality of peaks and a plurality of valleys, and the processing step may further include a second processing step of partially removing the plurality of peaks.

[0030] In the glass substrate processing method described in

[23]

[22] , the second processing step may include a step of irradiating a laser onto a plurality of the ridges.

[0031] In the glass substrate processing method described in

[24]

[22] , the second processing step may include a step of impacting abrasive material onto a plurality of the ridges. [Effects of the Invention]

[0032] According to the embodiments of this disclosure, the adhesion of the element to the bottom surface of the recess can be improved. [Brief explanation of the drawing]

[0033] [Figure 1] This is a plan view showing a wiring board according to one embodiment. [Figure 2A] This is a cross-sectional view of the wiring board in Figure 1 along line II-II. [Figure 2B] This is a cross-sectional view showing an example of a through electrode. [Figure 2C] This is a cross-sectional view showing an example of a through electrode. [Figure 3] This is a cross-sectional view showing an example of a recess and an element. [Figure 4A] This is a cross-sectional view showing an example of the bottom surface of a recess. [Figure 4B] This figure shows an example of the area of ​​a mountainous region and the area of ​​a valley. [Figure 4C] This figure shows an example of a mountain-shaped area that approximates a trapezoid. [Figure 4D] This figure shows an example of the slope angle of the mountainous area and the slope angle of the valley. [Figure 5A] This figure shows a method for measuring the surface roughness of the bottom surface of a recess. [Figure 5B] This figure shows the measurement area in the coarse region. [Figure 5C] This figure shows a method for measuring the parallelism of the bottom surface of a recess. [Figure 6] This is a cross-sectional view showing an example of a processing step for processing a glass substrate. [Figure 7] This is a cross-sectional view showing an example of the process of forming through electrodes in through holes. [Figure 8] This is a cross-sectional view showing an example of the bottom surface of a recess formed by the first processing step. [Figure 9] This is a cross-sectional view showing an example of the second processing step. [Figure 10] This is a cross-sectional view showing an example of the process for forming through electrodes. [Figure 11] This is a cross-sectional view showing an example of the process for forming through electrodes. [Figure 12] This is a cross-sectional view showing an example of the process for forming through electrodes. [Figure 13] This is a cross-sectional view showing an example of the polishing process. [Figure 14] This is a cross-sectional view showing an example of the process of mounting elements in a recessed area. [Figure 15] This is a cross-sectional view showing an example of the process of mounting elements in a recessed area. [Figure 16] This is a cross-sectional view showing an example of an adhesive layer formed on the bottom surface of a recess. [Figure 17A] This is a cross-sectional view showing an example of an adhesive layer and element located in a recess. [Figure 17B] This is a cross-sectional view showing an example of an adhesive layer and element located in a recess. [Figure 17C] This is a cross-sectional view showing an example of an adhesive layer and element located in a recess. [Figure 18] This is a cross-sectional view showing an example of the process for forming a redistribution layer. [Figure 19]This is a cross-sectional view showing an example of the process for forming a redistribution layer. [Figure 20] This is a cross-sectional view showing a modified example of a wiring board. [Figure 21] This is a cross-sectional view showing a modified example of a wiring board. [Figure 22] This is a cross-sectional view showing a modified example of a wiring board. [Figure 23] This is a cross-sectional view showing a modified example of a wiring board. [Figure 24] This figure shows an example of a product that incorporates a circuit board. [Modes for carrying out the invention]

[0034] In this specification, unless otherwise specified, terms meaning base materials such as "substrate," "base material," "board," "sheet," and "film" are not distinguished from each other solely on the basis of differences in name. For example, "substrate" is a concept that includes materials that may be called sheets or films.

[0035] In this specification, unless otherwise specified, the term "plane" refers to the plane of a plate-like member in question that coincides with the planar direction of the member when viewed as a whole and in a broad sense. The term "normal direction" as used with respect to a plate-like member refers to the direction normal to the plane of the member.

[0036] In this specification, unless otherwise specified, terms relating to shape and geometric conditions, as well as values ​​that specify the degree of shape and geometric conditions, may be interpreted based on the function they achieve, without being bound by their strict meaning. Examples of terms relating to shape and geometric conditions include "parallel" and "orthogonal." Examples of values ​​that specify the degree of shape and geometric conditions include length values ​​and angle values.

[0037] In this specification and these drawings, unless otherwise specified, when the positional relationship of a second component to a first component is described using terms such as "above," "below," "upper side," "lower side," "upward," or "downward," the second component may or may not be in contact with the first component. In this specification and these drawings, unless otherwise specified, when the positional relationship of a second component to a first component is described using terms such as "above," "upper side," or "upward," depending on the usage conditions of the product, the second component may be located "below," "downward," or "downward" of the first component.

[0038] In this specification, if multiple candidate upper limits and multiple candidate lower limits are given for a certain parameter, the numerical range of that parameter may be constructed by combining any one candidate upper limit and any one candidate lower limit. For example, consider the case where it is stated that "Parameter B is, for example, A1 or greater, and may be A2 or greater, and may be A3 or greater. Parameter B is, for example, A4 or less, and may be A5 or less, and may be A6 or less." In this case, the numerical range of parameter B may be A1 or greater and A4 or less, A1 or greater and A5 or less, A1 or greater and A6 or less, A2 or greater and A4 or less, A2 or greater and A5 or less, A2 or greater and A6 or less, A3 or greater and A4 or less, A3 or greater and A5 or less, and A3 or greater and A6 or less.

[0039] In this specification and these drawings, unless otherwise specified, identical parts or components having similar functions are denoted by the same or similar reference numerals. Dimensional ratios in the drawings may differ from actual ratios for illustrative purposes. In this specification and these drawings, some components may be omitted from the drawings.

[0040] In this specification and these drawings, unless otherwise specified, one embodiment of this specification may be combined with other embodiments or modifications, to the extent that it does not contradict. Other embodiments or modifications may also be combined with each other, to the extent that it does not contradict.

[0041] In this specification and these drawings, unless otherwise specified, when multiple steps are disclosed regarding a method such as a manufacturing method, other steps not disclosed may be performed between the disclosed steps. The order of the disclosed steps may be changed to the extent that it does not create a contradiction.

[0042] The configuration of the wiring board and its manufacturing method will be described in detail with reference to the drawings. However, the technical concept of the embodiments of this disclosure shall not be construed as being limited only to the following specific embodiments.

[0043] Figure 1 is a plan view showing an example of a wiring board 10. The wiring board 10 comprises a glass substrate 12 and at least one element 40 mounted on the glass substrate 12. The wiring board 10 may have a plurality of elements 40 arranged in the plane direction of the wiring board 10. The plurality of elements 40 may be arranged in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 are included in the plane direction of the wiring board 10. The second direction D2 intersects the first direction D1. The second direction D2 may be perpendicular to the first direction D1. The first direction D1 and the second direction D2 may be the directions in which the edges of the glass substrate 12 extend.

[0044] Figure 2A is a cross-sectional view of the wiring board 10 in Figure 1 along line II-II. The glass substrate 12 includes a first surface 13 and a second surface 14. The second surface 14 is located on the opposite side of the first surface 13 in the thickness direction of the glass substrate 12. The thickness direction is also referred to as the third direction D3. The third direction D3 is perpendicular to the first direction D1 and the second direction D2.

[0045] (Glass substrate) The glass substrate 12 includes at least one recess 20 located on the first surface 13. The element 40 is located in the recess 20. The glass substrate 12 may include a plurality of recesses 20. Each of the plurality of elements 40 may be located in a recess 20. One element 40 may be placed in one recess 20. Multiple elements 40 may be placed in one recess 20.

[0046] The number of recesses 20 contained in the glass substrate 12 constituting one wiring board 10 may be, for example, one or more, two or more, or three or more. The number of recesses 20 contained in the glass substrate 12 constituting one wiring board 10 may be, for example, 10 or less, eight or less, or six or less.

[0047] The glass substrate 12 contains a glass material. Examples of glass materials include alkali-free glass, borosilicate glass, and quartz glass.

[0048] (element) Element 40 may be a semiconductor element including a transistor formed from a semiconductor such as silicon. Examples of semiconductor elements include CPUs, GPUs, FPGAs, sensors, and memories. The semiconductor element may also be a chiplet in which semiconductor elements such as CPUs, GPUs, FPGAs, sensors, and memories are divided according to their function. Element 40 may also be a passive element such as a resistor or capacitor. Element 40 may include terminals exposed on its surface.

[0049] (Through electrode) The glass substrate 12 may include at least one through-hole 15 penetrating from the first surface 13 to the second surface 14. The wiring board 10 may have at least one through-electrode 25 located in the through-hole 15. The glass substrate 12 may include a plurality of through-holes 15. A through-electrode 25 may be formed in each of the plurality of through-holes 15.

[0050] The through-hole 15 includes a wall surface 16 extending from the first surface 13 to the second surface 14. The through-electrode 25 includes at least a layer made of a metallic material covering the wall surface 16. The through-electrode 25 is configured to at least partially close the through-hole 15. "Closing" means shielding the space of the through-hole 15 with a solid material in the planar direction of the first surface 13. As shown in Figure 2A, the through-electrode 25 may be formed over the entire area of ​​the through-hole 15.

[0051] Figure 2B is a cross-sectional view showing an example of a through electrode 25. Reference numeral 131 represents a virtual plane parallel to the first surface 13. The virtual plane 131 can be positioned at any location between the first surface 13 and the second surface 14 in the third direction D3. At the position of the virtual plane 131, the space of the through hole 15 is shielded by the through electrode 25. Therefore, it can be said that the through electrode 25 at least partially closes the through hole 15.

[0052] Figure 2C is a cross-sectional view showing another example of the through electrode 25. In the example shown in Figure 2C, the space of the through hole 15 is shielded by the through electrode 25 at the position of the virtual surface 131. Therefore, in the example shown in Figure 2C, it can be said that the through electrode 25 at least partially closes the through hole 15.

[0053] The through electrode 25 is conductive. The through electrode 25 may contain metallic materials such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, and zinc. The through electrode 25 may also contain compounds of these metallic materials.

[0054] (1st redistribution layer) The wiring board 10 may include a first redistribution layer 30 located on the first surface 13. The first redistribution layer 30 includes at least one wiring layer. In the example shown in Figure 2A, the first redistribution layer 30 includes a first wiring layer 301 located on the first surface 13. Wiring layers such as the first wiring layer 301 include an insulating layer 31 and a conductive layer 32.

[0055] The insulating layer 31 includes a layer made of an insulating material having insulating properties. For example, the insulating layer 31 may include an organic layer made of an organic material having insulating properties. Examples of organic materials include polyimide and epoxy. For example, the insulating layer 31 may also include an inorganic layer made of an inorganic material having insulating properties. Examples of inorganic materials include silicon nitride and silicon oxide.

[0056] The insulating layer 31 may include an opening 311. The opening 311 may penetrate the insulating layer 31 in the third direction D3.

[0057] The conductive layer 32 may be electrically connected to the terminal 44 of the element 40. The conductive layer 32 may be electrically connected to the through electrode 25. The terminal 44 of the element 40 and the through electrode 25 may be electrically connected by the conductive layer 32.

[0058] The conductive layer 32 may include vias 33 located at the opening 311 of the insulating layer 31. For example, the conductive layer 32 may include vias 33 connected to terminal 44 of element 40. For example, the conductive layer 32 may include vias 33 connected to through electrode 25. Each via 33 extends in a third direction D3.

[0059] The conductive layer 32 may include wiring 34 extending in the planar direction of the wiring board 10. The wiring 34 may extend at least partially in a first direction D1 or a second direction D2. The wiring 34 may be located on the upper surface of the insulating layer 31.

[0060] In this specification, "top surface" means the surface located opposite the "bottom surface" in the third direction D3. "Bottom surface" means the surface facing the glass substrate 12 in the third direction D3.

[0061] The conductive layer 32 is conductive. The conductive layer 32 may contain metallic materials such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, and zinc. The conductive layer 32 may also contain compounds of these metallic materials.

[0062] (2nd redistribution layer) The wiring board 10 may include a second redistribution layer 35 located on the second surface 14. The second redistribution layer 35 includes at least one wiring layer. In the example shown in Figure 2A, the second redistribution layer 35 includes a first wiring layer 351 located on the second surface 14. Wiring layers such as the first wiring layer 351 include an insulating layer 36 and a conductive layer 37.

[0063] The insulating layer 36, like the insulating layer 31, includes a layer made of an insulating material having insulating properties. The insulating layer 36 may include an opening 361. The opening 361 may penetrate the insulating layer 36 in the third direction D3.

[0064] The conductive layer 37 is conductive, similar to the conductive layer 32. The conductive layer 37 may be electrically connected to the through electrode 25. The conductive layer 37 may include vias 38 located at the opening 361 of the insulating layer 36. For example, the conductive layer 37 may include vias 38 connected to the through electrode 25. Each via 38 extends in the third direction D3.

[0065] The recess 20 and element 40 of the glass substrate 12 will be described in detail. Figure 3 is a cross-sectional view showing an example of the recess 20 and element 40.

[0066] As shown in Figure 3, the recess 20 includes a side surface 21 and a bottom surface 22. The element 40 includes an upper surface 41, a lower surface 42, and a side surface 43. The lower surface 42 of the element 40 faces the bottom surface 22 of the recess 20. The upper surface 41 of the element 40 is located opposite the lower surface 42 in the third direction D3. The side surface 43 extends from the upper surface 41 toward the lower surface 42.

[0067] The side surface 43 of element 40 does not have to be in contact with the side surface 21 of recess 20. In other words, there may be a gap between the side surface 43 of element 40 and the side surface 21 of recess 20. The gap may be filled with a resin material such as an insulating layer 31.

[0068] The wiring board 10 may include an adhesive layer 45 located between the bottom surface 22 and the element 40. The lower surface of the adhesive layer 45 may be in contact with the bottom surface 22. The upper surface of the adhesive layer 45 may be in contact with the lower surface 42 of the element 40.

[0069] The adhesive layer 45 may be configured to harden upon some trigger; that is, the adhesive layer 45 may contain a resin material. Examples of triggers include heating and light irradiation.

[0070] Examples of resin materials for the adhesive layer 45 include polymers such as epoxy resin, acrylic resin, polyurethane, silicone resin, polyimide, and polyester. The resin material of the adhesive layer 45 may also contain monomers. The resin material content in the adhesive layer 45 may be, for example, 70.0% by volume or more, 75.0% by volume or more, or 80.0% by volume or more. The resin material content in the adhesive layer 45 may be, for example, 100.0% by volume or less, 95.0% by volume or less, or 90.0% by volume or less. The resin material content in the adhesive layer 45 is calculated based on a cross-sectional image of the adhesive layer 45.

[0071] The resin material of the adhesive layer 45 may be the same as or different from the material of the insulating layer 31.

[0072] The resin material of the adhesive layer 45 may contain a curing agent. The curing agent is, for example, a polymerization initiator. The polymerization initiator may generate radicals or cations by heating or light irradiation. Whether the resin material of the adhesive layer 45 contains a curing agent is determined by infrared absorption spectroscopy. Specifically, if organic components such as CH are detected in the analysis results by infrared absorption spectroscopy of a sample obtained by Soxhlet extraction of the adhesive layer 45, it is determined that the resin material of the adhesive layer 45 contains a curing agent.

[0073] The adhesive layer 45 may contain multiple fillers. The fillers may be composed of inorganic materials such as silica or glass. The filler content in the adhesive layer 45 may be, for example, 0.0 volume% or more, 5.0 volume% or more, or 10.0 volume% or more. The filler content in the adhesive layer 45 may be, for example, 30.0 volume% or less, 25.0 volume% or less, or 20.0 volume% or less. The filler content in the adhesive layer 45 is calculated based on a cross-sectional image of the adhesive layer 45.

[0074] A cross-sectional image of the adhesive layer 45 is obtained by observing the cross-section of the adhesive layer 45 with a scanning electron microscope (SEM). The region of the cross-sectional image is divided into a region of resin material and a region of filler by image processing. The resin material content in the adhesive layer 45 is calculated by dividing the area of ​​the resin material region by the total area of ​​the adhesive layer 45 and multiplying the result by 100. The filler content in the adhesive layer 45 is calculated by dividing the area of ​​the filler region by the total area of ​​the adhesive layer 45 and multiplying the result by 100.

[0075] The adhesive layer 45 does not have to be placed over the entire bottom surface 22. For example, the adhesive layer 45 does not have to be in contact with the side surface 21 of the recess 20. In this case, the adhesive layer 45 includes a side surface 46 that is away from the side surface 21 of the recess 20 in the planar direction of the wiring board 10.

[0076] The base surface 22 includes a rough area 23. The rough area 23 has a desired surface roughness. The rough area 23 is the region of the base surface 22 on which the surface roughness measurement is performed. The rough area 23 has a first reference length Lr1 in the first direction D1 and a second reference length Lr2 in the second direction D2. The first reference length Lr1 and the second reference length Lr2 are both 1 mm. Therefore, the rough area 23 is a region that has a square shape with sides of 1 mm in plan view. "Plan view" means viewing the object along the normal direction of the first surface 13.

[0077] Figure 4A is a cross-sectional view showing an example of the bottom surface 22 of the recess 20. For example, the rough region 23 may include a plurality of peaks 231 and a plurality of valleys 232.

[0078] Areas of the bottom surface 22 other than the rough area 23 may have the same surface roughness as the rough area 23. For example, areas of the bottom surface 22 other than the rough area 23 may include multiple peaks 231 and multiple valleys 232.

[0079] The inclusion of a rough region 23 in the bottom surface 22 means that the surface roughness of the bottom surface 22 is relatively large. Increasing the surface roughness of the bottom surface 22 improves the adhesion of the adhesive layer 45 to the bottom surface 22. The reason is not particularly limited, but for example, the greater the surface roughness of the bottom surface 22, the greater the contact area between the bottom surface 22 and the adhesive layer 45, thus improving adhesion. The adhesion of the adhesive layer 45 to the bottom surface 22 may also be improved by the anchoring effect of the multiple peaks 231 and multiple valleys 232.

[0080] By improving the adhesion of the adhesive layer 45 to the bottom surface 22, the peeling of the adhesive layer 45 from the bottom surface 22 is suppressed. Consequently, the peeling of the element 40 from the bottom surface 22 is suppressed.

[0081] The surface roughness of the rough region 23 is defined as the maximum height Sz1. The maximum height Sz1 is the sum of the maximum peak heights of the multiple peaks 231 and the maximum valley depths of the multiple valleys 232.

[0082] Figure 4A shows, for reference, the method for calculating the maximum height Rz. The maximum height Rz is the sum of the maximum peak heights Rp of multiple peaks 231 and the maximum valley depths Rv of multiple valleys 232 in a cross-section of a glass substrate 12 having a first reference length Lr1 in a first direction D1. In other words, the maximum height Rz is calculated based on the roughness of each position of the base surface 22 in one-dimensional coordinates. The maximum height Rz is measured according to JIS B 0601:2013. The maximum height Sz1 is an extension of the maximum height Rz to the surface. In other words, the maximum height Sz1 is calculated based on the roughness of each position of the base surface 22 in two-dimensional coordinates.

[0083] To improve the adhesion between the adhesive layer 45 and the element 40 to the bottom surface 22, it is preferable that the bottom surface 22 includes a rough area with a certain surface area. In this embodiment, a rough area 23 having a square shape with sides of 1 mm is defined on the bottom surface 22, and the maximum height Sz1 is adopted instead of the maximum height Rz, thereby ensuring the adhesion between the adhesive layer 45 and the element 40 to the bottom surface 22.

[0084] In addition to the maximum height Sz1, the average surface roughness Sa is also known as an indicator of roughness. However, the average surface roughness Sa may not adequately reflect the situation in which peaks 231 with abnormally large peak heights Rp exist locally. When peaks 231 with abnormally large peak heights Rp exist locally, the element 40 will tilt relative to the bottom surface 22. The maximum height Sz1 can adequately reflect the situation in which peaks 231 with abnormally large peak heights Rp exist locally. Therefore, it is possible to ensure good adhesion between the adhesive layer 45 and the element 40 to the bottom surface 22.

[0085] The maximum height Sz1 of the rough region 23 is, for example, 0.1 μm or more, may be 1.0 μm or more, or 2.0 μm or more. The maximum height Sz1 of the rough region 23 is, for example, 100 μm or less, may be 50.0 μm or less, may be 20.0 μm or less, may be less than 10.0 μm, may be 8.0 μm or less, or may be 5.0 μm or less.

[0086] The maximum height Sz1 of the rough region 23 of the base surface 22 may be greater than the maximum height Sz2 of the first surface 13. The maximum height Sz1 may be, for example, 5 times or more the maximum height Sz2, and may also be 10 times or more, or 20 times or more.

[0087] The maximum height Sz2 of the first surface 13 is measured in a region of the first surface 13 adjacent to the recess 20 in a plan view, which has a square shape with sides of 1 mm.

[0088] In Figure 4A, the dotted line labeled Ls is the average line. The average line Ls extends parallel to the plane direction of the first surface 13 of the glass substrate 12. In the third direction D3, the average line Ls is located midway between the peak 231 having the maximum peak height and the valley 232 having the maximum valley depth. Each of the multiple peaks 231 is located above the average line Ls. Each of the multiple valleys 232 is located below the average line Ls.

[0089] In the rough region 23, the sum of the areas of the multiple peaks 231 in plan view may be greater than the sum of the areas of the multiple valleys 232 in plan view. This state may be achieved, for example, by partially removing the multiple peaks 231 through a second processing step described later.

[0090] The ratio of the total area of ​​multiple peaks 231 in a plan view to the total area of ​​multiple valleys 232 in a plan view is, for example, 1.05 or more, may be 1.20 or more, or may be 1.50 or more. The ratio of the total area of ​​multiple peaks 231 in a plan view to the total area of ​​multiple valleys 232 in a plan view is, for example, 3.00 or less, may be 2.50 or less, or may be 2.00 or less.

[0091] Figure 4B shows an example of the area of ​​the peaks 231 and valleys 232 in a cross-sectional view. The hatched area labeled "Sq1" represents the area of ​​the peaks 231. The hatched area labeled "Sq2" represents the area of ​​the valleys 232.

[0092] In the rough region 23, the sum of the areas Sq1 of the multiple peaks 231 in cross-sectional view may be greater than the sum of the areas Sq2 of the multiple valleys 232 in cross-sectional view. This state may be achieved by partially removing the multiple peaks 231 through a second processing step described later, similar to the case of area in plan view.

[0093] The ratio of the total area Sq1 of the multiple peaks 231 in a cross-sectional view to the total area Sq2 of the multiple valleys 232 in a cross-sectional view is, for example, 1.05 or more, may be 1.20 or more, or may be 1.50 or more. The ratio of the total area Sq1 of the multiple peaks 231 in a cross-sectional view to the total area Sq2 of the multiple valleys 232 in a cross-sectional view is, for example, 3.00 or less, may be 2.50 or less, or may be 2.00 or less.

[0094] Figure 4C shows an example of peaks 231 and valleys 232 in cross-sectional view. At least one of the multiple peaks 231 may have a shape that approximates a trapezoid 233 in cross-sectional view. The trapezoid 233 includes a lower base 2331, an upper base 2332, a first leg 2333 and a second leg 2334, and points Pa, Pb, Pc, and Pd. The lower base 2331 is the straight line between points Pa and Pb where the peak 231 and the mean line Ls are tangent. The upper base 2332 is the straight line between points Pc and Pd. The lower base 2331 and the upper base 2332 are parallel to the first surface 13. The trapezoid 233 is inscribed in the peak 231 at points Pa, Pb, Pc, and Pd. The trapezoid 233 is determined such that its area is maximized.

[0095] The length W2 of the upper base 2332 may have a certain ratio or greater to the length W1 of the lower base 2331. The ratio W2 / W1, which is the ratio of the length W2 of the upper base 2332 to the length W1 of the lower base 2331, is, for example, 0.50 or more, may be 0.60 or more, or may be 0.70 or more.

[0096] The area of ​​trapezoid 233 may have a certain ratio or higher to the area Sq1 of the peak portion 231. The ratio of the area of ​​trapezoid 233 to the area Sq1 of the peak portion 231 may be, for example, 0.70 or higher, 0.80 or higher, or 0.90 or higher.

[0097] At least one of the multiple peaks 231 may include an upper portion that is substantially parallel to the first surface 13 in a cross-sectional view. Whether a peak 231 includes an upper portion substantially parallel to the first surface 13 may be determined based on the ratio of the distance H2 to the height H1 of the trapezoid 233. The distance H2 is the maximum distance in the third direction D3 between the upper base 2332 of the trapezoid 233 and the upper portion of the peak 231. If the ratio of the distance H2 to the height H1 is 0.20 or less, it is determined that a peak 231 includes an upper portion substantially parallel to the first surface 13.

[0098] Trapezoid 233 contains a first angle θ1 and a second angle θ2. The first angle θ1 is the angle between the upper base 2332 and the first leg 2333. The second angle θ2 is the angle between the upper base 2332 and the second leg 2334. Both the first angle θ1 and the second angle θ2 are obtuse angles; that is, both the first angle θ1 and the second angle θ2 are greater than 90 degrees.

[0099] The mountain section 231 may be configured such that the first angle θ1 or the second angle θ2 is sufficiently large. For example, at least one of the first angle θ1 and the second angle θ2 may be 100 degrees or more, 105 degrees or more, 110 degrees or more, 115 degrees or more, or 120 degrees or more.

[0100] Figure 4D shows an example of the inclination angle θ3 of the peak 231 and the inclination angle θ4 of the valley 232. The inclination angle θ3 is the angle formed by the inclined portion of the peak 231 and the normal to the first surface 13. The inclination angle θ4 is the angle formed by the inclined portion of the valley 232 and the normal to the first surface 13. The normal to the first surface 13 is parallel to the third direction D3.

[0101] The inclination angle θ3 is measured at point Pe. Point Pe is the intersection of the first median line Ls1 and the peak 231. The first median line Ls1 is a hypothetical straight line that extends parallel to the mean line Ls and is located at a distance of Rp / 2 from the mean line Ls in the third direction D3. Rp is the height (peak height) of the peak 231.

[0102] The slope angle θ4 is measured at point Pf. Point Pf is the intersection of the second median line Ls2 and the valley 232. The second median line Ls2 is a hypothetical straight line that extends parallel to the mean line Ls and is located at a distance of Rv / 2 from the mean line Ls in the third direction D3. Rv is the depth of the valley 232 (valley depth).

[0103] The inclination angle θ3 may be greater than the inclination angle θ4. The difference between the inclination angle θ3 and the inclination angle θ4 may be, for example, 1.0 degree or more, 2.0 degrees or more, 3.0 degrees or more, or 5.0 degrees or more. The difference between the inclination angle θ3 and the inclination angle θ4 may be, for example, 15.0 degrees or less, 12.0 degrees or less, 10.0 degrees or less, or 8.0 degrees or less.

[0104] Figure 5A shows a method for measuring the surface roughness of the bottom surface 22. The bottom surface 22 of the recess 20 has a center point C1 in plan view. The rough area 23 has a center point C2 that coincides with the center point C1 of the bottom surface 22. In other words, the position of the rough area 23 on the bottom surface 22 is determined based on the center point C1.

[0105] Figure 5B shows the measurement area in the rough region 23. The maximum height Sz1 in the rough region 23 is calculated based on the measurement results of peak height Rp and valley depth Rv in the first measurement area 241, second measurement area 242, third measurement area 243, fourth measurement area 244, and fifth measurement area 245. Each of the first measurement area 241 to the fifth measurement area 245 is a square region extending in the first direction D1 and the second direction D2, with a length N1. The length N1 is a predetermined value between 20 μm and 100 μm.

[0106] The fifth measurement area 245 is located at the center point C2. The center point of the fifth measurement area 245 coincides with the center point C2. The first measurement areas 241 to the fourth measurement areas 244 are all located near the corners of the rough area 23. The first measurement areas 241 to the fourth measurement areas 244 are all located at a distance M1 in the first direction D1 from the edge of the rough area 23 extending in the second direction D2. The first measurement areas 241 to the fourth measurement areas 244 are all located at a distance M2 in the second direction D2 from the edge of the rough area 23 extending in the first direction D1. Distances M1 and M2 are equal. Distances M1 and M2 are predetermined values ​​between 10 μm and 50 μm.

[0107] The maximum peak height Rp of all peaks 231 included in the rough region 23, and the maximum valley depth Rv of all valleys 232 included in the rough region 23, are likely to appear in one of the first measurement area 241 to the fifth measurement area 245. By measuring the peak height Rp and valley depth Rv in the first measurement area 241 to the fifth measurement area 245, rather than the entire rough region 23, the maximum height Sz1 in the rough region 23 can be calculated efficiently.

[0108] The maximum height Sz1 may be calculated in each of the first measurement area 241 to the fifth measurement area 245. Numerical ranges disclosed in this application with respect to the rough area 23, such as the numerical range of the maximum height Sz1, may be satisfied in each of the first measurement area 241 to the fifth measurement area 245.

[0109] The bottom surface 22 of the recess 20 may have a desired degree of parallelism. The degree of parallelism is the maximum difference in coordinates in the third direction D3 between the first position P1, second position P2, third position P3, and fourth position P4 of the bottom surface 22. The first position P1, second position P2, third position P3, and fourth position P4 are the positions of the four corners of the bottom surface 22 in a plan view, as shown in Figure 5A. The four corners of the bottom surface 22 are defined as the positions of the intersections between the contour of the recess 20 and a virtual circumscribing circle C3 that circumscribes the contour of the recess 20 in a plan view.

[0110] Figure 5C shows the method for measuring the parallelism of the base surface 22. The coordinates of the first position P1, second position P2, third position P3, and fourth position P4 in the third direction D3 are measured by bringing the probe 70 of the three-dimensional measuring instrument into contact with the base surface 22 at each position.

[0111] The parallelism of the base surface 22 is, for example, 1.0 mm or less, but may also be 0.5 mm or less, 0.2 mm or less, or 0.1 mm or less.

[0112] Examples of the dimensions of the components of the wiring board 10 are described below.

[0113] As shown in Figure 3, the glass substrate 12 has a thickness T1. The thickness T1 of the glass substrate 12 is, for example, 8 mm or more, may be 10 mm or more, or 12 mm or more. The thickness T1 of the glass substrate 12 is, for example, 20 mm or less, may be 18 mm or less, or 15 mm or less.

[0114] As shown in Figure 3, the recess 20 has a depth T2. The depth T2 of the recess 20 is, for example, 5 mm or more, may be 6 mm or more, or 7 mm or more. The depth T2 of the recess 20 is, for example, 10 mm or less, may be 9 mm or less, or 8 mm or less. The depth T2 is measured at the center point of the recess 20 in a plan view.

[0115] The depth T2 of the recess 20 may be determined relative to the thickness T1 of the glass substrate 12. The ratio T2 / T1, which is the ratio of the depth T2 of the recess 20 to the thickness T1 of the glass substrate 12, is, for example, 0.10 or more, may be 0.20 or more, may be 0.30 or more, or may be 15.0 or more. The ratio T2 / T1 is, for example, 0.70 or less, may be 0.60 or less, or may be 0.50 or less.

[0116] As shown in Figure 1, the recess 20 has a first dimension S1 in the first direction D1 and a second dimension S2 in the second direction D2. The first dimension S1 and the second dimension S2 are, for example, 3 mm or more, may be 5 mm or more, or 7 mm or more. The first dimension S1 and the second dimension S2 are, for example, 50 mm or less, may be 40 mm or less, or 30 mm or less. The first dimension S1 and the second dimension S2 are measured on the first surface 13.

[0117] The first dimension S1 may be greater than the depth T2 of the recess 20. The ratio S1 / T2, which is the ratio of the first dimension S1 to the depth T2, is, for example, 1.5 or more, may be 2.0 or more, or may be 2.5 or more. The ratio S1 / T2 is, for example, 5.0 or less, may be 4.0 or less, or may be 3.0 or less.

[0118] The second dimension S2 may be greater than the depth T2 of the recess 20. The numerical range for S2 / T2, which is the ratio of the second dimension S2 to the depth T2, may be the same as the numerical range for the ratio S1 / T2 described above.

[0119] As shown in Figure 2A, the through-hole 15 in the glass substrate 12 has a dimension S3 in the first direction D1. Dimension S3 is, for example, 5 μm or more, may be 10 μm or more, or 20 μm or more. Dimension S3 is, for example, 200 μm or less, may be 100 μm or less, or 80 μm or less. Dimension S3 is measured on the first surface 13.

[0120] As shown in Figure 3, the adhesive layer 45 has a thickness T3. The thickness T3 of the adhesive layer 45 is, for example, 1 μm or more, may be 3 μm or more, or 10 μm or more. The thickness T3 of the adhesive layer 45 is, for example, 200 μm or less, may be 100 μm or less, or 50 μm or less. The thickness T3 is the distance in the third direction D3 between the mean line Ls and the lower surface 42 of the element 40. The thickness T3 is measured at the center point of the recess 20 in a plan view.

[0121] The above-mentioned dimensions of the components of the wiring board 10 are calculated based on cross-sectional images of the wiring board 10 obtained by electron microscopy. The cross-section is obtained by cutting the wiring board 10 along a cutting plane that passes through the center point C1 of the recess 20 in a plan view and is perpendicular to the first surface 13.

[0122] (Manufacturing method for wiring boards) An example of a manufacturing method for the wiring board 10 will be described.

[0123] First, a glass substrate 12 is prepared. Next, as shown in Figure 6, a processing step is performed to form at least one recess 20 on the first surface 13 of the glass substrate 12. Also, as shown in Figure 6, a through-hole forming step is performed to form a through-hole 15 in the glass substrate 12.

[0124] In the processing step, the recess 20 may be formed by etching. For example, a resist layer is formed on the first surface 13. Subsequently, an opening is made in the resist layer at a position corresponding to the recess 20. Then, the glass substrate 12 is processed at the opening in the resist layer. As a result, as shown in Figure 6, the recess 20 is formed in the glass substrate 12. Examples of processing methods include wet etching and dry etching. Examples of dry etching include reactive ion etching and deep reactive ion etching.

[0125] In the processing step, the recess 20 may be formed by machining using a tool such as a drill. The dimensions of the tool in the first direction D1 may be smaller than the first dimension S1 of the recess 20. In this case, the recess 20 may be formed by scanning the tool with respect to the glass substrate 12 in the first direction D1. The tool may also be scanned with respect to the glass substrate 12 in the second direction D2.

[0126] In the through-hole formation process, the through-hole 15 may be formed by etching. For example, a resist layer is formed on the first surface 13. Subsequently, an opening is made in the resist layer at a position corresponding to the through-hole 15. Next, the glass substrate 12 is processed at the opening in the resist layer. As a result, as shown in Figure 6, the through-hole 15 is formed in the glass substrate 12. Examples of etching methods are the same as in the processing process, such as wet etching and dry etching.

[0127] In the through-hole formation process, the through-hole 15 may be formed by machining using a tool such as a drill.

[0128] The machining process may be performed before the through-hole formation process. The machining process may be performed after the through-hole formation process.

[0129] The processing step may be performed simultaneously with the through-hole formation step. For example, a resist layer is formed on the first surface 13. Subsequently, openings are made in the resist layer at positions corresponding to the through-holes 15 and recesses 20. Next, the glass substrate 12 is processed at the openings in the resist layer. As a result, as shown in Figure 6, through-holes 15 and recesses 20 are formed simultaneously in the glass substrate 12.

[0130] Next, as shown in Figure 7, a through-electrode formation step may be performed to form a through-electrode 25 in the through-hole 15. The through-electrode formation step may include a seed layer formation step and a plating step, which will be described later.

[0131] The processing steps will be described in detail. The processing steps may include a first processing step and a second processing step.

[0132] In the first processing step, at least one recess 20 is formed on the first surface 13. Figure 8 is a cross-sectional view showing an example of the bottom surface 22 of the recess 20 formed in the first processing step. The bottom surface 22 of the recess 20 formed in the first processing step includes a plurality of peaks 231 and a plurality of valleys 232.

[0133] In the state shown in Figure 8, after the first processing step has been performed and before the second processing step has been performed, the rough region 23 of the bottom surface 22 of the recess 20 has a large maximum height Sz1. In the state shown in Figure 8, the maximum height Sz1 is, for example, 100 μm or more, may be 150 μm or more, or may be 200 μm or more. In the state shown in Figure 8, the maximum height Sz1 is, for example, 500 μm or less, may be 400 μm or less, or may be 300 μm or less.

[0134] Figure 9 is a cross-sectional view showing an example of the second machining process. In the second machining process, multiple peaks 231 are partially removed. As a result, the height of each of the multiple peaks 231 is reduced. By performing the second machining process, the maximum height Sz1 of the rough region 23 can be adjusted.

[0135] In the second processing step, the tip of the peak 231 may be particularly shaved. As a result, the sharpness of the tip of the peak 231 is reduced.

[0136] The area of ​​the bottom surface 22 where processing is carried out in the second processing step includes at least the area of ​​the bottom surface 22 that overlaps with the adhesive layer 45 in a plan view. The area of ​​the bottom surface 22 where processing is carried out in the second processing step is also called the second processing area. The second processing area does not have to be the entire area of ​​the bottom surface 22. The area ratio of the second processing area is, for example, 90% or more and 95% or less. The area ratio of the second processing area is the ratio of the area of ​​the second processing area in a plan view to the contour of the recess 20 in a plan view. The second processing area does not have to be in contact with the contour of the recess 20 in a plan view.

[0137] When the tips of multiple peaks 231 are each reduced, the mean line Ls shifts downward in the third direction D3. As a result, the area of ​​the portion classified as a peak 231 in the coarse region 23 may increase.

[0138] In the second processing step, the multiple peaks 231 may be removed by dry etching. An example of dry etching is blasting. In blasting, the multiple peaks 231 are removed by the collision of particulate abrasive material L1 with the multiple peaks 231. The maximum height Sz1 of the rough area 23 can be adjusted by controlling the type of abrasive material, the collision speed, the blasting time, etc. Abrasive materials include, for example, SiC (silicon carbide), zirconia, alumina, garnet, iron, stainless steel, etc.

[0139] In the second processing step, the multiple peaks 231 may be removed by laser processing. In laser processing, the multiple peaks 231 are removed by irradiating them with a laser L1. The wavelength of the laser is, for example, 500 nm or more and 1600 nm or less. A pulsed laser L1 may be irradiated onto the multiple peaks 231. A laser L1 focused by a lens may be irradiated onto the multiple peaks 231.

[0140] The second processing step may include a laser irradiation step and a wet etching step. The laser irradiation step may cause modification of the multiple peaks 231 and multiple valleys 232. The wet etching step may preferentially remove the modified portions of the multiple peaks 231 and multiple valleys 232. As a result, for example, the multiple peaks 231 are each shaved off and the multiple valleys 232 are each gouged out more deeply.

[0141] The through-electrode formation process will be described in detail. The through-electrode formation process may include a seed layer formation process and a plating process.

[0142] In the seed layer formation process, as shown in Figure 10, a seed layer 251 is formed on the first surface 13, the second surface 14, and the wall surface 16 of the glass substrate 12. For example, the seed layer 251 is formed by physical deposition such as sputtering. The seed layer 251 may cover the entire wall surface 16.

[0143] The seed layer 251 may contain metallic materials such as copper, nickel, titanium, chromium, and zinc. The seed layer 251 may also contain compounds of these metallic materials.

[0144] In the plating process, as shown in Figure 11, a plating layer 252 is deposited on the seed layer 251 by electroplating. Through the seed layer formation process and the plating process, a through electrode 25 including the seed layer 251 and the plating layer 252 is obtained.

[0145] The plating layer 252 may contain metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, and zinc, or alloys using these metals. The plating layer 252 may contain these metals or alloys using these metals as its main component. The "main component" is a component that constitutes 51 atomic percent or more of the plating layer 252. For example, the plating layer 252 may contain copper as its main component.

[0146] The plating process may be carried out until the through electrode 25 closes the through hole 15, as shown in Figure 12. In the example shown in Figure 12, the plating process is carried out until the entire space of the through hole 15 is filled by the through electrode 25. Alternatively, the plating process may be terminated before the through electrode 25 closes the through hole 15, as shown in Figure 11. In other words, the plating process may be terminated while the space of the through hole 15 remains. The space of the through hole 15 may be continuous from the first surface 13 to the second surface 14.

[0147] Next, a polishing step may be performed as shown in Figure 13. The polishing step may include at least one of a first polishing step and a second polishing step. In the example shown in Figure 13, the polishing step includes a first polishing step and a second polishing step. In the first polishing step, the seed layer 251 and plating layer 252 located on the first surface 13 are removed by polishing. In the second polishing step, the seed layer 251 and plating layer 252 located on the second surface 14 are removed by polishing. Polishing may be, for example, chemical mechanical polishing.

[0148] The first polishing step forms a first end face 255 on the through electrode 25. The second polishing step forms a second end face 256 on the through electrode 25.

[0149] Next, a mounting process is carried out in which the element 40 is mounted in the recess 20. The mounting process may include an adhesive layer formation process and a placement process. In the adhesive layer formation process, as shown in Figure 14, an adhesive layer 45 is formed on the bottom surface 22 of the recess 20. In the placement process, as shown in Figure 15, the element 40 is placed on the adhesive layer 45.

[0150] The implementation process will now be described in detail. Figure 16 is a cross-sectional view showing an example of an adhesive layer 45 formed on the bottom surface 22 during the adhesive layer formation process. The adhesive layer 45 shown in Figure 16 is formed, for example, by applying a solution containing the material of the adhesive layer 45 to the bottom surface 22 of the recess 20. The solution includes, for example, a resin material constituting the adhesive layer 45 and a curing agent. The solution may further contain a solvent. As shown in Figure 16, the adhesive layer 45 may be formed so as not to be in contact with the side surface 21 of the recess 20.

[0151] Since the solution is fluid, it can penetrate into the valleys of the bottom surface 22 of the recess 20. As a result, the contact area between the lower surface of the adhesive layer 45 and the bottom surface 22 increases compared to when the bottom surface 22 is flat.

[0152] As shown in Figure 16, in the state before the element 40 is placed, the adhesive layer 45 may include an upper surface 451 that is not flat. For example, the upper surface 451 of the adhesive layer 45 may include a curved surface.

[0153] Figure 17A is a cross-sectional view showing an example of the placement process. In the placement process, the element 40 may be placed on the adhesive layer 45 before it is cured. The upper surface 451 of the adhesive layer 45 is deformed by being pressed by the lower surface 42 of the element 40. As a result, the upper surface 451 of the adhesive layer 45 can have a shape corresponding to the lower surface 42 of the element 40. For example, if the lower surface 42 of the element 40 is flat, the portion of the upper surface 451 of the adhesive layer 45 that overlaps with the element 40 in a plan view is also flat.

[0154] The mounting process may include a curing step in which the adhesive layer 45 is cured after the element 40 has been placed on the adhesive layer 45. In the curing step, a trigger is applied to the adhesive layer 45 so that the curing agent contained in the adhesive layer 45 generates radicals or cations. For example, the adhesive layer 45 may be heated. For example, the adhesive layer 45 may be irradiated with light. The light is, for example, ultraviolet light.

[0155] As the adhesive layer 45 hardens, the lower surface of the adhesive layer 45 can adhere closely to the bottom surface 22 of the recess 20, and the upper surface of the adhesive layer 45 can adhere closely to the lower surface 42 of the element 40.

[0156] As shown in Figure 17A, in a plan view, the contour of the adhesive layer 45 may coincide with the contour of the element 40. For example, in a plan view, the adhesive layer 45 may include a side surface 46 that overlaps with the side surface 43 of the element 40. "Side surface 46 overlapping with side surface 43" means that the distance in the first direction D1 between the position of side surface 43 in contact with the upper surface 41 of the element 40 and the position of side surface 46 in contact with the upper surface of the adhesive layer 45 is less than 10 μm.

[0157] Figure 17B is a cross-sectional view showing another example of the mounting process. As shown in Figure 17B, in a plan view, the contour of the adhesive layer 45 may be located inside the contour of the element 40. For example, in a plan view, the adhesive layer 45 may include a side surface 46 located inside the side surface 43 of the element 40. In other words, in a plan view, the side surface 46 of the adhesive layer 45 may overlap the bottom surface 42 of the element 40. The distance in the first direction D1 between the position of the side surface 43 in contact with the top surface 41 of the element 40 and the position of the side surface 46 in contact with the top surface of the adhesive layer 45 may be 10 μm or more.

[0158] "Component A is located inside component B" means that, in the planar direction of the first surface 13, the distance from component A to the center point C1 of the bottom surface 22 of the recess 20 is smaller than the distance from component B to the center point C1. Conversely, "Component A is located outside component B" means that, in the planar direction of the first surface 13, the distance from component A to the center point C1 is larger than the distance from component B to the center point C1.

[0159] Figure 17C is a cross-sectional view showing another example of the mounting process. As shown in Figure 17C, in a plan view, the contour of the adhesive layer 45 may be located outside the contour of the element 40. For example, the adhesive layer 45 may include an outer peripheral portion 47 located outside the side surface 43 of the element 40 in a plan view.

[0160] As shown in Figure 17C, the outer peripheral portion 47 may include a portion located above the lower surface 42 of the element 40. This portion is created when the upper surface of the adhesive layer 45 is pressed by the lower surface 42 of the element 40. The distance K1 in the third direction D3 between the upper surface of the outer peripheral portion 47 and the lower surface 42 of the element 40 is, for example, 10 μm or more, may be 20 μm or more, or 50 μm or more. The distance K1 is, for example, 200 μm or less, may be 150 μm or less, or 100 μm or less.

[0161] As shown in Figure 17C, the outer peripheral portion 47 of the adhesive layer 45 does not have to be in contact with the side surface 21 of the recess 20. In other words, the bottom surface 22 of the recess 20 may include a portion that does not overlap with the adhesive layer 45 in a plan view.

[0162] Next, a process is carried out to form redistribution layers such as the first redistribution layer 30 and the second redistribution layer 35. For example, as shown in Figure 18, an insulating layer 31 is formed on the first surface 13. The insulating layer 31 may also be formed in the gap between the element 40 and the side surface 21 of the recess 20. As shown in Figure 18, an insulating layer 36 may be formed on the second surface 14.

[0163] Next, as shown in Figure 19, a step is performed to form an opening 311 in the insulating layer 31. If the material of the insulating layer 31 is photosensitive, the opening 311 may be formed in the insulating layer 31 by exposure and development. Alternatively, the opening 311 may be formed in the insulating layer 31 by partially etching the insulating layer 31. Next, a step is performed to form a conductive layer 32. For example, vias 33 are formed in the opening 311, and wiring 34 is formed on the insulating layer 31. As a result, the first rewiring layer 30 shown in Figure 2A is obtained.

[0164] Furthermore, as shown in Figure 19, a step is performed to form an opening 361 in the insulating layer 36. If the material of the insulating layer 36 is photosensitive, the opening 361 may be formed in the insulating layer 36 by exposure and development. Alternatively, the opening 361 may be formed in the insulating layer 36 by partially etching the insulating layer 36. Subsequently, a step is performed to form a conductive layer 37. For example, vias 38 are formed in the opening 361. As a result, the second redistribution layer 35 shown in Figure 2A is obtained.

[0165] In the wiring board 10 of this embodiment, the bottom surface 22 of the recess 20 includes a rough region 23. The rough region 23 has a maximum height Sz1 of 0.1 μm or more. Therefore, the adhesion of the adhesive layer 45 to the bottom surface 22 can be improved. As a result, peeling of the element 40 from the bottom surface 22 of the recess 20 can be suppressed.

[0166] The above-described embodiment can be modified in various ways. Hereinafter, modifications will be described with reference to the drawings as necessary. In the following description and the drawings used therein, parts that can be configured similarly to the above-described embodiment will be given the same reference numerals as those used for the corresponding parts in the above-described embodiment. Duplicate explanations will be omitted. Furthermore, if it is clear that the effects and advantages obtained in the above-described embodiment can also be obtained in the modifications, the explanation may be omitted.

[0167] (First variation) Figure 20 is a cross-sectional view showing the wiring board 10 in the first modified example.

[0168] The first redistribution layer 30 may include a plurality of wiring layers stacked in a third direction D3. For example, the first redistribution layer 30 may include a first wiring layer 301 and a second wiring layer 302 located on the first wiring layer 301. The first wiring layer 301 and the second wiring layer 302 each include an insulating layer 31 and a conductive layer 32. Each insulating layer 31 may include an opening 311. The conductive layer 32 may include vias 33 located in each of the openings 311 of the plurality of insulating layers 31.

[0169] The second redistribution layer 35 may include a plurality of wiring layers stacked in a third direction D3. For example, the second redistribution layer 35 may include a first wiring layer 351 and a second wiring layer 352 located on the first wiring layer 351. The first wiring layer 351 and the second wiring layer 352 each include an insulating layer 36 and a conductive layer 37. Each insulating layer 36 may include an opening 361. The conductive layer 37 may include vias 38 located in each of the openings 361 of the plurality of insulating layers 36.

[0170] (Second variation) Figure 21 is a cross-sectional view showing the wiring board 10 in a second modified example. The through electrode 25 may be configured to partially close the through hole 15. For example, the through electrode 25 may include a wall portion 253 extending along the wall surface 16 and a closing portion 254 that shields the through hole 15 in part along the plane direction of the first surface 13.

[0171] The closing portion 254 may be located between the first surface 13 and the second surface 14 in the third direction D3. In this case, a resin layer 26 may be formed in the through hole 15 between the closing portion 254 and the first surface 13, and between the closing portion 254 and the second surface 14.

[0172] (Third variation) Figure 22 is a cross-sectional view showing the wiring board 10 in a third modified example.

[0173] The glass substrate 12 may include a through hole 15 that penetrates the glass substrate 12 from the bottom surface 22 of the recess 20 to the second surface 14. The wiring board 10 may include a through electrode 25 located in the through hole 15 that penetrates the glass substrate 12 from the bottom surface 22 to the second surface 14. Although not shown, the conductive layer 37 of the second rewiring layer 35 may be electrically connected to the through electrode 25. The conductive layer 37 may include wiring 39 located on the insulating layer 36.

[0174] Although not shown in the diagram, the glass substrate 12 may further include through holes 15 that penetrate the glass substrate 12 from the first surface 13 to the second surface 14. The wiring board 10 may further include through electrodes 25 located in the through holes 15 that penetrate the glass substrate 12 from the first surface 13 to the second surface 14.

[0175] (Fourth variation) Figure 23 is a cross-sectional view showing the wiring board 10 in the fourth modified example. The glass substrate 12 includes the recess 20, but does not necessarily include the through hole 15.

[0176] Figure 24 shows an example of a product on which the wiring board 10 is mounted. The wiring board 10 can be used in a variety of products. For example, it can be mounted in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, etc.

[0177] We have described several variations of the above-described embodiment, but of course, it is also possible to combine multiple variations as appropriate and apply them to the above-described embodiment. [Examples]

[0178] The embodiments of this disclosure will be described in more detail by reference to examples. The embodiments of this disclosure are not limited to the following examples unless they exceed the gist of the disclosure.

[0179] (Example 1) A glass substrate 12 having a thickness T1 of 11 mm was prepared. The glass substrate 12 was made of alkali-free glass containing borosilicate glass. Next, a processing step was performed to form a recess 20 on the first surface 13 of the glass substrate 12. The processing step included the first and second processing steps described above. A through-hole forming step was also performed to form a through-hole 15 in the glass substrate 12. The dimension S3 of the through-hole 15 was 100 μm. A through-electrode forming step was also performed to form a through-electrode 25 in the through-hole 15.

[0180] The dimensions of the recess 20 were as follows: First dimension S1: 25mm Second dimension S2: 25mm Depth T2 of recess 20: 5mm

[0181] The bottom surface 22 of the recess 20 contained a rough region 23. The maximum height Sz1 of the rough region 23 was 2.8 μm. The maximum height Sz1 was measured using a shape analysis laser microscope VK-X1000 manufactured by Keyence Corporation.

[0182] The parallelism of the bottom surface 22 of the recess 20 was 0.07 mm.

[0183] Next, a mounting process was carried out to mount the element 40 into the recess 20. The mounting process included an adhesive layer formation process and a placement process.

[0184] The adhesive layer formation step included a coating step of applying a solution containing the material for the adhesive layer 45 to the bottom surface 22 of the recess 20. The solution contained solids and a solvent. The solvent was methyl ethyl ketone. The composition of the solids was as follows: • Epoxy resin: 80% by volume • Hardener: 5% by volume • Silica filler: 15% by volume

[0185] In the coating process, a solution in which the solvent had been appropriately dried so as not to spread was dropped into the recess 20 using a dropper. Subsequently, the solvent of the solution coated on the recess 20 was dried. As a result, an adhesive layer 45 was formed on the bottom surface 22 of the recess 20.

[0186] Next, a placement step was carried out in which the element 40 was placed on the adhesive layer 45. The outer surface of the element 40 was made of epoxy resin. The thickness of the element 40 was 2 mm. In plan view, the element 40 had a square outline with sides of 20 mm.

[0187] Next, the adhesive layer 45 was heated at 100°C for 30 minutes. As a result, the adhesive layer 45 was cured.

[0188] Next, an adhesion evaluation was conducted to assess the adhesion of the element 40 to the bottom surface 22 of the recess 20. In the adhesion evaluation, a PET film with a thickness of 100 μm was adhered to the upper surface of the element 40 via strong double-sided adhesive tape, and then a tensile test was performed by pulling the PET film at a 90-degree angle to the bottom surface 22 of the recess 20. If the peel strength when the element 40 peels off from the recess 20 is 4.7 N / 10 mm or more, the adhesion evaluation result is judged to be "good". If the peel strength is less than 4.7 N / 10 mm, the adhesion evaluation result is judged to be "poor". The adhesion evaluation result in Example 1 was "good". The value of 4.7 N / 10 mm is the peel strength of Nichiban cellophane tape (No. 405) on a stainless steel plate. If a peel strength equal to or greater than that of cellophane tape is obtained, the adhesion can be said to be "good".

[0189] Next, an insulating layer 31 was formed on the first surface 13 and on the upper surface of the element 40. Subsequently, a plurality of openings 311 were formed in the insulating layer 31 located on the upper surface of the element 40. Subsequently, a conductive layer 32 was formed, including vias 33 located at each of the plurality of openings 311. The openings 311 and vias 33 were formed so as to overlap a plurality of terminals 44 located on the upper surface of the element 40 in a plan view.

[0190] Next, a continuity evaluation was performed to assess the electrical connection between the multiple terminals 44 of the element 40 and the corresponding vias 33. If the multiple terminals 44 and vias 33 are electrically connected, the continuity evaluation result is determined to be "good". If the multiple terminals 44 and vias 33 are not electrically connected, the continuity evaluation result is determined to be "poor". In Example 1, the continuity evaluation result was "good".

[0191] (Comparative Example 1) Except for adjusting the processing steps to reduce the maximum height Sz1 of the bottom surface 22 of the recess 20, the recess 20 and through hole 15 were formed in the glass substrate 12 in the same manner as in Example 1. Subsequently, the element 40 was mounted in the recess 20, as in Example 1. Also, adhesion evaluation and conductivity evaluation were performed, as in Example 1.

[0192] The maximum height Sz1 of the rough region 23 was 0.04 μm. The parallelism of the bottom surface 22 of the recess 20 was 0.01 mm. The adhesion evaluation result was "poor". The conductivity evaluation result was "good".

[0193] (Comparative Example 2) Except for adjusting the processing steps to increase the maximum height Sz1 of the bottom surface 22 of the recess 20, the recess 20 and through hole 15 were formed in the glass substrate 12 in the same manner as in Example 1. Subsequently, the element 40 was mounted in the recess 20, as in Example 1. Also, adhesion evaluation and conductivity evaluation were performed, as in Example 1.

[0194] The maximum height Sz1 of the rough region 23 was 260 μm. The parallelism of the bottom surface 22 of the recess 20 was 1.2 mm. The adhesion evaluation result was "good". The continuity evaluation result was "poor". In the continuity evaluation, a via 33 located in at least one of the multiple openings 311 was not electrically connected to the terminal 44 on the upper surface of the element 40.

[0195] (Example 2) Except for adjusting the processing steps so that the maximum height Sz1 of the bottom surface 22 of the recess 20 was greater than that in Comparative Example 1, the recess 20 and through hole 15 were formed in the glass substrate 12 in the same manner as in Example 1. Subsequently, the element 40 was mounted in the recess 20, as in Example 1. Also, adhesion evaluation and conductivity evaluation were performed, as in Example 1.

[0196] The maximum height Sz1 of the rough region 23 was 0.2 μm. The parallelism of the bottom surface 22 of the recess 20 was 0.06 mm. The adhesion evaluation result was "good". The conductivity evaluation result was "good".

[0197] (Comparative Example 3) Except for adjusting the processing steps so that the maximum height Sz1 of the bottom surface 22 of the recess 20 was smaller than in Example 2, the recess 20 and through hole 15 were formed in the glass substrate 12 in the same manner as in Example 1. Subsequently, the element 40 was mounted in the recess 20, as in Example 1. Also, adhesion evaluation and conductivity evaluation were performed, as in Example 1.

[0198] The maximum height Sz1 of the rough region 23 was 0.08 μm. The parallelism of the bottom surface 22 of the recess 20 was 0.02 mm. The adhesion evaluation result was "poor". The conductivity evaluation result was "good".

[0199] (Example 3) Except for adjusting the processing steps so that the maximum height Sz1 of the bottom surface 22 of the recess 20 is greater than in Example 1, the recess 20 and through hole 15 were formed in the glass substrate 12 in the same manner as in Example 1. Subsequently, the element 40 was mounted in the recess 20, as in Example 1. Also, adhesion evaluation and conductivity evaluation were performed, as in Example 1.

[0200] The maximum height Sz1 of the rough region 23 was 9.4 μm. The parallelism of the bottom surface 22 of the recess 20 was 0.82 mm. The adhesion evaluation result was "good". The conductivity evaluation result was "good".

[0201] (Comparative Example 4) Except for adjusting the processing steps so that the maximum height Sz1 of the bottom surface 22 of the recess 20 is greater than in Example 3, the recess 20 and through hole 15 were formed in the glass substrate 12 in the same manner as in Example 1. Subsequently, the element 40 was mounted in the recess 20, as in Example 1. Also, adhesion evaluation and conductivity evaluation were performed, as in Example 1.

[0202] The maximum height Sz1 of the rough region 23 was 11 μm. The parallelism of the bottom surface 22 of the recess 20 was 1.05 mm. The adhesion evaluation result was "good". The conductivity evaluation result was "poor".

[0203] Table 1 shows the evaluation results for Examples 1-3 and Comparative Examples 1-4. Good adhesion and conductivity were achieved when the maximum height Sz1 was 0.2 μm or more and 9.4 μm or less, and the parallelism was 0.06 mm or more and 0.82 mm or less. [Table 1] [Explanation of symbols]

[0204] 10 Wiring board 12 Glass substrate 13 Page 1 14 Side 2 15 Through holes 16 Wall surface 20 recesses 21 Side view 22 Bottom 23 Coarse area 231 Yamabe 232 Tanibe 25 Through electrode 26 Resin layer 30 1st redistribution layer 31 Insulating layer 32 Conductive layer 35 2nd redistribution layer 36 Insulating layer 37 Conductive layer 40 elements 45 Adhesive layer 46 Side view 47 Outer area

Claims

1. A glass substrate, Page 1 and, The second surface located on the opposite side of the first surface, The first surface comprises at least one recess, The recess includes the side surface and the bottom surface, The bottom surface includes a rough region that, in plan view, has a square shape with sides of 1 mm. The aforementioned rough region is a glass substrate having a maximum height Sz1 of 0.1 μm or more and less than 10 μm.

2. The glass substrate according to claim 1, comprising at least one through hole penetrating the glass substrate from the first surface to the second surface.

3. The glass substrate according to claim 1, further comprising at least one through hole penetrating the glass substrate from the bottom surface to the second surface.

4. The glass substrate according to any one of claims 1 to 3, wherein the maximum height Sz1 of the rough region is five times or more the maximum height Sz2 of the first surface.

5. The aforementioned rough region includes multiple peaks and multiple valleys, The glass substrate according to any one of claims 1 to 3, wherein the area of ​​the multiple peaks in a plan view is greater than the area of ​​the multiple valleys in a plan view.

6. The aforementioned rough region includes multiple peaks and multiple valleys, The glass substrate according to any one of claims 1 to 3, wherein the area of ​​the multiple peaks in a cross-sectional view is larger than the area of ​​the multiple valleys in a plan view.

7. The glass substrate according to claim 6, wherein at least one of the plurality of ridges has a shape that approximates a trapezoid in cross-sectional view.

8. The glass substrate according to claim 7, wherein at least one of the plurality of ridges includes an upper portion substantially parallel to the first surface in a cross-sectional view.

9. The glass substrate according to claim 7, wherein the angle formed by the upper base and the legs of the trapezoid is 100 degrees or more.

10. The glass substrate according to claim 6, wherein the angle between the normal to the first surface and the inclined portion of the peak is greater than the angle between the normal to the first surface and the inclined portion of the valley.

11. The glass substrate according to claim 1 or 2, wherein the rough region has a center point that coincides with the center point of the bottom surface.

12. A wiring board, The glass substrate according to claim 2, The glass substrate comprises a through electrode located in the through hole, The through hole in the glass substrate includes the wall surface, The through electrode is a wiring board that includes at least a layer made of a metal material covering the wall surface.

13. The wiring board according to claim 12, wherein the through electrode is formed over the entire area of ​​the through hole.

14. The first surface comprises at least one wiring layer, The wiring substrate according to claim 12 or 13, wherein the wiring layer includes an insulating layer and a conductive layer electrically connected to the through electrode.

15. The wiring board according to claim 12, comprising an element located in the recess and including a terminal.

16. The first surface comprises at least one wiring layer, The wiring substrate according to claim 15, wherein the wiring layer includes an insulating layer and a conductive layer electrically connected to the through electrode and the terminal of the element.

17. A wiring board, The glass substrate according to claim 1, Located in the aforementioned recess, the element includes a terminal, The first surface comprises at least one wiring layer, The wiring substrate includes an insulating layer and a conductive layer electrically connected to the terminals of the element.

18. The adhesive layer is located between the element and the bottom surface of the recess, The wiring board according to any one of claims 15 to 17, wherein the adhesive layer comprises a resin material and a curing agent.

19. The wiring board according to claim 18, wherein the adhesive layer includes a side located on the inside of the side surface of the element in a plan view.

20. The adhesive layer includes an outer peripheral portion located on the outside of the side surface of the element in a plan view. The wiring board according to claim 18, wherein the outer peripheral portion includes a portion located above the lower surface of the element.

21. A method for processing a glass substrate, A step of preparing a glass substrate including a first surface and a second surface located opposite the first surface, The process includes a machining step of forming at least one recess on the first surface, The recess includes the side surface and the bottom surface, The bottom surface includes a rough region that, in plan view, has a square shape with sides of 1 mm. A method for processing a glass substrate, wherein the rough region has a maximum height Sz1 of 0.1 μm or more and less than 10 μm.

22. The processing step includes a first processing step of forming at least one recess on the first surface, The bottom surface of the recess formed by the first processing step includes a plurality of peaks and a plurality of valleys, The method for processing a glass substrate according to claim 21, wherein the processing step further includes a second processing step of partially removing a plurality of the aforementioned peaks.

23. The method for processing a glass substrate according to claim 22, wherein the second processing step includes irradiating a plurality of the peaks with a laser.

24. The method for processing a glass substrate according to claim 22, wherein the second processing step includes a step of impacting a plurality of the ridges with an abrasive material.

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