Electronic control unit

Abstract

The objective is to enable analysis of reset factors during the initialization process of the first core, which does not have non-volatile memory. [Solution] An electronic control device comprising a microcomputer including a first core and a second core having a first non-volatile memory includes a first startup step of starting the first core, an abnormality determination step of determining whether or not there is an abnormality in the microcomputer during the initialization process of the first core after the first startup step, and a second startup step of starting the second core after the abnormality determination step. If an abnormality in the microcomputer is detected in the abnormality determination step and the second startup step is not yet completed, the device includes a first step of starting the second core, and a second step of performing an interrupt process in the second core to enable writing to the first non-volatile memory and writing information regarding the abnormality of the microcomputer to the first non-volatile memory.

Description

Technical Field

[0001] The present disclosure relates to an electronic control device, and is particularly a technology effective when applied to a technique for recording abnormal information in an electronic control device.

Background Art

[0002] Japanese Unexamined Patent Application Publication No. 2020-144699 discloses a control device that, when detecting a sign of a stack overflow, records a detection history in a non-volatile memory area and determines that the reset is due to a stack overflow when there is a detection history at the time of recovery from a reset.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a microcomputer with a multi-core configuration mounted on an in-vehicle electronic control unit (ECU) is reset, if the reset cause is an abnormality during a periodic task, failure information is recorded in a non-volatile memory, enabling subsequent analysis of the reset cause. On the other hand, if the reset cause is during the initialization process before the periodic task, and the first core does not have a non-volatile memory, since the first core does not have a non-volatile memory, it is impossible to record the abnormal information of the first core, and subsequent analysis of the reset cause may be difficult.

[0005] The present disclosure aims to provide a technology that enables analysis of the reset cause during the initialization process of a first core without a non-volatile memory in a microcomputer with a multi-core configuration.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief overview of some of the representative disclosures is as follows:

[0008] According to one embodiment, an electronic control device comprising a microcomputer including a first core without non-volatile memory and a second core having a first non-volatile memory, A first startup step that starts the first core, After the first startup step, an abnormality determination step is performed to determine whether or not there is an abnormality in the microcomputer during the initialization process of the first core, The process includes, after the abnormality detection step, a second startup step of starting the second core, In the abnormality detection step, if an abnormality in the microcomputer is detected and the second startup step has not been completed, The first step is to start the second core, The second core includes a second step of performing an interrupt process that enables writing to the first non-volatile memory and writing information regarding an abnormality of the microcomputer to the first non-volatile memory. [Effects of the Invention]

[0009] According to the electronic control device of the above embodiment, a technology is provided that enables the analysis of reset factors during the initialization process of the first core. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 shows an example of the configuration of an electronic control unit including a microcomputer equipped with multiple cores (2 cores) according to the embodiment. [Figure 2] Figure 2 is a flowchart showing the startup process of the electronic control unit shown in Figure 1. [Figure 3]Figure 3 is a flowchart illustrating the process of recording the abnormalities identified in the abnormality detection 206 in Figure 2. [Figure 4] Figure 4 shows an example configuration of an electronic control unit including a microcomputer equipped with multiple cores (3 cores) according to Modification 1. [Figure 5] Figure 5 is a flowchart showing the startup process of the electronic control unit shown in Figure 4. [Figure 6] Figure 6 is a flowchart relating to Modification Example 2. [Modes for carrying out the invention]

[0011] Examples and modifications will be described below with reference to the drawings. However, in the following description, the same reference numerals will be used for the same components, and repeated explanations may be omitted. In addition, the drawings may be more schematic than the actual embodiments in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. [Examples]

[0012] Figure 1 shows an example configuration of an electronic control unit including a microcomputer equipped with multiple cores (2 cores) according to the embodiment. Figure 2 is a flowchart showing the startup of the electronic control unit in Figure 1. Figure 3 is a flowchart showing the process of recording the abnormality determined by abnormality detection 206 in Figure 2.

[0013] As shown in Figure 1, the electronic control unit 100 is composed of a microcomputer (referred to as a microcontroller) 101 having a first core 102 and a second core 106. Each of the first core 102 and the second core 106 includes an arithmetic processing unit such as a central processing unit (CPU).

[0014] The first core 102 includes a reset process 103 during initialization, a periodic control and reset process 105 during periodic processing, and a reset control 104 that controls the reset of the microcontroller 101.

[0015] The second core 106 includes an arithmetic processing unit, a recording processing unit, and a first non-volatile memory (referred to as the first NvM) 115. The arithmetic processing unit of the second core 106 includes an initialization process and a cycle control 107 during the periodic process.

[0016] The recording processing unit of the second core 106 includes a recording process (first recording process) 111 during normal processing and a recording process (second recording process) 112 during interrupt processing. The first NvM 115 includes a first recording area 113 that is a recording area during normal processing and a second recording area 114 that is a recording area during interrupt processing. The first recording area 113 is configured to record abnormal information during normal processing by the recording process 111 during normal processing. The second recording area 114 is configured to record information regarding an abnormality during interrupt processing by the recording process 112 during interrupt processing. The abnormality during interrupt processing is information regarding an abnormality at the time of initialization of the first core 102. The information regarding the abnormality at the time of initialization of the first core 102 includes information regarding the presence or absence of a reset of the microcomputer 101 (reset factor: reset determination reason).

[0017] When an abnormality occurs in the microcomputer 101 during the periodic process of the first core 102, an abnormality occurrence notification 108 is sent to the second core 106, and the recording process 111 is executed by an abnormality recording process command 110 via the cycle control 107, and the content of the abnormality (abnormal information) is recorded in the first recording area 113. Thereafter, a recording completion notification 109 is sent to the reset process 105 of the first core 102, and the microcomputer 101 is reset 104 by software.

[0018] When it is determined that the microcomputer 101 is abnormal in the abnormality determination process at the time of initialization of the first core 102, the second core 106 is started in a route different from the normal one (the method of storing abnormality information during the periodic processing of the first core 102 described above) (started by an interrupt request to the second core 106). Then, the recording process 112 of the interrupt process is performed by the abnormality recording process command 116, and the content of the abnormality is recorded in the second recording area 114. Thereafter, the microcomputer 101 is reset 210 (see FIG. 2). Here, the different route means that, for example, the first core 102 starts the second core 106 by an interrupt request transmitted by the reset process 103 during the initialization process of the first core 102. Thereafter, the started second core 106 executes an interrupt process to make the second recording area 114 writable. Thereafter, the second core 106 records (writes) the content of the abnormality (abnormality information: reset factor) at the time of initialization of the first core 102 in the second recording area 114 by the recording process 112 that receives the abnormality recording process command 116.

[0019] That is, in the abnormality determination step (step 206) at the time of initialization of the first core 102, when an abnormality of the microcomputer 101 is detected and the startup step of the second core 106 is not completed, the following steps are executed. 1) First step: The first core 102 starts the second core 106 by an interrupt request. 2) Second step: 2-1) Based on the reception of the interrupt request, the second core 106 executes an interrupt process to make the second recording area 114 of the first non-volatile memory writable. 2-2) Based on the abnormality recording process command 116, the second core 106 executes the recording process 112 to write information regarding the abnormality at the time of initialization of the microcomputer 101 in the second recording area 114 of the first non-volatile memory 115. 3) Third step: After the writing of information regarding an anomaly to the second recording area 114 of the first non-volatile memory 115 is completed, a recording completion notification 109 is sent to the reset process 103 of the first core 102, and the reset process 103 causes the microcontroller 101 to be reset 104 by software.

[0020] As a result, information regarding abnormalities during the initialization of the microcomputer 101 is written to the second recording area 114 of the first non-volatile memory 115 of the second core 106, making it possible to analyze the reset factors during the initialization process of the first core 102, which does not have non-volatile memory.

[0021] Furthermore, under normal circumstances, the first non-volatile memory 115 of the second core 106 is not writable, and therefore cannot record information regarding abnormalities in the microcontroller 101. However, interrupt processing enables the writing of abnormality information to the second recording area 114 of the first non-volatile memory 115. This allows the second core 106 to be forcibly started even if it is not running in the normal sequence, and abnormality information is written to the second recording area 114 of the first non-volatile memory 115. As a result, the abnormality information stored in the second recording area 114 can be retrieved later. This makes it possible to analyze the reset cause during the initialization process of the first core from the abnormality information stored in the second recording area 114.

[0022] Next, based on Figure 2, we will explain the steps (processes) for recording the details (information) of an anomaly.

[0023] The microcontroller 101 consists of a first core 102 and a second core 106. The microcontroller 101 starts up from the first core. The first core is started in core startup (step 203). Step 203 is the first startup step.

[0024] The first core 102, after undergoing FBL processing (step 204), performs microcontroller initialization and diagnostic activation (step 205), which enables the initialization of the first core 102 of the microcontroller 101 and the diagnostics during the initialization of the first core 102. FBL processing (step 204) is Flash Bootloader processing, which is started as the first software instance of the boot phase after reset. The Flash Bootloader then checks for the presence of a flash reprogramming request and whether valid application software exists. Depending on the result, if reprogramming of the electronic control unit 100 is required, it starts the reprogramming sequence. If reprogramming is not required, it proceeds to step 205.

[0025] The first core 102 checks whether there is an abnormality in step 205 (step 206: abnormality judgment step). If there is no abnormality (206: No), the first core 102 starts each core (in this case, the second core 106) in the Core startup step (step 207), and then proceeds to normal task processing (step 208) to process a normal task. If there is an abnormality (206: Yes), it proceeds to step 217, which will be described later.

[0026] The second core 106 is started by the core startup (step 211) of the first core 102, which is initiated by each core startup (step 207). Step 207 is the second startup step. Subsequently, the second core 106 proceeds through microcontroller initialization and diagnostic activation (step 212), which enables the initialization of the second core 106 and the diagnostics during the initialization of the second core 106 by the microcontroller 101, and DEM initialization (step 213), before transitioning to normal task processing (step 214), which processes normal tasks. Here, DEM (Diagnostic Event Manager) refers to a function that records fault information. In DEM initialization (step 213), the second core 106 initializes the contents of the first recording area 113 of the first non-volatile memory 115.

[0027] If an abnormality is detected during the normal Task processing (step 208) abnormality detection (step 209) or normal Task processing (step 214) abnormality detection (step 215), the details of the abnormality (information) are recorded in the first recording area 113 of the first non-volatile memory 115 of the second core 106 by the DEM NvM writing process (step 216). After that, a reset (step 210) is performed to software reset the microcontroller 101. As a result, the microcontroller 101 is reset, and the core startup (step 203) is executed again.

[0028] If an abnormality is detected during the initialization abnormality detection step (step 206: abnormality detection step), the first core 102 starts the second core 106 via a different route (steps 217-219) than the normal route (steps 211-213). Then, the details (information) of the abnormality are recorded in the second recording area 114 of the first non-volatile memory 115. After that, a reset (step 210) is performed to software reset the microcontroller 101.

[0029] (Step 217) The first core 102 starts the second core 106 via a different route than the normal route (steps 211-213). During this alternative route for starting the second core 106, microcontroller initialization and diagnostic activation (step 212) and DEM initialization (step 213) are not performed, and the first core 102 generates an interrupt request to the second core 106. This interrupt request is to make the second recording area 114 of the non-volatile memory 115 writable.

[0030] (Step 218) Based on the receipt of the interrupt request, the second core 106 executes an interrupt process that makes the second recording area 114 of the first non-volatile memory writable.

[0031] (Step 219) The second core 106, through recording processing 112, writes information regarding an abnormality during the initialization of the microcomputer 101 (the reason for the reset decision) to the second recording area 114 of the first non-volatile memory 115.

[0032] The process then proceeds to step 210. In step 210, a recording completion notification 109 is sent to the reset process 103 of the first core 102. The reset process 103 then resets the microcontroller 101 by software 104, and the core startup (step 203) is executed again.

[0033] This makes it possible to analyze the reset factors during the initialization process of the first core.

[0034] Figure 3 illustrates the process of recording the abnormality determined in step 206.

[0035] (Step 301) The anomaly recording flowchart is initiated on the second core, 106.

[0036] (Step 302) Initialize the abnormal record variable x (x=0).

[0037] (Step 303) Initialize the variable k, which is the test number used to count the number of tests (k=0).

[0038] x is treated as a bitmask, with the smallest bit of x being 0 (zero). If the kth smallest bit is 1, it indicates an anomaly in the item with check number k. Note that the range of k is 0 to N (an integer), and N must be less than or equal to the number of bits in x.

[0039] (Steps 304, 305) Check if there are any abnormalities in item k (inspection number k). If there are abnormalities (305: Yes), proceed to step 306. If there are no abnormalities (305: No), proceed to step 307.

[0040] (Step 306) The operation of adding 2^k to x (x = x + 2^k) is performed. This means that the k-th bit of x is set to 1.

[0041] (Step 307) Increment k (k = k + 1). If there is no abnormality in step 305 (305: No), skip step 306 and increment k.

[0042] (Step 308) Determine if all items have been checked (k>N?). If checked (308:Yes), proceed to step 309. If not checked (308:No), proceed to step 304 and check for any abnormalities in the item with the next check number (k+1).

[0043] (Step 309) Check if the abnormal record variable x is zero (0) (x=0?). If the abnormal record variable x is zero (0) (309:Yes), proceed to step 310 and continue processing. If the abnormal record variable x is not zero (0) (309:No), proceed to step 311.

[0044] (Step 310) Continue processing.

[0045] (Step 311) The second core 106 is started, and the second recording area 114 of the first non-volatile memory 115 is made writable. Then, the abnormal recording variable x is recorded in the second recording area 114.

[0046] The characteristics of the embodiment can be summarized as follows.

[0047] 1) In the abnormality detection step (step 206), if an abnormality is detected during the initialization process of the microcontroller 101 and the startup of the second core 106 has not been completed, the system includes steps 217 and 218 (referred to as the first step) to start the second core 106, and step 219 (referred to as the second step) to enable writing to the first non-volatile memory (115, 114) of the second core 106 and write information regarding the abnormality during the initialization process of the microcontroller 101 to the first non-volatile memory (115, 114) of the second core 106. Normally, the first non-volatile memory 115 of the second core 106 is not in a writable state and therefore cannot record information regarding the abnormality of the microcontroller 101, but the interrupt processing enables the writing of the abnormality. Therefore, even if the second core 106 is not started in the normal sequence, the system forcibly starts the second core 106 and writes information regarding the abnormality of the microcontroller 101. Therefore, it is possible to later read out the abnormal information from the first non-volatile memory (115,114) and analyze whether a reset occurred and what the cause was.

[0048] 2) After step 219 (the second step), there is further step 210 (referred to as the third step) which resets the microcontroller 101. By resetting the microcontroller 101, it may be possible to clear any abnormal states that occurred during the initialization process of the microcontroller 101.

[0049] 3) Information regarding abnormalities during the initialization process of the microcontroller 101 includes information regarding whether or not the microcontroller 101 was reset. This allows us to determine that if the microcontroller 101 is reset (step 210) and no abnormality information is recorded in the first non-volatile memory (115, 114), the reset of the microcontroller 101 was caused by an abnormality other than the microcontroller 101, such as a hardware abnormality. In other words, if the microcontroller 101 is reset (step 210) while the abnormality recording variable x explained in Figure 3 is not recorded, it can be determined that the cause is an abnormality other than the microcontroller 101, such as a hardware abnormality.

[0050] 4) The first non-volatile memory 115 includes a first recording area 113 where abnormal information is written during normal control, and a second recording area 114 which is different from the first recording area 113. Information regarding abnormalities during the initialization process of the microcontroller 101 is written to the second recording area 114. This ensures that information regarding abnormalities during the initialization process of the microcontroller 101 is written reliably, without being restricted by predetermined procedures or recording areas like Autosar.

[0051] 5) When the second core 106 is started by an interrupt handler (corresponding to steps 217-219), a startup process is performed that omits some processes, which differs from the normal startup sequence of the second core 106 (the normal startup sequence corresponds to steps 211-213). In other words, when the second core 106 is started by an interrupt handler (corresponding to steps 217-219), the core initialization and diagnostic activation (step 211) and DEM initialization (step 213) are omitted. This allows for the immediate writing of information regarding abnormalities during the initialization process of the microcontroller 101 to the second recording area 114 of the first non-volatile memory 115 of the second core 106.

[0052] (modified version) Although the embodiment described a microcomputer 101 having a first core 102 and a second core 106, this disclosure is also applicable when the number of cores provided in the microcomputer is three. Figure 4 is a diagram showing an example configuration of an electronic control device including a microcomputer equipped with multiple cores (3 cores) according to Modification 1. Figure 5 is a flowchart diagram of the startup of the electronic control device in Figure 4. Figure 6 is a flowchart diagram according to Modification 2.

[0053] (Variation 1) As shown in Figure 5, the electronic control unit 100a is composed of a microcomputer (referred to as a microcontroller) 101a having a first core 102, a second core 106, and a third core 401. Since the second core 106 and the third core 401 have the same configuration and function, Figure 4 schematically depicts the configuration of the third core 401. The third core 401 has an arithmetic processing unit, a recording processing unit, and a second non-volatile memory (referred to as the second NvM) 403, which are configured similarly to the second core 106. Note that the configuration and function of the first core 102 and the second core 106 are the same as described in Figures 1 and 2, so redundant explanations are omitted.

[0054] The arithmetic processing unit of the third core 401 includes initialization processing and periodic control during periodic processing. The recording processing unit of the third core 401 includes recording processing during normal processing (third recording processing) and recording processing during interrupt processing (fourth recording processing).

[0055] The second NvM403 has a third recording area 405, which is designated as a recording area during normal processing, and a fourth recording area 406, which is designated as a recording area during interrupt processing. The third recording area 405 is configured to record abnormal information during normal processing through recording processing during normal processing. The fourth recording area 406 is configured to record abnormal information during interrupt processing through recording processing during interrupt processing. An abnormality during interrupt processing is, for example, abnormal information during the initialization of the first core 102.

[0056] In the modified example, a scenario is assumed where some kind of abnormality occurs in the second core 106, preventing the writing of the abnormal information from the initialization of the first core 102 to the second recording area 114 of the first non-volatile memory 115 of the second core 106. In such a case, the configuration is such that the abnormal information from the initialization of the first core 102 is written to the fourth recording area 406 of the second NvM 403 provided in the third core 401.

[0057] Next, the startup flowchart will be explained using Figure 5. In Figure 5, steps identical to those in Figure 2 are numbered the same, and explanations that overlap with those in Figure 2 are omitted. The differences between the flowchart in Figure 5 and the flowchart in Figure 2 are the inclusion of step 502 and the provision of steps 517-519 in the third core 401, which are similar to steps 217-219 described in the second core 106. Although the third core 401 has steps similar to steps 211-216 described in the second core 106, these steps are omitted from Figure 5 for the sake of simplifying the diagram.

[0058] The following mainly explains the differences from the explanation in Figure 2.

[0059] (Step 206) In step 206, the first core 102 checks whether there is an abnormality in step 205. If there is no abnormality (206: No), the first core 102 proceeds to start each core (in this case, the second core 106 and the third core 401) in step 207, and then transitions to normal task processing (step 208), which processes a normal task. If there is an abnormality (206: Yes), it proceeds to step 502, which will be described later.

[0060] (Step 502) The first core 102 checks whether the second core 106 can be started by an interrupt request in order to execute steps 217-219 of the second core 106. If the second core 106 can be started (502: Yes), steps 217-219 and step 210 are executed sequentially, as in Figure 2. If the second core 106 cannot be started (502: No), the first core 102 makes an interrupt request to the third core 401 in order to execute steps 517-519 of the third core 401.

[0061] (Step 517) The first core 102 starts the third core 401 via a different route than the normal route (starting the third core 401 in steps 211-213 of Figure 2). In this alternative route for starting the third core 401, microcontroller initialization and diagnostic activation (corresponding to step 212) and DEM initialization (corresponding to step 213) are not performed, and the first core 102 generates an interrupt request to the third core 401. This interrupt request is to make the fourth recording area 406 of the second NvM 403 writable.

[0062] (Step 518) The third core 401, upon receiving an interrupt request, executes an interrupt process that makes the fourth recording area 406 of the second NvM 403 writable.

[0063] (Step 519) The third core 401, through interrupt handling and recording processing (corresponding to the recording processing 112 of the second core 106), writes information regarding an abnormality during the initialization of the microcomputer 101a (the reason for the reset decision) to the fourth recording area 406 of the second NvM 403.

[0064] The process then proceeds to step 210. In step 210, a recording completion notification 109 is sent to the reset process 103 of the first core 102. The reset process 103 then performs a software reset 104 on the microcomputer 101a, and the core startup (step 203) is executed again.

[0065] This makes it possible to analyze the reset factors during the initialization process of the first core.

[0066] (Modification 2) The flowchart relating to Modification 2 will be explained using Figure 6. The flowchart in Figure 6 is a modified version of the flowchart in Figure 5.

[0067] In the flowchart of Figure 5, a step 502 is provided to check whether the second core 106 is writable before it is started via an alternative route (interrupt request). On the other hand, the flowchart of Figure 6 is an example of a configuration in which, instead of providing step 502, the second core 106 is started via an alternative route (interrupt request: step 217), and a step 602 is provided to determine whether the operation of the started second core 106 is normal.

[0068] Step 602 starts the second core 106 via a separate route (interrupt request: step 217), performs a first determination in step 217 as to whether the second core 106 was actually started, a second determination in step 218 as to whether the second storage area 114 was actually made writable, and a third determination in step 219 as to whether information regarding the abnormality was actually written to the second storage area 114. If any of the first to third determinations result in a "no" (No), steps 517-519 of the third core 401 are executed.

[0069] The following mainly explains the differences from the explanation in Figure 5.

[0070] (Step 206) In step 206, the first core 102 checks whether there is an abnormality in step 205. If there is no abnormality (206: No), the first core 102 proceeds to start each core (in this case, the second core 106 and the third core 401) in step 207, and then transitions to normal task processing (step 208), which processes a normal task. If there is an abnormality (206: Yes), it proceeds to step 217.

[0071] (Step 217) The first core 102 starts the second core 106 via a different route than the normal route (steps 211-213). In this alternative route for starting the second core 106, microcontroller initialization and diagnostic activation (step 212) and DEM initialization (step 213) are not performed, and the first core 102 generates an interrupt request to the second core 106. This interrupt request is to make the second recording area 114 of the non-volatile memory 115 writable. Here, the first core 102 can be configured to start the operation of step 602 based on the generation of the interrupt request.

[0072] Step 602 performs a first determination based on the interrupt request to determine whether the second core 106 was actually able to start up. If the first determination is that it could not start up (No), proceed to step 517. If the first determination is that it could start up, proceed to step 218.

[0073] (Step 218) Based on the receipt of the interrupt request, the second core 106 executes an interrupt process that makes the second recording area 114 of the first non-volatile memory writable.

[0074] Step 602 performs a second determination to determine whether the second recording area 114 can be made writable. If the second determination determines that it cannot be made writable (No), proceed to step 517. If the second determination determines that it can be made writable, proceed to step 219.

[0075] (Step 219) The second core 106, through recording processing 112, writes information regarding an abnormality during the initialization of the microcomputer 101 (the reason for the reset decision) to the second recording area 114 of the first non-volatile memory 115.

[0076] Step 602 performs a third determination to determine whether or not the information regarding the anomaly could be written to the second recording area 114. If the third determination is that the writing was unsuccessful (No), the process proceeds to step 517. If the third determination is that the writing was successful (Yes), the process proceeds to step 210.

[0077] Subsequently, the process proceeds to step 210. In step 210, a recording completion notification 109 is sent to the reset process 103 of the first core 102. The reset process 103 then performs a software reset 104 on the microcomputer 101a, and the core startup (step 203) is executed again. This makes it possible to analyze the reset cause during the initialization process of the first core.

[0078] If the answer in step 602 is No, then steps 517, 518, and 519 are executed, as described in Modification 1. After that, the process proceeds to step 210, in which the microcomputer 101a is reset by software 104, and the core startup (step 203) is executed again.

[0079] This makes it possible to analyze the reset factors during the initialization process of the first core.

[0080] The modifications can be summarized as follows:

[0081] 1) The microcontroller 101 further includes a third core 401 having a second non-volatile memory 403. If the interrupt processing in the first step (steps 217, 218) cannot be performed in the second core 106, there are steps 517, 518 (referred to as the fourth step) to start the third core 401, and step 519 (referred to as the fifth step) to perform interrupt processing that enables writing to the fourth recording area 406 of the second non-volatile memory 403 of the third core 401, and to write information regarding an abnormality during the initialization process of the microcomputer 101a (reset factor) to the second non-volatile memory (403, 406) of the third core 401.

[0082] In other words, the system checks whether interrupt processing is possible in the second core 106 (step 502), and if it is determined that it is not possible (502: No), it performs interrupt processing on the third core 401 instead of the second core 106, starts the core (steps 517, 518), and writes information about the abnormality during the initialization process of the first core to the second non-volatile memory (403, 406) of the third core 406 (step 519).

[0083] As a result, even if it is not possible to write information regarding an anomaly during the initialization process of the first core to the first non-volatile memory (115,114) of the second core 106, it is possible to record information regarding the anomaly during the initialization process of the first core (reset cause) in the second non-volatile memory (403,406) of the third core 406.

[0084] The disclosure made by the Discloser has been described in detail above based on examples and modifications, but it goes without saying that the disclosure is not limited to the above examples and modifications and can be modified in various ways. [Explanation of symbols]

[0085] 100: Electronic control unit 101, 101a: Microcomputer (microcontroller) 102: First Core 106: Second Core 113: First recording area 114: Second recording area 115: First non-volatile memory 401: Third Core 403: Second non-volatile memory 405: Third recording area 406: Fourth recording area

Claims

1. An electronic control device comprising a microcomputer including a first core without non-volatile memory and a second core having a first non-volatile memory, A first startup step that starts the first core, After the first startup step, an abnormality determination step is performed to determine whether or not there is an abnormality in the microcomputer during the initialization process of the first core, The abnormality detection step is followed by a second startup step of starting the second core, In the abnormality detection step, if an abnormality in the microcomputer is detected and the second startup step has not been completed, The first step is to start the second core, An electronic control device comprising: a second step of performing an interrupt process in the second core to enable writing to the first non-volatile memory, and writing information regarding an abnormality of the microcomputer to the first non-volatile memory.

2. In the electronic control device according to claim 1, An electronic control device further comprising a third step of resetting the microcomputer after the second step.

3. In the electronic control device according to claim 1, An electronic control device that includes information regarding abnormalities in the microcomputer, including information regarding whether or not the microcomputer has been reset.

4. In the electronic control device according to claim 1, The first non-volatile memory includes a first recording area on which abnormal information is written during normal control, and a second recording area different from the first recording area. An electronic control device in which information regarding the malfunction of the microcomputer is written to the second recording area.

5. In the electronic control device according to claim 1, An electronic control device in which, when the second core is started by the interrupt processing, a startup process is performed in which some processing that differs from the normal startup sequence of the second core is omitted.

6. In the electronic control device according to claim 1, The microcomputer further comprises a third core having a second non-volatile memory, If the first step cannot be performed in the second core, the fourth step is to start the third core, An electronic control device comprising: a fifth step of performing an interrupt process that enables writing to the second non-volatile memory, and writing information regarding the abnormality of the microcomputer to the second non-volatile memory.

7. In the electronic control device according to claim 6, The second non-volatile memory includes a third recording area where abnormal information is written during normal control, and a fourth recording area different from the third recording area. An electronic control device in which information regarding the malfunction of the microcomputer is written to the fourth recording area.

Images