Recording head and data recognition method

Abstract

The present invention provides a recording head that can update eigenvalues ​​while suppressing increases in memory capacity and head size. [Solution] The recording head 810 has a memory section 20 configured using a fuse element or an antifuse element. The memory section 20 has a main memory circuit M0 for storing eigenvalues ​​related to the recording head 810, and correction memory circuits M1 and M2 for storing correction values ​​for updating the eigenvalues.

Description

Technical Field

[0001] The present invention relates to a recording head including a memory configured using a fuse element or an anti-fuse element, and a data recognition method.

Background Art

[0002] Among recent recording heads, there are some equipped with an OTP (One Time Programmable) memory in order to store product-specific information such as a serial number and parameters for driving the recording head after the product is completed. As the OTP memory, memories using a fuse element or an anti-fuse element are known. Patent Document 1 describes a recording head including a memory using an anti-fuse element. At the time of manufacturing the recording head, the driving conditions of the head are stored in the memory as information (unique value) specific to the recording head. As related art of the OTP memory, Patent Document 2 describes an electric circuit in which a fuse element and an anti-fuse element are combined to enable rewriting of 1-bit (binary) information a plurality of times.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the recording head described in Patent Document 1, the memory using an antifuse element cannot be rewritten, and therefore the eigenvalues ​​stored in the memory (e.g., head drive conditions) cannot be updated. For this reason, if the head drive conditions change, for example, the performance of the recording head may deteriorate. However, by providing a separate OTP memory to store the updated eigenvalues, the performance deterioration of the recording head can be suppressed. However, in this case, the addition of the OTP memory creates the problem of increasing the memory capacity.

[0005] Furthermore, if a rewritable memory circuit described in Patent Document 2 is used as the memory for storing eigenvalues, the eigenvalues ​​can be updated. However, in this case, the circuit becomes more complex, and the area required to form the memory increases. As a result, the recording head becomes larger, which is a problem.

[0006] The object of the present invention is to provide a recording head that can update eigenvalues ​​while suppressing an increase in memory capacity and head size. [Means for solving the problem]

[0007] A recording head according to one aspect of the present invention is a recording head having a memory section configured using a fuse element or an antifuse element, wherein the memory section comprises a main memory circuit for storing eigenvalues ​​relating to the recording head and at least one correction memory circuit for storing correction values ​​for updating the eigenvalues. [Effects of the Invention]

[0008] According to the present invention, it is possible to suppress increases in memory capacity and head size, and update eigenvalues. [Brief explanation of the drawing]

[0009] [Figure 1] This is a perspective view showing the schematic configuration of a recording device to which the recording head of the present invention can be attached. [Figure 2]Figure 1 is a perspective view of the recording head mounted on the recording device shown. [Figure 3] This is a schematic diagram illustrating a recording head according to a first embodiment of the present invention. [Figure 4] This is a schematic diagram illustrating an example of a memory circuit that stores eigenvalues. [Figure 5] This is a schematic diagram showing the state of the memory circuit after the rank value has been written. [Figure 6] This flowchart shows an example of data recognition processing. [Figure 7] This is a schematic diagram showing the state of the memory circuit used for correction during the first reuse. [Figure 8] This is a schematic diagram showing the state of the memory circuit used for correction during the second reuse. [Figure 9] This is a schematic diagram showing an example of a memory circuit that stores concentration rank values. [Figure 10] This is a schematic diagram showing an example of a memory circuit that stores correction values ​​for concentration rank values. [Figure 11] This is a schematic diagram illustrating a recording head according to a third embodiment of the present invention. [Figure 12] This is a schematic diagram showing an example of a memory circuit for correction. [Figure 13] This flowchart shows an example of data recognition processing. [Figure 14] This is a schematic diagram illustrating a recording head according to a fourth embodiment of the present invention. [Figure 15] This is a schematic diagram showing an example of a memory circuit for correction. [Figure 16] This is a schematic diagram showing the state of the memory circuit used for correction during the second reuse. [Figure 17] This flowchart shows an example of data recognition processing. [Modes for carrying out the invention]

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the embodiments are merely examples and are not intended to limit the scope of the present invention to those embodiments. In each drawing, components having the same function may be denoted by the same reference numerals, and the description thereof may be omitted.

[0011] (First Embodiment) FIG. 1 is a perspective view showing a schematic configuration of a recording apparatus to which a recording head of the present invention can be attached. The recording apparatus 900 includes a recording control unit (not shown). The recording control unit controls the operation of each component of the recording apparatus 900 according to an electrical signal such as recording data from the outside. The recording apparatus 900 has a recording head 810 that discharges a liquid such as ink as a component. The recording head 810 performs recording, for example, according to an inkjet method. The recording head 810 is mounted on a carriage 920. The carriage 920 is attached to a lead screw 904 having a spiral groove 921. By rotating the lead screw 904, the recording head 810 can move along the guide 919 in the direction of arrow a or arrow b together with the carriage 920. A carriage substrate (not shown) for electrically connecting to a contact pad of the recording head 810 described later is mounted on the carriage 920. The recording paper P is conveyed onto the platen 906 by a paper conveyance unit (not shown). The paper pressing plate 905 presses the recording paper P against the platen 906 along the carriage movement direction. Recording on the recording paper P is performed by repeating the reciprocating movement of the recording head 810 and the conveyance of the recording paper P.

[0012] FIG. 2 is a perspective view of the recording head 810 mounted on the recording apparatus 900 shown in FIG. 1. A plurality of ejection ports 813 for ejecting a liquid are formed in a row on the element substrate 100. Various circuits (not shown) including an energy generating element (hereinafter also referred to as a heater) for generating ejection energy for ejecting the liquid from the ejection ports are formed on the element substrate 100. The element substrate 100 is electrically connected to a contact pad 815 for electrically connecting to the recording apparatus 900 via a flexible film wiring substrate 814.

[0013] The recording head 810 includes an ink tank 812. The ink tank 812 has, for example, a fibrous or porous ink-retaining material (not shown), which holds the ink. The recording head 810 receives electrical signals from the carriage substrate mounted on the carriage 920 via a contact pad 815 and ejects ink according to these electrical signals. Although the recording head 810 shown in Figure 2 has an integrated configuration of the element substrate 100 and the ink tank 812, it is also possible to have a configuration in which the ink tank can be separated.

[0014] In order to eject ink from the ejection port 813, the heater needs to be energized. However, since there are individual differences in the element substrate 100, the optimal energy for ejection differs for each element substrate 100. To adjust this ejection energy, two parameters are used: the voltage applied to the heater and the time the heater is energized. In the recording device 900, the voltage applied to the heater is kept constant, and the energizing time is adjusted. However, since the energizing time is relatively short, it is preferable to manage the energizing time using the pulse width of the electrical signal. Hereafter, this pulse width will be referred to as the drive pulse width. Alternatively, a method in which the energizing time is kept constant and the applied voltage is adjusted, or a method in which both the applied voltage and the energizing time are adjusted may also be applied.

[0015] Figure 3 is a schematic diagram illustrating the configuration of a recording head 810 according to a first embodiment of the present invention. In Figure 3, the electrical connection between the main body 900a of the recording device 900 and the element substrate 100 of the recording head 810 is schematically shown. The main body 900a of the recording device 900 includes a control unit 10. The control unit 10 includes a constant current circuit 201, a voltage detection circuit 202, a constant voltage circuit 203, a memory control circuit 204, a heater control circuit 151, a heater power supply generation circuit 152, a driver drive power supply generation circuit 153, and a logic power supply circuit 154. Details of these circuits will be described later.

[0016] The element substrate 100 includes a memory section 20, a heater circuit 101, a heater shift register 102, and a memory shift register 110. The memory section 20 is constructed using a fuse element or an antifuse element and includes a memory circuit (initial value) M0, a memory circuit (correction 1) M1, and a memory circuit (correction 2) M2. The memory circuit M0 can be called the main memory circuit. Both memory circuits M1 and M2 can be called correction memory circuits. In the heater circuit 101, a combination of a heater and a driver (heater driver) (not shown) is formed corresponding to each discharge port 813. In this embodiment, the number of discharge ports 813 is 512, and the number of heater and heater driver combinations is 512.

[0017] The heater shift register 102 is configured to select which heater to energize from among the heaters in the heater circuit 101. The heater control circuit 151 outputs a data signal DATAH to the heater shift register 102 so that the desired heater is energized. This data signal DATAH is synchronized with the timing signal CLK. The same signal used as the timing signal CLK is the same signal used for the memory control circuit 204, which will be described later. After the data output to the heater shift register 102 for energizing the desired heater is complete, the latch signal LTH is turned ON to hold the data and the operation of each heater driver is switched.

[0018] The heater circuit 101 has two power supply inputs in addition to the signal input from the heater shift register 102: one is the heater power supply VH, and the other is the driver power supply VHT. The heater power supply generation circuit 152 generates the heater power supply VH, and the driver drive power supply generation circuit 153 generates the driver power supply VHT. The operation of the heater driver is switched using the latch signal LTH, and the driver power supply VHT is supplied to that heater driver. In this embodiment, the driver power supply VHT is set to 5 volts. The heater power supply VH for the current that flows when the heater is energized is set to 24 volts. In addition, the logic power supply circuit 154 supplies power supply VDD to all logic elements formed on the element substrate 100. In this embodiment, power supply VDD is set to 3.3 volts.

[0019] The memory shift register 110 is an element that switches data to turn on / off transistors that operate when writing data to or reading data from memory circuits M0 to M2. Details of the memory shift register 110 will be described later.

[0020] Memory circuit M0 is for storing information (eigenvalues) specific to the recording head 810. Memory circuits M1 and M2 are used when updating eigenvalues, and store correction values ​​for updating the eigenvalues. Memory circuits M0 and M2 all consist of OPT memory using fuse elements or antifuse elements. The memory capacity of memory circuits M1 and M2 is smaller than the memory capacity of memory circuit M0.

[0021] Here, we will explain in detail an example of the eigenvalues ​​and correction values ​​of the recording head 810. Since the reuse of the recording head 810 is gaining attention from an environmental protection perspective, the following section will specifically explain the eigenvalues ​​and correction values ​​using such reuse as an example.

[0022] When a newly manufactured recording head 810 is shipped, a dedicated inspection device is used to measure the optimal ejection energy, i.e., the drive pulse width, and this information is stored as an intrinsic value in the memory circuit M0. For example, the drive pulse width is managed using multiple rank values, and the optimal rank value among these rank values ​​is stored as an intrinsic value in the memory circuit M0 based on the measurement results. The memory circuit M0 is configured to store the number of bits of information (bit data) necessary to store the rank value. In this embodiment, the drive pulse width is managed using rank values ​​from 1 to 255. In this case, the memory circuit M0 has the number of bits necessary to store 255 different pieces of information, i.e., a capacity of 8 bits.

[0023] A recording head 810 that has used up the ink it was filled with during manufacturing can be reused by cleaning the inside of the recording head 810 and refilling it with ink (first reuse). At this time, the optimal driving conditions for the reused recording head 810 may differ from the optimal driving conditions at the time of head manufacturing. For this reason, even during the first reuse, the optimal ejection energy (driving pulse width) is measured using a dedicated inspection device to obtain the optimal rank value. Then, the amount of change in the optimal rank value at the time of reuse relative to the optimal rank value at the time of head manufacturing, that is, the amount of change from before to after the update of the eigenvalue, is stored in the memory circuit M1 as a correction value (correction 1).

[0024] After the first reuse, the recording head 810, having used up all the ink it was filled with, can be reused again by cleaning the inside of the recording head 810 and refilling it with ink (second reuse). At this time, the optimal driving conditions for the reused recording head 810 may differ from the optimal driving conditions for the first reuse. Therefore, during the second reuse, a dedicated inspection device is used to measure the optimal ejection energy (driving pulse width) and obtain the optimal rank value. The amount of change in the optimal rank value during the second reuse relative to the optimal rank value calculated during the first reuse, i.e., the change in the eigenvalue from before to after the update, is stored in the memory circuit M2 as a correction value (correction 2).

[0025] Furthermore, regarding the timing of saving the correction values ​​to memory circuits M1 and M2, it is preferable to obtain the latest rank value during the inspection process performed between refilling the ink and re-shipping, and save the difference between that and the previously calculated optimal rank value as bit data.

[0026] In this embodiment, both the memory circuit M1 used during the first reuse and the memory circuit M2 used during the second reuse have a capacity to store 2 bits of information (bit data). The reason for this is briefly explained below.

[0027] It has been found that the optimal drive pulse width for the recording head 810 is the same or slightly shorter between the time of new manufacture and the first reuse, and between the first reuse and the second reuse. For example, when the heater is repeatedly energized when ejecting ink droplets, the film on the surface of the heater is gradually worn away. As the film on the surface of the heater is worn away, the heat from the heater is more easily transferred to the ink. Therefore, as the film on the surface of the heater is worn away, the optimal drive pulse width for ejection shortens accordingly. However, the change in drive pulse width varies depending on the type of ink used and the material of the film. In the recording head 810 of this embodiment, the change in the rank value of the drive pulse width is set to a maximum of 3 ranks per reuse. The number of bits in memory circuits M1 and M2 is set to 2 so that a correction value showing a change of up to 3 ranks can be stored. Note that the rank value increases as the drive pulse width shortens.

[0028] Furthermore, although this embodiment describes the reuse process as being performed twice, the number of reuses is not limited to two and may be any number of times. If reuse is performed three or more times, a memory circuit for storing the correction value should be provided for each reuse. In other words, the same number of correction memory circuits as the number of reuses should be provided. In this case, the capacity of the correction memory circuit for each reuse should be smaller than the capacity of the main memory circuit M0. Furthermore, although only memory circuits M0 to M2 are shown in Figure 3, memory circuits (OTP memory) that store various unique values ​​such as serial numbers and other rank values ​​may also be provided.

[0029] Next, we will explain the specific configurations of memory circuits M0 to M2. Note that memory circuits M1 and M2 have the same configuration as memory circuit M0, except for the number of elements within the circuit. Therefore, we will explain the configuration of memory circuit M0 in detail, and omit detailed explanations of memory circuits M1 and M2.

[0030] Figure 4(a) is a schematic diagram illustrating one example configuration of the memory circuit M0. This memory circuit M0 consists of eight antifuse elements A01 to A08 connected in parallel, and is configured to store 8 bits of data. Antifuse elements A03 to A07 are omitted from the illustration. Antifuse elements A01 to A08 are all in their initial non-conductive state.

[0031] One end of the antifuse element A01 is connected to terminal IM, and the other end of the antifuse element A01 is grounded via transistor J01. Transistor J01 is, for example, a MOS (metal-oxide-semiconductor) type FET (field-effect transistor). One terminal (source or drain) of transistor J01 is connected to the antifuse element A01, and the other terminal of transistor J01 is at ground potential (GND). A drive voltage conversion element K01, which generates the drive voltage for transistor J01, is connected to the gate terminal of transistor J01. When the voltage value supplied to the gate terminal exceeds a threshold, transistor J01 transitions from a non-conductive state to a conductive state. When transistor J01 becomes conductive, the power supply voltage supplied to terminal IM is applied to the antifuse element A01.

[0032] Antifuse elements A02 to A08 have the same structure as antifuse element A01, with one end connected to terminal IM and the other end grounded via transistors J02 to J08. Drive voltage conversion elements K02 to K08, which generate the driving voltage for transistors J02 to J08, are connected to the gate terminals of transistors J02 to J08. Transistor J01 and drive voltage conversion element K01 constitute driver circuit D01. Similarly, transistors J02 to J08 and drive voltage conversion elements K02 to K08 each constitute driver circuits D02 to D08. Note that transistors J03 to J07, drive voltage conversion elements K03 to K07, and driver circuits D03 to D07 are not shown in the diagram.

[0033] Both memory circuits M1 and M2 are equipped with two each of the antifuse element A, transistor J, and drive voltage conversion element K that constitute memory circuit M0, and are configured to store 2 bits of data.

[0034] In the memory circuits M0 to M2 described above, data can be written by selectively making the antifuse element A conduct. The conduction of the antifuse element A can be performed by a dedicated device or by the recording device 900. To make the antifuse element A conduct, the transistor J connected to the antifuse element A is turned ON, and a high voltage is applied between the two electrodes constituting the antifuse element A. This causes dielectric breakdown of the gate oxide film between the two electrodes, resulting in a conductive state. To turn ON the desired transistor J, the memory shift register 110 is controlled, and the signal level of the drive voltage conversion element K connected to the target transistor J is set to High.

[0035] As an example, the procedure for making the antifuse element A01 of the memory circuit M0 shown in Figure 4(a) conduct is described. In the recording device 900, the constant voltage circuit 203 supplies a DC voltage of 24 volts to the terminal IM of the memory circuit M0 via the contact pad 815. Subsequently, the memory control circuit 204 outputs a data signal DATAM and a latch signal LTM to the memory shift register 110. The memory control circuit 204 controls the drive voltage conversion element K01 in the memory circuit M0 to be at a high level, and the drive voltage conversion elements K02 to K08 to be at a low level. As a result, only transistor J01 is turned ON, and the 24 volt voltage supplied to terminal IM is applied to the antifuse element A01. If this voltage application is rapidly switched ON / OFF, the antifuse element A01 will become conduction. In this embodiment, the antifuse element A01 is made conduction by repeatedly switching the voltage application ON / OFF at a frequency of 6 MHz. While the average number of ON / OFF cycles required to activate an antifuse element is said to be 10,000, there are individual differences in antifuse elements, and in some cases, it may take 60,000 ON / OFF cycles to activate it. Therefore, in this embodiment, the number of ON / OFF cycles of voltage application is set to a maximum of 60,000.

[0036] In the above operation description, the constant voltage circuit 203 supplies a DC voltage of 24 volts to terminal IM of the memory circuit M0, but this is not the only way. Since the driver power supply generation circuit 153 also outputs a DC voltage of 24 volts, the driver power supply generation circuit 153 may be used instead of the constant voltage circuit 203. In this case, the constant voltage circuit 203 can be omitted.

[0037] Next, a method for reading whether the antifuse element A is conducting or not in the memory circuits M0 to M2 described above will be explained. This reading of the state of the antifuse element A can be performed using a dedicated device or the recording device 900.

[0038] As an example, we will explain how to read the states of antifuse elements A01 to A08 in the memory circuit M0 shown in Figure 4(a). Since only one antifuse element can be read in a single reading operation, the states of antifuse elements A01 to A08 are read sequentially in eight separate operations.

[0039] To read the state of the antifuse element A01, transistor J01 must be turned ON. In the recording device 900, the memory control circuit 204 outputs a signal to the memory shift register 110. The memory control circuit 204 controls the voltage conversion element K01 to be at a High level and the drive voltage conversion elements K02 to K08 to be at a Low level. Next, the constant current circuit 201 supplies a constant current to terminal IM, and the voltage detection circuit 202 measures the voltage at terminal IM and determines whether the measured voltage is the same as the voltage at terminal GND. If the voltage at terminal IM is the same as the voltage at terminal GND, it can be determined that the antifuse element A01 is conducting. On the other hand, if the antifuse element A01 is not conducting, the constant current circuit 201 will always operate to supply current, which may cause the constant current circuit 201 to fail. In this embodiment, a limiter function is provided to avoid failure of the constant current circuit 201. This limiter function has a limit voltage set to prevent the internal voltage of the constant current circuit 201 from rising above a certain level. When the internal voltage reaches the limit voltage, the output of the constant current circuit 201 is stopped. When the limiter function is activated, it can be determined that the antifuse element A01 is in a non-conductive state.

[0040] The status of antifuse elements A02 to A08 can be read using the same procedure as for reading the status of antifuse element A01.

[0041] Figure 4(b) is a schematic diagram illustrating another configuration example of the memory circuit M0. This memory circuit M0 consists of eight fuse elements F01 to F08 connected in parallel, and is configured to store 8 bits of data. Fuse elements F03 to F07 are omitted from the illustration. All fuse elements F01 to F08 are in their initial conductive state.

[0042] One end of fuse element F01 is connected to terminal IM, and the other end of fuse element F01 is grounded via transistor J11. Fuse elements F02 to F08 have the same structure as fuse element F01, with one end connected to terminal IM and the other end grounded via transistors J12 to J18. Transistors J11 to J18 are the same as those shown in Figure 4(a). Drive voltage conversion elements K11 to K18, which generate the driving voltage for transistors J11 to J18, are connected to the gate terminals of transistors J11 to J18. Drive voltage conversion elements K11 to K18 are the same as those shown in Figure 4(a) as K01 to K08. Transistor J11 and drive voltage conversion element K11 constitute driver circuit D01. Similarly, transistors J12 to J18 and drive voltage conversion elements K12 to K18 constitute driver circuits D02 to D08, respectively. Note that transistors J13-J17, drive voltage conversion elements K13-K17, and driver circuits D03-D07 are omitted from the diagram.

[0043] Both memory circuits M1 and M2 are equipped with two fuse elements F, two transistors J, and two drive voltage conversion elements K that constitute memory circuit M0, and are configured to store 2 bits of data.

[0044] In the memory circuits M0 to M2 described above, data can be written by selectively disconnecting the fuse element F. Disconnecting the fuse element F can be done using a dedicated device or the recording device 900. To disconnect the fuse element F, the transistor J connected to the fuse element F is turned ON, causing a large current to flow through the fuse element F. When a large current flows through the fuse element F, the fuse element F heats up and then melts.

[0045] As an example, the procedure for disconnecting the fuse element F02 of the memory circuit M0 shown in Figure 4(b) will be described. In the recording device 900, the constant voltage circuit 203 supplies a DC voltage of 24 volts to the terminal IM of the memory circuit M0 via the contact pad 815. Subsequently, the memory control circuit 204 outputs a data signal DATAM and a latch signal LTM to the memory shift register 110. The memory control circuit 204 controls the drive voltage conversion element K12 in the memory circuit M0 to be at a high level, while the drive voltage conversion elements K11, K13~K08 are at a low level. As a result, only the transistor J12 turns ON, and the 24 volt voltage supplied to terminal IM is applied between both terminals of the fuse element F02. Because the resistance value of the fuse element F02 is very small, a large current flows through the fuse element F02. As a result, the fuse element F02 heats up and melts. In this embodiment, all of the fuse elements F01~F08 are configured to melt when a current of 70 milliamperes or more flows through them. In this case as well, the driver power supply generation circuit 153 may be used instead of the constant voltage circuit 203.

[0046] In the memory circuits M0 to M2 described above, the procedure for reading whether the fuse element F is conducting or not is basically the same as the procedure for reading the state of the antifuse element A described earlier. To avoid repetition, the explanation for reading the state of the fuse element F will be omitted.

[0047] The above describes the specific configuration, data writing method, and data reading method of memory circuits M0 to M2.

[0048] Next, we will specifically explain the data stored in the memory circuit M0. In the following explanation, we will use the memory circuit M0 shown in Figure 4(a) as an example and assume that the rank value of the drive pulse width measured when the recording head 810 was newly manufactured is "200".

[0049] Figure 5 schematically shows the state when the rank value "200" is written to the memory circuit M0. The memory circuit M0 stores binary data based on the conduction / non-conduction state of antifuse elements A01 to A08. Specifically, antifuse element A01 is the most significant bit and A08 is the least significant bit, with a conduction state being "1" and a non-conduction state being "0". The memory circuit M0 stores the decimal rank value "200" as the 8-bit binary number "11001000". In this case, antifuse elements A01, A02, and A05 are in a conduction state, and antifuse elements A03, A04, and A06 to A08 are in a non-conduction state.

[0050] Next, we will describe the data recognition process in which the recording device 900 reads the state of memory circuits M0 to M2 and recognizes the rank value of the drive pulse width. Here, we assume that the recording head 810 is newly manufactured and that "200" is stored in memory circuit M0 as the initial value of the drive pulse width rank, as shown in Figure 5. Also, since no reuse has been performed, we assume that both memory circuits M1 and M2 are in their initial state (all antifuse elements A are in a non-conductive state), that is, all bits of data are "0".

[0051] Figure 6 is a flowchart of the data recognition process in which the control unit 10 of the recording device 900 recognizes the rank value of the drive pulse width stored in the memory circuit M (M0 to M2). Figure 6(a) is the flowchart of the entire recognition process (hereinafter referred to as the main flow), and Figure 6(b) is a detailed flowchart for reading each bit data in the memory circuit M (M0 to M2).

[0052] First, in step S1, the control unit 10 reads the data stored in the memory circuit M. Here, it reads whether each bit of the 8-bit data stored in the memory circuit M0 is "0" or "1". Since the method for reading a single bit has already been described, we will now explain how to read all the bits in the memory.

[0053] In step S11, the bit to be read is determined. Since only one bit can be read in a single reading operation, the bits are read one by one from the leftmost bit of the memory circuit M0. In step S11, the state of the antifuse element A01, which is the leftmost bit, is read first. The memory control circuit 204 outputs a signal to the memory shift register 110, setting only the drive voltage conversion element K01 to a high level, and setting all the drive voltage conversion elements K02~K08 and the drive voltage conversion elements K of the memory circuits M1 and M2 to a low level. As a result, only the transistor J01 connected to the antifuse element A01 turns ON.

[0054] Next, in step S12, the constant current circuit 201 supplies a constant current to terminal IM. In this embodiment, a current of 20 microamperes is supplied. In this state, in step S13, the voltage detection circuit 202 measures the voltage to determine whether the voltage at terminal IM is the same as the voltage at terminal GND. If the voltage at terminal IM is approximately the same as the voltage at terminal GND, the bit is "1" (the antifuse element A01 is conducting); otherwise, the bit is "0". After the voltage measurement, in step S14, the constant current output from the constant current circuit 201 is stopped. The data read here, indicating whether each bit's data is "0" or "1", is stored in the memory unit (not shown) of the recording device 900.

[0055] Next, in step S15, it is determined whether the read bit is the rightmost bit. If it is the rightmost bit, the process returns to the main flow; otherwise, step S16 sets the next bit to be read. At this point in the explanation, the read bit is not the rightmost bit, so the process proceeds to step S16, where the memory control circuit 204 controls the memory shift register 110 so that the next bit to be read is the bit one position to the right (in this case, the second bit from the left). Then, the process returns to step S12 and reads the second bit from the left. This process is repeated until the rightmost bit has been read, and once the rightmost bit has been read, the process returns to the main flow.

[0056] Returning to the main flow, in step S2, the actual rank value stored in the memory circuit M0, which was read in step S1, is recognized. In step S1, the stored data, read bit by bit from the leftmost bit to the rightmost bit, is recognized as an 8-bit value. Since the read data is 1·1·0·0·1·0·0·0 from the leftmost bit, these are recognized as the 8-bit binary data "11001000", and the rank value in decimal is recognized as "200".

[0057] Next, in step S3, the data stored in memory circuit M1 is read. The data reading process is as described in step S1, following the memory bit data reading flow in Figure 6(b). Two bits of data are read from memory circuit M1. At this point in the explanation, no reuse has been performed, so memory circuit M1 is in its initial state (all bits are "0"). Therefore, the change from the first reuse in the next step S4 is recognized as "0".

[0058] Next, in step S5, the data stored in memory circuit M2 is read. The data reading process is as described in step S1, following the memory bit data reading flow in Figure 6(b). Two bits of data are read from memory circuit M2. At this point in the explanation, no reuse has been performed, so memory circuit M2 is in its initial state (all bits are "0"). Therefore, the change from the second reuse in the next step S6 is recognized as "0".

[0059] Finally, in step S7, the rank value is calculated based on the data (eigenvalues, correction values) recognized in steps S2, S4, and S6. At this point in the explanation, reuse has not been performed, so the initial value "200" recognized in step S2 is recognized as the rank value of the drive pulse width.

[0060] Next, we will explain the operation of the recording head 810 after its first reuse. Here, we will assume that the rank value of the drive pulse width at the time of manufacture (initial value) is "200," and that the rank has changed to "202" after one reuse.

[0061] Figure 7 schematically shows the state of memory circuits M1 and M2 during the first reuse. Figure 7(a) shows the state of memory circuit M1, and Figure 7(b) shows the state of memory circuit M2. Memory circuit M1 is a 2-bit memory with two antifuse elements A11 and A12 connected in parallel. Antifuse elements A11 and A12 are connected to the GND terminal via driver circuits D11 and D12, respectively. Antifuse elements A11 and A12 and driver circuits D11 and D12 have the same structure as antifuse element A and driver circuit D of memory circuit M0 shown in Figure 4(a). Memory circuit M2 is also a 2-bit memory with two antifuse elements A21 and A22 connected in parallel. Antifuse elements A21 and A22 are connected to the GND terminal via driver circuits D21 and D22, respectively. The antifuse elements A21 and A22 and the driver circuits D21 and D22 have the same structure as the antifuse element A and driver circuit D of the memory circuit M0 shown in Figure 4(a).

[0062] During the first reuse, the drive pulse width is measured, and the difference (change) between its rank value and the initial value ("200") is stored as a correction value in memory circuit M1. Here, the optimal drive pulse width rank during the first reuse is "202," which is "2" greater than the initial value of "200." The decimal number "2" is represented as "10" in binary. Of the two bits in memory circuit M1, the upper bit is antifuse element A11, and the lower bit is antifuse element A12. Therefore, antifuse element A11 is in a conducting state, and antifuse element A12 is in a non-conducting state. Since the second reuse has not been performed, memory circuit M2 is in its initial state (antifuse elements A21 and A22 are non-conducting), i.e., "0".

[0063] The following describes the process by which the control unit 10 of the recording device 900 recognizes the optimal drive pulse width rank value in the state of memory circuits M1 and M2 shown in Figure 7. This recognition process is performed according to the procedure shown in Figure 6, but some parts of the process differ from the previous explanation.

[0064] The processing from steps S1 to S2 is as described above. Next, in step S3, the data stored in the memory circuit M1 is read. The data reading process is as described in step S1, in the memory bit data reading flow shown in Figure 6(b). Two bits of data are read from the memory circuit M1. Here, it is read that the upper bit of the two bits is "1" and the lower bit is "0".

[0065] In step S4, since the upper bit is "1" and the lower bit is "0", it is recognized that the memory circuit M1 stores "10" in binary, which is "2" in decimal. The processing from steps S5 to S6 is as described above. In calculating the rank value in step S7, since the memory circuit M2 is "0", "202", which is obtained by adding the memory circuit's "2" (change during the first reuse) to the memory circuit M0's "200" (initial value), is recognized as the rank value of the latest drive pulse width. The above describes the process for recognizing the rank value of the drive pulse width of the recording head 810 after it has been reused once.

[0066] Next, we will explain the operation of the recording head 810 when it is reused a second time. Here, we will assume that the rank value of the drive pulse width at the time of manufacture (initial value) is "200", and the rank value of the drive pulse width during the first reuse is "202". Furthermore, the rank value corresponding to the drive pulse width measured during the second reuse will be "203".

[0067] Figure 8 schematically shows the state of memory circuits M1 and M2 during the second reuse. Figure 8(a) shows the state of memory circuit M1, and Figure 8(b) shows the state of memory circuit M2. During the second reuse, the drive pulse width is measured, and the difference (change) between its rank value and the rank value "202" from the first reuse is stored in memory circuit M2 as a correction value. Here, the optimal drive pulse width rank for the second reuse is "203," which is "1" higher than the rank value "202" from the first reuse. The decimal number "1" is represented as "01" in binary. Of the two bits of memory circuit M2, the upper bit is antifuse element A21, and the lower bit is antifuse element A22. Therefore, antifuse element A21 is in a non-conductive state, and antifuse element A22 is in a conductive state.

[0068] The following describes the process by which the control unit 10 of the recording device 900 recognizes the optimal drive pulse width rank value in the state of memory circuits M1 and M2 shown in Figure 8. This recognition process is performed according to the procedure shown in Figure 6, but some parts of the process differ from the previous explanation.

[0069] The processes from steps S1 to S4 are as described above. Next, in step S5, the data stored in the memory circuit M2 is read. The data reading process is as described in step S1, in the memory bit data reading flow shown in Figure 6(b). Two bits of data are read from the memory circuit M2. Here, it is read that the upper bit of the two bits is "0" and the lower bit is "1".

[0070] In step S6, it is recognized that the memory circuit M2 stores "01" in binary, or "1" in decimal, because the upper bit is "0" and the lower bit is "1". In step S7, "203", which is the sum of "200" (initial value) of the memory circuit M0, "2" (change from the first reuse) of the memory circuit M1, and "1" (change from the second reuse) of the memory circuit M2, is recognized as the rank value of the latest drive pulse width. The above describes the process for recognizing the rank value of the drive pulse width of the recording head 810 after it has been reused twice. Steps S1 and S2 can be called the eigenvalue recognition process. Steps S3 and S4 can be called the correction value recognition process. Step S5 can be called the calculation process.

[0071] As described above, with the recording head 810 of this embodiment, the eigenvalues ​​(initial values) can be updated by providing memory circuits M1 and M2 for correcting the eigenvalues. Specifically, if the eigenvalues ​​stored when the recording head 810 was newly manufactured change during reuse, the change in the eigenvalues ​​can be stored in memory circuits M1 and M2, so that the latest eigenvalues ​​of the recording head 810 can always be recognized.

[0072] Furthermore, since the memory capacities of memory circuits M1 and M2 are sufficiently smaller than those of memory circuit M0, the increase in memory capacity can be suppressed compared to the case where a separate memory circuit with the same capacity as memory circuit M0 is provided. Furthermore, since the memory circuits M0 to M2 have a simple circuit configuration and require a small area to form the memory, it is possible to suppress the need to increase the size of the recording head 810.

[0073] In the recording head 810 of this embodiment, the memory circuits M0 to M2 may be constructed using either a fuse element or an antifuse element. However, a memory circuit using an antifuse element requires less area to form compared to a memory circuit using a fuse element. For example, the area of ​​a memory circuit using an antifuse element can be reduced to about one-third of that of a memory circuit using a fuse element. Therefore, it is preferable to form the memory circuits M0 to M2 using antifuse elements. Furthermore, the eigenvalues ​​stored in the memory circuit M0 are not limited to the rank value of the drive pulse width. Any rank value of data can be used as an eigenvalue, as long as the data can be updated based on the correction value.

[0074] (Second embodiment) A recording head according to a second embodiment of the present invention will now be described. The recording head of this embodiment has the same configuration as the recording head 810 of the first embodiment, except that the eigenvalues ​​increase or decrease. In the description of the recording head of this embodiment, the same reference numerals as in the first embodiment will be used to represent the same components as in the first embodiment. Furthermore, explanations of the same components as in the first embodiment will be omitted.

[0075] In the recording head 810 of the first embodiment, the eigenvalue (drive pulse width rank) changed in the positive direction during reuse. In contrast, in the recording head 810 of this embodiment, the eigenvalue changes in either the positive or negative direction. Below, we will describe an example of saving an eigenvalue called the concentration rank, which is a ranking of the concentration of droplets ejected from the recording head 810 and landed on the paper. However, the eigenvalue is not limited to the concentration rank. Any data that changes in either the positive or negative direction due to reuse may be used as the eigenvalue.

[0076] The density rank value is a value obtained by driving the recording head 810 with the drive pulse width described in the first embodiment and ranking the impact pattern (printed pattern) that lands on the paper according to the density value measured by a densitometer. The recording device 900 reads this density rank value and controls the number of ink droplets ejected according to the density rank value so that the printed pattern reaches the desired density level when printing solid patterns or halftone patterns. This density rank value may change slightly in the positive or negative direction when reused, but it has been found that the amount of change is within 2.

[0077] The electrical connection between the element substrate 100 of the recording head 810 and the main body 900a of the recording device 900 in this embodiment is as shown in Figure 3. However, memory circuit M0 stores the density rank value, memory circuit M1 stores the change in density rank value during the first reuse, and memory circuit M2 stores the change in density rank value during the second reuse. In this embodiment, the density rank is managed using rank values ​​from 0 to 31. In this case, memory circuit M0 has a capacity of 5 bits. The data reading and data writing methods for memory circuits M0 to M2 are the same as in the first embodiment.

[0078] Figure 9 is a schematic diagram showing the configuration of a memory circuit M0 that stores concentration rank values. This memory circuit M0 consists of five antifuse elements A01 to A05 connected in parallel, and is configured to store 5 bits of data. Driver circuits D01 to D05 are connected to each of the antifuse elements A01 to A05. The antifuse elements A01 to A05 and the driver circuits D01 to D05 have the same structure as the antifuse element A and driver circuit D of the memory circuit M0 described in the first embodiment.

[0079] In the example in Figure 9, the initial value of the concentration rank is set to "17". When the decimal number "17" is represented in binary, it becomes "10001". In the memory circuit M0, in order to store "10001", antifuse elements A01 and A05 are in a conductive state, and antifuse elements A02, A03, and A04 are in a non-conductive state.

[0080] Figure 10 is a schematic diagram showing the configuration of memory circuits M1 and M2 that store changes in concentration rank values. Figure 10(a) shows memory circuit M1, and Figure 10(b) shows memory circuit M2. The memory circuit M1 shown in Figure 10(a) is a 3-bit memory consisting of three antifuse elements A11 to A13 connected in parallel. Driver circuits D11 to D13 are connected to each of the antifuse elements A11 to A13. The leftmost antifuse element A11 represents the sign (positive or negative), and the remaining antifuse elements A12 and A13 are used to store 2 bits of data. Here, the sign (positive or negative) indicates whether a correction value is added to a fixed value or subtracted from a fixed value. The antifuse elements A11 to A13 and driver circuits D11 to D13 have the same structure as antifuse element A and driver circuit D of the memory circuit M1 described in the first embodiment.

[0081] In the example in Figure 10(a), the change during the first reuse is set to +2. Because it is "positive," the antifuse element A11 in the memory circuit M1 is in a non-conductive state. Also, the decimal number "2" is represented as "10" in binary. In the memory circuit M1, the antifuse element A12 is in a conductive state and the antifuse element A13 is in a non-conductive state in order to store "10".

[0082] The memory circuit M2 shown in Figure 10(b) is a 3-bit memory consisting of three antifuse elements A21 to A23 connected in parallel. Driver circuits D21 to D23 are connected to each of the antifuse elements A21 to A23. The leftmost antifuse element A21 represents the sign (positive or negative), and the remaining antifuse elements A22 and A23 are used to store 2 bits of data. The antifuse elements A21 to A23 and the driver circuits D21 to D23 have the same structure as the antifuse element A and driver circuit D of the memory circuit M2 described in the first embodiment.

[0083] In the example in Figure 10(b), the change during the second reuse is set to -1. Because it is "negative," the antifuse element A21 in the memory circuit M2 is set to conduct. Also, the decimal number "1" is represented as "01" in binary. In the memory circuit M2, in order to store "01," the antifuse element A22 is set to be non-conductive and the antifuse element A23 is set to conduct.

[0084] Next, we will describe the data recognition process in which the control unit 10 of the recording device 900 reads the state of memory circuits M0 to M2 and recognizes the density rank value. The flow for reading the data stored in memory circuits M0 to M2 is the same as the flow for reading the rank value of the drive pulse width shown in Figure 6, except that the amount of change (correction value) during reuse is signed (positive or negative). Here, we will describe the recognition process of the amount of change during reuse.

[0085] The memory circuits M1 and M2 are in the state shown in Figure 10 after two reuses. During the first reuse, the bit data of memory circuit M1 is set as follows: antifuse element A11 is "0", antifuse element A12 is "1", and antifuse element A13 is "0". Antifuse element A11 is the sign bit that indicates positive or negative, and antifuse elements A12 and A13 are the upper and lower bits of the 2-bit data, respectively. Since the sign bit is "0", it is recognized as a change in the positive direction. The 2-bit data is "10" in binary, which is "2" in decimal, so the change during the first reuse is recognized as +2.

[0086] During the second reuse, the bit data of memory circuit M2 is set as follows: antifuse element A21 is "1", antifuse element A22 is "0", and antifuse element A13 is "1". Antifuse element A21 is the sign bit that indicates positive or negative, and antifuse elements A22 and A23 are the upper and lower bits of the 2-bit data, respectively. Since the sign bit is "1", it is recognized as a change in the negative direction. The 2-bit data is "01" in binary, which is "1" in decimal, so the change during the second reuse is recognized as minus 1.

[0087] The control unit 10 of the recording device 900 recognizes "18" as the latest density rank for the recording head 810 that has been reused for the second time. This value is the sum of the initial rank value of "17", the change of +2 from the first reuse, and the change of -1 from the second reuse.

[0088] As described above, the recording head 810 of this embodiment can update eigenvalues ​​that increase or decrease due to changes during reuse, and can recognize the latest eigenvalues ​​of the recording head 810.

[0089] In addition, in the recording head 810 of this embodiment, as in the first embodiment, the memory circuits M0, M1, and M2 may be configured using either a fuse element or an antifuse element. However, as explained in the first embodiment, the area of ​​a memory circuit using an antifuse element is smaller than that of a memory circuit using a fuse element, so it is preferable to use an antifuse element.

[0090] (Third embodiment) A recording head according to a third embodiment of the present invention will now be described. In the recording heads 810 of the first and second embodiments, the memory circuit for storing the change in eigenvalue during reuse was provided for each reuse. The recording head of this embodiment differs from that of the first and second embodiments in that the memory circuit for storing the change in eigenvalue during reuse is used in common for all reuses. In the description of the recording head of this embodiment, the same reference numerals as in the first and second embodiments will be used to represent the same components. Furthermore, explanations of the same components as in the first and second embodiments will be omitted.

[0091] Figure 11 is a schematic diagram illustrating the configuration of a recording head 810 according to a third embodiment of the present invention. In Figure 11, the electrical connection between the main body 900a of the recording device 900 and the element substrate 100 of the recording head 810 is schematically shown. Note that only the parts related to the memory circuit are shown in Figure 11, and other elements are omitted.

[0092] The main body 900a of the recording device 900 includes a control unit 10. The control unit 10 includes a constant current circuit 201, a voltage detection circuit 202, and a constant voltage circuit 203. These circuits are basically the same as those described in the first embodiment. Note that the memory control circuit 204, heater control circuit 151, heater power supply generation circuit 152, driver drive power supply generation circuit 153, and logic power supply circuit 154 are omitted.

[0093] The element substrate 100 has a memory section 20 and a memory shift register 110. The memory section 20 has a memory circuit (initial value) M0 and a memory circuit (correction value) M3. The memory circuit M3 can be called a correction memory circuit. The memory circuit M3 stores the amount by which the rank value of the drive pulse width, which is an intrinsic value, has changed during reuse, i.e., the correction value of the initial rank value. The memory circuit M3 is configured to be used in common throughout the entire reuse process. The memory circuit M0 and the memory shift register 110 are basically the same as those described in the first embodiment. Note that the heater circuit 101 and heater circuit 101 are omitted.

[0094] Figure 12 is a schematic diagram illustrating the configuration of the memory circuit M3. This memory circuit M3 consists of four antifuse elements A31 to A34 connected in parallel, and is configured to store 4 bits of data. Driver circuits D31 to D34 are connected to each of the antifuse elements A31 to A34. The antifuse elements A31 to A34 and the driver circuits D31 to D34 have the same structure as the antifuse element A and driver circuit D of the memory circuit M0 described in the first embodiment.

[0095] In the example shown in Figure 12, the maximum rank change per reuse is set to 3. In this case, a maximum of 2 bits are required per reuse, and assuming two reuses, the memory circuit M3 is configured to store 4 bits of data. Note that the number of reuses is not limited to two. The number of reuses may be three or more. In this case, the number of antifuse elements A should be increased according to the number of reuses.

[0096] In memory circuit M3, data is written by making the antifuse elements A conductive. Here, data is written by making the antifuse elements A conductive in order, starting from the leftmost antifuse element A in memory circuit M3. When writing data, the conductive state of the antifuse elements A in memory circuit M3 is checked, and then the antifuse element A to be made conductive is determined. If the memory circuit has never been reused, all antifuse elements A in memory circuit M3 are in a non-conductive state.

[0097] Figure 12(a) shows the state of the memory circuit M3 during the first reuse, and Figure 12(b) shows the state of the memory circuit M3 during the second reuse. Here, the rank change (increase) during the first reuse is set to "2", and the rank change during the second reuse is set to "1".

[0098] During the first reuse, the antifuse elements in the memory circuit M3 are checked for conductivity, starting from the leftmost antifuse element A31. The antifuse elements to be made conductive are then identified from among the non-conductive elements. At this point, all antifuse elements A31 to A34 in the memory circuit M3 are in a non-conductive state. Since the rank value has increased by "2", the antifuse elements to be made conductive are determined to be antifuse elements A31 and A32. As shown in Figure 12(a), both antifuse elements A31 and A32 are made conductive.

[0099] During the second reuse, the antifuse element A31 at the left end of the memory circuit M3 is checked for continuity, and the antifuse element to be made continuous is identified from among the non-continuing elements. Here, antifuse elements A31 and A32 of the memory circuit M3 are in a continuous state. Since the rank value has increased by "1", the target for continuity is determined to be antifuse element A33. Antifuse element A33 is made continuous as shown in Figure 12(b).

[0100] Next, we will explain the process by which the recording device 900 reads the state of memory circuits M0 and M3 and recognizes the rank value of the drive pulse width. Here, we will explain assuming that the rank value stored in memory circuit M0 is "200" and that memory circuit M3 is in the state shown in Figure 12(b).

[0101] Figure 13 is a flowchart of the data recognition process in which the control unit 10 of the recording device 900 recognizes the rank value of the drive pulse width stored in the memory circuit M (M0, M3). Note that the memory bit data reading flow in steps S31 and S33 of the flowchart in Figure 13 is the same as that shown in Figure 6(b), so the illustration and explanation are omitted. Also, the process of recognizing the initial value of the rank in step S32 is the same as in the first embodiment, so the explanation is omitted here.

[0102] The processing from steps S31 to S32 is the same as steps S1 to S2 shown in Figure 6(a). In step S33, the data stored in the memory circuit M3 is read. The data reading process is as shown in the memory bit data reading flow in Figure 6(b). Four bits of data are read from the memory circuit M3. At this point in the explanation, two reuses have been performed, so the bit data of the state of the memory circuit M3 shown in Figure 12(b) is read.

[0103] Next, in step S34, the correction value represented by each bit data of the memory circuit M3 read in step S33 is recognized. In step S33, it was read that the antifuse elements A31 to A33 of the memory circuit M3 are conducting. Therefore, in step S34, it is recognized that the correction value is "3".

[0104] Finally, in step S35, the initial rank value of "200" and the correction value of "3" are added together to obtain "203," which is recognized as the rank value of the latest drive pulse width. Steps S31 and S32 can be called the eigenvalue recognition process. Steps S33 and S34 can be called the correction value recognition process. Step S35 can be called the calculation process.

[0105] As described above, with the recording head 810 of this embodiment, the eigenvalue can be updated using a common memory circuit M3 for each reuse, and the latest eigenvalue of the recording head 810 can be recognized. By using a common memory circuit M3, the increase in the area required for memory formation can be suppressed.

[0106] In the recording head 810 of this embodiment, the memory circuits M0 and M3 may be configured using either a fuse element or an antifuse element. However, as described in the first embodiment, the area of ​​a memory circuit using an antifuse element is smaller than that of a memory circuit using a fuse element, so it is preferable to use an antifuse element.

[0107] (Fourth embodiment) A recording head according to a fourth embodiment of the present invention will now be described. The same reference numerals as those used in the first to third embodiments will be used to represent components similar to those in the first to third embodiments. Furthermore, explanations of components similar to those in the first to third embodiments will be omitted.

[0108] In the recording head 810 of the third embodiment, the eigenvalue (drive pulse width rank) changed in the positive direction during reuse. In contrast, in the recording head 810 of this embodiment, the eigenvalue changes in either the positive or negative direction. The eigenvalue in this embodiment is the density rank described in the second embodiment. The density rank value is an eigenvalue whose value increases or decreases due to reuse.

[0109] Figure 14 is a schematic diagram illustrating the configuration of a recording head 810 according to a fourth embodiment of the present invention. In Figure 14, the electrical connection between the main body 900a of the recording device 900 and the element substrate 100 of the recording head 810 is schematically shown. Note that only the parts related to the memory circuit are shown in Figure 14, and other elements are omitted.

[0110] The main body 900a of the recording device 900 includes a control unit 10. The control unit 10 includes a constant current circuit 201, a voltage detection circuit 202, and a constant voltage circuit 203. These circuits are basically the same as those described in the first embodiment. Note that the memory control circuit 204, heater control circuit 151, heater power supply generation circuit 152, driver drive power supply generation circuit 153, and logic power supply circuit 154 are omitted.

[0111] The element substrate 100 has a memory section 20 and a memory shift register 110. The memory section 20 has a memory circuit (initial value) M0, a memory circuit (positive correction) M4, and a memory circuit (negative correction) M5. The memory circuit M4 can be called a memory circuit for storing a correction value to be added to a fixed value (initial value) (also referred to as a memory circuit for positive correction). The memory circuit M5 can be called a memory circuit for storing a correction value to be subtracted from a fixed value (initial value) (also referred to as a memory circuit for negative correction). The memory circuit M0 and the memory shift register 110 are basically the same as those described in the second embodiment. Note that the heater circuit 101 and the heater circuit 101 are omitted.

[0112] Memory circuit M0 stores the concentration rank. In this embodiment, as in the second embodiment, the concentration rank is managed with rank values ​​from 0 to 31, so memory circuit M0 has a capacity of 5 bits. Memory circuit M4 stores the positive change in concentration rank (positive correction value) during reuse, and memory circuit M5 stores the negative change in concentration rank (negative correction value) during reuse. Memory circuits M4 and M5 are configured to be used in common for all reuses. Below, we will specifically describe each configuration assuming the initial rank value is "17", the change during the first reuse is +2, and the change during the second reuse is -1.

[0113] Figure 15 is a schematic diagram illustrating the configuration of memory circuits M4 and M5. Memory circuit M4 consists of four antifuse elements A41 to A44 connected in parallel, and is configured to store 4 bits of data. Driver circuits D41 to D44 are connected to each of the antifuse elements A41 to A44. The antifuse elements A41 to A44 and driver circuits D41 to D44 have the same structure as antifuse element A and driver circuit D of memory circuit M0 described in the first embodiment.

[0114] The memory circuit M5 consists of four antifuse elements A51 to A54 connected in parallel, and is configured to store 4 bits of data. Driver circuits D51 to D54 are connected to each of the antifuse elements A51 to A54. The antifuse elements A51 to A54 and driver circuits D51 to D54 have the same structure as the antifuse element A and driver circuit D of the memory circuit M0 described in the first embodiment.

[0115] Figure 15(a) shows the state of memory circuit M4 during the first reuse, and Figure 15(b) shows the state of memory circuit M5 during the first reuse. During the first reuse, the rank value change is +2. Therefore, in memory circuit M4, antifuse elements A41 and A42 are in a conducting state, and antifuse elements A43 and A44 are in a non-conducting state. On the other hand, in memory circuit M5, since the rank change is not negative, all antifuse elements A51 to A54 are in a non-conducting state.

[0116] Figure 16 shows the state of memory circuit M5 during the second reuse. During the second reuse, the rank value change is -1. Therefore, in memory circuit M5, antifuse element A11 is in a conductive state, and antifuse elements A42 to A44 are in a non-conductive state. Note that memory circuit M4 during the second reuse is in the same state as in Figure 15(a).

[0117] Next, we will explain the process by which the recording device 900 reads the states of memory circuits M0, M4, and M5 and recognizes the concentration rank value. Here, memory circuit M0 is in the state shown in Figure 9, memory circuit M4 is in the state shown in Figure 15(a), and memory circuit M5 is in the state shown in Figure 16.

[0118] Figure 17 is a flowchart of the data recognition process in which the control unit 10 of the recording device 900 recognizes the concentration rank values ​​stored in the memory circuit M (M0, M4, M5). Note that the memory bit data reading flow in steps S41, S43, and S45 of the flowchart in Figure 17 is the same as that shown in Figure 6(b), so the illustration and explanation are omitted. Also, the process of recognizing the initial value of the rank in step S42 is the same as in the first embodiment, so the explanation is omitted here.

[0119] The processes from steps S41 to S42 are the same as steps S1 to S2 shown in Figure 6(a). In step S43, the bit data stored in the memory circuit M4 is read. The data reading process is as shown in the memory bit data reading flow in Figure 6(b). Four bits of data are read from the memory circuit M4. At this point in the explanation, since two reuses have occurred, the bit data of the state of the memory circuit M4 shown in Figure 15(a) is read.

[0120] Next, in step S44, the positive correction value represented by each bit data of the memory circuit M4 read in step S43 is recognized. In step S43, it was read that the antifuse elements A41 and A42 of the memory circuit M4 are conducting, and the antifuse elements A43 and A44 are not conducting. Therefore, in step S44, it is recognized that the value to correct the rank value to the positive side is "2". Note that here, the number of reuses is irrelevant, and the correction value at the time of reading is recognized.

[0121] Next, in step S45, the bit data stored in the memory circuit M5 is read. The data reading process is as shown in the memory bit data reading flow in Figure 6(b). Four bits of data are read from the memory circuit M5. At this point in the explanation, two reuses have been performed, so the bit data of the state of the memory circuit M5 shown in Figure 16 is read.

[0122] Next, in step S46, the negative correction value represented by each bit data of the memory circuit M5 read in step S45 is recognized. In step S45, it was read that the antifuse element A51 of the memory circuit M5 is conducting, and the antifuse elements A52 to A54 are not conducting. Therefore, in step S46, it is recognized that the value to correct the rank value to the negative side is "1".

[0123] Finally, in step S47, the initial rank value of "17", the positive correction value of "2", and the negative correction value of "1" are all added together to arrive at "18", which is recognized as the rank value of the latest drive pulse width. Note that adding the negative correction value of "1" means subtracting "1". Steps S41 and S42 can be called the eigenvalue recognition process. Steps S43 to S46 can be called the correction value recognition process. Step S47 can be called the calculation process.

[0124] As described above, the recording head 810 of this embodiment can update eigenvalues ​​even for those whose amount of change during reuse increases or decreases, and the latest eigenvalues ​​of the recording head 810 can be recognized.

[0125] In addition, in the recording head 810 of this embodiment, the memory circuits M0, M4, and M5 may be configured using either fuse elements or antifuse elements. However, as explained in the first embodiment, the area of ​​a memory circuit using antifuse elements is smaller than that of a memory circuit using fuse elements, so it is preferable to use antifuse elements.

[0126] This embodiment includes the following configurations and methods. (Composition 1) A recording head having a memory section configured with a fuse element or an antifuse element, The aforementioned memory unit is A main memory circuit for storing eigenvalues ​​related to the recording head, A recording head characterized by having at least one correction memory circuit for storing correction values ​​for updating the aforementioned eigenvalues. (Configuration 2) The recording head according to configuration 1, characterized in that the correction value is the amount of change from before the update to after the update of the eigenvalue. (Composition 3) The recording head according to configuration 1 or 2, characterized in that the correction value is stored in the at least one correction memory circuit when the recording head is reused. (Composition 4) The recording head according to configuration 3, characterized in that the at least one correction memory circuit includes the same number of correction memory circuits as the number of times the recording head is reused. (Composition 5) The recording head according to configuration 4, characterized in that the capacity of the correction memory circuit, which is present for each reuse, is smaller than the capacity of the main memory circuit. (Composition 6) The recording head according to configuration 4 or 5, wherein the correction memory circuit consists of a plurality of bits, and one of the bits represents whether to add the correction value to the fixed value or subtract the correction value from the fixed value. (Composition 7) The recording head according to configuration 3, characterized in that the at least one correction memory circuit includes a correction memory circuit that is used in common for multiple reuses of the recording head. (Composition 8) The recording head according to configuration 3, characterized in that the at least one correction memory circuit includes a memory circuit for storing a correction value to be added to the eigenvalue and a memory circuit for storing a correction value to be subtracted from the eigenvalue. (Composition 9) The recording head according to any one of configurations 1 to 9, characterized in that the aforementioned eigenvalue is a value relating to the drive pulse width for driving the recording head. (Composition 10) The recording head according to any one of configurations 1 to 9, characterized in that the eigenvalue is a value relating to the density of a printed material printed using the recording head. (Method 1) A data recognition method for a recording head, comprising a memory section configured using a fuse element or an antifuse element, wherein an eigenvalue relating to the recording head and a correction value for updating the eigenvalue are stored as bit data in the memory section, An eigenvalue recognition step involves reading the bit data of the eigenvalue from the memory unit and recognizing the eigenvalue, A correction value recognition step involves reading the bit data of the correction value from the memory unit and recognizing the correction value, A data recognition method characterized by comprising a calculation step of calculating the latest eigenvalue based on the eigenvalue recognized in the eigenvalue recognition step and the correction value recognized in the correction value recognition step. (Method 2) The memory unit includes a number of correction memory circuits equal to the number of times the recording head is reused, and for each reuse, the correction value at that time is stored as bit data in the corresponding correction memory circuit. The data recognition method according to Method 1, characterized in that the correction value recognition step includes reading bit data from the corresponding correction memory circuit for each reuse to recognize the correction value at the time of reuse. (Method 3) The memory unit has a correction memory circuit consisting of multiple bits, one of which represents a code indicating whether to add the correction value to the fixed value or subtract the correction value from the fixed value, and the remaining bits store the correction value. The data recognition method according to Method 1, characterized in that the correction value recognition step includes reading bit data from the correction memory circuit and recognizing the correction value and the sign. (Method 4) The memory unit includes a memory circuit that stores a positive correction value added to the eigenvalue as bit data, and a memory circuit that stores a negative correction value subtracted from the eigenvalue as bit data. The data recognition method according to Method 1, characterized in that the correction value recognition step includes reading bit data from a memory circuit that stores the positive correction value to recognize the positive correction value, and reading bit data from a memory circuit that stores the negative correction value to recognize the negative correction value. [Explanation of Symbols]

[0127] 810 Recording head 20 Memory section M0 Memory Circuit M1 memory circuit M2 memory circuit

Claims

1. A recording head having a memory section configured with a fuse element or an antifuse element, The aforementioned memory unit is A main memory circuit for storing eigenvalues ​​related to the recording head, A recording head characterized by having at least one correction memory circuit for storing correction values ​​for updating the aforementioned eigenvalues.

2. The recording head according to claim 1, characterized in that the correction value is the amount of change from before the update to after the update of the eigenvalue.

3. The recording head according to claim 2, characterized in that the correction value is stored in the at least one correction memory circuit when the recording head is reused.

4. The recording head according to claim 3, characterized in that the at least one correction memory circuit includes the same number of correction memory circuits as the number of times the recording head is reused.

5. The recording head according to claim 4, characterized in that the capacity of the correction memory circuit, which is present for each reuse, is smaller than the capacity of the main memory circuit.

6. The recording head according to claim 4 or 5, characterized in that the correction memory circuit comprises a plurality of bits, one of which represents whether to add the correction value to the fixed value or subtract the correction value from the fixed value.

7. The recording head according to claim 3, characterized in that the at least one correction memory circuit includes a correction memory circuit that is used in common for multiple reuses of the recording head.

8. The recording head according to claim 3, characterized in that the at least one correction memory circuit includes a memory circuit for storing a correction value to be added to the eigenvalue and a memory circuit for storing a correction value to be subtracted from the eigenvalue.

9. The recording head according to claim 1, characterized in that the eigenvalue is a value relating to the drive pulse width for driving the recording head.

10. The recording head according to claim 1, characterized in that the eigenvalue is a value relating to the density of a printed material printed using the recording head.

11. A data recognition method for a recording head, comprising a memory section configured using a fuse element or an antifuse element, wherein an eigenvalue relating to the recording head and a correction value for updating the eigenvalue are stored as bit data in the memory section, An eigenvalue recognition step involves reading the bit data of the eigenvalue from the memory unit and recognizing the eigenvalue, A correction value recognition step involves reading the bit data of the correction value from the memory unit and recognizing the correction value, A data recognition method characterized by comprising a calculation step of calculating the latest eigenvalue based on the eigenvalue recognized in the eigenvalue recognition step and the correction value recognized in the correction value recognition step.

12. The memory unit includes a number of correction memory circuits equal to the number of times the recording head is reused, and for each reuse, the correction value at that time is stored as bit data in the corresponding correction memory circuit. The data recognition method according to claim 11, characterized in that the correction value recognition step includes reading bit data from the corresponding correction memory circuit each time the reuse is performed to recognize the correction value at the time of reuse.

13. The memory unit has a correction memory circuit consisting of multiple bits, one of which represents a code indicating whether to add the correction value to the fixed value or subtract the correction value from the fixed value, and the remaining bits store the correction value. The data recognition method according to claim 11, characterized in that the correction value recognition step includes reading bit data from the correction memory circuit and recognizing the correction value and the sign.

14. The memory unit includes a memory circuit that stores a positive correction value added to the eigenvalue as bit data, and a memory circuit that stores a negative correction value subtracted from the eigenvalue as bit data. The data recognition method according to claim 11, characterized in that the correction value recognition step includes reading bit data from a memory circuit that stores the positive correction value to recognize the positive correction value, and reading bit data from a memory circuit that stores the negative correction value to recognize the negative correction value.

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