Electronic devices and methods for manufacturing the same

Abstract

The present invention provides an electronic device and a method for manufacturing the same that can improve the yield of electronic devices. [Solution] The electronic device includes a substrate, vias, conductive elements, and a circuit structure. The vias penetrate the substrate and include a first via and a second via. The conductive elements are arranged within the vias and include a first conductive element and a second conductive element. The first conductive element is arranged within the first via. The second conductive element is arranged within the second via. The circuit structure is arranged on the substrate and is electrically connected to the conductive elements. In a first direction, there is a first gap between two adjacent first conductive elements. There is a second gap between two adjacent second conductive elements. The first gap is greater than the second gap.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly, to a design of an electronic device having a via substrate and a method for manufacturing the same.

Background Art

[0002] In the manufacturing process of an electronic device, different materials arranged to form the electronic device have different physical properties (e.g., thermal expansion coefficient), so the manufactured electronic device may have a poor yield. For example, a through glass via (TGV) substrate in an electronic device is likely to crack due to the stress mismatch problem between different materials, resulting in a decrease in the yield of the electronic device.

Summary of the Invention

Problems to be Solved by the Invention

[0003] In the manufacturing process of an electronic device, different materials arranged to form the electronic device have different physical properties, so the manufactured electronic device may have a poor yield.

Means for Solving the Problems

[0004] The present invention relates to an electronic device, or a design and manufacturing method capable of improving the yield of an electronic device.

[0005] According to some embodiments of the present invention, an electronic device includes a substrate, vias, conductive elements, and a circuit structure. The vias penetrate the substrate and include a first via and a second via. The conductive elements are arranged within the vias and include a first conductive element and a second conductive element. The first conductive element is arranged within the first via. The second conductive element is arranged within the second via. The circuit structure is arranged on the substrate and is electrically connected to the conductive elements. In a first direction, there is a first spacing between two adjacent first conductive elements. There is a second spacing between two adjacent second conductive elements. The first spacing is greater than the second spacing.

[0006] According to several other embodiments of the present invention, the electronic device includes a substrate, vias, conductive elements, and a circuit structure. The vias penetrate the substrate and include a first via and a second via. The conductive elements are arranged within the vias and include a first conductive element and a second conductive element. The first conductive element is arranged within the first via. The second conductive element is arranged within the second via. The circuit structure is arranged on the substrate and is electrically connected to the conductive elements. The first conductive element fills the first via. The second conductive element fills the second via. [Effects of the Invention]

[0007] According to embodiments of the present invention, the conductive elements formed on the substrate have a discontinuous shape. Therefore, multiple parts with different structures can be formed on the upper and / or lower surfaces of the substrate, thereby aligning the stresses generated when the electronic device heats up and improving the yield of the electronic device. [Brief explanation of the drawing]

[0008] [Figure 1A] This is a schematic partial top view of an electronic device according to one embodiment of the present invention. [Figure 1B] This is a schematic partial cross-sectional view of an electronic device along the cross-sectional line A-A' according to one embodiment of the present invention. [Figure 2] This is a schematic flowchart of the manufacturing method for an electronic device according to the first embodiment of the present invention. [Figure 3]This is a schematic flowchart of a method for manufacturing an electronic device according to a second embodiment of the present invention. [Figure 4] This is a schematic flowchart of a method for manufacturing an electronic device according to a third embodiment of the present invention. [Figure 5] This is a schematic flowchart of the method for manufacturing an electronic device according to the fourth embodiment of the present invention. [Figure 6] This is a schematic flowchart of a method for manufacturing an electronic device according to a fifth embodiment of the present invention. [Figure 7] This is a schematic partial cross-sectional view of a package structure according to one embodiment of the present invention. [Modes for carrying out the invention]

[0009] The present invention can be understood by referring to the following detailed description with reference to the accompanying drawings. It should be noted that, for the sake of reader understanding and the brevity of the drawings, only a portion of the electronic devices are shown in the drawings of the present invention, and certain elements in the drawings are not necessarily drawn to scale. Furthermore, the quantities and sizes of each element in the drawings are approximate and are not intended to limit the scope of the present invention.

[0010] Throughout the specification and appended claims of this invention, specific terms are used to refer to particular elements. Those skilled in the art should understand that electronic device manufacturers may use different names to refer to the same element. This specification is not intended to distinguish between elements that have the same function but different names. In the following specification and claims, terms such as “include,” “encompass,” and “have” are open terms and should be interpreted as “include, but not limited to….” Accordingly, the terms “include,” “equip,” and / or “have” as used in the description of this invention indicate the presence of a corresponding feature, region, step, operation, and / or element, but are not limited to the presence of one or more corresponding features, regions, steps, operations, and / or elements.

[0011] The directional terms such as “up,” “down,” “front,” “back,” “left,” and “right” used in this invention are merely directions referring to the drawings. Therefore, the directional terms used are for illustrative purposes only and not to limit the invention. In the drawings, each drawing illustrates the general characteristics of the methods, structures, and / or materials used in a particular embodiment. However, the drawings should not be interpreted as defining or limiting the scope or properties covered by the embodiments. For example, for clarity, the relative sizes, thicknesses, and locations of various film layers, regions, and / or structures may be reduced or enlarged.

[0012] When a corresponding component (e.g., a film layer or region) is described as being "on top of another component," that component may be directly on top of the other component, or there may be another component between them. On the other hand, when a component is described as being "directly on top of another component," there is no component between them.

[0013] The terms “equal,” “same,” “substantially,” or “approximately” are generally interpreted as being within 20% of a given value or range, or within 10%, 5%, or 0.5% of a given value or range.

[0014] Ordinal numbers such as "first" and "second" used in the specification and claims are for the purpose of modifying elements, and these terms do not imply or indicate that an element has a preceding ordinal number, nor do they represent the order of a particular element to another element or the order of a method of manufacture. Ordinal numbers are used solely to clearly distinguish an element having a particular name from another element having the same name. The same terms may not be used in the claims and specification. Therefore, a first element in the specification may be a second element in a claim.

[0015] It should be noted that in the following embodiments, without departing from the spirit of the present invention, the features in several different embodiments can be replaced, recombined, and mixed to complete other embodiments. The features of each embodiment can be arbitrarily mixed and combined as long as they do not violate the spirit of the present invention or conflict with each other.

[0016] The electrical connections or couplings described in the present invention can refer to either direct connections or indirect connections. In the case of a direct connection, the terminals of two components on the circuit are directly connected or interconnected by a conductive wire segment. In the case of an indirect connection, there may be a switch, diode, capacitor, inductor, other appropriate components, or a combination of the above between the terminals of two components on the circuit, but the present invention is not limited thereto.

[0017] In the present invention, the measurement methods for thickness, length, width, and area may be methods of measurement by employing an optical microscope. The thickness can be obtained by measuring the cross-sectional image of an electron microscope, but the present invention is not limited thereto. Furthermore, there may be a certain error between any two values or directions for comparison. When the first value is equal to the second value, it means that there may be an error of about 10% between the first value and the second value. When the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees. When the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0018] The process of the electronic device of the present invention can be provided through, for example, a wafer-level package (WLP) process or a panel-level package (PLP) process, and may also be a chip first process or a chip last RDL first process.

[0019] The electronic device of the present invention can be applied to a power module, a semiconductor package device, a display device, a light-emitting device, a backlight device, an antenna device, a sensing device, or a tile-attaching device, but the present invention is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of these, but the present invention is not limited thereto. The electronic device may have a drive system, a control system, a light source system, and other peripheral systems, thereby supporting a display device, an antenna device, a wearable device (including, for example, extended reality or virtual reality), an in-vehicle device (including, for example, a front windshield of a vehicle), or a tile-attaching device. The manufacturing method of the package device in the present invention can be applied to, for example, a wafer-level package (WLP) process or a panel-level package (PLP) process. The wafer-level package or panel-level package process can include a chip-first process or a chip-last process, but the present invention is not limited thereto. The electronic device can include package devices such as a high bandwidth memory (HBM) package, a system on a chip (SoC), a system in a package (SiP), an antenna in package (AiP), a co-packaged optics (CPO), or various combinations of the above-described devices, but the present invention is not limited thereto.

[0020] FIG. 1A is a schematic partial top view of an electronic device according to one embodiment of the present invention. FIG. 1B is a schematic partial cross-sectional view of an electronic device according to one embodiment of the present invention.

[0021] Referring to Figure 1A, the electronic device 1 of this embodiment has a plurality of electronic units 2 arranged in an array. Each of the electronic units 2 may comprise a plurality of electronic elements 3 having the same or different functions. Viewed from the perspective of Figure 1B, in this embodiment, each of the electronic units 2 of the electronic device 1 may include a substrate 10, vias T, conductive elements 20, and a circuit structure 30.

[0022] The material of the substrate 10 may include, for example, a suitable ceramic material. For example, the material of the substrate 10 may include a transparent material, glass, alkali-free glass, or quartz glass. The thermal expansion coefficient of the substrate 10 may be 3 ppm / °C or more and 10 ppm / °C or less. The light transmittance of the substrate 10 may be 75% or more. The light may include white light, UV light, etc. In this embodiment, the substrate 10 is a glass substrate.

[0023] A via T penetrates, for example, the substrate 10. In this embodiment, via T includes a first via T1 and a second via T2 located in the peripheral region PA of the electronic device 1. The first via T1 is, for example, further from the center of the electronic unit 2 than the second via T2. From another viewpoint, the first via T1 is further from the active region AA of the electronic device 1 than the second via T2. In this embodiment, the opening p1 of the first via T1 in the X direction is greater than the opening p2 of the second via T2 in the X direction. The X direction is perpendicular to the normal direction (Z direction) of the substrate 10. According to some embodiments, in the X direction, the substrate 10 has a width L. The peripheral region PA is a range of 1 / 4*L from the side surface 10S of the substrate 10.

[0024] It should be noted that via T may further include a third via T3. The third via T3 is located in the active region AA of the electronic device 1. Based on this, the third via T3 is, for example, closer to the center of the electronic unit 2 than the second via T2. In this embodiment, the opening p3 of the third via T3 in the X direction is smaller than the opening p2 of the second via T2 in the X direction. The opening is the minimum width of the via in the cross-sectional view.

[0025] The conductive element 20 is located within a via T. In some embodiments, the conductive element 20 may be conformally formed on the substrate 10. For example, the conductive element 20 may be located on at least a portion of the surface of the substrate 10 and within at least a portion of a via T. In this embodiment, the conductive element 20 includes a first conductive element 22 and a second conductive element 24. The first conductive element 22 is located within a first via T1. The second conductive element 24 is located within a second via T2. In this embodiment, the first conductive element 22 and the second conductive element 24 located within the first via T1 and the second via T2 may be signal transmission elements and / or heat dissipation elements. It should be noted that the conductive element 20 may further include a third conductive element 26. The third conductive element 26 may be located within a third via T3 and fill the third via T3.

[0026] In this embodiment, there is a first spacing d1 between two adjacent first conductive elements 22 in the X direction. There is a second spacing d2 between two adjacent second conductive elements 24 in the X direction. Since the opening p1 of the first via T1 is larger than the opening p2 of the second via T2, the first spacing d1 is larger than the second spacing d2. Similarly, the second spacing d2 may be larger than the third spacing d3 between adjacent conductive elements near the center of the active region AA.

[0027] The circuit structure 30 is placed on the substrate 10 and electrically connected to the conductive element 20. In this embodiment, the circuit structure 30 is a rewiring structure. A rewiring structure is defined as comprising at least one conductive layer M and at least one insulating layer IL configured to enable the rewiring of a circuit and / or to further increase the area of ​​the circuit fan-out. Different electronic elements may also be electrically connected to each other via the rewiring structure. For example, the rewiring structure is configured as a substrate for routing an electrical interface between one connection and another. A method for forming a rewiring structure may include providing a lamination of at least one conductive layer M and at least one insulating layer IL. The formation method may include performing processes such as photolithography, etching, surface treatment, laser, or electroplating. Surface treatment may include roughening the surface of at least one conductive layer M and / or at least one insulating layer IL to improve their adhesive properties. The purpose of the rewiring structure is to extend a connection to a wider spacing or to rewiring a connection to another connection with a different spacing. In some embodiments, the insulating layer IL of the redistribution structure is made of polyimide (PI), polyphenyl sulfide (PSP), polybenzoxazole (PBO), epoxy, polymer, isophenylamine, or silicon oxide (SiO2). x ), or silicon nitride (SiN x ) is also acceptable.

[0028] In this embodiment, the circuit structure 30 includes circuit structures 32 and 34. Circuit structures 32 and 34 are arranged on the substrate 10. More specifically, circuit structure 32 is positioned above the substrate 10 in the vertical direction Z. Circuit structure 34 is positioned below the substrate 10 in the vertical direction Z. Circuit structures 32 and 34 may be electrically connected to each other via conductive elements 20.

[0029] In this embodiment, the electronic device 1 further includes a filler material F. The filler material F is placed within the via T. Alternatively, the filler material F may be configured to fill other portions of the via T not occupied by the conductive element 20. More specifically, the filler material F includes a first filler material F1 and a second filler material F2. The first filler material F1 fills the first via T1. The second filler material F2 fills the second via T2. The filler material F may include a suitable composition of polymer, metal, alloy, graphene, or silicon carbide. According to some embodiments, the thermal expansion coefficients of the first filler material F1 and the second filler material F2 may be the same or different. The thermal expansion coefficient of the first filler material F1 may be smaller than that of the second filler material F2. According to some embodiments, the Young's modulus of the first filler material F1 and the second filler material F2 may be the same or different. The Young's modulus of the first filler material F1 may be less than that of the second filler material F2. The Young's modulus can be determined through a universal tester or other suitable test method.

[0030] Referring to Figure 1B, from another perspective, via T can include first vias T1 and T2 located in the peripheral region PA of electronic device 1, and a third via T3 located in the active region AA of electronic device 1. The first conductive elements 22 and 24 in the first via T1 and T2 can be configured for signal transmission, respectively. The first filler material F1 and 2 filler material F2 in the first via T1 and T2 can be configured for heat dissipation, respectively. The third conductive element 26 in the third via T3 can also be configured for signal transmission.

[0031] In this embodiment, the electronic device 1 further includes a connecting element CU1. Multiple electronic elements 3 can be electrically connected to a circuit structure 32 via a pad PAD and the connecting element CU1. The connecting element CU1 is positioned between the pad PAD and the circuit structure 32. The material of the connecting element CU1 may include copper, nickel, tin, silver, gold, gallium, or other suitable materials. The multiple electronic elements 3 may be, for example, the same electronic element or different electronic elements. In some embodiments, the multiple electronic elements 3 may include general integrated circuits (ICs), high-bandwidth memory (HBMs), flash memory, electronic integrated circuits (EICs), photonic integrated circuits (PICs), capacitors, or other suitable electronic elements. Furthermore, the electronic device 1 further includes a connecting element CU2. The circuit structure 34 can be electrically connected to components such as an intermediate layer (not shown) via the connecting element CU2.

[0032] In this embodiment, the electronic device 1 further includes an intermediate layer UF. The intermediate layer UF is positioned between a plurality of electronic elements 3 and a circuit structure 32. More specifically, the intermediate layer UF can directly contact the active surface of the electronic elements 3 and fill the space between two adjacent connecting elements CU1. The material of the intermediate layer UF may include a suitable inorganic or organic material.

[0033] In this embodiment, the electronic device 1 further includes a sealing layer PL. The sealing layer PL surrounds, for example, a plurality of electronic elements 3. In some other embodiments, the sealing layer PL may cover a plurality of electronic elements 3. According to some embodiments, the sealing layer PL can expose the back surface of the electronic elements 3, thereby facilitating heat dissipation of the electronic device 1. The material of the sealing layer PL may include an epoxy molding compound (EMC).

[0034] In some embodiments, the electronic device 1 can be formed by performing the manufacturing method described in the following embodiments.

[0035] Figure 2 is a schematic flowchart of a method for manufacturing an electronic device according to the first embodiment of the present invention.

[0036] Referring to Figure 2, in this embodiment, the electronic device 1a can be formed by performing the following steps.

[0037] Perform step (1): Provide a substrate 10 having via T.

[0038] In some embodiments, vias T can be formed by performing laser modification, drilling, or etching processes. The substrate 10 can be formed by stacking two or more subsubstrates in combination with a stacking method such as heating, pressurizing, or bonding. Further descriptions of the substrate 10 and vias T can be found in the embodiments described above and will not be detailed here. According to some embodiments, subsubstrates with vias formed on them can be stacked. Alternatively, the subsubstrates may be stacked first, and then the vias may be formed.

[0039] Step (2) is performed: A buffer layer BF is formed on the substrate 10.

[0040] In some embodiments, the buffer layer BF can be formed by performing a suitable deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), printing, coating, or any other suitable method. The placement of the buffer layer BF allows it to cover the sides of the substrate 10 or the sidewalls of vias T. Furthermore, the buffer layer BF can fill pits, irregularities, or microcracks that occur on the corresponding surface of the substrate 10 during the process, reducing the possibility of defects occurring in the subsequently formed seed layer S1 and / or conductive element 20. In some embodiments, the material of the buffer layer BF may include suitable organic and / or inorganic materials. For example, the material of the buffer layer BF may include polyimide (PI), parylene, benzocyclobutene (BCB), epoxy, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or silicon-containing compounds. In some embodiments, the buffer layer BF may include a multilayer structure. The buffer layer BF may include a laminated structure of inorganic layer / organic layer / inorganic layer. In some embodiments, the buffer layer BF may have a viscosity of 0.1 kJ / m³ 2 ~100kJ / m 2 It can possess toughness.

[0041] According to some embodiments, the formation of a buffer layer BF can relatively reduce the roughness of the surface of the substrate 10 or the sidewalls of the vias T. For example, the surface roughness of the substrate 10 may be 5 microns or less. The surface roughness of the buffer layer BF may be 3 microns or less. In some embodiments, the determination of roughness is defined by observing the side surfaces of each substrate 10 using a scanning electron microscope (SEM) or a transmission electron microscope (TEM). A difference of 0.15 μm to 1 μm between the peaks and valleys of the side surface relief can be considered low roughness. The SEM or TEM can observe the surface relief state of the side surfaces of each sub-substrate with vias at the same appropriate magnification, and the relief state can be compared by taking a unit length (e.g., 10 μm). "Appropriate magnification" means that at least 10 relief peaks are visible on at least one surface in the field of view at this magnification.

[0042] Perform step (3): Form the seed layer S1 on the substrate 10.

[0043] The seed layer S1 can be placed on a buffer layer BF. The seed layer S1 can be formed by a suitable deposition process, such as chemical plating, electroplating, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or plasma CVD (PECVD), but the present invention is not limited to these. The seed layer S1 may include seed layers S11 and S12 that are stacked in sequence. In some embodiments, the materials of seed layer S11 and seed layer S12 may include titanium nitride, titanium, copper, tungsten, or ruthenium.

[0044] Perform step (4): Form the conductive element 20 on the substrate 10.

[0045] The conductive element 20 can be placed, for example, on a seed layer S1. In some embodiments, the conductive element 20 can be formed by a chemical plating process or an electroplating process. The rest of the description of the conductive element 20 can be found in the embodiments described above and will not be detailed here. In this embodiment, the conductive element 20 has a thickness of 2 to 40 microns.

[0046] Perform step (5): Form the filler material F on the substrate 10.

[0047] The filler material F can, for example, fill vias T. In some embodiments, the filler material F can be formed by a suitable deposition process, such as coating or injection. In this embodiment, the surface F_s of the filler material F exposed by the vias T may be substantially coplanar with the surface 20_s of the conductive element 20. The rest of the description of the filler material F will not be detailed here, as it can be found in the embodiments described above.

[0048] Perform step (6a): Form the seed layer S2 on the substrate 10.

[0049] The seed layer S2 can be placed, for example, on the surface F_s of the filler material F and the surface 20_s of the conductive element 20. That is, the seed layer S2 can cover the surface F_s of the filler material F and the surface 20_s of the conductive element 20. In some embodiments, the seed layer S2 can be formed by a suitable deposition process. The seed layer S2 may include seed layers S21 and S22 that are stacked in sequence.

[0050] Perform step (7a): Form the mask pattern PR on the substrate 10.

[0051] The mask pattern PR can be placed, for example, on a conductive element 20', and can expose, for example, a portion of the conductive element 20'. In this embodiment, the mask pattern PR overlaps with at least the via T. In some embodiments, the mask pattern PR can be formed by sequentially performing a suitable coating process, an exposure process, and a development process. The material of the mask pattern PR can include a suitable organic material.

[0052] Perform step (8a): Using the mask pattern PR, perform the etching process on the conductive element 20', seed layer S2, conductive element 20, and seed layer S1.

[0053] In some embodiments, the etching process performed on the conductive element 20', seed layer S2, conductive element 20, and seed layer S1 may be a wet etching process. The etching solution used in the wet etching process may include hydrofluoric acid. In this embodiment, the seed layer S2 after the wet etching process may have a taper angle θ1. The taper angle θ1 may be, for example, 35 to 90 degrees.

[0054] In this embodiment, multiple etching processes are sequentially performed on the surfaces of the conductive element 20', seed layer S2, conductive element 20, and seed layer S1 exposed by the mask pattern PR. Because the etching selectivity for hydrofluoric acid differs between seed layer S21 and seed layer S22 of seed layer S2, seed layer S2 can include an undercut. More specifically, at least one side of seed layer S22 protrudes beyond seed layer S21 in the X direction. Alternatively, both sides of seed layer S22 protrude beyond seed layer S21 in the X direction. The width w2 of the portion of seed layer S22 that protrudes beyond seed layer S21 in the X direction may be, for example, 0.1 microns to 1 micron. Similarly, seed layer S1 can also include an undercut for the reasons described above. According to some embodiments, both sides of seed layer S2 may include an undercut. More specifically, both sides of seed layer S22 protrude beyond seed layer S21 in the X direction. In other words, the projected length of seed layer S22 is greater than the projected length of seed layer S21. The width w2 of the portion of seed layer S22 that protrudes beyond seed layer S21 in the X direction on both sides may be, for example, 0.1 microns to 1 micron.

[0055] In this embodiment, the seed layer S11 has a thickness of 0.5 microns to 50 microns. Furthermore, after the etching process, the seed layer S11 has a length L in the X direction of the surface 10_s of the substrate 10. The length L is 5 times to 20 times the thickness of the seed layer S11. Therefore, the adhesion between the seed layer, the conductive element, and the buffer layer BF can be improved.

[0056] Figure 3 is a schematic flowchart of a method for manufacturing an electronic device according to a second embodiment of the present invention. It should be noted that the embodiment in Figure 3 uses some of the reference numerals and details of the embodiment in Figure 2. The same or similar elements are given the same reference numerals, and the same technical details are omitted from the explanation.

[0057] Referring to Figure 3, in this embodiment, the electronic device 1b can be formed by performing the following steps.

[0058] Perform steps (1) to (5). Detailed steps can be found in the embodiments described above and will not be described in detail here.

[0059] Step (6b): Perform a thinning process to expose the surface 10_s of the substrate 10.

[0060] More specifically, a thinning process can be used to remove a portion of the filler material F, conductive element 20, seed layer S1, and buffer layer BF on two opposing sides of the substrate 10, thereby exposing the surface 10_s of the substrate 10. In some embodiments, the thinning process performed may include a polishing process and / or a dry etching process.

[0061] In this embodiment, the material of the substrate 10 has relatively large differences in properties compared to the materials of the buffer layer BF, filler material F, conductive element 20, and seed layer S1. Therefore, after the thinning process, the buffer layer BF, filler material F, conductive element 20, and seed layer S1 located within the via T are stepped relative to the substrate 10. In this embodiment, the distance db between the surface of the buffer layer BF and the surface 10_s of the substrate 10 in the vertical direction Z is 0.1 nanometers to 200 nanometers. The distance df between the surface of the filler material F and the surface 10_s of the substrate 10 in the vertical direction Z is 0.1 nanometers to 2000 nanometers, 0.5 nanometers to 1000 nanometers, 2 nanometers to 800 nanometers, or 10 nanometers to 500 nanometers. By designing the buffer layer BF, filler material F, conductive element 20, and seed layer S1 to have steps relative to the substrate 10, the adhesion ability between the conductive element 20' and the seed layer S2 can be improved.

[0062] Perform step (6a): Form the seed layer S2 on the substrate 10.

[0063] In this embodiment, the seed layer S2 covers the substrate 10, the buffer layer BF, the filler material F, the conductive element 20, and the seed layer S1 located within the via T. More specifically, the seed layer S2 can fill the gaps between the buffer layer BF, the filler material F, the conductive element 20, and the seed layer S1 located within the via T and the substrate 10. The rest of the description of the seed layer S2 can be found in the embodiments described above and will not be elaborated here.

[0064] Step (7b) is performed: the mask pattern PR' is formed on the substrate 10.

[0065] The mask pattern PR' is placed on the seed layer S2 and exposes a portion of the seed layer S2. In this embodiment, the mask pattern PR' does not overlap with the via T and exposes at least the portion of the seed layer S2 that overlaps with the via T. In some embodiments, the mask pattern PR' can be formed by sequentially performing a suitable coating process, an exposure process, and a development process.

[0066] Perform step (9): Form the conductive element 20' on the substrate 10.

[0067] The conductive element 20' is positioned, for example, within a space defined by the mask pattern PR'. More specifically, the conductive element 20' overlaps with at least a portion of the via T. The conductive element 20' overlaps with the via T and is positioned on a seed layer S2 exposed by the mask pattern PR'. In some embodiments, the conductive element 20' can be formed by performing a chemical plating process or an electroplating process. In this embodiment, the conductive element 20' has a thickness of 2 to 60 microns. The rest of the description of the conductive element 20' can be found in the embodiments described above and will not be elaborated here.

[0068] In this embodiment, the conductive element 20' defined by the mask pattern PR' may include a taper angle θ2. The taper angle θ2 may be, for example, 80 degrees to 120 degrees.

[0069] Perform step (10): Use the conductive element 20' to perform the etching process on the seed layer S2.

[0070] It should be noted that in this embodiment, the mask pattern PR' is removed before performing the etching process.

[0071] In this embodiment, multiple wet etching processes are sequentially performed on the surfaces of seed layers S22 and S21 exposed by the mask pattern PR. Since the etching selectivity for hydrofluoric acid differs between seed layer S21 and seed layer S22, seed layer S2 may contain undercuts. More specifically, the width w2 of the portion of seed layer S22 that protrudes beyond seed layer S21 in the X direction may be 0.1 microns to 1 micron.

[0072] In this embodiment, the seed layer S21 has a thickness of 0.5 microns to 50 microns. Furthermore, after the etching process, the seed layer S21 has a length L in the X direction of the surface 10_s of the substrate 10. The length L is 5 times to 20 times the thickness of the seed layer S21.

[0073] Figure 4 is a schematic flowchart of a method for manufacturing an electronic device according to a third embodiment of the present invention. It should be noted that the embodiment in Figure 4 uses some of the reference numerals and details of the embodiment in Figure 3. The same or similar elements are given the same reference numerals, and the same technical details are omitted from the explanation.

[0074] Referring to Figure 4, in this embodiment, the electronic device 1c can be formed by performing the following steps.

[0075] Steps (1) to (6b) are carried out. Detailed steps can be found in the embodiments described above and will not be described in detail here. It should be noted that in this embodiment, the filler material F is a conductive material.

[0076] Step (11) is performed: an insulating layer PAS is formed on the substrate 10.

[0077] In some embodiments, the insulating layer PAS can be formed by a suitable process method. In this embodiment, the insulating layer PAS covers the substrate 10, and the buffer layer BF, filler material F, conductive element 20, and seed layer S1 located within the via T. More specifically, the insulating layer PAS can fill the step created between the buffer layer BF, filler material F, conductive element 20, and seed layer S1 located within the via T and the substrate 10.

[0078] Perform step (12): Remove a portion of the insulating layer PAS on the substrate 10 to expose at least a portion of the filler material F.

[0079] Methods for removing the insulating layer PAS include performing an etching process on the insulating layer PAS using a laser, etching, plasma treatment, photolithography, or a mask pattern (not shown) to form a recess R1 and expose at least a portion of the filler material F. However, the removal method is not limited thereto.

[0080] Perform step (13): Form the conductive element 20” on the substrate 10.

[0081] The conductive element 20” is, for example, placed in a recess R1 of the insulating layer PAS. More specifically, the conductive element 20” overlaps with at least a portion of the via T and is placed on the filler material F exposed by the insulating layer PAS, so that it can be electrically connected to the filler material F and form a path for signal transmission. In some embodiments, the conductive element 20” can be formed by performing a suitable deposition process. In this embodiment, before forming the conductive element 20” the barrier layer BA can first be formed in the recess R1 of the insulating layer PAS and on a portion of the surface of the insulating layer PAS. The material and method of forming the barrier layer BA may be the same as or similar to that of the seed layer S1. The barrier layer BA also includes undercuts.

[0082] Figure 5 is a schematic flowchart of a method for manufacturing an electronic device according to the fourth embodiment of the present invention. It should be noted that the embodiment in Figure 5 uses some of the reference numerals and details of the embodiment in Figure 3. The same or similar elements are given the same reference numerals, and the same technical details are omitted from the explanation.

[0083] Referring to Figure 5, the main difference between the method for forming the electronic device 1d in this embodiment and the method for forming the electronic device 1b described above is that in step (6b), the buffer layer BF located on the surface 10_s of the substrate 10 is not completely removed.

[0084] In this embodiment, after the thinning process, a portion of the buffer layer BF still remains on the surface 10_s of the substrate 10. Therefore, there is no step between the buffer layer BF and the substrate 10.

[0085] Figure 6 is a schematic flowchart of a method for manufacturing an electronic device according to the fifth embodiment of the present invention. It should be noted that the embodiment in Figure 6 uses some of the reference numerals and details of the embodiment in Figure 2. The same or similar elements are given the same reference numerals, and the same technical details are omitted from the explanation.

[0086] Referring to Figure 6, in this embodiment, the electronic device 1e can be formed by performing the following steps.

[0087] Perform steps (1) to (4). Detailed steps can be found in the embodiments described above and will not be described in detail here.

[0088] Perform step (7c): Form the mask pattern "PR" on the substrate 10.

[0089] In this embodiment, the mask pattern PR" is placed on the seed layer S1 and fills the vias T, exposing a portion of the seed layer S1. In this embodiment, the mask pattern PR" fills the vias T, and the exposed seed layer S1 does not overlap with the vias T.

[0090] Perform step (8b): Use the mask pattern PR to perform the etching process on the conductive element 20 and seed layer S1.

[0091] In some embodiments, the etching process performed on the conductive element 20 and the seed layer S1 is a wet etching process. The etching solution used in the wet etching process contains hydrofluoric acid. In this embodiment, the seed layer S1 after the wet etching process may include a taper angle θ1. The taper angle θ1 may be, for example, 35 to 90 degrees.

[0092] In this embodiment, multiple etching processes are sequentially performed on the surfaces of the conductive element 20 and seed layer S1 exposed by the mask pattern PR. Since the etching selectivity for hydrofluoric acid differs between seed layer S11 and seed layer S12 of seed layer S1, seed layer S1 can contain undercuts. More specifically, seed layer S12 protrudes beyond seed layer S11 in the X direction. The width w1 of the portion of seed layer S12 that protrudes beyond seed layer S12 in the X direction may be 0.1 microns to 1 micron.

[0093] In this embodiment, after performing a wet etching process on the conductive element 20 and the seed layer S1, a recess R2 is formed that exposes a portion of the buffer layer BF.

[0094] In this embodiment, the seed layer S11 has a thickness of 0.5 microns to 50 microns. Furthermore, after the etching process, the seed layer S11 has a length L in the X direction of the surface 10_s of the substrate 10. The length L is 5 times to 20 times the thickness of the seed layer S11.

[0095] Step (14) is performed: filler material F is formed on the substrate 10. In this embodiment, the filler material F can, for example, fill vias T and fill recesses R2. In some embodiments, the filler material F can be formed by performing a suitable deposition process. Since the depth of the recesses R2 is less than the depth of vias T (or the thickness of the substrate 10), the filler material F that overlaps with vias T in the vertical direction Z has recesses. The maximum depth df of the recesses is 0.1 nanometers to 100 nanometers.

[0096] The distance dt between the upper surface of the filler material F and the buffer layer BF exposed by the recess R2 is 15 to 50 microns.

[0097] Figure 7 is a schematic partial cross-sectional view of a package structure according to one embodiment of the present invention. It should be noted that the embodiment in Figure 7 uses some of the reference numerals and details of the embodiments in Figures 1 to 6. The same or similar elements are given the same reference numerals, and the same technical details are omitted from the description.

[0098] In this embodiment, the electronic device 1000 includes a substrate 10, vias T, a circuit structure 30, and a plurality of different or identical electronic elements arranged on the circuit board 1, and can implement a 2.5D package structure in which the plurality of electronic elements are arranged horizontally. Furthermore, the electronic device 1000 includes a plurality of electronic elements embedded in the substrate 10 (details will be described later), thereby providing better integration capabilities.

[0099] In this embodiment, the package structure 1000 includes three electronic elements 3a, 3b, and 3c. Electronic element 3a may be, for example, a high-bandwidth memory (HBM) and can be electrically connected to an electronic element (e.g., electronic element 4a or electronic element 4b) embedded in the substrate 10 via a pad PAD1 and a circuit structure 30 (e.g., a redistribution structure). Electronic element 3b may be, for example, a system-on-integrated chip (SoIC) and is packaged by a sealing layer PL and can be electrically connected to an electronic element embedded in the substrate 10 via a pad PAD2 and a circuit structure 30. Electronic element 3c may be a photonic integrated circuit (PIC) and can be electrically connected to an electronic element embedded in the substrate 10 via a connection element CU1 and a circuit structure 30, and can establish a communication path via an optical fiber F.

[0100] In this embodiment, the package structure 1000 includes electronic elements embedded in the substrate 10, such as electronic element 4a or electronic element 4b. Electronic element 4a may be an embedded deep trench capacitor (eDTC). Electronic element 4b may be an integrated voltage regulator (IVR).

[0101] In this embodiment, the circuit board 1 may include the electronic devices 1a, 1b, 1c, 1d, or 1e of the embodiments described above. According to some embodiments, the circuit board 1 may have at least one other via T'. In the X direction, the width of the other via T' may be greater than the width of the via T of the substrate 10. According to some embodiments, the thickness of the substrate included in the circuit board 1 is greater than the thickness of the substrate 10. According to some embodiments, the Young's modulus of the substrate of the circuit board 1 is greater than the Young's modulus of the substrate 10. With the above-described design, the circuit board 1 can mount more elements or the reliability of the electronic devices can be improved. According to some embodiments, the circuit board 1 may include glass.

[0102] As described above, in the method for manufacturing electronic devices provided by some embodiments of the present invention, the conductive elements formed on the substrate have a discontinuous shape. Therefore, multiple parts having different structures can be formed on the upper and / or lower surfaces of the substrate, thereby aligning the stresses generated when the electronic device heats up and improving the yield of the electronic device. [Industrial applicability]

[0103] The electronic device and its manufacturing method of the present invention can be applied to panel-level packages and methods for manufacturing the same. [Explanation of symbols]

[0104] 3, 3a, 3b, 3c electronic elements 10 circuit boards 10S circuit board side view 20 Conductive elements 22 First Conductive Related 24 Second conductive element 26 Third conductive element 30, 32, 34 circuit structure A-A' Section Line AA Active Area CU1, CU2 connecting elements F Filling material F1 1st filling material F2 2nd filling material IL insulating layer L Length M conductive layer PA surrounding area PAD PAS insulating layer PL sealing layer T Beer T1 First Via T2 Second Via T3 Third Via UF middle layer X, Y, Z directions d1 First interval d2 2nd interval d3 Third interval p1, p2, p3 aperture

Claims

1. circuit board and The substrate penetrates the via and includes a first via and a second via, Displaced within the via, the conductive element includes a first conductive element and a second conductive element, wherein the first conductive element is disposed within the first via and the second conductive element is disposed within the second via. A circuit structure arranged on the substrate and electrically connected to the conductive element, An electronic device comprising, in a first direction, having a first gap between two adjacent first conductive elements and a second gap between two adjacent second conductive elements, wherein the first gap is larger than the second gap.

2. The electronic device according to claim 1, wherein a filling material is placed in the via.

3. The electronic device according to claim 1, wherein, in the first direction, the first via has a first opening, the second via has a second opening, and the first opening is larger than the second opening.

4. Displaced on the conductive element, First seed tier, A second seed layer is placed on the first seed layer, A seed layer including, The electronic device according to claim 1, further comprising, wherein at least one side of the second seed layer protrudes beyond the first seed layer in the first direction, and the width of the portion of the second seed layer that protrudes beyond the first seed layer in the first direction is 0.1 microns to 1 micron.

5. The electronic device according to claim 4, wherein the second seed layer includes a taper angle, and the taper angle is 35 degrees to 90 degrees.

6. Another conductive element disposed on the seed layer and overlapping at least a portion of the vias The electronic device according to claim 4, further comprising:

7. The electronic device according to claim 6, wherein the second conductive element includes a taper angle, and the taper angle is 80 degrees to 120 degrees.

8. The electronic device according to claim 2, wherein there is a distance between the surface of the filler material and the surface of the substrate in the vertical direction, the vertical direction is perpendicular to the first direction, and the distance is between 0.1 nanometers and 200 nanometers.

9. circuit board and The substrate penetrates the via and includes a first via and a second via, Displaced within the via, the conductive element includes a first conductive element and a second conductive element, wherein the first conductive element is disposed within the first via and the second conductive element is disposed within the second via. A circuit structure arranged on the substrate and electrically connected to the conductive element, An electronic device comprising, wherein the first conductive element fills the first via, and the second conductive element fills the second via.

10. The electronic device according to claim 9, wherein the conductive element overlaps with the packing element in the vertical direction, the packing element has a recess, and the maximum depth of the recess is 0.1 nanometers to 100 nanometers.

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