Display control system and signal level control circuit

Abstract

Reduces the duration of the white streaks that appear on the LCD display unit screen when the power is forcibly turned off. [Solution] The DISP signal control circuit 200 includes a delay circuit section 220 that delays the vertical synchronization signal by a delay time, an inverter circuit section 230 that inverts the signal level of the output signal of the delay circuit section 220, a D-FF 240 that takes the vertical synchronization signal as the input to the D terminal, takes the output signal of the inverter circuit section 230 as the input to the CLK terminal, holds the signal level of the input signal of the D terminal at the timing of the rising edge of the input signal of the CLK terminal, and outputs a signal with a signal level inverted relative to the held input signal level to the Q terminal, and a bipolar transistor 260 that is placed between the signal line of the DISP signal and ground (GND), and is in a non-conductive state when the signal level of the output signal of the Q terminal is low level, and conducts when it is high level.

Description

Technical Field

[0001] The present invention relates to a display control system and a signal level control circuit, and particularly to a display control system and a signal level control circuit for switching the screen of a liquid crystal display unit between a display state and a non-display state.

Background Art

[0002] Conventionally, various techniques have been provided to solve problems occurring in the display of liquid crystal display units. For example, in Patent Document 1, in a liquid crystal display unit adopting a configuration in which light is projected from a backlight onto a liquid crystal display panel, causes for the display to become invisible are assumed to include burnout of a fluorescent lamp, failure of an inverter circuit, failure of a power supply to the inverter circuit, etc., and one or more types of abnormality detection means capable of detecting abnormalities in these display systems are provided. When one or more types of abnormality detection means detect an abnormality, an abnormality display corresponding to the detection content is presented to the user visually or the like by an abnormality display means.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, when the device enters an abnormal state such as freezing and the power of the device is forcibly turned off, in a conventional display control system that controls the display of a liquid crystal display unit, white streaks may appear on the screen of the liquid crystal display unit. This will be described below.

[0005] Conventional display control systems include a power management unit connected to a power switch, a first board equipped with a first control unit capable of communicating with the power management unit, and a second board equipped with an FET placed in the wire between the power management unit and the liquid crystal display unit, and a second control unit capable of switching the conduction and non-conduction states of the FET and communicating with the first control unit. The second control unit, which is further away from the power management unit, will lose voltage later than the first control unit, which is closer to the power management unit, and will stop operating later than the first control unit.

[0006] The first control unit outputs a Vertical Synchronizing Signal (VSYNC) and an image data signal to the liquid crystal display unit. The second control unit outputs a display control signal (DISP signal) to the liquid crystal display unit, which displays the screen when the signal level is high and turns off the screen when the signal level is low.

[0007] In the event of a forced power off due to an abnormality such as the device freezing, if the user presses and holds the power switch for 5 seconds or more while the power is on, the power management unit will detect the 5-second or longer press and hold of the power switch and forcibly switch the device, including the display control system, to a power-off state.

[0008] At this time, on the first board side, such as the first control unit, the output of image data signals from the first control unit to the liquid crystal display unit stops, and the signal level of the vertical synchronization signal from the first control unit to the liquid crystal display unit becomes low, and the low-level vertical synchronization signal continues.

[0009] After the first board, such as the first control unit, stops outputting the image data signal and the vertical synchronization signal signal level becomes low, and the vertical synchronization signal continues at a low level, on the second board, such as the second control unit, the signal level of the DISP signal from the second control unit to the liquid crystal display unit transitions from high to low, the low-level DISP signal continues, and voltage is no longer supplied to the liquid crystal display unit.

[0010] From the moment the output of the image data signal stops and the signal level of the vertical synchronization signal goes low, until the moment the signal level of the DISP signal transitions from high to low, until the moment the low-level DISP signal resumes, and until the voltage supply to the liquid crystal display unit stops, the DISP signal remains at a high level and the output of the image data signal stops. As a result, white streaks appear on the screen of the liquid crystal display unit during this period.

[0011] This invention has been made in view of the above circumstances, and aims to shorten the duration of the appearance of white streaks that appear on the screen of the liquid crystal display unit when the power is forcibly turned off. [Means for solving the problem]

[0012] A display control system according to one aspect of the present invention is a display control system for controlling the display of a liquid crystal display unit, wherein the display control system comprises a power management unit to which a power switch is connected, a first board equipped with a first control unit that is supplied with voltage from the power management unit and can communicate with the power management unit, and a second board equipped with a second control unit that is supplied with voltage from the power management unit and can communicate with the first control unit, wherein the first control unit outputs a vertical synchronization signal to the liquid crystal display unit, the second control unit outputs a screen display control signal to the liquid crystal display unit such that when the signal level is high, the screen of the liquid crystal display unit is displayed, and when the signal level is low, the screen of the liquid crystal display unit is not displayed, and the second board is further equipped with a signal level control circuit that controls the signal level of the screen display control signal, the signal level control circuit controls the vertical synchronization signal during one low-level period T of the vertical synchronization signal. Low A single low-level period T of the vertical synchronization signal that is longer than the above. Low and one high-level period T High The combined period T Low +T High A predetermined delay time T that is shorter than DDelay it by a fraction, and use the vertical synchronization signal for the predetermined delay time T D A delay circuit unit that delays it by a fraction and outputs a first signal, an inverter circuit unit that inverts the signal level of the first signal output by the delay circuit unit and outputs a second signal with the signal level of the first signal inverted, using the vertical synchronization signal as the input to the D terminal and the second signal output by the inverter circuit unit as the input to the CLK terminal, holding the signal level of the vertical synchronization signal input to the D terminal at the timing of the rising edge of the second signal input to the CLK terminal, and a D flip-flop that outputs a third signal with the signal level inverted with respect to the held signal level of the vertical synchronization signal to the / Q terminal, and a switching circuit unit that is disposed between the signal line through which the second control unit outputs the screen display control signal to the liquid crystal display unit and the ground, and is in a non-conducting state when the signal level of the third signal is at a low level and is in a conducting state when the signal level of the third signal is at a high level.

[0013] In a signal level control circuit according to an aspect of the present invention, in the signal level control circuit, the vertical synchronization signal output from the first control unit to the liquid crystal display unit is delayed by a predetermined delay time T that is longer than one low-level period T of the vertical synchronization signal and shorter than the period T + T obtained by combining one low-level period T and one high-level period T of the vertical synchronization signal. Low Delay it by a fraction, and use the vertical synchronization signal for the predetermined delay time T Low and one high-level period T High combined period T Low +T High Delay it by a fraction, and use the vertical synchronization signal for the predetermined delay time T D Delay it by a fraction, and use the vertical synchronization signal for the predetermined delay time T DThe system comprises: a delay circuit section that outputs a first signal delayed by several minutes; an inverter circuit section that inverts the signal level of the first signal output by the delay circuit section and outputs a second signal with the signal level of the first signal inverted; a D flip-flop that takes the vertical synchronization signal as input to the D terminal, takes the second signal output by the inverter circuit section as input to the CLK terminal, holds the signal level of the vertical synchronization signal input to the D terminal at the rising edge timing of the second signal input to the CLK terminal, and outputs a third signal with a signal level inverted with respect to the held signal level of the vertical synchronization signal as output to the / Q terminal; and a switching circuit section that outputs a screen display control signal to the liquid crystal display unit, which is positioned between the signal line that outputs the screen display control signal to the liquid crystal display unit and ground, and is in a non-conductive state when the signal level of the third signal is low and conductive when the signal level of the third signal is high. [Effects of the Invention]

[0014] According to the present invention, a predetermined delay time T is obtained from the falling edge of the vertical synchronization signal. DA second signal, input to the CLK terminal of the D flip-flop, rises after a delay of a few minutes. If the signal level of the vertical synchronization signal input to the D terminal of the D flip-flop is low at the timing of the second signal's rise, the signal level of the third signal output from the / Q terminal of the D flip-flop becomes high, causing the switching circuit to conduct. As a result, the signal level of the screen display control signal input to the liquid crystal display unit becomes low, turning off the screen of the liquid crystal display unit. In this way, by using the vertical synchronization signal to control the signal level of the screen display control signal in the signal level control circuit, it becomes possible to shorten the time from the falling edge of the vertical synchronization signal to the low level of the screen display control signal when the vertical synchronization signal no longer rises to a high level due to a forced power off. This shortens the duration for which white lines appear on the screen of the liquid crystal display unit when the power is forcibly turned off. [Brief explanation of the drawing]

[0015] [Figure 1] This is a system configuration diagram of a display control system according to one embodiment of the present invention. [Figure 2] This figure shows the timing chart for some of the signals in the display control system shown in Figure 1. [Figure 3] This is a system configuration diagram of the display control system in the comparative example. [Figure 4] This figure shows the sequence of LCD screen blackouts during normal power-off using the display control system of the comparative example shown in Figure 3. [Figure 5] This figure shows the sequence of LCD screen blackouts when the display control system of the comparative example in Figure 3 is forcibly powered off. [Figure 6] Figure 5 shows an example of white lines that appear on the LCD screen during the screen blackout sequence when the power is forcibly turned off. [Modes for carrying out the invention]

[0016] The following describes a display control system according to one embodiment of the present invention, with reference to the drawings.

[0017] First, the system configuration of the display control system 100 according to one embodiment of the present invention will be described with reference to Figure 1. Figure 1 is a system configuration diagram of the display control system 100 according to one embodiment of the present invention.

[0018] The display control system 100 controls the display of the LCD (Liquid Crystal Display) 130 and comprises a main board 110 equipped with a PMIC (Power Management Integrated Circuit) 111 and a CPU (Central Processing Unit) 112, and a panel board 120 equipped with an FET (Field Effect Transistor) 121, a CPU 122, and a DISP signal control circuit 200.

[0019] The PMIC111 is connected to a power switch (PSW). The PMIC111 is an IC that manages power, such as converting a 24V voltage to a 3.3V voltage (3.3V1C). When the user turns on the PMIC111 using the power switch PSW, it supplies a voltage of 3.3(V) (3.3V1_C) to the CPU112, CPU122, FET121, and the D-FF (D flip-flop) 240 of the DISP signal control circuit 200. When the user turns off the power using the power switch PSW (for example, pressing the power switch PSW for less than 5 seconds (5 seconds is just an example and is not limited to this) (normal power off operation), or pressing the power switch PSW for 5 seconds (5 seconds is just an example and is not limited to this) or longer (forced power off operation)), the voltage (3.3V1_C) becomes 0(V), and voltage is no longer supplied from the PMIC111 to the CPU112, CPU122, FET121, D-FF240, etc. Furthermore, CPU122, which is further away from PMIC111, will lose voltage later than CPU112, which is closer to PMIC111, and will therefore stop operating later than CPU112.

[0020] CPU112 is constructed, for example, by an ASIC (Application Specific Integrated Circuit), and receives voltage (3.3V 1C) from PMIC111. CPU112 can communicate with PMIC111 and can communicate with CPU122 mounted on panel board 120.

[0021] FET121 is placed in the wire between PMIC111 and LCD130 and is switched between a conductive state and a non-conductive state by CPU122. Note that FET121 is just one example of a switching circuit, and the switching circuit placed in the wire between PMIC111 and LCD130 may be a switching circuit other than an FET.

[0022] The CPU 122 is supplied with voltage (3.3V1_C) from the PMIC 111. The CPU 122 can communicate with the CPU 112 mounted on the main board 110. The CPU 122 switches the FET 121 between a conductive state and a non-conductive state. For example, the CPU 122 controls the FET 121 to be conductive when the power is turned on and to be non-conductive when the power is turned off. The voltage supplied to the LCD 130 (3.3V1_REC) is 3.3V when the FET 121 is controlled to be conductive by the CPU 122, and 0V when the FET 121 is controlled to be non-conductive by the CPU 122.

[0023] The CPU 112 outputs a vertical synchronization signal to the LCD 130 and the buffer circuit section 210 of the DISP signal control circuit 200, which are connected to the signal line that outputs the vertical synchronization signal (hereinafter referred to as the "vertical synchronization signal line" as appropriate). The vertical synchronization signal is a signal that indicates the timing for starting the scanning of one screen (one frame). When the power is on, the CPU 112 outputs a vertical synchronization signal (VSYNC) to the LCD 130 and the buffer circuit section 210, which alternates between a high level (greater than 0(V), for example, 2(V)) and a low level (0(V)) as a signal level. In the case of a normal power off by pressing the power switch PSW for less than 5 seconds (5 seconds is just an example and is not limited to this), the CPU 112 receives an off-mode transition instruction signal from the PSW 111, which is output by the PMIC 111 when it detects that the power switch PSW has been pressed for less than 5 seconds, and sets the vertical synchronization signal to a low level, and continues to output the low-level vertical synchronization signal to the LCD 130 and the buffer circuit section 210. In the case of a forced power off by pressing and holding the power switch PSW for 5 seconds or more, the CPU 112 will stop operating because voltage will no longer be supplied to it from PSW111. As a result, the vertical synchronization signal will become low level, and a low-level vertical synchronization signal will continue to be input to the LCD 130 and the buffer circuit 210.

[0024] Furthermore, the CPU 112 outputs image data signals of images to be displayed on the screen of the LCD 130, which are stored in memory (not shown), to the LCD 130 connected to the signal line that outputs said image data signals. The image data signals have two signal levels: high level (greater than 0(V), for example 2(V): image data value "1") and low level (0(V): image data value "0").

[0025] The CPU 122 outputs a screen display control signal (DISP signal) to the LCD 130, which is connected to the signal line that outputs the DISP signal (hereinafter referred to as the "DISP signal line" as appropriate). The DISP signal is used to switch the LCD 130 screen between a display state and a non-display state. When the signal level is high (greater than 0(V), for example, 2(V)), the LCD 130 screen is displayed, and when the signal level is low (0(V)), the LCD 130 screen is non-displayed. The CPU 122 transitions the DISP signal level from low to high during startup, etc. In the case of a normal power off by pressing the power switch PSW for less than 5 seconds, the CPU 122 receives an off-mode transition instruction signal from the CPU 112, which is output by the CPU 112 after it receives an off-mode transition instruction signal from the PMIC 111, and transitions the DISP signal level from high to low, continuing to output a low-level DISP signal to the LCD 130.

[0026] The DISP signal control circuit 200 mounted on the panel board 120 controls the signal level of the DISP signal, which transitions from a high level to a low level when the power is forcibly turned off. It comprises a buffer circuit section 210, a delay circuit section 220, an inverter circuit section 230, a D-FF 240, a resistor element 250, and a bipolar transistor 260. A predetermined delay time T, which will be described later, is also controlled. D This is a single low-level period T of the vertical synchronization signal. Low (See Figure 2) Longer than the single low-level period T of the vertical synchronization signal. Low (See Figure 2) and one high-level period T High (See Figure 2) The combined period T Low +T High It is shorter than this. Therefore, when the signal level of the vertical synchronization signal repeatedly switches between high and low levels, there is a predetermined delay time T after the signal level of the vertical synchronization signal transitions from high to low. DAt the time elapsed, the signal level of the vertical synchronization signal is high. On the other hand, in the case of a forced power off, the signal level of the vertical synchronization signal input to the DISP signal control circuit 200 remains low, and a predetermined delay time T occurs after the signal level of the vertical synchronization signal transitions from high to low. D At the point when this time has elapsed, the signal level of the vertical synchronization signal is low.

[0027] The buffer circuit section 210 is positioned between the signal line (vertical synchronization signal line) on which the CPU 112 outputs a vertical synchronization signal, the D terminal of the D flip-flop 240, and the delay circuit section 220 (one end of the resistor element 221 that constitutes the delay circuit section 220). The input terminal of the buffer circuit section 210 is connected to the vertical synchronization signal line, and the vertical synchronization signal is input to the input terminal of the buffer circuit section 210. The output terminal of the buffer circuit section 210 is connected to the input terminal of the delay circuit section 220 (one end of the resistor element 221 that constitutes the delay circuit section 220) and the D terminal of the D-FF 240, and the signal output from the output terminal of the buffer circuit section 210 (hereinafter referred to as "buffer output signal") is input to the input terminal of the delay circuit section 220 and the D terminal of the D-FF 240. The buffer output signal has two signal levels: high level (greater than 0(V), for example, 2(V)) and low level (0(V)). The signal level of the vertical synchronization signal input to the input terminal of the buffer circuit 210 is the same as the signal level of the buffer output signal output from the output terminal of the buffer circuit 210. The buffer circuit 210 is configured to suppress the influence of the DISP signal control circuit 200 on the vertical synchronization signal.

[0028] The delay circuit section 220 includes a resistor 221 and a capacitor 222. One end of the resistor 221 is connected to the output terminal of the buffer circuit section 210, and the other end is connected to one end of the capacitor 222. One end of the capacitor 222 is connected to the other end of the resistor 221 and also to the input terminal of the inverter circuit section 230, and the other end is connected to GND (ground).

[0029] The buffer output signal output by the buffer circuit 210 is input to the input terminal (one end of the resistor element 221) of the delay circuit 220, and the delay circuit 220 delays the buffer output signal input to the input terminal during one low-level period T of the vertical synchronization signal. Low (See Figure 2) Longer than the single low-level period T of the vertical synchronization signal. Low (See Figure 2) and one high-level period T High (See Figure 2) The combined period T Low +T High A predetermined delay time T that is shorter than D The buffered output signal is delayed by a predetermined delay time T. D A signal delayed by several minutes (hereinafter referred to as the "first signal") is output from the output terminal (one end of the capacitor element 222). The first signal output from the output terminal of the delay circuit 220 is input to the input terminal of the inverter circuit 230. The signal level of the first signal can be high level (greater than 0(V), for example, 2(V)) or low level (0(V)). The signal level of the buffer output signal input to the input terminal of the delay circuit 220 is the same as the signal level of the first signal output from the output terminal of the delay circuit 220.

[0030] Delay time T of delay circuit section 220 D This is determined by the resistance of the resistive element 221 and the capacitance of the capacitive element 222.

[0031] High-level period T High This is the low-level period T. Low A predetermined delay time T that is longer than D is within the above range (low-level period T) Low Longer than, period T Low +T High Within a range shorter than the above, the low-level period T Low It may also be considered to be more than twice that amount of time.

[0032] High-level period T High This is the low-level period T. Low A predetermined delay time T that is longer than D This is the low-level period T. LowIt may also be assumed to be twice the time.

[0033] In this embodiment, the high-level period T High This is the low-level period T. Low Longer than (T High >T Low ), Low-level period T Low When = 2 (μs), the predetermined delay time T D This is the low-level period T. Low Twice the time (T Low Let's assume that ×2 = 4 (μs).

[0034] The input terminal of the inverter circuit 230 is connected to the output terminal of the delay circuit 220 (one end of the capacitor element 222), and the CLK terminal of the D-FF240 is connected to the output terminal of the inverter circuit 230.

[0035] The first signal output by the delay circuit 220 is input to the input terminal of the inverter circuit 230. The inverter circuit 230 inverts the signal level of the first signal input to the input terminal and outputs a signal with the signal level of the first signal inverted (hereinafter referred to as the "second signal") from its output terminal. The second signal output from the output terminal of the inverter circuit 230 is input to the CLK terminal of the D-FF240. The signal level of the second signal can be high level (greater than 0(V), for example, 2(V)) or low level (0(V)).

[0036] The D terminal of the D-FF240 is connected to the output terminal of the buffer circuit section 210, the CLK terminal is connected to the output terminal of the inverter circuit section 230, and one end of the resistor element 250 is connected to the / Q terminal.

[0037] In the D-FF240, the buffer output signal (vertical synchronization signal via the buffer circuit 210) output by the buffer circuit 210 is used as the input to the D terminal, and the second signal output by the inverter circuit 230 is used as the input to the CLK terminal. In the following, the buffer output signal input to the D terminal will be referred to as the "D signal" as appropriate, and the second signal input to the CLK terminal will be referred to as the "CLK signal" as appropriate.

[0038] The D-FF240 holds the signal level of the D signal input to the D terminal at the rising edge of the second signal (the rising edge of the CLK signal) when the signal level of the CLK signal input to the CLK terminal transitions from a low level to a high level. The signal level of the D signal input to the D terminal is then inverted (hereinafter referred to as the "third signal" or " / Q signal") and this signal is output from the / Q terminal. The / Q signal output from the D-FF240's / Q terminal remains unchanged from the rising edge of the CLK signal input to the D-FF240's CLK terminal until the next rising edge of the CLK signal. The / Q signal has two signal levels: high level (greater than 0(V), e.g., 2(V)) and low level (0(V)).

[0039] One end of the resistor 250 is connected to the / Q terminal of the D-FF240, and the / Q signal is input from the / Q terminal of the D-FF240. The other end is connected to the base of the bipolar transistor 260, and a signal (hereinafter referred to as "OUT1 signal") is output to the base of the bipolar transistor 260. The OUT1 signal has two signal levels: high level (greater than 0(V), e.g., 2(V)) and low level (0(V)). The signal level of the / Q signal input to one end of the resistor 250 is the same as the signal level of the OUT1 signal output from the other end of the resistor 250.

[0040] The bipolar transistor 260 is an NPN type bipolar transistor and is positioned between the signal line (DISP signal line) to which the CPU 122 outputs the DISP signal and GND (ground). Specifically, the base of the bipolar transistor 260 is connected to the other end of the resistor element 250, the collector is connected to the DISP signal line, and the emitter is connected to GND.

[0041] The perpolar transistor 260 becomes non-conductive when the signal level of the OUT1 signal input to its base is low (when the signal level of the / Q signal output from the / Q terminal of the D-FF240 is low). In this case, the signal level of the DISP signal input to the LCD130 becomes the signal level of the DISP signal output by the CPU122. The bipolar transistor 260 becomes conductive when the signal level of the OUT1 signal input to its base is high (when the signal level of the / Q signal output from the / Q terminal of the D-FF240 is high). In this case, the DISP signal line is connected to GND, and the signal level of the DISP signal on the DISP signal line becomes low.

[0042] Note that the bipolar transistor 260 is just one example of a switching circuit, and the switching circuit placed between the DISP signal line and GND may be a switching circuit other than a bipolar transistor.

[0043] The LCD130 displays an image on its screen when the DISP signal level is high, and displays an image on the screen based on the image data signal while maintaining vertical synchronization with the vertical synchronization signal. On the other hand, the LCD130 turns off the screen when the DISP signal level is low. When the DISP signal level is high, the LCD130 displays an image on its screen by operating the drive circuits that drive each part of the LCD130. On the other hand, when the DISP signal level is low, the LCD130 prevents an image from being displayed on its screen by stopping the drive circuits that drive each part of the LCD130. The frame rate of the LCD130 is 60Hz or 120Hz, and the high-level period of the vertical synchronization signal T High and low-level period T Low The combined period T High +T Low In the former case, it is approximately 0.017 ms, and in the latter case, it is approximately 0.008 ms.

[0044] Next, we will explain the sequence for turning off the LCD 130 screen during normal power-off by the display control system 100, whose system configuration is shown in Figure 1 (the sequence for switching the LCD 130 screen from the displayed state to the hidden state).

[0045] When the power is on, PMIC111 detects that the power switch PSW has been pressed for less than 5 seconds and outputs an off-mode transition instruction signal to CPU112. When CPU112 receives the off-mode transition instruction signal from PMIC111, it outputs the off-mode transition instruction signal to CPU122. When CPU112 receives the off-mode transition instruction signal from PMIC111, it stops outputting the image data signal to LCD130. As a result, the signal level of the image data signal from CPU112 to LCD130 remains low, with no image data. When CPU122 receives the off-mode transition instruction signal from CPU112, it transitions the signal level of the DISP signal from high to low, and continues to output the low-level DISP signal to LCD130. CPU112 sets the signal level of the vertical synchronization signal to low, and continues to output the low-level vertical synchronization signal to LCD130. CPU122 controls FET121 to a non-conductive state. As a result, the voltage (3.3V1_REC) becomes 0 (V), and no voltage is supplied to the LCD130. In the normal power-off sequence for the LCD130 screen, the DISP signal is maintained at a low level before the vertical sync signal is maintained at a low level, so no white streaks appear on the LCD130 screen.

[0046] Next, the operation of the display control system shown in Figure 1 will be explained with reference to Figure 2. Figure 2 is a timing chart of some of the signals in the display control system shown in Figure 1.

[0047] The vertical synchronization signal level is low, the CLK signal level is high, the D signal level is low, the / Q signal (OUT1 signal) level is low, and the DISP signal level is high.

[0048] At timing T1 in this state, the CPU 112 transitions the signal level of the vertical synchronization signal from a low level to a high level. The high-level vertical synchronization signal is input to the input terminal of the buffer circuit 210, and a high-level buffer output signal is output from the output terminal of the buffer circuit 210. The high-level buffer output signal (D signal) output from the output terminal of the buffer circuit 210 is input to the D terminal of the D-FF240.

[0049] A high-level buffer output signal, which is output from the output terminal of the buffer circuit section 210, is input to the input terminal of the delay circuit section 220, and a predetermined delay time T is applied by the delay circuit section 220. D The buffer output signal is delayed by a predetermined delay time T from the output terminal of the delay circuit section 220. D A first signal with a high signal level, delayed by several minutes, is output.

[0050] A first signal with a high signal level output from the output terminal of the delay circuit 220 is input to the input terminal of the inverter circuit 230. The inverter circuit 230 inverts the signal level of the first signal from high to low, and a second signal with a low signal level (the inverted signal level of the first signal) is output from the output terminal of the inverter circuit 230. The second signal (CLK signal) with a low signal level output from the output terminal of the inverter circuit 230 is input to the CLK terminal of the D-FF240. The CLK signal input to the CLK terminal of the D-FF240 is delayed from timing T1 to delay time T D At the elapsed timing T2, the signal level transitions from high to low (falling edge of the CLK signal). In the D-FF240, at the falling edge of the CLK signal input to the CLK terminal, the signal level of the / Q signal output from the / Q terminal remains low, the signal level of the OUT1 signal remains low, the bipolar transistor 260 remains non-conductive, and the signal level of the DISP signal remains high.

[0051] The circuit operation when CPU112 outputs a vertical synchronization signal whose signal level alternates between high and low is as follows:

[0052] At timing T3, the CPU 112 transitions the signal level of the vertical synchronization signal from a high level to a low level. The low-level vertical synchronization signal is input to the input terminal of the buffer circuit 210, and a low-level buffer output signal is output from the output terminal of the buffer circuit 210. The low-level buffer output signal (D signal) output from the output terminal of the buffer circuit 210 is input to the D terminal of the D-FF240.

[0053] A buffer output signal with a low signal level, output from the output terminal of the buffer circuit section 210, is input to the input terminal of the delay circuit section 220, and a predetermined delay time T is applied by the delay circuit section 220. D The buffer output signal is delayed by a predetermined delay time T from the output terminal of the delay circuit section 220. D A first signal with a low signal level, delayed by several minutes, is output.

[0054] A first signal with a low signal level output from the output terminal of the delay circuit 220 is input to the input terminal of the inverter circuit 230. The inverter circuit 230 inverts the signal level of the first signal from low to high, and a second signal with a high signal level, which is the inverted signal level of the first signal, is output from the output terminal of the inverter circuit 230. The second signal (CLK signal) with a high signal level output from the output terminal of the inverter circuit 230 is input to the CLK terminal of the D-FF240. The CLK signal input to the CLK terminal of the D-FF240 is delayed from timing T3 to delay time T D At the elapsed time T5, the signal level transitions from a low level to a high level (the rising edge of the CLK signal).

[0055] The elapsed time from timing T3, when the signal level of the vertical synchronization signal transitions from a high level to a low level, to timing T5 is longer than the low-level period TLow of the vertical synchronization signal. Low and high-level period T High The combined period T Low +T High Because it is shorter, the signal level of the vertical synchronization signal at timing T5 is high.

[0056] At timing T5, a high-level vertical synchronization signal output by the CPU 112 is input to the input terminal of the buffer circuit 210, and a high-level buffer output signal is output from the output terminal of the buffer circuit 210. The high-level output signal (D signal) output from the output terminal of the buffer circuit 210 is input to the D terminal of the D-FF240.

[0057] At timing T5, the CLK signal input to the CLK terminal of the D-FF240 is on its rising edge, and the signal level of the D signal input to the D terminal of the D-FF240 is high. The D-FF240 maintains the high signal level of the D signal input to the D terminal at the timing of the rising edge of the CLK signal input to the CLK terminal, outputs a low-level / Q signal from the / Q terminal, and the low-level OUT1 signal is input to the base of the bipolar transistor 260. The bipolar transistor 260 remains non-conductive, and the signal level of the DISP signal remains high.

[0058] At timings T4 and T6, the same circuit operation as at timings T1 and T2 occurs. At timing T4, the signal level of the vertical synchronization signal transitions from a low level to a high level, and from timing T4, the delay time T DAt the elapsed timing T6, the signal level of the CLK signal input to the CLK terminal of the D-FF240 transitions from a high level to a low level (falling edge of the CLK signal). In the D-FF240, at the falling edge of the CLK signal input to the CLK terminal, the signal level of the / Q signal output from the / Q terminal remains at a low level, the signal level of the OUT1 signal remains at a low level, the bipolar transistor 260 remains in a non-conductive state, and the signal level of the DISP signal remains at a high level.

[0059] The circuit operation at timings T7 to T10 is the same as the rotational operation at timings T3 to T6.

[0060] The circuit operation when the signal level of the vertical synchronization signal input to the DISP signal control circuit 200 remains low due to a forced power off is as follows:

[0061] At timing T11, the forced power-off causes the signal level of the vertical sync signal on the vertical sync signal line to transition from high to low. The low-level vertical sync signal is input to the input terminal of the buffer circuit 210, and a low-level buffer output signal is output from the output terminal of the buffer circuit 210. The low-level buffer output signal (D signal) output from the output terminal of the buffer circuit 210 is input to the D terminal of the D-FF240.

[0062] A buffer output signal with a low signal level, output from the output terminal of the buffer circuit section 210, is input to the input terminal of the delay circuit section 220, and a predetermined delay time T is applied by the delay circuit section 220. D The buffer output signal is delayed by a predetermined delay time T from the output terminal of the delay circuit section 220. D A first signal with a low signal level, delayed by several minutes, is output.

[0063] A first signal with a low signal level output from the output terminal of the delay circuit 220 is input to the input terminal of the inverter circuit 230. The inverter circuit 230 inverts the signal level of the first signal from low to high, and a second signal with a high signal level, which is the inverted signal level of the first signal, is output from the output terminal of the inverter circuit 230. The second signal (CLK signal) with a high signal level output from the output terminal of the inverter circuit 230 is input to the CLK terminal of the D-FF240. The CLK signal input to the CLK terminal of the D-FF240 is delayed from timing T11 by time T D At the elapsed time T12, the signal level transitions from a low level to a high level (the rising edge of the CLK signal).

[0064] Due to the forced power off, the signal level of the vertical sync signal on the vertical sync signal line remains low, and there is a delay time T from the timing T11 when the signal level of the vertical sync signal transitions from high to low. D At the elapsed timing T12, the signal level of the vertical synchronization signal is low.

[0065] At timing T12, a low-level vertical synchronization signal is input to the input terminal of the buffer circuit 210, and a low-level buffer output signal is output from the output terminal of the buffer circuit 210. The low-level output signal (D signal) output from the output terminal of the buffer circuit 210 is input to the D terminal of the D-FF240.

[0066] At timing T12, the CLK signal input to the CLK terminal of the D-FF240 is on its rising edge, and the signal level of the D signal input to the D terminal of the D-FF240 is low. The D-FF240 maintains the low signal level of the D signal input to the D terminal at the timing of the rising edge of the CLK signal input to the CLK terminal, outputs a high-level / Q signal from the / Q terminal, and the high-level OUT1 signal is input to the base of the bipolar transistor 260, causing the bipolar transistor 260 to conduct, and the signal level of the DISP signal transitions from high to low.

[0067] The following describes the display control system 100C, which is compared to the display control system 100 of this embodiment, with reference to Figures 3 to 6.

[0068] Figure 3 is a system configuration diagram of the comparative example display control system 100C. The display control system 100C controls the display of the LCD 130 and comprises a main board 110C equipped with a PMIC 111 connected to a power switch PSW and a CPU 112C, and a panel board 120C equipped with an FET 121 and a CPU 122C.

[0069] The comparative example PMIC111 operates in the same manner as the PMIC111 of this embodiment. Similarly, the comparative example LCD130 operates in the same manner as the LCD130 of this embodiment.

[0070] CPU112C receives voltage (3.3V1_C) from PMIC111. CPU112C can communicate with PMIC111 and can communicate with CPU122C mounted on panel board 120C.

[0071] The CPU122C is supplied with voltage (3.3V1_C) from the PMIC111. The CPU122C can communicate with the CPU112C mounted on the main board 110C. The CPU122C switches the FET121, which is located in the wire between the PMIC111 and the LCD130, between a conductive state and a non-conductive state. The voltage supplied to the LCD130 (3.3V1_REC) becomes 3.3V when the FET121 is controlled to be conductive by the CPU122C, and becomes 0V when the FET121 is controlled to be non-conductive by the CPU122C.

[0072] The CPU112C outputs vertical synchronization signals and image data signals to the LCD130. When the power is on, the CPU112C outputs a vertical synchronization signal to the LCD130 that alternates between high and low levels as a signal level. In the case of a normal power off by pressing the power switch PSW for less than 5 seconds, the CPU112C receives an off-mode transition instruction signal from PSW111, lowers the vertical synchronization signal to a low level, and continues to output a low-level vertical synchronization signal to the LCD130. In the case of a forced power off by pressing and holding the power switch PSW for 5 seconds or more, the CPU112C stops operating because voltage is no longer supplied to it from PSW111. As a result, the vertical synchronization signal becomes low, and a low-level vertical synchronization signal is continuously input to the LCD130.

[0073] The CPU122C outputs a display control signal (DISP signal) to the LCD130. The CPU122C transitions the signal level of the DISP signal from low to high during startup, etc. In the case of a normal power off by pressing the power switch PSW for less than 5 seconds, the CPU122C receives an off-mode transition instruction signal from the CPU112C and transitions the DISP signal from high to low, continuously outputting a low-level DISP signal to the LCD130. In the case of a forced power off by pressing and holding the power switch PSW for 5 seconds or more, the operation of the CPU122C stops because voltage is no longer supplied to the CPU122C, causing the DISP signal to become low, and a low-level DISP signal is continuously input to the LCD130.

[0074] The comparative example display control system 100C differs from the display control system 100 of this embodiment in that it does not include a DISP signal control circuit 200.

[0075] Next, we will explain the sequence of screen blackout of the LCD 130 during normal power-off using the comparative example display control system 100C, whose system configuration is shown in Figure 3 (the sequence of switching the LCD 130 screen from the displayed state to the hidden state), with reference to Figure 4. Figure 4 is a diagram illustrating the sequence of screen blackout of the LCD 130 during normal power-off using the comparative example display control system shown in Figure 3.

[0076] In a normal power-off state, the PMIC111 detects when the power switch PSW is pressed for less than 5 seconds while the power is on and outputs an off-mode transition instruction signal to the CPU112C. When the CPU112C receives the off-mode transition instruction signal from the PMIC111, it outputs an off-mode transition instruction signal to the CPU122C.

[0077] The screen-off sequence for LCD130 at this time is as shown in Figure 4, and the processes are carried out in the following order: (1), (2), (3), (4).

[0078] (1) When the CPU112C receives an off-mode transition instruction signal from the PMIC111, it stops outputting image data signals to the LCD130. As a result, the signal level of the image data signal from the CPU112C to the LCD130 remains low, indicating no image data. (2) The CPU122C transitions the signal level of the DISP signal from a high level to a low level, and continues to output the DISP signal with a low signal level to the LCD130. (3) The CPU112C lowers the signal level of the vertical synchronization signal and continues to output the low-level vertical synchronization signal to the LCD130. (4) The CPU 122 controls the FET 121 to a non-conductive state. As a result, the voltage (3.3V1_REC) becomes 0 (V), and no voltage is supplied to the LCD 130.

[0079] In the normal power-off sequence for the LCD130 screen described above, the DISP signal is maintained at a low level before the vertical sync signal is maintained at a low level, so no white streaks appear on the LCD130 screen.

[0080] Next, we will explain the sequence of screen blackout for the LCD 130 when the display control system 100C of the comparative example, whose system configuration is shown in Figure 3, is forcibly powered off in the event of an abnormality such as the device freezing, with reference to Figure 5. Figure 5 is a diagram illustrating the sequence of screen blackout for the LCD 130 when the display control system of the comparative example in Figure 3 is forcibly powered off.

[0081] In the case of a forced power off, the PMIC 111 detects that the power switch PSW has been pressed for 5 seconds or more. However, unlike in the case of a normal power off, the PMIC 111 does not output the above-mentioned off-mode transition instruction signal to the CPU 112C, nor does the CPU 122C receive the off-mode transition instruction signal from the CPU 112C. Therefore, the screen off sequence of the LCD 130 in the case of a forced power off is different from the screen off sequence of the LCD 130 shown in Figure 4 in the case of a normal power off, and is the screen off sequence of the LCD 130 shown in Figure 5 below, in the order of (1) and (2) below. In addition, the display control system 100C in the comparative example differs from the display control system 100 in this embodiment in that it does not have a DISP signal control circuit 200. Therefore, the display control system 100C cannot perform the circuit operations of timing T11 and timing T12 in Figure 2.

[0082] (1) On the main board 110 side, such as the CPU112C, the output of image data signals from the CPU112C to the LCD130 stops, and the signal level of the vertical synchronization signal from the CPU112C to the LCD130 becomes low, and the low-level vertical synchronization signal continues.

[0083] (2) On the panel board 120 side, such as the CPU 122C, the signal level of the DISP signal from the CPU 122C to the LCD 130 transitions from a high level to a low level, and the low-level DISP signal continues while voltage is no longer supplied to the LCD 130.

[0084] In the LCD130 screen blackout sequence during the forced power-off described above, from the moment the image data signal output stops and the vertical synchronization signal goes low and the low-level vertical synchronization signal begins to continue, until the DISP signal level transitions from high to low and the low-level DISP signal begins to continue, and the voltage supply to the LCD130 stops (for example, 0.1 seconds), the DISP signal remains high and the image data signal output stops. As a result, during this period, white streaks appear on the LCD130 screen, as shown in Figure 6 as an example.

[0085] According to the above embodiment, a predetermined delay time T is set from the falling edge of the buffer output signal input to the D terminal of the D-FF240. D The CLK signal, which is input to the CLK terminal of the D flip-flop with a delay of a few minutes, rises in the air. If the signal level of the buffer output signal input to the D terminal of the D flip-flop is low at the time the CLK signal rises, the signal level of the / Q signal output from the / Q terminal of the D flip-flop 240 becomes high, the OUT1 signal input to the base of the bipolar transistor 260 also becomes high, the bipolar transistor 260 becomes conductive, and the signal level of the DISP signal input to the LCD 130 becomes low, turning off the LCD 130 screen. In this way, by using the vertical synchronization signal to control the signal level of the DISP signal in the DISP signal control circuit 200, it becomes possible to shorten the time from the falling edge of the vertical synchronization signal to the low level of the DISP signal when the vertical synchronization signal no longer rises to a high level due to a forced power off. This makes it possible to shorten the appearance time of the white streaks that appear on the LCD 130 screen when the power is forcibly turned off.

[0086] Also, a predetermined delay time T D to T Low By setting it to ×2 or higher, the signal level of the buffer output signal (which switches signal levels at the same timing as the vertical synchronization signal) input to the D terminal of the D-FF240 and held at timings T5 and T9 when the vertical synchronization signal is repeatedly switching between low and high levels will reliably become high even if there is a time lag in the transition timing of the vertical synchronization signal from low to high by the CPU112, thus preventing the DISP signal from being mistakenly changed from high to low.

[0087] Also, a predetermined delay time T D to T Low By multiplying by 2, the duration for which white lines appear on the LCD130 screen when the power is forcibly turned off can be significantly reduced.

[0088] Furthermore, since the DISP signal control circuit 200 is a hardware circuit, it can stabilize the transition of the DISP signal level from high to low when the power is forcibly turned off.

[0089] It should be noted that the present invention is not limited to the configurations of the embodiments described above, and various modifications are possible. Furthermore, the configurations and processes shown in the embodiments described above using Figures 1 and 2 are merely one embodiment of the present invention, and the present invention is not intended to be limited to these configurations and processes. [Explanation of Symbols]

[0090] 100 Display Control System 110 Mainboard 111 PMIC (power management IC) 112 CPU 120 Panel Board 121 FET 122 CPU 130 LCD 200 DISP signal control circuit 210 Buffer circuit section 220 Delay Circuit Section 221 Resistor element 222 Capacitor Risk 230 Inverter Circuit Section 240 D-FF (D flip-flop) 250 Resistor element 260 bipolar transistors

Claims

1. In a display control system that controls the display of a liquid crystal display unit, The aforementioned display control system is A power management unit to which a power switch is connected, and a first board equipped with a first control unit that receives voltage from the power management unit and is capable of communicating with the power management unit, The system includes a second board to which voltage is supplied from the power management unit and which is equipped with a second control unit that can communicate with the first control unit, The first control unit outputs a vertical synchronization signal to the liquid crystal display unit. The second control unit outputs a screen display control signal to the liquid crystal display unit such that when the signal level is high, the screen of the liquid crystal display unit is displayed, and when the signal level is low, the screen of the liquid crystal display unit is turned off. The second board is further equipped with a signal level control circuit that controls the signal level of the screen display control signal. The aforementioned signal level control circuit is The vertical synchronization signal, one low-level period T of the vertical synchronization signal. Ｌｏｗ A single low-level period T of the vertical synchronization signal that is longer than the above. Ｌｏｗ and one high-level period T Ｈｉｇｈ The combined period T Ｌｏｗ +T Ｈｉｇｈ A predetermined delay time T that is shorter than Ｄ The vertical synchronization signal is delayed by a predetermined delay time T. Ｄ A delay circuit section that outputs a first signal delayed by several minutes, An inverter circuit unit that inverts the signal level of the first signal output by the delay circuit unit and outputs a second signal obtained by inverting the signal level of the first signal, A D flip-flop takes the aforementioned vertical synchronization signal as the input to the D terminal, the second signal output by the inverter circuit as the input to the CLK terminal, holds the signal level of the vertical synchronization signal input to the D terminal at the rising edge timing of the second signal input to the CLK terminal, and outputs a third signal, which is the inverted signal level of the held vertical synchronization signal, to the Q terminal. A display control system comprising: a second control unit, a switching circuit section disposed between a signal line that outputs the screen display control signal to the liquid crystal display unit and ground, which is in a non-conductive state when the signal level of the third signal is low, and in a conductive state when the signal level of the third signal is high.

2. The high-level period T Ｈｉｇｈ is longer than the low-level period T Ｌｏｗ and The predetermined delay time T Ｄ This is the low-level period T. Ｌｏｗ The display control system according to claim 1, wherein the time is more than twice the time of the previous method.

3. The predetermined delay time T Ｄ This is the low-level period T. Ｌｏｗ The display control system according to claim 2, wherein the time is twice that of the previous method.

4. The display control system according to claim 1, wherein the signal level control circuit further comprises a buffer circuit disposed between a first signal line on which the first control unit outputs the vertical synchronization signal and the D terminal of the D flip-flop and the delay circuit.

5. In a signal level control circuit, The first control unit outputs a vertical synchronization signal to the liquid crystal display unit, and the low-level period T of the vertical synchronization signal Ｌｏｗ A single low-level period T of the vertical synchronization signal that is longer than the above. Ｌｏｗ and one high-level period T Ｈｉｇｈ The combined period T Ｌｏｗ +T Ｈｉｇｈ A predetermined delay time T that is shorter than Ｄ The vertical synchronization signal is delayed by a predetermined delay time T. Ｄ A delay circuit section that outputs a first signal delayed by several minutes, An inverter circuit unit that inverts the signal level of the first signal output by the delay circuit unit and outputs a second signal obtained by inverting the signal level of the first signal, A D flip-flop takes the aforementioned vertical synchronization signal as the input to the D terminal, the second signal output by the inverter circuit as the input to the CLK terminal, holds the signal level of the vertical synchronization signal input to the D terminal at the rising edge timing of the second signal input to the CLK terminal, and outputs a third signal, which is the inverted signal level of the held vertical synchronization signal, to the Q terminal. A signal level control circuit comprising: a second control unit which outputs a screen display control signal to the liquid crystal display unit, the screen of the liquid crystal display unit being displayed when the signal level is high, and the screen of the liquid crystal display unit being turned off when the signal level is low, is disposed between the signal line that outputs the screen display control signal to the liquid crystal display unit and ground; and a switching circuit section which is in a non-conductive state when the signal level of the third signal is low, and in a conductive state when the signal level of the third signal is high.

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