Substrate having a SiGe layer on a silicon substrate and method for manufacturing the same

Abstract

The objective is to provide a method for manufacturing a substrate having a SiGe layer on a silicon substrate that significantly improves substrate warping (BOW). [Solution] A method for manufacturing a substrate having a SiGe layer on a silicon substrate, comprising the steps of: vapor-depositing a SiGe layer on the main surface, on the edge portion, and on a region adjacent to the edge portion on the main back surface of a silicon substrate having a main surface, a main back surface, and an edge portion; and removing the SiGe layer vapor-deposited on the edge portion and on the region adjacent to the edge portion on the main back surface by polishing, leaving the SiGe layer vapor-deposited on the main surface.

Description

Technical Field

[0001] The present invention relates to a substrate having a SiGe layer on a silicon substrate and a method for manufacturing the same.

Background Art

[0002] SiGe and Ge are materials widely used in various devices such as electronics, optics, and RF. In particular, for SiGe, recently, instead of the Fin structure adopted in current logic ICs, in semiconductors after the next generation, GAA and CFETs that stack NMOS and CMOS have been proposed, and it is a material that plays an important role in these manufacturing processes (Non-Patent Document 1).

[0003] However, in the equilibrium phase diagram, SiGe is known to have a large separation between the liquidus line and the solidus line, and its distribution coefficient is as large as 2 to 5, making it prone to polycrystallization. Even if a single crystal can grow, it is known that the growth rate is slow and it is difficult to achieve constantly (Non-Patent Document 2).

[0004] Therefore, for semiconductor devices, SiGe is grown on a Si substrate, and such a substrate is sometimes called a virtual SiGe substrate. In this SiGe growth (heteroepitaxial growth), it is important how to relax the lattice constant difference between Si and Ge. The lattice constant of a Si crystal is 0.5431 nm, and the lattice constant of a Ge crystal is 0.56754 nm, with a difference of about 4.5% between the two. SiGe uses a SiGe mixed crystal to relax this lattice constant difference. When the composition ratio of Ge is x, the lattice constant of the SiGe mixed crystal is "0.5431 nm + x × 0.02 nm + x squared × 0.0027 nm". For example, assuming x is 0.3, the lattice constant becomes 0.5493 nm, and the lattice mismatch is only 0.14%. Due to this lattice mismatch, dislocations and defects grow in the subsequently grown epitaxial layer, leading to quality degradation. However, there is a critical film thickness, and it is said that even if there is a lattice mismatch, as long as the critical film thickness is not exceeded, no defects will occur (Non-Patent Document 3).

Prior Art Documents

[0005] [Patent Document 1] Japanese Patent Publication No. 2010-267969 [Patent Document 2] Japanese Patent Publication No. 2005-011848 [Non-patent literature]

[0006] [Non-Patent Document 1] Materials from the 1st Workshop Meeting of the Industry-Academia Collaboration Committee on Crystal Growth, Processing, and Evaluation of Semiconductors, Japan Society of Applied Physics, "Crystal Technology Supporting the Resurgence of Semiconductors," (June 21, 2023) [Non-Patent Document 2] Ichiro Yonenaga, "Growth of High-Quality SiGe Crystals and Elucidation of Basic Physical Properties," Materia, 47(1), 3 (2008). [Non-Patent Document 3] Katsuaki Sato, "Fundamentals and Challenges of Heteroepitaxy: 1st Workshop Meeting of the Research Group on 3C-SiC Technology for IoT in Harsh Environments" (2019) [Non-Patent Document 4] Wong, Lydia Helena, “Strain relaxation in SiGe / Si heteroepitaxy”, Nanyang Technological University, Singapore. [Non-Patent Document 5] D. Rouchon et.al., “Germanium content and strain in Si1-xGex alloys characterized by Raman spectroscopy”, J. Crystal Growth, 392, 66 (2014). [Overview of the project] [Problems that the invention aims to solve]

[0007] In reality, SiGe substrates with SiGe epitaxial films of 1 μm or even thicker are required, rather than the thin SiGe epitaxial films of the critical thickness mentioned above. Therefore, due to the difference in lattice constants, lattice-like irregularities occur on the surface, known as cross-hatching, and dislocations from the interface between the Si substrate and the SiGe epitaxial layer can reach the surface, generating defects. In addition to these, there is also the problem of wafer warping caused by this difference in lattice constants (this warping is not limited to SiGe substrates but is common to heteroepitaxial growth substrates).

[0008] As mentioned above, this warping problem is caused by lattice mismatch, and has traditionally been avoided by optimizing epitaxial growth conditions (e.g., buffer structure) along with defect reduction.

[0009] For example, Patent Document 2 discloses an improved method for manufacturing a semiconductor substrate, comprising: a first step of forming a SiGe concentration gradient layer on a Si single crystal substrate in which the Ge concentration increases with thickness; a second step of forming a SiGe concentration constant layer on the SiGe concentration gradient layer in which the Ge concentration is constant; and a third step of forming a strained Si layer on the SiGe concentration constant layer, wherein at least one of the layers in the first, second, and third steps is formed by epitaxial growth. The method further includes a step of removing the epitaxial layers formed on the back surface and chamfered surface of the substrate during epitaxial growth, following the third step. In this method, the so-called buffer layer is limited to the production of a forward-graded buffer layer (in which the Ge concentration increases as it gets thicker), but in reality, a reverse-graded buffer layer in which a layer with a high concentration is formed and then the concentration is temporarily reduced has also been proposed (for example, Non-Patent Document 4), so a good SiGe substrate is not necessarily provided. In other words, it is clear that the method is limited as described above because it cannot solve the problem of warping (BOW) in addition to defects.

[0010] The present invention was made to solve the above problems and aims to provide a method for manufacturing a substrate having a SiGe layer on a silicon substrate that significantly improves substrate warping, i.e., BOW. [Means for solving the problem]

[0011] The present invention has been made to achieve the above objective and provides a method for manufacturing a substrate having a SiGe layer on a silicon substrate, comprising the steps of vapor-depositing a SiGe layer on the main surface, on the edge portion, and on a region adjacent to the edge portion on the main back surface of a silicon substrate having a main surface, a main back surface, and an edge portion, and removing the SiGe layer vapor-deposited on the edge portion and on the region adjacent to the edge portion on the main back surface by polishing, leaving the SiGe layer vapor-deposited on the main surface.

[0012] According to this method for fabricating a substrate having a SiGe layer on a silicon substrate, even when forming a thick SiGe epitaxial layer, substrate warpage (BOW) is reduced, and a virtual SiGe substrate can be fabricated in which cross-hatching caused by lattice mismatch between silicon and SiGe on the surface is suppressed.

[0013] In this case, the area adjacent to the edge portion on the main back surface can be set to a range of 1 μm to 5 μm from the boundary between the main back surface and the edge portion toward the center of the silicon substrate.

[0014] This makes it possible to further reduce board warping (BOW).

[0015] In this case, the SiGe layer on the surface of the silicon substrate may be lattice-relaxed, and the SiGe layer on the surface side of the silicon substrate at the edge portion may contain SiGe having tensile stress.

[0016] This further reduces board warping (BOW).

[0017] At this time, the SiGe layer in the region adjacent to the edge portion on the back surface side and the main back surface of the silicon substrate of the edge portion is not lattice-relaxed, and the SiGe layer in the region adjacent to the edge portion on the back surface side and the main back surface of the silicon substrate of the edge portion can include SiGe having compressive stress.

[0018] Thereby, the warp (BOW) of the substrate can be further reduced.

[0019] At this time, the step of leaving the SiGe layer can include, in this order, the step of removing the SiGe layer in the edge portion, the step of removing the SiGe layer in the region adjacent to the edge portion on the main back surface, and the step of polishing the surface of the SiGe layer on the main surface.

[0020] Thereby, the warp (BOW) of the substrate can be further reduced, and the defects on the surface of the SiGe layer can be further reduced.

[0021] At this time, in the step of polishing the surface of the SiGe layer on the main surface, the surface of the SiGe layer on the main surface can be polished so that the surface roughness Sa when measured in a 30 μm square region by AFM is 0.2 nm or less.

[0022] By polishing so that the surface roughness Sa when measured in a 30 μm square region by AFM is 0.2 nm or less, the influence of crosshatch can be more effectively alleviated.

[0023] The present invention has also been made to achieve the above objective, and provides a substrate having a SiGe layer on a silicon substrate having a diameter of 300 mm having a main surface, a main back surface and an edge portion, wherein the main back surface and the edge portion are not provided with a SiGe layer, and the main surface is provided with a lattice-relaxed SiGe layer, the Bow of the substrate is 5 μm or less, and the surface roughness Sa of the SiGe layer, measured by AFM in a 30 μm square area, is 0.2 nm or less.

[0024] With a substrate having a SiGe layer on a silicon substrate, even with a thick SiGe epitaxial layer, the substrate warpage (BOW) is reduced, and the cross-hatching that occurs on the surface due to lattice mismatch between silicon and SiGe is suppressed, resulting in a virtual SiGe substrate. [Effects of the Invention]

[0025] As described above, according to the method for manufacturing a substrate having a SiGe layer on a silicon substrate of the present invention, even when forming a thick SiGe epitaxial layer, it is possible to manufacture a virtual SiGe substrate in which substrate warping (BOW) is reduced and cross-hatching occurring on the surface due to lattice mismatch between silicon and SiGe is suppressed. Furthermore, according to the present invention, a substrate having a SiGe layer on a silicon substrate reduces the warping (BOW) of the substrate even with a thick SiGe epitaxial layer, and suppresses cross-hatching on the surface caused by lattice mismatch between silicon and SiGe, resulting in a virtual SiGe substrate.

[0026] In particular, the small BOW (Block Edge) makes it less likely for defocusing to occur in processes such as photolithography, and also helps suppress transport errors caused by substrate warping in various device manufacturing processes. [Brief explanation of the drawing]

[0027] [Figure 1]This is a schematic cross-sectional view of a substrate having a SiGe layer on a silicon substrate according to an embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view of the edge portion of a silicon substrate in an embodiment of the present invention, specifically in which a SiGe epitaxial layer is provided on the silicon substrate, particularly on the edge portion. [Figure 3] The results of Raman spectroscopy measurements performed at various positions on the edge of the SiGe substrate of the present invention, on which the SiGe layer is formed, are shown (a) on the surface of the edge and (b) on the back of the edge. [Figure 4] The changes in BOW at each stage in the example are shown: silicon substrate, after epitaxial growth, after edge polishing, after backside polishing (removal of SiGe from the outer periphery of the backside), and after surface polishing. [Modes for carrying out the invention]

[0028] The present invention will be described in detail below with reference to the drawings, but the present invention is not limited to these descriptions.

[0029] As described above, there was a need for a method to fabricate a substrate having a SiGe layer on a silicon substrate (hereinafter also referred to as a "virtual SiGe substrate," "SiGe substrate," or "SiGe epitaxial substrate") that would significantly improve substrate warping (BOW).

[0030] The inventors of this invention have diligently studied the above-mentioned problems and, as a result, have focused not only on the growth conditions for SiGe epitaxial growth, but also on the stress applied to the entire substrate, and in particular on the stress of the SiGe film that wraps around the edges of the substrate and the back surface of the substrate during epitaxial growth. They have found that it is possible to control this stress, that is, to control the warp (BOW) of the substrate by focusing not only on the epitaxial growth conditions but also on the effects of processing. In other words, by combining the adjustment of processing conditions after epitaxial growth in addition to the epitaxial growth conditions, the warp (BOW) of the substrate can be significantly improved. Based on these findings, the inventors of this invention have completed the present invention.

[0031] In other words, as a result of diligent study on the above-mentioned problems, the present inventors have found that by a method for manufacturing a substrate having a SiGe layer on a silicon substrate, which includes the steps of vapor-depositing a SiGe layer on the main surface, on the edge portion, and on the region adjacent to the edge portion on the main back surface of a silicon substrate having a main surface, a main back surface, and an edge portion, and removing the SiGe layer vapor-deposited on the edge portion and the region adjacent to the edge portion on the main back surface by polishing, leaving the SiGe layer vapor-deposited on the main surface, it is possible to manufacture a virtual SiGe substrate in which the warping (BOW) of the substrate is reduced, even with a thick SiGe epitaxial layer, and cross-hatching that occurs on the surface due to lattice mismatch between silicon and SiGe is suppressed, even with a thick SiGe epitaxial layer, and thus the present invention has been completed.

[0032] The inventors have also conducted extensive research on the above-mentioned problems and have found that a silicon substrate with a diameter of 300 mm having a main surface, a main back surface, and an edge portion, and a SiGe layer formed on the silicon substrate, wherein the main back surface and the edge portion are not provided with a SiGe layer, and the main surface is provided with a lattice-relaxed SiGe layer, the Bow of the substrate is 5 μm or less, and the surface roughness Sa of the SiGe layer, measured by AFM in a 30 μm square area, is 0.2 nm or less, can reduce the warp (BOW) of the substrate even with a thick SiGe epitaxial layer, and can also suppress cross-hatching on the surface caused by lattice mismatch between silicon and SiGe, thus completing the present invention.

[0033] Furthermore, Patent Document 1 discloses a method for simultaneously polishing both sides of a silicon substrate in which SiGe is laminated on one side, and depositing a stress compensation layer on the side opposite to the side on which the SiGe is laminated. However, in this method, SiGe remains on at least the back surface, and there is no mention of SiGe at the edges. As a result, SiGe remains, and there are concerns about the use of this substrate, such as the possibility of contamination of process equipment by SiGe, diffusion of Ge due to heat treatment in the device process, and disruption of the stress balance between the front and back surfaces for stress compensation when the SiGe composition profile changes as the process progresses, such as etching.

[0034] [Substrate having a SiGe layer on a silicon substrate] Figure 1 shows a schematic cross-sectional view of a SiGe substrate in an embodiment of the present invention. As shown in Figure 1, the SiGe substrate in an embodiment of the present invention is a SiGe substrate (SiGe epitaxial substrate) 1 in which a SiGe layer 3 is grown on a silicon substrate (silicon single crystal substrate) 2.

[0035] The silicon substrate 2 is a silicon substrate with a diameter of 300 mm having a main surface, a main back surface, and an edge portion 4. Other conditions are not particularly limited; it may be doped, the conductivity type may be p-type or n-type, the resistivity may be low or high, and it can be a silicon single crystal substrate manufactured using the same single crystal manufacturing equipment and procedures as conventional methods.

[0036] The SiGe layer 3 is not present on the main back surface or edge portion 4 of the silicon substrate 2, but a lattice-relaxed SiGe layer 3 is present on the main surface. The Bow of the SiGe substrate 1 is 5 μm or less, and the surface roughness Sa of the SiGe layer 3, measured by AFM in a 30 μm square area, is 0.2 nm or less.

[0037] Although defects occur in the SiGe layer 3 grown on the silicon substrate 2 due to lattice constant differences, with the SiGe substrate according to the present invention as described above, even with a thick SiGe epitaxial layer, the warping (BOW) of the substrate is reduced, and the cross-hatching that occurs on the surface due to lattice mismatch between silicon and SiGe is suppressed, resulting in a virtual SiGe substrate.

[0038] In particular, the small BOW (Block of Warping) makes it less likely for defocusing to occur in processes such as photolithography, and it is possible to suppress the occurrence of transport errors caused by substrate warping in various device manufacturing processes.

[0039] [Method for fabricating a substrate having a SiGe layer on a silicon substrate] Next, we will describe a general method for manufacturing SiGe substrates. As shown in Figure 1, a SiGe layer 3 is grown on a silicon substrate 2. There are no particular restrictions on the SiGe growth conditions, but generally, it is grown under reduced pressure at a temperature of 600-800°C using monogermane (GeH4) and monosilane (SiH4) or dichlorosilane (H2SiCl2) gas as raw materials.

[0040] Furthermore, in order to mitigate the introduction of dislocations due to lattice constant differences in the SiGe layer 3 grown on the silicon substrate 2, methods such as a forward-graded buffer layer that gradually increases the Ge concentration in the SiGe, as disclosed in Patent Document 2, or a reverse-graded buffer layer that grows a SiGe layer with a high Ge concentration and then decreases the Ge concentration, as disclosed in Non-Patent Document 4, may be devised.

[0041] Next, the method for manufacturing a SiGe substrate according to the present invention will be described below, step by step. The present invention relates to a method for manufacturing a SiGe substrate, which includes the steps of vapor-depositing a SiGe layer 3 on the main surface, on the edge portion 4, and on a region adjacent to the edge portion (hereinafter also referred to as the "near edge portion") 7 on the main surface of a silicon substrate 2 having a main surface, a main back surface, and an edge portion 4, and removing the vapor-deposited SiGe layer 3 on the edge portion 4 and the region adjacent to the edge portion 7 on the main back surface by polishing, leaving the vapor-deposited SiGe layer 3 on the main surface.

[0042] (Process of growing a SiGe layer in the vapor phase) First, the epitaxial growth of the SiGe layer 3 on the silicon substrate 2 will be explained, focusing on the edge portion 4 of the silicon substrate 2 shown in Figure 2. In the SiGe substrate manufacturing method of the present invention, when the SiGe layer 3 is grown in the vapor phase on the silicon substrate 2, the SiGe layer 3 is intentionally grown in the vapor phase on the edge portion 4 and the area near the edge portion 7. At the edge portion 4, there are R-shaped areas in the X1 portion 5 on the surface side and the X2 portion 6 on the back side.

[0043] The area of ​​the edge vicinity 7 can be defined as 1 μm to 5 μm from the boundary between the main back surface and the edge portion 4 toward the center of the silicon substrate 2. This makes it possible to further reduce board warping (BOW).

[0044] Figure 3 shows the results of Raman spectroscopy measurements performed at various positions on the edge of the SiGe substrate 1 on which the SiGe layer 3 is formed ((a) surface of the edge, (b) back surface of the edge). The SiGe layer 3 on the surface of the silicon substrate 2 can be lattice-relaxed. That is, the SiGe grown on the R-shaped portion of the edge 4 can be lattice-relaxed on the surface of the X1 portion 5 on the surface side, and the film can be formed so that the layer contains SiGe with tensile stress on the X1 portion 5. In this case, as disclosed in Non-Patent Literature 5, the Si-Si Raman shift in the relaxed SiGe is 500-502 cm⁻¹. -1 As shown in Figure 3(a), the surface of the silicon substrate 2 is relaxed SiGe, and part X1 5 is 500 cm². -1While some areas are below this range, the average is generally between 500 and 502 cm. -1 This indicates that it is under tensile stress. This further reduces board warping (BOW).

[0045] On the other hand, the SiGe layer 3 on the back side (X2 portion 6) and near the edge 7 of the silicon substrate 2 at the edge portion 4 may not be lattice relaxed, and the SiGe layer 3 in the X2 portion 6 and near the edge 7 may contain SiGe with compressive stress. In fact, as shown in Figure 3(b), the Raman shift on the back side is 504 to 504.5 cm near the edge on the back side. -1 And X2 part 6 is 502cm -1 It is larger than that. The Raman coefficient of Si-Si in relaxed SiGe, as described in Non-Patent Document 5, is (500-502 cm²). -1 From this perspective, it can be seen that there is a large compressive stress. This further reduces board warping (BOW).

[0046] There are several methods for adjusting the way stress is applied, and they are not particularly limited, but this can be done using the substrate and the susceptor that supports the substrate during epitaxial growth. For example, a susceptor with holes around its periphery can be used, and growth can be carried out by allowing gas to flow around the periphery of the back surface. In this way, the edges on the surface side become relaxed SiGe except for the outermost periphery, and the back surface becomes SiGe with the compressive stress described above due to the conditions optimized for the surface side and partial growth.

[0047] (Process of leaving the SiGe layer intact) Next, the SiGe layer 3 on the edge portion 4 and the back surface is removed by polishing, leaving the SiGe layer 3 on the main surface. The process of leaving the SiGe layer intact may include, in this order, the steps of removing the SiGe layer 3 at the edge portion 4, removing the SiGe layer 3 in the vicinity of the edge portion 7, and polishing the surface of the SiGe layer 3 on the main surface.

[0048] This allows for a further reduction in substrate warpage (BOW) and a reduction in defects on the surface of the SiGe layer 3.

[0049] Patent Document 2 states that the SiGe epitaxial layer can be removed by wet etching, but due to its composition, SiGe is easily etched unevenly and difficult to remove uniformly. For this reason, polishing such as CMP is preferable. The amount of polishing of the SiGe on the edge portion 4 and the back surface should be set so that each SiGe is completely removed.

[0050] By performing CMP (Chemical Polishing) on ​​the outermost surface, surface cross-hatching can be further reduced, and by removing the stress remaining in the outermost layer, BOW (Block-on Welding) can be further mitigated. The amount of CMP used in this process should be such that the surface roughness Sa measured by AFM in a 30 μm square area is 0.2 nm or less, thereby more effectively mitigating the effects of cross-hatching. [Examples]

[0051] The present invention will be described in detail below with reference to examples, but this is not intended to limit the present invention.

[0052] SiGe epitaxial substrates were fabricated as follows. A single-crystal silicon substrate with a diameter of 300 mm, a crystal orientation of (100), boron doping, and a resistivity of 10 Ω·cm was prepared, and its BOW (Body-on-Wave) was first measured using an LNSW (Laser-Sweeping Scale) device manufactured by Kobelco Research Institute.

[0053] Next, using a reduced-pressure CVD apparatus, a 5 μm thick SiGe (Ge composition ratio = 30%) layer was grown on a single-crystal silicon substrate using SiH2Cl2 gas and GeH4 gas as raw materials, with a gas flow rate of 1000 sccm, a chamber pressure of 10 Torr (1333 Pa), a growth temperature of 610°C, and a growth time of 60 min.

[0054] For this process, a perforated susceptor was used to support the substrate, allowing SiGe to grow on the back surface as well. The BOW of the substrate after epitaxial growth was measured in the same way as the substrate before epitaxial growth.

[0055] Next, the edges were polished using a polishing method similar to that used for general silicon wafer edge polishing. However, it was found that the polishing speed of SiGe was about 1 / 5 that of Si, and polishing took five times longer than the polishing time required for a 5 μm removal area of ​​silicon. In this state, the BOW of the substrate was measured in the same way as the substrate before epitaxial growth.

[0056] Next, the SiGe on the back surface was polished using the same polishing method as for general silicon wafer back surface polishing. However, since the polishing speed of SiGe is about 1 / 5 that of Si, the polishing time was five times longer than the time required to remove 5 μm of silicon. In this state, the BOW of the substrate was measured in the same way as the substrate before epitaxial growth.

[0057] Finally, the surface of the SiGe layer remaining on the main surface of the silicon single crystal substrate was polished, taking into account that the polishing speed of SiGe is about 1 / 5 that of silicon. In order to reduce the Sa to 0.2 nm or less using a 30 μm square AFM, it was necessary to polish the SiGe surface to 90 nm. In this state, the BOW of the substrate was measured in the same way as the substrate before epitaxial growth.

[0058] Figure 4 summarizes the changes in BOW at each stage. The BOW on the initial substrate is very small, but after SiGe epitaxial growth, the BOW becomes larger on the negative side (concave shape). After this, polishing the edges and removing the SiGe alleviates the concave shape, and removing the SiGe from the back surface significantly improves the BOW, and the shape becomes convex. The BOW was further improved after surface CMP.

[0059] As described above, according to the embodiments of the present invention, a good virtual (relaxed) SiGe substrate with low BOW and suppressed surface roughness Sa was obtained.

[0060] This specification includes the following embodiments: [1] A method for manufacturing a substrate having a SiGe layer on a silicon substrate, comprising the steps of vapor-depositing a SiGe layer on the main surface, on the edge portion, and on a region adjacent to the edge portion on the main back surface of a silicon substrate having a main surface, a main back surface, and an edge portion, and removing the SiGe layer vapor-deposited on the edge portion and on a region adjacent to the edge portion on the main back surface by polishing, leaving the SiGe layer vapor-deposited on the main surface. [2] A method for manufacturing a substrate having a SiGe layer on the silicon substrate according to [1], comprising making the range of the region adjacent to the edge portion on the main back surface 1 μm to 5 μm from the boundary between the main back surface and the edge portion toward the center of the silicon substrate. [3]: A method for manufacturing a substrate having a SiGe layer on a silicon substrate according to [1] or [2] above, comprising: making the SiGe layer on the surface of the silicon substrate lattice-relaxed, and making the SiGe layer on the surface side of the silicon substrate at the edge portion contain SiGe having tensile stress. [4]: A method for manufacturing a substrate having a SiGe layer on a silicon substrate according to [1], [2], or [3], comprising: not lattice relaxing the SiGe layer on the back side of the silicon substrate at the edge portion and in the region adjacent to the edge portion on the main back surface, and comprising including SiGe having compressive stress in the SiGe layer on the back side of the silicon substrate at the edge portion and in the region adjacent to the edge portion on the main back surface. [5]: A method for manufacturing a substrate having a SiGe layer on a silicon substrate according to [1], [2], [3], or [4], comprising the steps of leaving the SiGe layer in place of: removing the SiGe layer at the edge; removing the SiGe layer in a region adjacent to the edge on the main back surface; and polishing the surface of the SiGe layer on the main surface. [6]: A method for producing a substrate having a SiGe layer on a silicon substrate as described in [5], comprising the step of polishing the surface of the SiGe layer on the main surface, wherein the surface of the SiGe layer on the main surface is polished so that the surface roughness Sa measured by AFM in a 30 μm square area is 0.2 nm or less. [7] A substrate having a SiGe layer on a silicon substrate, comprising a silicon substrate with a diameter of 300 mm having a main surface, a main back surface and an edge portion, and a SiGe layer formed on the silicon substrate, wherein the main back surface and the edge portion are not provided with a SiGe layer, and the main surface is provided with a lattice-relaxed SiGe layer, the Bow of the substrate is 5 μm or less, and the surface roughness Sa of the SiGe layer, measured by AFM in a 30 μm square area, is 0.2 nm or less.

[0061] It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention. [Explanation of Symbols]

[0062] 1…SiGe substrate (SiGe epitaxial substrate), 2...Silicon substrate (silicon single crystal substrate), 3...SiGe layer, 4...Edge portion, 5...X1 part, 6...X2 part, 7…The area adjacent to the edge on the main back surface (near-edge area).

Claims

1. A step of vapor-depositing a SiGe layer on the main surface, on the edge portion, and on the region adjacent to the edge portion on the main back surface of a silicon substrate having a main surface, a main back surface, and an edge portion, A method for manufacturing a substrate having a SiGe layer on a silicon substrate, characterized by including the step of removing the SiGe layer grown in vapor phase on the edge portion and on the region adjacent to the edge portion on the main back surface by polishing, and leaving the SiGe layer grown in vapor phase on the main surface.

2. A method for manufacturing a substrate having a SiGe layer on a silicon substrate according to claim 1, characterized in that the range of the region adjacent to the edge portion on the main back surface is 1 μm or more and 5 μm or less from the boundary between the main back surface and the edge portion toward the center of the silicon substrate.

3. The SiGe layer on the surface of the silicon substrate is lattice-relaxed. The method for manufacturing a substrate having a SiGe layer on a silicon substrate according to claim 1, characterized in that the SiGe layer on the surface side of the silicon substrate at the edge portion contains SiGe having tensile stress.

4. The SiGe layer in the region adjacent to the edge portion on the back side of the silicon substrate and on the main back side of the edge portion is not lattice relaxed. A method for manufacturing a substrate having a SiGe layer on a silicon substrate according to claim 1, characterized in that the SiGe layer on the back side of the silicon substrate at the edge portion and in the region adjacent to the edge portion on the main back surface contains SiGe having compressive stress.

5. The step of leaving the SiGe layer intact is: The steps include removing the SiGe layer at the edge portion, The steps include removing the SiGe layer in the region adjacent to the edge portion on the main back surface, A method for producing a substrate having a SiGe layer on a silicon substrate according to any one of claims 1 to 4, characterized in that it includes, in this order, the step of polishing the surface of the SiGe layer on the main surface.

6. The method for producing a substrate having a SiGe layer on a silicon substrate according to claim 5, characterized in that, in the step of polishing the surface of the SiGe layer on the main surface, the surface of the SiGe layer on the main surface is polished so that the surface roughness Sa measured by AFM in a 30 μm square area is 0.2 nm or less.

7. A silicon substrate with a diameter of 300 mm having a main surface, a main back surface and an edge portion, and a substrate having a SiGe layer formed on the silicon substrate, The main back surface and the edge portion are not provided with a SiGe layer, but the main surface is provided with a lattice-relaxed SiGe layer. The Bow of the aforementioned substrate is 5 μm or less. A substrate having a SiGe layer on a silicon substrate, characterized in that the surface of the SiGe layer has a surface roughness Sa of 0.2 nm or less when measured in a 30 μm square region by AFM.

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