Insulated switch

Abstract

It increases the high level of the switch drive signal. [Solution] The isolation switch 400 includes a switch circuit 422 connected between a first node T4 and a second node T5 and switched on / off by a switch drive signal Vg; a first transformer 431 and a second transformer 432 in which a first primary coil 431p and a second primary coil 432p are connected in parallel between a power terminal VCC and a ground terminal GND, and a first secondary coil 431s and a second secondary coil 432s are connected in series with each other; a first pulse generation circuit 411 and a second pulse generation circuit 412 that pulse-drive the first primary coil 431p and the second primary coil 432p respectively in response to an input pulse DIN; and a switch drive circuit 421 that receives induced voltages Vs1 and Vs2 generated in the first secondary coil 431s and the second secondary coil 432s respectively and generates a switch drive signal Vg.

Description

Technical Field

[0001] The present disclosure relates to an isolation switch.

Background Art

[0002] Conventionally, an isolation switch configured to drive a switch element of a secondary circuit system in response to a control signal of a primary circuit system while electrically insulating between the primary circuit system and the secondary circuit system has been used in various applications (such as a power supply device or a motor drive device).

[0003] As an example of the related prior art, Patent Document ① by the applicant of the present application can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document ①

[0005] [Summary] In the conventional isolation switch, there is room for consideration regarding the signal transmission method.

[0006] The isolation switch according to the present disclosure includes a switch circuit connected between a first node and a second node and configured to be turned on / off by a switch drive signal, a first transformer and a second transformer in which a first primary coil and a second primary coil are connected in parallel between a power supply terminal and a ground terminal and a first secondary coil and a second secondary coil are connected in series with each other, a first pulse generation circuit and a second pulse generation circuit configured to pulse-drive the first primary coil and the second primary coil respectively in response to an input pulse, and a switch drive circuit configured to generate the switch drive signal by receiving induced voltages generated in the first secondary coil and the second secondary coil respectively.

Brief Description of the Drawings

[0007] [Figure 1] Figure 1 shows the basic configuration of a signal transmission device. [Figure 2] Figure 2 shows the basic structure of a transformer chip. [Figure 3] Figure 3 is a perspective view of a semiconductor device used as a 2-channel transformer chip. [Figure 4] Figure 4 is a plan view of the semiconductor device shown in Figure 3. [Figure 5] Figure 5 is a plan view showing the layer in the semiconductor device of Figure 3 where the low-potential coil is formed. [Figure 6] Figure 6 is a plan view showing the layer in the semiconductor device of Figure 3 where the high-potential coil is formed. [Figure 7] Figure 7 is a cross-sectional view along the line VIII-VIII shown in Figure 6. [Figure 8] Figure 8 shows an enlarged view (separated structure) of region XIII shown in Figure 7. [Figure 9] Figure 9 is a schematic diagram showing an example of a transformer chip layout. [Figure 10] Figure 10 shows a comparative example of an insulated switch. [Figure 11] Figure 11 shows a first embodiment of an insulated switch. [Figure 12] Figure 12 shows a second embodiment of the insulated switch. [Figure 13] Figure 13 shows a third embodiment of the insulated switch. [Figure 14] Figure 14 shows a fourth embodiment of the insulated switch. [Figure 15] Figure 15 shows an example of a controller configuration. [Figure 16] Figure 16 shows a modified example of the controller. [Figure 17] Figure 17 shows a fifth embodiment of the insulated switch. [Figure 18] Figure 18 shows a sixth embodiment of the insulated switch. [Figure 19] FIG. 19 is a diagram showing a seventh embodiment of the insulation switch. [Figure 20] FIG. 20 is a diagram showing an eighth embodiment of the insulation switch. [Figure 21] FIG. 21 is a diagram showing a ninth embodiment of the insulation switch. [Figure 22] FIG. 22 is a diagram showing a tenth embodiment of the insulation switch. [Figure 23] FIG. 23 is a diagram showing a configuration example of the voltage control circuit.

[0008] [Detailed Description] <Signal Transmission Device (Basic Configuration)> FIG. 1 is a diagram showing the basic configuration of the signal transmission device. The signal transmission device 200 in this configuration example is a semiconductor integrated circuit device (so-called insulation gate driver IC) that transmits a pulse signal from the primary circuit system 200p (VCC1 - GND1 system) to the secondary circuit system 200s (VCC2 - GND2 system) while insulating between the primary circuit system 200p and the secondary circuit system 200s, and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by encapsulating a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving the supply of a power supply voltage VCC1 (for example, up to 7V with respect to GND1). For example, a pulse transmission circuit 211, buffers 212 and 213 are integrated in the controller chip 210.

[0010] The pulse transmission circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to an input pulse signal IN. More specifically, when notifying that the input pulse signal IN is at a high level, the pulse transmission circuit 211 performs pulse driving (single-shot or multiple-shot transmission pulse output) of the transmission pulse signal S11, and when notifying that the input pulse signal IN is at a low level, it performs pulse driving of the transmission pulse signal S21. That is, the pulse transmission circuit 211 pulse-drives either one of the transmission pulse signals S11 and S21 according to the logic level of the input pulse signal IN.

[0011] The buffer 212 receives the input of the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transchip 230 (specifically, the transformer 231).

[0012] [[ID=,8]]The buffer 213 receives the input of the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transchip 230 (specifically, the transformer 232). "

[0013] The driver chip 220 is a semiconductor chip that operates by receiving the supply of a power supply voltage VCC2 (for example, up to 30V with respect to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse reception circuit 223, and a driver 224.

[0014] The buffer 221 waveform-shapes the received pulse signal S12 induced in the transchip 230 (specifically, the transformer 231) and outputs it to the pulse reception circuit 223.

[0015] The buffer 222 waveform-shapes the received pulse signal S22 induced in the transchip 230 (specifically, the transformer 232) and outputs it to the pulse reception circuit 223.

[0016] The pulse receiving circuit 223 generates an output pulse signal OUT by driving a driver 224 in response to received pulse signals S12 and S22 input via buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 to raise the output pulse signal OUT to a high level in response to the pulse drive of the received pulse signal S12, and to lower the output pulse signal OUT to a low level in response to the pulse drive of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. For example, an RS flip-flop can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223.

[0018] The transformer chip 230 uses transformers 231 and 232 to DC-isolate the controller chip 210 and the driver chip 220, and outputs the transmitted pulse signals S11 and S21 input from the pulse transmitting circuit 211 as received pulse signals S12 and S22, respectively, to the pulse receiving circuit 223. In this specification, "DC-isolated" means that the objects to be isolated are not connected by a conductor.

[0019] More specifically, transformer 231 outputs a received pulse signal S12 from its secondary coil 231s in response to a transmitted pulse signal S11 input to its primary coil 231p. On the other hand, transformer 232 outputs a received pulse signal S22 from its secondary coil 232s in response to a transmitted pulse signal S21 input to its primary coil 232p.

[0020] Thus, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] In this example, the signal transmission device 200 has a separate transformer chip 230 containing only transformers 231 and 232, in addition to the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, both the controller chip 210 and the driver chip 220 can be formed using a general low-to-medium voltage process (several volts to tens of volts), eliminating the need to use a dedicated high-voltage process (several kV voltage), and thus reducing manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply unit or motor drive unit for in-vehicle equipment mounted on a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (xEVs such as BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV (plug-in hybrid electric vehicle / plug-in hybrid vehicle], or FCEV / FCV (fuel cell electric vehicle / fuel cell vehicle)).

[0024] <Trans-chip (basic structure)> Next, the basic structure of the transformer chip 230 will be described. Figure 2 shows the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that are opposed to each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that are opposed to each other in the vertical direction.

[0025] The primary coils 231p and 232p are both formed in the first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed in the second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is positioned directly above the primary coil 231p and faces it. Similarly, the secondary coil 232s is positioned directly above the primary coil 232p and faces it.

[0026] The primary coil 231p is laid in a spiral pattern, starting from its first end connected to internal terminal X21 and surrounding internal terminal X21 in a clockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral pattern, starting from its first end connected to internal terminal X23 and surrounding internal terminal X23 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. Internal terminals X21, X22, and X23 are arranged linearly in the order shown in the figure.

[0027] Internal terminal X21 is connected to external terminal T21 of the second layer 230b via conductive wiring Y21 and via Z21. Internal terminal X22 is connected to external terminal T22 of the second layer 230b via conductive wiring Y22 and via Z22. Internal terminal X23 is connected to external terminal T23 of the second layer 230b via conductive wiring Y23 and via Z23. External terminals T21 to T23 are arranged in a straight line and are used for wire bonding to the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral pattern, starting from its first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. On the other hand, the secondary coil 232s is laid in a spiral pattern, starting from its first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure and are used for wire bonding with the driver tip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, respectively, and are DC-isolated from the primary coils 231p and 232p. In other words, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-isolated from the controller chip 210 by the transformer chip 230.

[0030] <Trans-chip (2-channel type)> Figure 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. Figure 4 is a plan view of the semiconductor device 5 shown in Figure 3. Figure 5 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed. Figure 6 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed. Figure 7 is a cross-sectional view along the line VIII-VIII shown in Figure 6. Figure 8 is an enlarged view of region XIII shown in Figure 7, showing the separation structure 130.

[0031] Referring to Figures 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0032] Wide-bandgap semiconductors consist of semiconductors with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of a wide-bandgap semiconductor is preferably 2.0 eV or greater. The wide-bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a laminated structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a rectangular shape (in this form, a rectangular shape) when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long side of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along a first direction X and face a second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short side of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in a second direction Y and face a first direction X. The chip sidewalls 44A to 44D consist of a ground surface.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that aligns with the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0037] The insulating sidewalls 53A to 53D include the first insulating sidewall 53A, the second insulating sidewall 53B, the third insulating sidewall 53C, and the fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are connected to the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form a ground surface that is flush with the chip sidewalls 44A to 44D.

[0038] The insulating layer 51 consists of a multilayer insulating laminate structure including a bottom insulating layer 55, an upper insulating layer 56, and a plurality (11 layers in this embodiment) of interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The upper insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the upper insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the upper insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the upper insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0039] Each of the multiple interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the bottom insulating layer 55 side and a second insulating layer 59 on the top insulating layer 56 side. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). Preferably, the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layer 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the dielectric strength (dielectric breakdown voltage) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layer 57 are arbitrary and are not limited to any specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed on the insulating layer 51. The first functional device 45 includes one or more (in this embodiment, more) transformers 21 (corresponding to the transformers mentioned earlier). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51, spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed spaced apart in the first direction X.

[0043] The multiple transformers 21 specifically include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating sidewall 53C to the insulating sidewall 53D in a plan view. The multiple transformers 21A to 21D each have a similar structure. The structure of the first transformer 21A will be used as an example below. The explanation of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D will be omitted, as the explanation of the structure of the first transformer 21A will be applied mutatis mutandis.

[0044] Referring to Figures 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within the insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in the region sandwiched between the bottom insulating layer 55 and the top insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0045] The low-potential coil 22 is formed within the insulating layer 51 on the side of the bottom insulating layer 55 (semiconductor chip 41), and the high-potential coil 23 is formed within the insulating layer 51 on the side of the top insulating layer 56 (main insulating surface 52) relative to the low-potential coil 22. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 in between. The placement of the low-potential coil 22 and the high-potential coil 23 is arbitrary. Furthermore, the high-potential coil 23 only needs to face the low-potential coil 22 with one or more interlayer insulating layers 57 in between.

[0046] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of interlayer insulating layer 57) is appropriately adjusted according to the dielectric breakdown voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this configuration, the low-potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55. In this configuration, the high-potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56.

[0047] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 that is spirally routed between the first inner end 24 and the first outer end 25. The first helical portion 26 is spirally routed in an elliptical (long oval) shape in plan view. The portion forming the innermost periphery of the first helical portion 26 defines an elliptical first inner region 66 in plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first helical portion 26 is 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in the direction perpendicular to the helical direction. The first turn pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the first turn pitch is 1 μm or more and 3 μm or less. The first turn pitch is defined by the distance between two adjacent portions in the first helical portion 26 in the direction perpendicular to the helical direction.

[0049] The winding shape of the first helical portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the forms shown in Figure 5, etc. The first helical portion 26 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The first inner region 66 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the first helical portion 26.

[0050] The low-potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a laminated structure including a barrier layer and a main body layer. The barrier layer partitions a recess space within the interlayer insulating layer 57. The barrier layer may contain at least one of titanium and titanium nitride. The main body layer may contain at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second helical portion 29 that is spirally routed between the second inner end 27 and the second outer end 28. The second helical portion 29 is spirally routed in an elliptical (oval) shape in plan view. In this embodiment, the portion forming the innermost periphery of the second helical portion 29 defines an elliptical second inner region 67 in plan view. The second inner region 67 of the second helical portion 29 faces the first inner region 66 of the first helical portion 26 in the normal direction Z.

[0052] The number of turns of the second helical section 29 may be between 5 and 30. The number of turns of the second helical section 29 relative to the number of turns of the first helical section 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical section 29 exceeds the number of turns of the first helical section 26. Of course, the number of turns of the second helical section 29 may be less than the number of turns of the first helical section 26, or it may be equal to the number of turns of the first helical section 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second helical portion 29 is 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in the direction perpendicular to the helical direction. Preferably, the width of the second helical portion 29 is equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions in the second helical portion 29 in a direction perpendicular to the helical direction. Preferably, the second winding pitch is equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second helical portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the forms shown in Figure 6, etc. The second helical portion 29 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The second inner region 67 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the second helical portion 29.

[0056] It is preferable that the high-potential coil 23 is formed from the same conductive material as the low-potential coil 22. In other words, it is preferable that the high-potential coil 23 includes a barrier layer and a main body layer, similar to the low-potential coil 22.

[0057] Referring to Figure 4, the semiconductor device 5 includes a plurality (12 in this figure) of low-potential terminals 11 and a plurality (12 in this figure) of high-potential terminals 12. The plurality of low-potential terminals 11 are electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high-potential terminals 12 are electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] Multiple low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple low-potential terminals 11 are formed in the region on the insulating side wall 53B side, spaced apart in the second direction Y from the multiple transformers 21A to 21D, and are arranged with spacing in the first direction X.

[0059] The multiple low-potential terminals 11 include a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this configuration, two of each of the multiple low-potential terminals 11A to 11F are formed. The number of multiple low-potential terminals 11A to 11F is arbitrary.

[0060] The first low-potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low-potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low-potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low-potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low-potential terminal 11E is formed in the region between the first low-potential terminal 11A and the second low-potential terminal 11B in a plan view. The sixth low-potential terminal 11F is formed in the region between the third low-potential terminal 11C and the fourth low-potential terminal 11D in a plan view.

[0061] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0062] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0063] Multiple high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51, spaced apart from multiple low-potential terminals 11. Specifically, the multiple high-potential terminals 12 are formed in the region on the insulating side wall 53A side, spaced apart in the second direction Y from the multiple low-potential terminals 11, and are arranged with spacing in the first direction X.

[0064] Multiple high-potential terminals 12 are each formed in a region adjacent to the corresponding transformers 21A to 21D in a plan view. The proximity of the high-potential terminals 12 to the transformers 21A to 21D means that, in a plan view, the distance between the high-potential terminals 12 and the transformer 21 is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0065] Specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D in a plan view. More specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high-potential coil 23 and in the region between adjacent high-potential coils 23 in a plan view. As a result, the multiple high-potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0066] The multiple high-potential terminals 12 include a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this configuration, two of each of the multiple high-potential terminals 12A to 12F are formed. The number of multiple high-potential terminals 12A to 12F is arbitrary.

[0067] The first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23) in a plan view. The second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23) in a plan view. The third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23) in a plan view. The fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23) in a plan view. The fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0069] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0070] Referring to Figures 5 to 7, the semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, each formed within the insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0071] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. Furthermore, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this configuration, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of transformers 21A to 21D to the same potential.

[0072] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Furthermore, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this configuration, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of transformers 21A to 21D to the same potential.

[0073] Multiple first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. Multiple first low-potential wirings 31 have similar structures. Below, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. For descriptions of the structures of other first low-potential wirings 31, the description of the structure of the first low-potential wiring 31 connected to the first transformer 21A will be applied mutatis mutandis, and the description will be omitted.

[0074] The first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (in this embodiment, multiple) pad plug electrodes 76, and one or more (in this embodiment, multiple) substrate plug electrodes 77.

[0075] It is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, it is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0076] The through-wiring 71 penetrates multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this configuration, the through-wiring 71 is formed in the region between the lowest insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through-wiring 71 has an upper end on the side of the uppermost insulating layer 56 and a lower end on the side of the lowest insulating layer 55. The upper end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0077] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The first electrode layer 78 forms the upper end of the through-wiring 71. The second electrode layer 79 forms the lower end of the through-wiring 71. The first electrode layer 78 is formed in an island shape and faces the low-potential terminal 11 (first low-potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] Multiple wiring plug electrodes 80 are embedded in multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the bottom insulating layer 55 to the top insulating layer 56 so as to be electrically connected to each other, and also electrically connect the first electrode layer 78 and the second electrode layer 79. Each of the multiple wiring plug electrodes 80 has a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this configuration, six wiring plug electrodes 80 are embedded within each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded within each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating multiple interlayer insulating layers 57.

[0081] The low-potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) within the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connection wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. It is preferable that the low-potential connection wiring 72 has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0082] The lead wire 73 is formed in the region between the semiconductor chip 41 and the through-wiring 71 within the interlayer insulating layer 57. In this embodiment, the lead wire 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead wire 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first and second ends. The first end of the lead wire 73 is located in the region between the semiconductor chip 41 and the lower end of the through-wiring 71. The second end of the lead wire 73 is located in the region between the semiconductor chip 41 and the low-potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip-like manner in the region between the first and second ends.

[0083] The first connecting plug electrode 74 is formed in the region between the through-wiring 71 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the first ends of the through-wiring 71 and the lead-out wiring 73. The second connecting plug electrode 75 is formed in the region between the low-potential connecting wiring 72 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the second ends of the low-potential connecting wiring 72 and the lead-out wiring 73.

[0084] Multiple pad plug electrodes 76 are formed in the region between the low-potential terminal 11 (first low-potential terminal 11A) and the through-wiring 71 within the uppermost insulating layer 56, and are electrically connected to the upper ends of the low-potential terminal 11 and the through-wiring 71, respectively. Multiple substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the lead-out wiring 73 within the lowermost insulating layer 55. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first end of the lead-out wiring 73, and are electrically connected to the first end of the semiconductor chip 41 and the lead-out wiring 73, respectively.

[0085] Referring to Figures 6 and 7, the multiple first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23), respectively. The multiple first high-potential wirings 33 each have a similar structure. Below, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. For descriptions of the structures of the other first high-potential wirings 33, the description of the structure of the first high-potential wiring 33 connected to the first transformer 21A will be applied mutatis mutandis, and the descriptions will be omitted.

[0086] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, more) pad plug electrodes 82. Preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 are formed of the same conductive material as the low-potential coil 22, etc. That is, preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0087] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulation layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (the first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is formed at an interval from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. Thereby, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the withstand voltage of the insulation layer 51 is enhanced.

[0088] The plurality of pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (the first high-potential terminal 12A) and the high-potential connection wiring 81 within the uppermost insulation layer 56 and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. The plurality of pad plug electrodes 82 each have a planar area less than the planar area of the high-potential connection wiring 81 in a plan view.

[0089] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulation layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. It is preferable that the distance D1 is 100 μm or more and 500 μm or less. The distance D2 may be from 1 μm to 50 μm. It is preferable that the distance D2 is from 5 μm to 25 μm. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the withstand voltage to be achieved.

[0090] Referring to FIGS. 6 and 7, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulation layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed with a different pattern (discontinuous pattern) from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A-21D. In other words, the dummy pattern 85 does not function as a transformer 21A-21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A-21D and suppresses electric field concentration on the high-potential coil 23. In this configuration, the dummy pattern 85 is routed with a line density equal to that of the high-potential coil 23 per unit area. The line density of the dummy pattern 85 being equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 is within ±20% of the line density of the high-potential coil 23.

[0092] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the dummy pattern 85 is formed in a region adjacent to the high-potential coil 23 with respect to the low-potential coil 22 with respect to the normal direction Z. Note that when we say that the dummy pattern 85 is adjacent to the high-potential coil 23 with respect to the normal direction Z, it means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential coil 22 with respect to the normal direction Z.

[0093] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 with respect to the normal direction Z, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the dummy pattern 85 is formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be suppressed even more effectively. The dummy pattern 85 includes a plurality of dummy patterns with different electrical states. The dummy pattern 85 may also include a high-potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the high-potential dummy pattern 86 is formed in a region adjacent to the high-potential coil 23 with respect to the normal direction Z relative to the low-potential coil 22. The high-potential dummy pattern 86 being adjacent to the high-potential coil 23 with respect to the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22 with respect to the normal direction Z.

[0095] The dummy pattern 85 includes a floating dummy pattern formed electrically in a floating state within the insulating layer 51 so as to be located around the transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is routed in a dense linear fashion so as to partially cover and partially expose the area surrounding the high-potential coil 23 in a plan view. The floating dummy pattern may be formed with ends or without ends.

[0097] The depth position of the floating dummy pattern within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated.

[0098] The number of floating lines is arbitrary and is adjusted according to the electric field to be mitigated. A floating dummy pattern may consist of multiple floating lines.

[0099] Referring to Figure 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using the surface layer of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (bottom insulating layer 55). In Figure 7, the second functional device 60 is simplified by dashed lines shown on the surface layer of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low-potential terminal 11 via low-potential wiring and to the high-potential terminal 12 via high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 to connect to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 to connect to the second functional device 60. A detailed explanation of the low-potential and high-potential wiring related to the second functional device 60 is omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The second functional device 60 may include a circuit network in which any two or more devices from among the passive device, semiconductor rectifier device, and semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0102] Passive devices may include semiconductor passive devices. Passive devices may include either a resistor or a capacitor, or both. Semiconductor rectifier devices may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. Semiconductor switching devices may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] Referring to Figures 5 to 7, the semiconductor device 5 further includes a sealing conductor 61 embedded in the insulating layer 51. In a plan view, the sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner, spaced apart from the insulating side walls 53A to 53D, and divides the insulating layer 51 into a device region 62 and an outer region 63. The sealing conductor 61 suppresses the intrusion of moisture and cracks from the outer region 63 into the device region 62.

[0104] The device region 62 is the region that includes the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. The outer region 63 is the region outside the device region 62.

[0105] The sealing conductor 61 is electrically isolated from the device region 62. Specifically, the sealing conductor 61 is electrically isolated from the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealing conductor 61 is electrically suspended. The sealing conductor 61 does not form a current path that connects to the device region 62.

[0106] In a plan view, the sealing conductor 61 is formed in a strip shape along the insulating side walls 53-53D. In this configuration, the sealing conductor 61 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. As a result, the sealing conductor 61 demarcates a rectangular (specifically, rectangular) device region 62 in a plan view. Furthermore, the sealing conductor 61 demarcates the outer rectangular ring (specifically, a rectangular ring shape) region 63 surrounding the device region 62 in a plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating main surface 52 side, a lower end on the semiconductor chip 41 side, and a wall portion extending wall-like between the upper end and the lower end. In this embodiment, the upper end of the seal conductor 61 is formed with a gap from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed with a gap from the semiconductor chip 41 toward the upper end side.

[0108] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side relative to the multiple low-potential terminals 11 and the multiple high-potential terminals 12. Furthermore, within the insulating layer 51, the sealing conductor 61 faces the first functional device 45 (multiple transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52. Within the insulating layer 51, the sealing conductor 61 may also face a portion of the second functional device 60 in a direction parallel to the insulating main surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, multiple) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 of the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. It is preferable that the seal plug conductors 64 and seal via conductors 65 are made of the same conductive material as the low-potential coil 22. That is, it is preferable that the seal plug conductors 64 and seal via conductors 65 include a barrier layer and a body layer, similar to the low-potential coil 22, etc.

[0110] Multiple seal plug conductors 64 are embedded in multiple interlayer insulating layers 57, each forming a rectangular ring (specifically, a rectangular ring) surrounding the device region 62 in a plan view. The multiple seal plug conductors 64 are stacked from the bottom insulating layer 55 toward the top insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 corresponds to the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] If a single annular seal conductor 61 is formed by an assembly of multiple seal plug conductors 64, it is not necessary for all of the multiple seal plug conductors 64 to be formed in an annular shape. For example, at least one of the multiple seal plug conductors 64 may be formed with ends. Alternatively, at least one of the multiple seal plug conductors 64 may be divided into multiple end-shaped strips. However, considering the risk of moisture and cracks entering the device region 62, it is preferable that the multiple seal plug conductors 64 be formed in an endless (annular) shape.

[0112] Multiple seal via conductors 65 are formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the bottom insulating layer 55. The multiple seal via conductors 65 are formed at intervals from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. If a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area greater than or equal to the planar area of ​​the seal plug conductor 64.

[0113] The width of the seal conductor 61 may be 0.1 μm or more and 10 μm or less. Preferably, the width of the seal conductor 61 is 1 μm or more and 5 μm or less. The width of the seal conductor 61 is defined by the width in the direction perpendicular to the direction in which the seal conductor 61 extends.

[0114] Referring to Figures 7 and 8, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the sealing conductor 61, which electrically isolates the sealing conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 consists of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). Preferably, the field insulating film 131 consists of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion to which the lower end (seal via conductor 65) of the seal conductor 61 bites toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The separation structure 130 includes an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. The inner end portion 130A demarcates the region where the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end portion 130A may be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end portion 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is connected to the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end portion 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0119] The main body portion 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in the main body portion 130C at a distance from the inner end portion 130A and the outer end portion 130B. The separation structure 130 can take various forms other than the field insulating film 131.

[0120] Referring to Figure 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. Preferably, the first inorganic insulating layer 141 contains USG (undopped silicate glass), which is silicon oxide without impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength on the high-potential coil 23 can be increased.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the dielectric breakdown voltage (V / cm) of USG exceeds the dielectric breakdown voltage (V / cm) of silicon nitride. Therefore, when thickening the inorganic insulating layer 140, it is preferable to form the first inorganic insulating layer 141 which is thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass) as examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable that the first inorganic insulating layer 141 be made of USG in order to increase the dielectric strength on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure consisting of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed in the area outside the seal conductor 61. The plurality of low-potential pad openings 143 expose a plurality of low-potential terminals 11, respectively. The plurality of high-potential pad openings 144 expose a plurality of high-potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that ride up over the periphery of the low-potential terminals 11. The inorganic insulating layer 140 may also have overlapping portions that ride up over the periphery of the high-potential terminals 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on an inorganic insulating layer 140. The organic insulating layer 145 may contain a photosensitive resin. The organic insulating layer 145 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than or equal to the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Also, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. With these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the dielectric strength on the high-potential coil 23 can be appropriately increased by the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0127] The organic insulating layer 145 includes a first portion 146 that covers the low-potential region and a second portion 147 that covers the high-potential region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 in between. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have overlapping portions that ride up on the periphery (overlap portion) of the low-potential pad openings 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose a plurality of high-potential terminals 12 (high-potential pad openings 144). The second portion 147 may have overlapping portions that ride up on the periphery (overlap portion) of the high-potential pad openings 144.

[0129] The second section 147 covers the transformers 21A to 21D and the dummy pattern 85 together. Specifically, the second section 147 covers the multiple high-potential coils 23, the multiple high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121 together.

[0130] Embodiments of the present disclosure can be implemented in other forms. In the embodiments described above, an example was given in which a first functional device 45 and a second functional device 60 are formed. However, a form may be adopted in which only the second functional device 60 is present, without the first functional device 45. In this case, the dummy pattern 85 may be removed. With this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] In other words, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, unwanted conduction between the high-potential terminal 12 and the sealing conductor 61 can be suppressed.

[0132] Furthermore, the above-described embodiment described an example in which a second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0133] Furthermore, the above-described embodiment described an example in which a dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0134] Furthermore, in the embodiments described above, an example was given in which the first functional device 45 consists of a multi-channel type including multiple transformers 21. However, a first functional device 45 consisting of a single-channel type including a single transformer 21 may also be employed.

[0135] <Trans arrangement> Figure 9 is a schematic plan view (top view) showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the semiconductor device 5 mentioned earlier). The transformer chip 300 in this figure includes a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of the secondary coil L1s that forms the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of the secondary coil L2s that forms the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Furthermore, pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coils forming the first transformer 301, the second transformer 302, the third transformer 303, and the fourth transformer 304 are not explicitly shown in this figure. However, each primary coil basically has the same configuration as the secondary coils L1s to L4s, and is positioned directly below each of the secondary coils L1s to L4s, facing them respectively.

[0139] Specifically, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Similarly, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Furthermore, pads a7 and b7 are connected to one end of the primary coil forming the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Similarly, pads a8 and b8 are connected to one end of the primary coil forming the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, pads a5-a8, b5-b8, c3 and c4, and d3 and d4 are led from the inside of the trans tip 300 to the surface via vias (not shown).

[0142] Of the above multiple pads, pads a1 to a8 correspond to the first current supply pads, pads b1 to b8 correspond to the first voltage measurement pads, pads c1 to c4 correspond to the second current supply pads, and pads d1 to d4 correspond to the second voltage measurement pads.

[0143] Therefore, with the transformer chip 300 in this configuration example, the series resistance component of each coil can be accurately measured during defective product inspection. Consequently, it becomes possible to appropriately reject not only defective products with open circuits in each coil, but also defective products with abnormal resistance values ​​in each coil (for example, short circuits between coils), and ultimately, to prevent defective products from reaching the market.

[0144] Furthermore, for the transformer chip 300 that has passed the above-mentioned defect inspection, the multiple pads can be used as means of connecting to the primary chip and the secondary chip (for example, the controller chip 210 and driver chip 220 mentioned above).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 should be connected to the signal input terminal or signal output terminal of the secondary chip, respectively. Also, pads c1 and d1, and pads c2 and d2 should be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 should be connected to the signal input terminal or signal output terminal of the primary chip, respectively. Also, pads c3 and d3, and pads c4 and d4 should be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] Here, the first transformers 301 to the fourth transformers 304 are arranged in a coupled configuration according to their respective signal transmission directions, as shown in Figure 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary side chip to the secondary side chip, are connected as a first pair by the first guard ring 305. Similarly, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary side chip to the primary side chip, are connected as a second pair by the second guard ring 306.

[0148] The reason for this coupling is to ensure voltage resistance between the primary and secondary coils when the primary and secondary coils forming the first to fourth transformers 301 to 304 are stacked in the vertical direction on the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 can be connected to low-impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] Furthermore, in the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between their respective primary coils. By adopting this configuration, it is possible to reduce the number of pads and miniaturize the transformer chip 300.

[0151] Furthermore, as shown in Figure 9, it is desirable that the primary and secondary coils forming the first to fourth transformers 301 to 304 be wound in a rectangular shape (or a track shape with rounded corners) when viewed from above the transformer tip 300. This configuration increases the area of ​​the overlapping portion between the primary and secondary coils, thereby improving the transmission efficiency of the transformer.

[0152] Of course, the transformer arrangement in this diagram is merely an example, and the number, shape, and placement of coils, as well as the placement of pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to semiconductor devices in general that integrate coils on a semiconductor chip.

[0153] <Insulated switch (comparative example)> Figure 10 shows a comparative example of the isolation switch 400 (an example of a circuit configuration to be compared with the embodiment described later). The isolation switch 400 in this comparative example transmits a pulse signal from the primary circuit system 400p to the secondary circuit system 400s while insulating the primary circuit system 400p (VCC-GND system) from the secondary circuit system 400s (PVDD-PGND system).

[0154] The isolation switch 400 may be mounted on electronic equipment A together with the load ZL1. Electronic equipment A may be, for example, industrial machinery or automotive equipment. The isolation switch 400 may also be offered to the market as a semiconductor integrated circuit device (a so-called isolation switch IC) formed by integrating it.

[0155] The isolation switch 400 is equipped with external terminals T1 to T5 as means for establishing an electrical connection with the outside of the device. External terminal T1 is connected to the application terminal of the power supply voltage VCC. External terminal T2 is connected to the application terminal of the input pulse signal DIN. External terminal T3 is connected to the application terminal of the ground voltage GND. External terminal T4 is connected to the first terminal of the load ZL1. The second terminal of the load ZL1 is connected to the application terminal of the power supply voltage PVDD. External terminal T5 is connected to the application terminal of the ground voltage PGND.

[0156] Furthermore, the isolation switch 400 includes a primary circuit 410, a secondary circuit 420, and an isolation circuit 430.

[0157] The primary circuit 410 is provided in the primary circuit system 400p. Referring to this figure, the primary circuit 410 includes a pulse generation circuit 411 and an oscillation circuit 413.

[0158] The pulse generation circuit 411 generates a transmit pulse signal Vp1 according to the logic level of the input pulse signal DIN. For example, the pulse generation circuit 411 generates the transmit pulse signal Vp1 when the input pulse signal DIN is at a high level. On the other hand, the pulse generation circuit 411 stops generating the transmit pulse signal Vp1 when the input pulse signal DIN is at a low level. The transmit pulse signal Vp1 may be pulse-driven, for example, between the power supply voltage VCC and the ground voltage GND.

[0159] The oscillator circuit 413 supplies a clock signal to the pulse generation circuit 411. The transmitted pulse signal Vp1 is pulse-driven in synchronization with the clock signal output from the oscillator circuit 413.

[0160] The secondary circuit 420 is provided in the secondary circuit system 400s. Referring to this figure, the secondary circuit 420 includes a switch drive circuit 421 and a switch circuit 422.

[0161] The switch drive circuit 421 generates a switch drive signal Vg in response to, for example, an induced voltage Vs1. As shown in the figure, the switch drive circuit 421 includes a diode D0, a resistor R0, a capacitor Cg, and a discharge circuit 421X.

[0162] The anode of diode D0 is connected to the terminal to which the induced voltage Vs1 is applied. The cathode of diode D0 is connected to the first terminal of resistor R0. The second terminal of resistor R0 and the first terminals of capacitor Cg and discharge circuit 421X are all connected to the terminals to which the switch drive signal Vg is applied. The second terminals of capacitor Cg and discharge circuit 421X are all connected to the external terminal T5. Capacitor Cg may be a parasitic capacitor associated with the gate-source of transistor M1, which will be described later. Note that diode D0, resistor R0, and capacitor Cg rectify and smooth the induced voltage Vs1 to generate the switch drive signal Vg.

[0163] The switch circuit 422 is connected between external terminals T4 and T5 and is switched on / off by the switch drive signal Vg. External terminal T4 corresponds to the first node. External terminal T5 corresponds to the second node.

[0164] For example, the switch circuit 422 includes a transistor M1 that conducts / blocks between external terminals T4 and T5 in response to a switch drive signal Vg. Transistor M1 may be, for example, an N-channel MOS (metal oxide semiconductor) field-effect transistor. The drain of transistor M1 is connected to external terminal T4. The source and back gate of transistor M1 are connected to external terminal T5. The gate of transistor M1 is connected to the application terminal of the switch drive signal Vg. Transistor M1 can be understood as an output transistor whose gate is connected to the application terminal of the switch drive signal Vg.

[0165] The isolation circuit 430 DC-isolates the pulse generation circuit 411 and the switch drive circuit 421, while transmitting the transmitted pulse signal Vp1 of the primary circuit system 400p as the induced voltage Vs1 of the secondary circuit system 400s. Referring to this figure, the isolation circuit 430 includes a transformer 431. The transformer 431 includes a primary coil 431p and a secondary coil 431s.

[0166] The first end of the primary coil 431p is connected to the application terminal of the transmitted pulse signal Vp1. The second end of the primary coil 431p is connected to the external terminal T3. The first end of the secondary coil 431s is connected to the application terminal of the induced voltage Vs1. The induced voltage Vs1 corresponds to the received pulse signal generated in the secondary coil 431s. The second end of the secondary coil 431s is connected to the external terminal T5. The secondary coil 431s is electromagnetically coupled to the primary coil 431p. The winding ratio of the primary coil 431p and the secondary coil 431s can be adjusted so that the switch drive signal Vg exceeds the on-threshold voltage Vth(M1) of transistor M1 when the transmitted pulse signal Vp is pulse-driven.

[0167] Next, the basic operation of the isolation switch 400 is explained. During the high-level period of the input pulse signal DIN, the transmission pulse signal Vp1 applied to the primary coil 431p is pulse-driven. At this time, an induced voltage Vs1 is generated in the secondary coil 431s. The induced voltage Vs1 is rectified and smoothed, raising the switch drive signal Vg to a signal level higher than the on-threshold voltage Vth(M1) of transistor M1. As a result, transistor M1 is turned on, and a drive current can be supplied to the load ZL1.

[0168] On the other hand, during the low-level period of the input pulse signal DIN, the pulse drive of the transmitted pulse signal Vp1 is stopped. Consequently, the induced voltage Vs1 also ceases to be generated. At this time, the switch drive signal Vg is reduced to a signal level lower than the on-threshold voltage Vth(M1) of transistor M1 by the action of the discharge circuit 421X. As a result, transistor M1 is in the off state, and no drive current is supplied to the load ZL1.

[0169] Thus, the insulating switch 400 in this comparative example transmits a pulse signal from the primary circuit system 400p to the secondary circuit system 400s while insulating the primary circuit system 400p and the secondary circuit system 400s through magnetic coupling using the transformer 431.

[0170] <Considerations regarding the switch drive signal Vg> Conventionally, DMOS (double-diffused MOS) or CMOS (complementary MOS) devices are widely used as transistor M1. When the power supply voltage PVDD of the secondary circuit system 400s is around 10 to 40V, there are no particular problems with selecting the above devices.

[0171] However, in recent years, there has been a demand or application for applying a high voltage of 600V as the power supply voltage PVDD. The aforementioned DMOS or CMOS devices may not be able to withstand such high voltages. Therefore, in order to meet the above requirements, it is necessary to use a device with a higher voltage rating than the DMOS or CMOS device as the transistor M1, such as a GaN device like a GaN-HEMT (high electron mobility transistor) or a SiC device like a SiC-MOSFET.

[0172] However, the on-threshold voltage of GaN or SiC devices is higher than that of DMOS or CMOS devices. Therefore, a mechanism is needed to raise the high level of the switch drive signal Vg.

[0173] In light of the above considerations, a novel embodiment capable of raising the high level of the switch drive signal Vg is proposed below.

[0174] <Insulated switch (first embodiment)> Figure 11 shows a first embodiment of the isolation switch 400. The isolation switch 400 of this embodiment is based on the comparative example (Figure 10) described earlier, and further includes a pulse generation circuit 412 and a transformer 432. The transistor M1 may be a GaN device or a SiC device.

[0175] As described above, the pulse generation circuit 411 generates the transmit pulse signal Vp1 according to the logic level of the input pulse signal DIN. For example, the pulse generation circuit 411 generates the transmit pulse signal Vp1 when the input pulse signal DIN is at a high level. On the other hand, the pulse generation circuit 411 stops generating the transmit pulse signal Vp1 when the input pulse signal DIN is at a low level. The transmit pulse signal Vp1 may be pulse-driven, for example, between the power supply voltage VCC and the ground voltage GND.

[0176] The pulse generation circuit 412 generates a transmit pulse signal Vp2 according to the logic level of the input pulse signal DIN. For example, the pulse generation circuit 412 generates the transmit pulse signal Vp2 when the input pulse signal DIN is at a high level. On the other hand, the pulse generation circuit 412 stops generating the transmit pulse signal Vp2 when the input pulse signal DIN is at a low level. The transmit pulse signal Vp2 may be pulse-driven, for example, between the power supply voltage VCC and the ground voltage GND.

[0177] In other words, pulse generation circuits 411 and 412 drive pulses on primary coils 431p and 432p respectively when the input pulse signal DIN is at a high level. On the other hand, pulse generation circuits 411 and 412 stop driving pulses on primary coils 431p and 432p respectively when the input pulse signal DIN is at a low level.

[0178] The oscillator circuit 413 supplies a common clock signal to the pulse generation circuits 411 and 412, respectively. The transmitted pulse signals Vp1 and Vp2 are pulse-driven in synchronization with the clock signal output from the oscillator circuit 413.

[0179] As mentioned above, transformer 431 includes a primary coil 431p and a secondary coil 431s. Transformer 432 also includes a primary coil 432p and a secondary coil 432s.

[0180] The first end of the primary coil 431p is connected to the application terminal of the transmitted pulse signal Vp1. The first end of the primary coil 432p is connected to the application terminal of the transmitted pulse signal Vp2. The second ends of the primary coils 431p and 432p are connected to the external terminal T3. In other words, the primary coils 431p and 432p are connected in parallel between the application terminal of the power supply voltage VCC and the application terminal of the ground voltage GND, as shown in the blown-out frame. Then, the conduction / non-conduction of the primary coils 431p and 432p is switched according to the input pulse signal DIN.

[0181] The first end of secondary coil 431s is connected to the first end of secondary coil 432s. The second end of secondary coil 431s is connected to external terminal T5. The second end of secondary coil 432s is connected to the anode of diode D0. In other words, secondary coils 431s and 432s are connected in series with each other.

[0182] The secondary coil 431s is electromagnetically coupled to the primary coil 431p. The secondary coil 432s is electromagnetically coupled to the primary coil 432p. The winding ratio of the primary coil 431p and the secondary coil 431s, and the winding ratio of the primary coil 432p and the secondary coil 432s can be adjusted so that when the transmitted pulse signals Vp1 and Vp2 are pulse-driven, the switch drive signal Vg exceeds the on-threshold voltage Vth(M1) of transistor M1.

[0183] The switch drive circuit 421 generates a switch drive signal Vg by receiving the induced voltages Vs1 and Vs2 generated in the secondary coils 431s and 432s, respectively. For example, the switch drive circuit 421 generates the switch drive signal Vg by rectifying the sum of the induced voltage Vs1 generated in the secondary coil 431s and the induced voltage Vs2 generated in the secondary coil 432s (=Vs1+Vs2). In addition to the components of the comparative example (Figure 10), the switch drive circuit 421 includes a capacitor C0. Capacitor C0 is connected between the cathode of diode D0 and the external terminal T5.

[0184] With the isolation switch 400 of this embodiment, the high level of the switch drive signal Vg is increased compared to the comparative example (Figure 10) described earlier. Therefore, even if the transistor M1 is a GaN device or a SiC device, it can be turned on / off without any problems. As a result, high-voltage driving of the load ZL1 becomes possible.

[0185] <Insulated switch (second embodiment)> Figure 12 shows a second embodiment of the insulated switch 400. The insulated switch 400 of this embodiment is based on the first embodiment (Figure 11) described above, but the configuration of the switch drive circuit 421 has been changed.

[0186] Referring to this figure, the switch drive circuit 421 includes capacitors C1 and C2, diodes D1 and D2, transistor P1, and resistor R2, instead of the previously mentioned diode D0 and resistor R0. Transistor P1 may be, for example, a P-channel type.

[0187] The first end of the secondary coil 431s and the anode of diode D1 are connected to the application terminal of the induced voltage Vs1. The cathode of diode D1 and the first end of capacitor C1 are connected to the application terminal of the rectified voltage V1. The second end of the secondary coil 431s and the second end of capacitor C1 are connected to the external terminal T5. Diode D1 and capacitor C1 can be understood as a rectifier circuit REC1 that rectifies and smooths the induced voltage Vs1 generated in the secondary coil 431s to produce the rectified voltage V1. The capacitance value of capacitor C1 may be, for example, 10pF.

[0188] The first end of the secondary coil 432s and the anode of diode D2 are connected to the application terminal of the induced voltage Vs2. The cathode of diode D2, the first end of resistor R0, and the first end of capacitor C2 are connected to the application terminal of the rectified voltage V2. The second end of the secondary coil 432s is connected to the application terminal of the rectified voltage V1. The second end of capacitor C2 is connected to the external terminal T5. Diode D2 and capacitor C2 can be understood as a rectifier circuit REC2 that rectifies and smooths the sum of the rectified voltage V1 and the induced voltage Vs2 generated in the secondary coil 432s (V1 + Vs2) to generate the rectified voltage V2. The capacitance value of capacitor C2 may be, for example, 1pF. That is, C1 may be >> C2. Capacitor C2 may be omitted.

[0189] The gate of transistor P1 is connected to the terminal to which the rectified voltage V1 is applied. The source of transistor P1 is connected to the second terminal of resistor R0. The drain of transistor P1 is connected to the terminal to which the switch drive signal Vg is applied. Transistor P1 conducts / blocks between the terminal to which the rectified voltage V2 is applied and the terminal to which the switch drive signal Vg is applied, depending on the gate-source voltage, i.e., the difference voltage between the rectified voltage V1 and the rectified voltage V2 (V2-V1).

[0190] Furthermore, in the isolation switch 400 of this embodiment, the operation of the pulse generation circuits 411 and 412 has also been changed in accordance with the change in the configuration of the switch drive circuit 421.

[0191] For example, the pulse generation circuit 412 generates a transmit pulse signal Vp2 when the input pulse signal DIN is at a high level to pulse-drive the primary coil 432p. That is, the pulse generation circuit 412 pulse-drives the primary coil 432p when it raises the switch drive signal Vg to a high level. On the other hand, the pulse generation circuit 412 stops generating the transmit pulse signal Vp2 and stops pulse-driving the primary coil 432p when the input pulse signal DIN is at a low level. That is, the pulse generation circuit 412 stops pulse-driving the primary coil 432p when it drops the switch drive signal Vg to a low level. This operation is the same as in the first embodiment described above.

[0192] In contrast, the pulse generation circuit 411 generates a transmission pulse signal Vp1 and pulse-drives the primary coil 432p whether the input pulse signal DIN is at a high level or a low level. That is, the pulse generation circuit 412 pulse-drives the primary coil 411p whether it raises the switch drive signal Vg to a high level or drops it to a low level.

[0193] Next, the basic operation of the isolation switch 400 in this embodiment will be described. During the high-level period of the input pulse signal DIN, the transmission pulse signal Vp1 applied to the primary coil 431p is pulse-driven. Consequently, an induced voltage Vs1 is generated across the terminals of the secondary coil 431s. The rectifier circuit REC1 rectifies and smooths the induced voltage Vs1 to generate a rectified voltage V1. The rectified voltage V1 may be, for example, 4V.

[0194] Furthermore, during the high-level period of the input pulse signal DIN, the transmission pulse signal Vp2 applied to the primary coil 432p is pulse-driven. Consequently, an induced voltage Vs2 is generated across the secondary coil 432s. At this time, the sum of the rectified voltage V1 and the induced voltage Vs2 (V1+Vs2) is applied to the anode of diode D2. The sum of the voltages (V1+Vs2) is rectified and smoothed in the rectifier circuit REC2 to generate a rectified voltage V2. The rectified voltage V2 may be, for example, 8V.

[0195] When the difference voltage between the rectified voltage V1 and the rectified voltage V2 (V2-V1) becomes higher than the on-threshold voltage Vth(P1) of transistor P1, transistor P1 turns on. Consequently, conduction occurs between the application terminal of the rectified voltage V2 and the application terminal of the switch drive signal Vg. At this time, the switch drive signal Vg is raised to a signal level higher than the on-threshold voltage Vth(M1) of transistor M1, i.e., to a high level (≒V2). As a result, transistor M1 turns on, and a drive current can be supplied to the load ZL1.

[0196] In this figure, the arrows attached to the primary coils 431p and 432p, and the secondary coils 431s and 432s, respectively, indicate the direction of the current flowing when the switch drive signal Vg is raised to a high level.

[0197] In contrast, during the low-level period of the input pulse signal DIN, the pulse drive of the transmitted pulse signal Vp1 continues, while the pulse drive of the transmitted pulse signal Vp2 is stopped. At this time, an induced voltage Vs1 is generated in the secondary coil 431s, so the charge stored in the capacitor C1, i.e., the rectified voltage V1, is maintained.

[0198] However, the induced voltage Vs2 is no longer generated in the secondary coil 432s. As a result, the charge supply to capacitor C2, and consequently to capacitor Cg, is interrupted. Consequently, the amount of charge discharged through the discharge circuit 421X exceeds the amount of charge supplied through transistor P1. As a result, the switch drive signal Vg decreases.

[0199] Furthermore, as the switch drive signal Vg decreases, the rectified voltage V2 also decreases. When the difference voltage between the rectified voltages V1 and V2 (V2-V1) falls below the on-threshold voltage Vth(P1) of transistor P1, transistor P1 turns off. As a result, the decrease in the rectified voltage V2 stops. In other words, the rectified voltage V2 is maintained at a value close to the rectified voltage V1. Subsequently, the switch drive signal Vg is further reduced to a signal level lower than the on-threshold voltage Vth(M1) of transistor M1 by the action of the discharge circuit 421X. As a result, transistor M1 turns off, and no drive current is supplied to the load ZL1.

[0200] As mentioned earlier, the charge stored in capacitors C1 and C2 is maintained even during the low-level period of the input pulse signal DIN. Therefore, when the input pulse signal DIN is next raised to a high level, the rectified voltage V2 begins to rise from a state where charge has already been stored in capacitors C1 and C2. As a result, the turn-on timing of transistor P1 is advanced, and the switch drive signal Vg is raised to a high level more quickly.

[0201] As described above, with the isolation switch 400 of this embodiment, the rise time of the switch drive signal Vg from the second time onward can be shortened compared to the first embodiment (Figure 11) described earlier.

[0202] <Insulated switch (third embodiment)> Figure 13 shows a third embodiment of the isolation switch 400. The isolation switch 400 of this embodiment is based on the second embodiment (Figure 12) described above, but includes a resistor R3 as a discharge circuit 421X that discharges the switch drive signal Vg.

[0203] Resistor R3 can be understood as a discharge resistor connected between the application terminal of the switch drive signal Vg and the external terminal T5. With the isolated switch 400 of this embodiment, the discharge circuit 421X can be formed very simply.

[0204] <Insulated switch (fourth embodiment)> Figure 14 shows a fourth embodiment of the isolation switch 400. The isolation switch 400 of this embodiment is based on the second embodiment (Figure 12) described above, and includes a transistor N1 and a controller X1 as components of the discharge circuit 421X. The transistor N1 may be, for example, an N-channel type.

[0205] The drain of transistor N1 is connected to the application terminal of the switch drive signal Vg. The source of transistor N1 is connected to the external terminal T5. Transistor N1 functions as a low-impedance discharge switch connected between the application terminal of the switch drive signal Vg and the external terminal T5.

[0206] The controller X1 drives the gate of transistor N1 in response to, for example, the induced voltage Vs2 generated in the secondary coil 432s. For example, the controller X1 turns on transistor N1 when no induced voltage Vs2 is present. On the other hand, the controller X1 turns off transistor N1 when an induced voltage Vs2 is present.

[0207] The controller X1 may operate using the rectified voltage V1 as its power source. Alternatively, the controller X1 may operate using the switch drive signal Vg as its power source.

[0208] With the isolation switch 400 of this embodiment, the switch drive signal Vg can be discharged faster compared to the third embodiment described above (Figure 13). Therefore, high-speed switching of the transistor M1 becomes possible.

[0209] <Controller> Figure 15 shows an example configuration of controller X1. In this example configuration, controller X1 operates using a rectified voltage V1 as its power source. As shown in the figure, controller X1 includes a capacitor C3, a transistor N2, a transistor P2, and resistors R4 to R6. Note that transistor N2 may be, for example, an N-channel type. Also, transistor P2 may be, for example, a P-channel type. A resistor Rg may be connected between the gate and source of transistor M1.

[0210] The source of transistor P2 is connected to the terminal to which the induced voltage Vs2 is applied. The gate of transistor P2 and the first terminal of resistor R4 are connected to the terminal to which the rectified voltage V1 is applied. The drain of transistor P2, the gate of transistor N2, and the first terminal of resistor R5 are connected to the terminal to which the voltage signal V3 is applied. The second terminal of resistor R4, the drain of transistor N2, and the first terminals of resistor R6 and capacitor C3 are connected to the terminal to which the voltage signal V4 is applied. The source of transistor N2, the second terminals of resistors R5 and R6, and the second terminal of capacitor C3 are connected to the terminal to which the ground voltage PGND is applied. The terminal to which the voltage signal V4 is applied is connected to the gate of transistor N1 as the output terminal of controller X1.

[0211] When no induced voltage Vs2 is present, transistor P2 is in the off state, so the voltage signal V3 is at a low level (≒PGND). At this time, transistor N2 is in the off state, so the voltage signal V4 is at a high level (≒V1). Therefore, transistor N1 is in the on state. On the other hand, when an induced voltage Vs2 is present, transistor P2 is in the on state, so the voltage signal V3 is at a high level (≒V1+Vs2). At this time, transistor N2 is in the on state, so the voltage signal V4 is at a low level (≒PGND). Therefore, transistor N1 is in the off state.

[0212] Figure 16 shows a modified example of controller X1. This modified controller X1 is based on the previously mentioned configuration example (Figure 15), but operates using the switch drive signal Vg as the power source. As shown in this figure, controller X1 includes a capacitor C4 and a diode D3 instead of transistor P2.

[0213] The anode of diode D3 is connected to the application terminal of the switch drive signal Vg. The cathode of diode D3 is connected to the first terminal of resistor R4. The first terminal of capacitor C4 is connected to the application terminal of the induced voltage Vs2. The second terminal of capacitor C4 is connected to the application terminal of the voltage signal V3.

[0214] When no induced voltage Vs2 is present, the voltage signal V3 is at a low level (≒PGND), so transistor N2 is in the off state. Consequently, the voltage signal V4 is at a high level (≒V1), so transistor N1 is in the on state. On the other hand, when an induced voltage Vs2 is present, the voltage signal V3 is at a high level (≒V1+Vs2), so transistor N2 is in the on state. Consequently, the voltage signal V4 is at a low level (≒PGND), so transistor N1 is in the off state.

[0215] <Insulated switch (5th embodiment)> Figure 17 shows a fifth embodiment of the isolation switch 400. The isolation switch 400 of this embodiment is based on the second embodiment (Figure 12) described above, and further includes transformers 433 and 434, capacitors C5 to C8, diodes D4 and D5, and resistors R1 and R2. Transformer 433 includes a primary coil 433p and a secondary coil 433s. Transformer 434 also includes a primary coil 434p and a secondary coil 434s. On the other hand, the resistor R0 described above has been removed.

[0216] The first end of primary coil 433p is connected to the application terminal of the transmitted pulse signal Vp1. The first end of primary coil 434p is connected to the application terminal of the transmitted pulse signal Vp2. The second ends of primary coils 433p and 434p are connected to the external terminal T3. In other words, primary coils 433p and 434p are connected in parallel between the application terminal of the power supply voltage VCC and the application terminal of the ground voltage GND, similar to the primary coils 431p and 432p mentioned earlier. Then, the conduction / non-conduction of primary coils 433p and 434p is switched according to the input pulse signal DIN.

[0217] In other words, pulse generation circuit 411 simultaneously pulses both primary coils 431p and 433p. Similarly, pulse generation circuit 412 simultaneously pulses both primary coils 432p and 434p.

[0218] The first end of the secondary coil 431s, the anode of diode D4, and the first end of capacitor C5 are connected to the application terminal of the induced voltage Vs1. The cathode of diode D4, the anode of diode D1, and the first end of capacitor C6 are connected to the application terminal of the boost voltage V5. The cathode of diode D1 and the second end of capacitor C5 are connected to the first end of resistor R1. The second end of resistor R1 and the first end of capacitor C1 are connected to the application terminal of the rectified voltage V1. The second end of the secondary coil 431s, the first end of the secondary coil 433s, and the second end of capacitor C1 are connected to the external terminal T5. The second end of the secondary coil 433s is connected to the second end of capacitor C6.

[0219] Diode D4 and capacitor C6 can be understood as a boost circuit CP1 that generates a boosted voltage V5 from the induced voltage Vs1 generated in the secondary coil 431s and the induced voltage Vs3 generated in the secondary coil 433s. The boost circuit CP1 increases the amplitude of the boosted voltage V5 to be greater than the amplitudes of the induced voltages Vs1 and Vs3 individually by charge pump operation using the induced voltages Vs1 and Vs3 which are pulsed in a differential manner.

[0220] The diode D1, resistor R1, and capacitor C1 can be understood as a rectifier circuit REC1 that rectifies the boosted voltage V5 to generate a rectified voltage V1.

[0221] The first end of the secondary coil 432s, the anode of diode D5, and the first end of capacitor C7 are connected to the application terminal of the induced voltage Vs2. The cathode of diode D5, the anode of diode D2, and the first end of capacitor C8 are connected to the application terminal of the boost voltage V6. The cathode of diode D2 and the second end of capacitor C7 are connected to the first end of resistor R2. The second end of resistor R2 and the first end of capacitor C2 are connected to the application terminal of the rectified voltage V2. The second end of the secondary coil 432s and the first end of the secondary coil 434s are connected to the application terminal of the rectified voltage V1. The second end of capacitor C2 is connected to the external terminal T5. The second end of secondary coil 434s is connected to the second end of capacitor C8.

[0222] Diode D5 and capacitor C8 can be understood as a boost circuit CP2 that generates a boosted voltage V6 from the induced voltage Vs2 generated in the secondary coil 432s and the induced voltage Vs4 generated in the secondary coil 434s. The boost circuit CP2 increases the amplitude of the boosted voltage V6 to be greater than the amplitudes of the induced voltages Vs2 and Vs4 respectively through charge pump operation using differentially pulsed induced voltages Vs2 and Vs4.

[0223] The diode D2, resistor R2, and capacitor C2 can be understood as a rectifier circuit REC2 that rectifies the sum of the rectified voltage V1 and the boosted voltage V6 to generate a rectified voltage V2.

[0224] The gate of transistor P1 is connected to the terminal to which the rectified voltage V1 is applied. The source of transistor P1 is connected to the terminal to which the rectified voltage V2 is applied. The drain of transistor P1 is connected to the terminal to which the switch drive signal Vg is applied. Transistor P1 conducts / blocks between the terminal to which the rectified voltage V2 is applied and the terminal to which the switch drive signal Vg is applied, depending on the gate-source voltage, i.e., the difference voltage between the rectified voltage V1 and the rectified voltage V2 (V2-V1).

[0225] With the isolation switch 400 of this embodiment, the high level of the switch drive signal Vg is further increased compared to the second embodiment described above (Figure 12) due to the operation of the boost circuits CP1 and CP2.

[0226] <Insulated switch (6th embodiment)> Figure 18 shows a sixth embodiment of the isolation switch 400. The isolation switch 400 of this embodiment is based on the first embodiment (Figure 11) described above, but the configuration of the switch circuit 640 has been changed. Referring to this figure, the switch circuit 640 includes transistors M1a and M1b instead of the transistor M1 described above. Transistors M1a and M1b may be, for example, N-channel type.

[0227] The source and back gate of transistors M1a and M1b are connected to a common node n1. The second terminal of the secondary coil 431s and the second terminal of capacitor Cg are also connected to the common node n1. The gates of transistors M1a and M1b are connected to the application terminal of the switch drive signal Vg.

[0228] In the first connection configuration, the drain of transistor M1a may be connected to the application terminal of the power supply voltage PVDD via the load ZL1, and the drain of transistor M1b may be connected to the application terminal of the ground voltage PGND. In this case, the switch circuit 640 functions as a lower switch.

[0229] In the second connection configuration, the drain of transistor M1a may be connected to the terminal where the ground voltage PGND is applied via the load ZL2, and the drain of transistor M1b may be connected to the terminal where the power supply voltage PVDD is applied. In this case, the switch circuit 640 functions as an upper switch.

[0230] Thus, the isolation switch 400 of this embodiment can be flexibly applied regardless of whether the external terminals T4 or T5 are high-potential nodes.

[0231] <Insulated switch (7th embodiment)> Figure 19 shows a seventh embodiment of the isolation switch 400. The isolation switch 400 of this embodiment is based on the second embodiment (Figure 12) described above, and, following the sixth embodiment (Figure 18) described above, the switch circuit 640 includes transistors M1a and M1b.

[0232] With the isolation switch 400 of this embodiment, it is possible to achieve faster switching while enjoying the same effects and advantages as the sixth embodiment described above (Figure 18).

[0233] <Insulated switch (8th embodiment)> Figure 20 shows an eighth embodiment of the isolation switch 400. The isolation switch 400 of this embodiment is based on the fifth embodiment (Figure 17) described above, and follows the sixth embodiment (Figure 18) described above, with the switch circuit 640 including transistors M1a and M1b.

[0234] With the isolation switch 400 of this embodiment, it is possible to generate a higher switch drive signal Vg while enjoying the same effects as the sixth embodiment described above (Figure 18).

[0235] <Insulated switch (9th embodiment)> Figure 21 shows a ninth embodiment of the isolation switch 400. The isolation switch 400 of this embodiment is based on the first embodiment (Figure 11) described above, and further includes a voltage control circuit 421Y as a component of the switch drive circuit 421.

[0236] When a GaN device or similar is used as transistor M1, a switch drive signal Vg with a certain degree of accuracy is required. For example, the switch drive signal Vg may require an output accuracy of 5V ± 10%. However, the rectifier circuit REC, consisting of diode D0 and capacitor C0, may not necessarily be able to achieve the above output accuracy.

[0237] Therefore, the isolation switch 400 of this embodiment includes a voltage control circuit 421Y as a component of the switch drive circuit 421. The voltage control circuit 421Y is preferably provided between the rectifier circuit REC and the application terminal of the switch drive signal Vg. The voltage control circuit 421Y stabilizes the switch drive signal Vg and outputs it to the gate of the transistor M1. With this configuration, the transistor M1 can be driven appropriately.

[0238] <Insulated switch (10th embodiment)> Figure 22 shows a tenth embodiment of the isolation switch 400. The isolation switch 400 of this embodiment is based on the second embodiment (Figure 12) described above, and further includes a voltage control circuit 421Y as a component of the switch drive circuit 421. As shown in this figure, the voltage control circuit 421Y can be introduced into the switch drive circuit 421 of various topologies, regardless of the preceding circuit configuration (rectifier circuits REC1 and REC2 in this figure).

[0239] <Voltage control circuit> Figure 23 shows an example configuration of the voltage control circuit 421Y. In this example configuration, the voltage control circuit 421Y includes a Zener diode Y1. The cathode of the Zener diode Y1 is connected to the application terminal of the switch drive signal Vg. The anode of the Zener diode Y1 is connected to an external terminal T5. The external terminal T5 can be understood as an example of a reference potential terminal. With this configuration, the voltage control circuit 421Y can be easily implemented.

[0240] <Combination of Embodiments> The various embodiments described so far may be combined in any way that does not contradict each other. For example, the third embodiment (Figure 13) and the fourth embodiment (Figure 14) may be applied simultaneously. That is, the discharge circuit 421X may include a first discharge path through resistor R3 and a second discharge path through transistor N1.

[0241] Furthermore, the voltage control circuit 421Y described above can be introduced in any of the third embodiment (Figure 13), fourth embodiment (Figure 14), fifth embodiment (Figure 17), sixth embodiment (Figure 18), seventh embodiment (Figure 19), and eighth embodiment (Figure 20). When introducing the voltage control circuit 421Y, if the output circuit 422 includes transistors M1a and M1b, the anode of the Zener diode Y1 should be connected to a common node nd rather than the external terminal T5. The common node nd can be understood as an example of a reference potential terminal.

[0242] <Note> According to this disclosure, the high level of the switch drive signal is increased. The above disclosure is further noted below.

[0243] [Note 1] A switch circuit (422) is connected between the first node (T4) and the second node (T5) and configured to be turned on / off by a switch drive signal (Vg), A first transformer (431) and a second transformer (432) are configured such that a first primary coil (431p) and a second primary coil (432p) are connected in parallel between the power terminal (VCC) and the ground terminal (GND), and a first secondary coil (431s) and a second secondary coil (432s) are connected in series with each other. A first pulse generation circuit (411) and a second pulse generation circuit (412) are configured to pulse-drive the first primary coil (431p) and the second primary coil (432p), respectively, in response to an input pulse (DIN). A switch drive circuit (421) is configured to generate the switch drive signal (Vg) by receiving the induced voltages (Vs1, Vs2) generated in the first secondary coil (431s) and the second secondary coil (432s), respectively, An insulated switch (400) equipped with [a specific feature].

[0244] [Note 2] The switch circuit (422) is an isolated switch (400) as described in Appendix 1, which includes at least one output transistor (M1, M1a, M1b) whose gate is connected to the application terminal of the switch drive signal (Vg).

[0245] [Note 3] The output transistors (M1, M1a, M1b) are GaN devices or SiC devices, as described in Appendix 2, and the isolation switch (400).

[0246] [Note 4] The switch drive circuit (421) is configured to generate the switch drive signal (Vg) by rectifying the sum of the first induced voltage (Vs1) generated in the first secondary coil (431s) and the second induced voltage (Vs2) generated in the second secondary coil (432s), as described in Appendix 2 or 3, for the isolated switch (400).

[0247] [Note 5] The isolation switch (400) described in Appendix 4 is configured such that the first pulse generation circuit (411) and the second pulse generation circuit (412) pulse-drive the first primary coil (431p) and the second primary coil (432p) respectively when the input pulse (DIN) is at a first logic level (e.g., high level), and stops pulse-driving the first primary coil (431p) and the second primary coil (432p) respectively when the input pulse (DIN) is at a second logic level (e.g., low level).

[0248] [Note 6] The switch drive circuit (421) includes a first rectifier circuit (REC1) configured to rectify a first induced voltage (Vs1) generated in the first secondary coil (431s) to generate a first rectified voltage (V1), a second rectifier circuit (REC2) configured to rectify the sum of the first rectified voltage (V1) and a second induced voltage (Vs2) generated in the second secondary coil (432s) to generate a second rectified voltage (V2), and a transistor (P1) configured to conduct / block the connection between the application terminal of the second rectified voltage (V2) and the application terminal of the switch drive signal (Vg) according to the difference voltage between the first rectified voltage (V1) and the second rectified voltage (V2), as described in Appendix 2 or 3, the isolated switch (400).

[0249] [Note 7] The isolation switch (400) as described in Appendix 6, wherein the first rectifier circuit (REC1) includes a first diode (D1) configured to be connected between the application terminal of the first induced voltage (Vs1) and the application terminal of the first rectified voltage (V1), and a first capacitor (C1) configured to be connected between the application terminal of the first rectified voltage (V1) and the second node (T5), and the second rectifier circuit (REC2) includes a second diode (D2) configured to be connected between the application terminal of the second induced voltage (Vs2) and the application terminal of the second rectified voltage (V2).

[0250] [Note 8] The isolation switch (400) described in Appendix 7 further includes a second capacitor (C2) configured to be connected between the application terminal of the second rectified voltage (V2) and the second node (T5).

[0251] [Note 9] The first pulse generation circuit (411) is configured to pulse-drive the first primary coil (431p) whether the input pulse (DIN) is at a first logic level (e.g., high level) or a second logic level (e.g., low level). The isolation switch (400) described in any of appendices 6 to 8 is configured such that the second pulse generation circuit (412) pulses the second primary coil (432p) when the input pulse (DIN) is at the first logic level (e.g., high level), and stops pulse driving the second primary coil (432p) when the input pulse (DIN) is at the second logic level (e.g., low level).

[0252] [Note 10] The switch drive circuit (421) is an isolated switch (400) as described in any of Appendix 2 to 9, which includes a discharge circuit (421X) configured to discharge the switch drive signal (Vg).

[0253] [Note 11] The discharge circuit (421X) is an isolated switch (400) as described in Appendix 10, which includes a discharge resistor (R3) configured to be connected between the application terminal of the switch drive signal (Vg) and the second node (T5).

[0254] [Note 12] The isolation switch (400) according to any one of appendices 6 to 9, wherein the switch drive circuit (421) includes a discharge switch (N1) configured to be connected between the application terminal of the switch drive signal (Vg) and the second node (T5), and a controller (X1) configured to drive the discharge switch (N1) in accordance with the second induced voltage (Vs2).

[0255] [Note 13] The controller (X1) is an isolation switch (400) as described in Appendix 12, which operates using the first rectified voltage (V1) or the switch drive signal (Vg) as a power source.

[0256] [Note 14] A third transformer (433) including a third primary coil (433p) and a third secondary coil (433s), A fourth transformer (434) including a fourth primary coil (434p) and a fourth secondary coil (434s), Furthermore, The first pulse generation circuit (411) simultaneously pulse-drives the first primary coil (431p) and the third primary coil (433p), The second pulse generation circuit (412) simultaneously pulse-drives the second primary coil (432p) and the fourth primary coil (434p), The switch drive circuit (421) includes a first boost circuit (CP1) configured to generate a first boost voltage (V5) from a first induced voltage (Vs1) generated in the first secondary coil (431s) and a third induced voltage (Vs3) generated in the third secondary coil (433s), a first rectifier circuit (REC1) configured to generate a first rectified voltage (V1) by rectifying the first boost voltage (V5), and a second induced voltage (Vs2) generated in the second secondary coil (432s) and a fourth induced voltage (Vs4) generated in the fourth secondary coil (434s). An isolation switch (400) as described in Appendix 2 or 3, comprising: a second boost circuit (CP2) configured to generate a second boost voltage (V6) from; a second rectifier circuit (REC2) configured to generate a second rectified voltage (V2) by rectifying the sum of the first rectified voltage (V1) and the second boost voltage (V6); and a transistor (P1) configured to conduct / block the connection between the application terminal of the second rectified voltage (V2) and the application terminal of the switch drive signal (Vg) according to the difference voltage between the first rectified voltage (V1) and the second rectified voltage (V2).

[0257] [Note 15] The switch circuit (422) is an isolated switch (400) as described in any of the appendices 2 to 14, comprising a first output transistor (M1a) and a second output transistor (M1b) as output transistors (M1), each having its gate connected to the application terminal of the switch drive signal (Vg) and its source connected to a common node.

[0258] [Note 16] The switch drive circuit (421) includes a voltage control circuit (421Y) configured to stabilize the switch drive signal (Vg), and is an insulated switch (400) according to any one of Appendices 1 to 15.

[0259] [Appendix 17] The voltage control circuit (421Y) includes a Zener diode (Y1) configured to be connected between the application end of the switch drive signal (Vg) and the reference potential end (T5, nd), and is an insulated switch (400) according to Appendix 16.

[0260] <Others> In addition, various technical features disclosed in this specification can be variously modified without departing from the gist of the technical creation in addition to the above embodiments. That is, the above embodiments should be considered to be illustrative in all respects and not restrictive. Also, the technical scope of the present disclosure is defined by the scope of the claims, and it should be understood that all modifications belonging to the meaning and scope equivalent to the scope of the claims are included.

Description of Reference Numerals

[0261] 5 Semiconductor device 11, 11A to 11F Low potential terminals 12, 12A to 12F High potential terminals 21, 21A to 21D Transformers 22 Low potential coil (primary side coil) 23 High potential coil (secondary side coil) 24 First inner end 25 First outer end 26 First spiral part 27 Second inner end 28 Second outer end 29 Second spiral part 31 First low potential wiring 32 Second low potential wiring 33 First high potential wiring 34 Second high potential wiring 41 Semiconductor chip 42 First main surface 43 Second Main Surface 44A~44D Chip sidewall 45. First Functional Device 51 Insulating layer 52 Insulation main surface 53A~53D Insulating sidewall 55. Bottom insulating layer 56. Top insulating layer 57 Interlayer insulating layer 58 First insulating layer 59 Second insulating layer 60 Second Functional Device 61 Seal conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Sea via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-voltage connection wiring 73 Pull-out wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrodes 77 Circuit board plug electrodes 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrodes 81 High-potential connection wiring 82 Pad plug electrodes 85 Dummy Patterns 86 High-Potential Dummy Pattern 87. First High-Potential Dummy Pattern 88. Second High-Potential Dummy Pattern 89 First area 90 Second area 91 Third area 92 First connection section 93 Pattern 1 94 Pattern 2 95 Pattern 3 96 First outer line 97 Second outer perimeter line 98 First intermediate line 99 First connection line 100 Slit 130 Separation structure 140 Inorganic insulation layer 141 First inorganic insulation layer 142 Second inorganic insulation layer 143 Low-potential pad opening 144 High-potential pad opening 145 Organic insulation layer 146 First part 147 Second part 148 Low-potential terminal opening 149 High-potential terminal opening 200 Signal transmission device 200p Primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmission circuit (pulse generator) 212, 213 Buffer 220 Driver chip (second chip) 221, 222 Buffer 223 Pulse reception circuit (RS flip-flop) 224 Driver 230 Transformer chip (third chip) 230a First wiring layer (lower layer) 230b Second wiring layer (upper layer) 231, 232 Transformer 231p, 232p Primary side coil 231s, 232s Secondary side coil 300 Transformer chip 301 First transformer 302 Second transformer 303 Third transformer 304 Fourth transformer 305 First guard ring 306 Second guard ring 400 Insulation switch 400p Primary circuit system ​​410 Primary circuit 411, 412 Pulse generation circuit 413 Oscillator Circuit 420 Secondary circuit 421 Switch drive circuit 421X discharge circuit 421Y Voltage Control Circuit 422 Switch Circuit 430 Isolation Circuit 431, 432, 433, 434 transformers 431p, 432p, 433p, 434p Primary coil 431s, 432s, 433s, 434s Secondary coil a1~a8 Pads (corresponding to the first current supply pads) b1~b8 Pads (corresponding to the first voltage measurement pads) c1~c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads A Electronic equipment C0, C1, C2, C3, C4, C5~C8, Cg Capacitors CP1, CP2 Boost Circuit D0, D1, D2, D3, D4, D5 diodes L1p, L2p primary coil L1s, L2s, L3s, L4s secondary coils M1, M1a, M1b transistors N1, N2 transistors nd common node P1, P2 transistors R0, R1, R2, R3, R4~R6, Rg resistance REC1, REC2 rectifier circuit T1, T2, T3, T4, T5 External terminals T21, T22, T23, T24, T25, T26 External terminals X 1st direction X1 Controller X21, X22, X23 internal terminals Y Second direction Y1 Zener diode Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 Via ZL1, ZL2 load

Claims

1. A switch circuit connected between the first node and the second node and configured to be turned on / off by a switch drive signal, A first transformer and a second transformer are configured such that a first primary coil and a second primary coil are connected in parallel between the power supply terminal and the ground terminal, and a first secondary coil and a second secondary coil are connected in series with each other. A first pulse generation circuit and a second pulse generation circuit are configured to pulse-drive the first primary coil and the second primary coil, respectively, in response to an input pulse. A switch drive circuit configured to generate the switch drive signal by receiving the induced voltage generated in the first secondary coil and the second secondary coil, respectively, An insulated switch equipped with this feature.

2. The isolation switch according to claim 1, wherein the switch circuit includes at least one output transistor whose gate is connected to the application terminal of the switch drive signal.

3. The isolation switch according to claim 2, wherein the output transistor is a GaN device or a SiC device.

4. The isolation switch according to claim 2, wherein the switch drive circuit is configured to generate the switch drive signal by rectifying the sum of the first induced voltage generated in the first secondary coil and the second induced voltage generated in the second secondary coil.

5. The isolation switch according to claim 4, wherein the first pulse generation circuit and the second pulse generation circuit are configured to perform pulse driving on the first primary coil and the second primary coil, respectively, when the input pulse is at a first logic level, and to stop the pulse driving on the first primary coil and the second primary coil, respectively, when the input pulse is at a second logic level.

6. The isolation switch according to claim 2, wherein the switch drive circuit includes a first rectifier circuit configured to rectify a first induced voltage generated in the first secondary coil to generate a first rectified voltage, a second rectifier circuit configured to rectify the sum of the first rectified voltage and a second induced voltage generated in the second secondary coil to generate a second rectified voltage, and a transistor configured to conduct / block the connection between the application terminal of the second rectified voltage and the application terminal of the switch drive signal according to the difference voltage between the first rectified voltage and the second rectified voltage.

7. The isolation switch according to claim 6, wherein the first rectifier circuit includes a first diode configured to be connected between the application terminal of the first induced voltage and the application terminal of the first rectified voltage, and a first capacitor configured to be connected between the application terminal of the first rectified voltage and the second node, and the second rectifier circuit includes a second diode configured to be connected between the application terminal of the second induced voltage and the application terminal of the second rectified voltage.

8. The isolation switch according to claim 7, wherein the second rectifier circuit further includes a second capacitor configured to be connected between the application terminal of the second rectified voltage and the second node.

9. The first pulse generation circuit is configured to pulse drive the first primary coil whether the input pulse is at a first logic level or a second logic level. The isolation switch according to claim 6, wherein the second pulse generation circuit is configured to pulse drive the second primary coil when the input pulse is at the first logic level, and to stop pulse driving the second primary coil when the input pulse is at the second logic level.

10. The insulated switch according to claim 2, wherein the switch drive circuit includes a discharge circuit configured to discharge the switch drive signal.

11. The isolation switch according to claim 10, wherein the discharge circuit includes a discharge resistor configured to be connected between the application terminal of the switch drive signal and the second node.

12. The isolation switch according to claim 6, wherein the switch drive circuit includes a discharge switch configured to be connected between the application terminal of the switch drive signal and the second node, and a controller configured to drive the discharge switch in accordance with the second induced voltage.

13. The isolation switch according to claim 12, wherein the controller operates using the first rectified voltage or the switch drive signal as a power source.

14. A third transformer including a third primary coil and a third secondary coil, A fourth transformer including a fourth primary coil and a fourth secondary coil, Furthermore, The first pulse generation circuit simultaneously pulse-drives the first primary coil and the third primary coil, The second pulse generation circuit simultaneously pulses the second primary coil and the fourth primary coil, The isolation switch according to claim 2, wherein the switch drive circuit includes: a first boost circuit configured to generate a first boost voltage from a first induced voltage generated in the first secondary coil and a third induced voltage generated in the third secondary coil; a first rectifier circuit configured to generate a first rectified voltage by rectifying the first boost voltage; a second boost circuit configured to generate a second boost voltage from a second induced voltage generated in the second secondary coil and a fourth induced voltage generated in the fourth secondary coil; a second rectifier circuit configured to generate a second rectified voltage by rectifying the sum of the first rectified voltage and the second boost voltage; and a transistor configured to conduct / block the connection between the application terminal of the second rectified voltage and the application terminal of the switch drive signal according to the difference voltage between the first rectified voltage and the second rectified voltage.

15. The isolation switch according to claim 2, wherein the switch circuit includes a first output transistor and a second output transistor as output transistors, each having its gate connected to the application terminal of the switch drive signal and its source connected to a common node.

16. The isolated switch according to any one of claims 1 to 15, wherein the switch drive circuit includes a voltage control circuit configured to stabilize the switch drive signal.

17. The isolation switch according to claim 16, wherein the voltage control circuit includes a Zener diode configured to be connected between the application terminal of the switch drive signal and the reference potential terminal.

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