Unidirectional hybrid switching circuit

Abstract

A unidirectional hybrid switch. At least one instance is a method of operating a hybrid switch, the method comprising: sensing a voltage across an upper terminal and a lower terminal of the hybrid switch, the hybrid switch being forward biased when the upper terminal has a higher voltage, and the hybrid switch being reverse biased when the lower terminal has a higher voltage; when the hybrid switch is forward biased, selectively conducting a forward current from the upper terminal to the lower terminal by sharing the forward current between a FET switch and a BJT switch, the selective conducting being performed when a control terminal is asserted; and when the hybrid switch is reverse biased, non-selectively conducting a reverse current from the lower terminal to the upper terminal.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of U.S. Application No. 18 / 530,478, filed December 6, 2023, entitled “Unidirectional Hybrid Switch Circuit,” which is incorporated herein by reference in its entirety as repeated below. Technical Field

[0003] This disclosure relates to electrically controlled switches, and more specifically, to hybrid switches comprising bidirectional double-base bipolar junction transistors (“BDBBJT”). Background Technology

[0004] Many electronic systems use high voltage and current. These systems are used in a wide range of applications, from electric vehicles to consumer appliances. For example, in some electric vehicles, approximately 1200 volts can be used to drive the electric motor.

[0005] During the operation of such electrical systems, it may be necessary to disconnect or decouple the load circuit from the high-voltage power supply. To achieve this, an electrically controlled switch can be used. In response to an assertion of a switching signal, the electrically controlled switch can couple the power supply to the load circuit. And in response to a cancellation assertion of the switching signal, the electrically controlled switch can decouple the load from the power supply. Summary of the Invention

[0006] One example is a method of operating a hybrid switch, the method comprising: sensing a voltage across an upper terminal and a lower terminal of the hybrid switch, the hybrid switch being forward biased when the upper terminal has a higher voltage and the hybrid switch being reverse biased when the lower terminal has a higher voltage; when the hybrid switch is forward biased, selectively conducting a forward current from the upper terminal to the lower terminal by sharing a forward current between a FET switch and a BJT switch, the selective conduction being performed when a control terminal is asserted; and when the hybrid switch is reverse biased, non-selectively conducting a reverse current from the lower terminal to the upper terminal.

[0007] In the example method, conducting the reverse current may further include: initially conducting the reverse current through a first diode; and then conducting the reverse current through the BJT switch. Conducting the reverse current may further include sharing the reverse current between the BJT switch and the FET switch. The first diode may be the body diode of the FET switch. The first diode may be a discrete diode. The first diode may be a silicon carbide diode having an anode coupled to the lower terminal and a cathode coupled to the upper terminal.

[0008] In the example method, selectively conducting the forward current may further include, in response to an assertion at the control terminal, conducting the forward current through the FET switch; and then conducting a first portion of the forward current through the FET switch and a second portion through the BJT switch. Selectively conducting the forward current may further include, in response to a cancellation assertion at the control terminal, deactivating the BJT switch and conducting the forward current through the FET switch; and then deactivating the FET switch.

[0009] The example method may further include at least one selected from the group consisting of: the FET switch comprising a plurality of FETs coupled in parallel; and the BJT switch comprising a plurality of BJTs coupled in parallel.

[0010] Another example is a hybrid switch comprising: an upper terminal, a lower terminal, and a control terminal; a BJT defining an upper base, a lower base, an upper collector-emitter junction coupled to the upper terminal, and a lower collector-emitter junction; a lower cascode FET defining a drain coupled to the lower collector-emitter junction, a source coupled to the lower terminal, and a gate coupled to the lower terminal; a main FET defining a drain coupled to the upper terminal, a source coupled to the lower terminal, and a gate coupled to the lower terminal; a diode having an anode coupled to the lower terminal and a cathode coupled to the upper terminal; and a driver coupled to the upper terminal, the lower terminal, the control terminal, the upper base, the lower base, the gate of the lower cascode FET, and the gate of the main FET. The driver can be configured to: sense an applied voltage across the upper terminal and the lower terminal; arrange the BJT and main FET to prevent current from flowing through the hybrid switch when the applied voltage is corrected at the upper terminal and the control terminal is de-asserted; allow forward current to flow from the upper terminal to the lower terminal when the applied voltage is corrected at the upper terminal and the control terminal is asserted, wherein the forward current is shared between the main FET and the BJT; and allow reverse current to flow through the hybrid switch when the applied voltage is corrected at the lower terminal.

[0011] In the example hybrid switch, when the driver enables the reverse current to flow, the driver can be configured to: allow the reverse current to initially flow through the diode; and then arrange the BJT such that the reverse current flows through the BJT.

[0012] In the example hybrid switch, when the driver enables the reverse current to flow, the driver may be further configured to arrange the main FET such that the reverse current is shared between the BJT and the main FET.

[0013] In the example hybrid switch, the diode may be the body diode of the main FET.

[0014] In the example hybrid switch, the diode may be a discrete diode that is different from the main FET.

[0015] In the example hybrid switch, the diode may be a silicon carbide diode.

[0016] In the example hybrid switch, when the driver enables the forward current to flow, the driver can be configured to: assert the gate of the main FET; and then arrange the BJT to be turned on in an active-on mode. When the applied voltage is corrected on the upper terminal and the control terminal becomes de-asserted, the driver can be configured to: de-asserte the BJT while maintaining the assertion state of the gate of the main FET; and then de-asserte the gate of the main FET to de-asserte the main FET.

[0017] The example hybrid switch may further include: an upper cascode FET defining a drain coupled to the upper terminal, a source coupled to the upper collector-emitter, and a gate coupled to the driver; the driver being coupled to the lower collector-emitter; and wherein when the applied voltage is corrected on the upper terminal and the control terminal changes from being asserted to being deasserted, the driver may be further configured to: de-enable the upper cascode FET; and drive a reverse recovery bias voltage to the lower collector-emitter. Attached Figure Description

[0018] To describe the exemplary embodiments in detail, reference will now be made to the accompanying drawings, in which:

[0019] Figure 1 It is a block diagram of a hybrid switch according to at least some embodiments;

[0020] Figure 2 This is a schematic diagram of a FET switch according to at least some embodiments;

[0021] Figure 3 A schematic diagram of a BJT switch according to at least some embodiments is shown;

[0022] Figures 4A to 4F A bidirectional double-base bipolar junction transistor with an example external electrical connection in a simplified form is shown to illustrate several operating states;

[0023] Figure 5 A block diagram of a driver according to at least some embodiments is shown;

[0024] Figure 6 A timing diagram is shown that is associated with the operation of the example hybrid switch according to at least some embodiments;

[0025] Figure 7 A schematic diagram of a BJT switch according to at least some embodiments; and

[0026] Figure 8 The method is illustrated according to at least some embodiments.

[0027] Many electrical connections in the figures are shown as direct couplings without intermediate devices, but this is not explicitly stated in the following description. However, this paragraph serves as the basis for the antecedent in the claims for referring to any electrical connection as a "direct coupling" of the electrical connection shown in the figures without intermediate devices.

[0028] definition

[0029] Various terms are used to refer to specific system components. Different companies may use different names to refer to components—this document does not intend to distinguish between components with different names but the same function. In the following discussion and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as meaning "including but not limited to...". Furthermore, the term "coupled" is intended to mean either an indirect or direct connection. Thus, if a first device is coupled to a second device, that connection can be either a direct connection or an indirect connection via other devices and connections.

[0030] As used herein, “a” and “the” refer to both the singular and plural references, unless the context clearly indicates otherwise. For example, “processor” programmed to perform various functions refers to one processor programmed to perform each and every function, or more than one processor programmed to perform each of the various functions. It should be clear that the initial reference to “a [referring to an object]” and subsequent references to “the [referring to an object]” for pre-foundational purposes should not preclude the possibility that the referenced object may be plural.

[0031] Regarding electrical devices (whether standalone or as part of an integrated circuit), the terms "input" and "output" refer to electrical connections to the device and should not be interpreted as verbs requiring action. For example, a differential amplifier (e.g., an operational amplifier) ​​may have a first differential input and a second differential input, and these "inputs" define electrical connections to the operational amplifier and should not be understood as requiring signals to be input to the operational amplifier.

[0032] An "assertion" should mean creating or maintaining a first predetermined state of a Boolean signal. Depending on the circuit designer's decision, a Boolean signal can be asserted as high or having a higher voltage, and a Boolean signal can be asserted as low or having a lower voltage. Similarly, a "cancel assertion" should mean creating or maintaining a second predetermined state of a Boolean signal, which is the opposite of the assertion state.

[0033] “FET” should mean field-effect transistor, such as junction gate FET (JFET) or metal-oxide-semiconductor field-effect transistor (MOSFET).

[0034] "BJT" should mean bipolar junction transistor, such as bidirectional double-base bipolar junction transistor.

[0035] The term "closing" in relation to an electronically controlled switch (such as a FET) should mean turning the switch on. For example, closing a FET used as an electronically controlled switch could mean driving the FET to a fully on state.

[0036] "Off" in the context of an electronically controlled switch (such as a FET) should mean that the electronically controlled switch is not turned on.

[0037] "Bidirectional double-base bipolar junction transistor" should mean a junction transistor having a base and collector-emitter junction on a first face or side of the body region and a base and collector-emitter junction on a second face or side of the body region. The base and collector-emitter junction on the first side are different from those on the second side.

[0038] The “collector-emitter” of a bipolar junction transistor (BJT) should refer to the region of the BJT through which the main load current flows. For the purposes of this specification and claims, the collector-emitter is specified as independent of the underlying device physical characteristics within the BJT. For example, in a double-sided double-base PNP transistor, the main load current can flow from the upper P-type region through the body N-type region and then out of the lower P-type region, and when used in this way, the upper and lower P-type regions are considered as the collector-emitter. However, in other cases, such as in co-pending and co-assigned U.S. Application 18 / 483,939, filed October 10, 2023, entitled “Methods and Systems of Operating a PNP Bi-Directional Double-Base Bipolar Junction Transistor,” the primary load current can flow from the upper N-type region through the body N-type region and then through the lower N-type region, and when used in this way, the upper and lower N-type regions are treated as collector-emitter junctions.

[0039] The “base” of a bipolar junction transistor (BJT) should mean the region through which control current flows in the BJT, and the control current is different from the main load current. For the purposes of this specification and claims, the base is specified as independent of the physical characteristics of the underlying device within the BJT. For example, in a double-sided double-base PNP transistor, control current may flow into either the upper N-type region or the lower N-type region, and when used in this way, both the upper and lower N-type regions are considered the base. However, in other cases, such as those described in the aforementioned co-pending and co-assigned U.S. Application 18 / 483,939, control current may flow into either the upper P-type region or the lower P-type region, and when used in this way, both the upper and lower P-type regions are considered the base.

[0040] The term "upper" in relation to components (e.g., upper terminal, upper collector-emitter, upper base) should not be interpreted as implying the position of the listed component relative to gravity. "Upper" can be derived from the position of the device in the example diagram.

[0041] The term "lower" in relation to components (e.g., lower terminal, lower collector-emitter, lower base) should not be interpreted as implying the position of the listed component relative to gravity. "Lower" can be derived from the position of the device in the example diagram.

[0042] "Controller" should be used individually or in combination to refer to individual circuit components, application-specific integrated circuits (ASICs), microcontrollers with control software, reduced instruction set computers (RISCs) with control software, digital signal processors (DSPs), processors with control software, programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), or programmable system-on-a-chip (PSOCs) configured to read inputs and drive outputs in response to inputs. Detailed Implementation

[0043] The following discussion relates to various embodiments of the invention. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure (including the claims). Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended only to illustrate that embodiment and is not intended to imply that the scope of this disclosure (including the claims) is limited to that embodiment.

[0044] In various applications, high-voltage and high-current switches may be required. For example, in some electric vehicles, it is common to couple load circuits to a high-voltage supply (e.g., 1200 V) and decouple the load circuits from the high-voltage supply. Silicon carbide (SiC) switches are used in many systems. To handle large currents, many SiC switches can be coupled in parallel, so that each SiC switch handles only a portion of the total current. However, using multiple SiC switches can result in large die areas and high costs. Furthermore, when multiple dies are connected in parallel, current sharing during load transients becomes difficult to achieve. This leads to slower switching on and off, and therefore higher switching losses.

[0045] To reduce the number of SiC switches used, various examples involve a hybrid switch comprising one or more large bandgap switches (e.g., SiC, GaN), one or more bidirectional double-base bipolar junction transistors (“BDB BJTs”), and in some cases, one or more discrete diodes. Adding BDB BJTs and discrete diodes allows for fewer total switches to be used for the design's rated current. BDB BJTs offer low conduction losses during the “on” state and can conduct large currents at a lower cost per ampere than SiC and gallium nitride (GaN) devices. However, BDB BJTs switch slower and therefore have higher switching losses compared to large bandgap devices. On the other hand, SiC devices can switch faster, but are more expensive to conduct the same current. The hybrid switch examples discussed herein achieve at least partially the benefits of both SiC / GaN devices and BDB BJTs by using SiC / GaN devices to handle the switch, resulting in low switching losses, and using BDB BJT devices to conduct most of the current during the “on” state, resulting in low conduction losses.

[0046] The various examples described herein provide techniques for operating hybrid switches to achieve unidirectional operation. That is, the hybrid switch selectively conducts current in one direction between its two terminals, rather than selectively allowing current to flow in the opposite direction. In other words, when the hybrid switch is reverse-biased, it non-selectively conducts reverse current. More specifically, the example hybrid switch senses the voltage across the hybrid switch between its upper and lower terminals, where forward bias is defined as a higher voltage at the upper terminal and reverse bias is defined as a higher voltage at the lower terminal. When forward-biased and when the control terminal is asserted, the example hybrid switch conducts forward current from the upper terminal to the lower terminal by sharing forward current between the FET switch and the BJT switch. When forward-biased but when the control terminal is deasserted, the hybrid switch blocks current flow. When the hybrid switch is reverse-biased, and regardless of or independent of the state of the control terminal, the example hybrid switch conducts reverse current from the lower terminal to the upper terminal. Initially, the reverse current is carried by one or more diodes. In one example, in steady state, the reverse current is carried by the BJT switch. In another instance, and again in steady state, the reverse current is shared between the BJT switch and the FET switch.

[0047] Figure 1 A block diagram of an example hybrid switch 100 is shown. Specifically, the example hybrid switch 100 defines an upper terminal 102, a lower terminal 104, and a control terminal 106. Internally, the example hybrid switch includes a driver 108, a FET switch 110, a BJT switch 112, and in some cases, a diode 114. Driver 108 defines the control terminal 106 and is coupled to the FET switch 110, as shown by connection 122, and to the BJT switch 112, as shown by connection 124. Driver 108 controls the on-state of the FET switch 110 and the BJT switch 112 by arranging voltage / current across connections 122 and 124. The FET switch 110 and the BJT switch 112 are electrically coupled in parallel, such that the forward current from the upper terminal 102 to the lower terminal 104 can be selectively shared between the FET switch 110 and the BJT switch 112. Diode 114 has an anode coupled to lower terminal 104 and a cathode coupled to upper terminal 102, and thus reverse current from lower terminal 104 to upper terminal 102 can first flow through diode 114, and then driver 108 can arrange hybrid switch 100 to conduct reverse current through FET switch 110, or share reverse current between FET switch 110 and BJT switch 112.

[0048] One example of the hybrid switch 100 may include a single FET switch 110, a single BJT switch 112, and a single diode 114 (if present). Another example of the hybrid switch 100 may have one or more FET switches 110, one or more BJT switches 112, and one or more diodes 114, such as... Figure 1 The following description is illustrated by a “stacked” arrangement of the respective FET switches 110, BJT switches 112, and diodes 114. When multiple FET switches 110 are present, they are connected in parallel to share the load current (forward or reverse) flowing through a portion of the FET branch 116 of the hybrid switch 100. Similarly, when multiple BJT switches 112 are present, they are connected in parallel to share the load current (forward or reverse) flowing through a portion of the BJT branch 118 of the hybrid switch 100. If the hybrid switch 100 incorporates diodes 114, the diodes are connected in parallel to share the reverse current initially flowing through a portion of the diode branch 120. To avoid overcomplicating the specification, the following discussion assumes a single FET switch 110, a single BJT switch 112, and a single diode 114. However, those skilled in the art will understand, with the benefit of this disclosure, that multiple switches and / or diodes may be present depending on the designed current-carrying capacity of any particular hybrid switch.

[0049] Figure 2 A schematic diagram of example FET switch 110 is shown. In some examples, FET switch 110 includes a FET constructed on a SiC substrate; hereinafter, only SiC FET 200 is shown. Example SiC FET 200 is an N-channel device defining a drain 202 coupled to an upper terminal 102, a source 204 coupled to a lower terminal 104, and a gate 206 coupled to a driver 108. Example SiC FET 200 also includes a body diode 208 defining an anode coupled to the source 204 and a cathode coupled to the drain 202. The presence of body diode 208 eliminates the need for implementing diode 114. However, if the current carrying capacity of body diode 208 is too low and / or if the heat dissipation capacity of body diode 208 is too low, then example hybrid switch may implement a separate diode 114. Furthermore, if SiC FET 200 is implemented as an insulated-gate device, in which case there is no body diode, then example hybrid switch may implement diode 114.

[0050] The gate 206 of the SiC FET 200 is coupled to the driver 108. When the gate 206 is asserted (e.g., driven with a high voltage relative to the source 204), the SiC FET 200 becomes on. When the hybrid switch 100 is forward biased, the SiC FET 200 thus carries at least a portion of the forward current. As discussed in more detail below, because the SiC FET 200 can have a faster switching time than the BJT switch 112, initially, the SiC FET 200 can carry all the forward current, and then, when the BJT switch 112 becomes on, the forward current can be shared with the BJT switch 112. While still forward biased but when the hybrid switch 100 will become off, the BJT switch 112 can be turned off, thereby forcing reverse current to flow only through the FET switch 110, and then turning off the FET switch 110.

[0051] When the hybrid switch 100 is reverse biased, the body diode 208 of the SiC FET 200 initially carries at least a portion of the reverse current. When the hybrid switch 100 is reverse biased, the driver 108 can also assert the gate 206 of the SiC FET 200 to allow a portion of the reverse current to flow through the SiC FET 200 from source to drain. However, the hybrid switch 100 non-selectively conducts the reverse current, and therefore the termination of the reverse current is based on the voltage across the hybrid switch 100 decreasing to 0. Therefore, the switching speed advantage of the SiC FET 200 may not be necessary in terms of turning off the reverse current. In other words, in some cases, the driver 108 avoids asserting the gate 206 of the SiC FET 200 during the period when the hybrid switch 100 is reverse biased.

[0052] Figure 2 The SiC FET 200 is presented based on FET switch 110; however, any other suitable wide-bandgap FET can be used, such as a FET constructed on GaN, and therefore the description based on SiC FET 200 should not be considered limiting. The specification now turns to a more detailed discussion of BJT switch 112.

[0053] Figure 3A schematic diagram of example BJT switch 112 is shown. Specifically, example BJT switch 112 includes BDB-BJT 300. Example BDB-BJT 300 defines an upper base 302, a lower base 304, an upper collector-emitter 306, and a lower collector-emitter 308. Example BJT switch 112 further includes a lower cascode FET 310, which defines a drain 312 coupled to the lower collector-emitter 308, a source 314 coupled to the lower terminal 104, a gate 316 coupled to the driver 108, and a body diode 318. Finally, example BJT switch 112 includes an upper cascode FET 320, which defines a drain 322 coupled to the upper collector-emitter 306, a source 324 coupled to the upper terminal 102, a gate 326 coupled to the driver 108, and a body diode 328.

[0054] The driver 108 is coupled to the BJT switch 112 via multiple electrical connections. Figure 3 In this example, the electrical connections to driver 108 include connections to the following: the gate 326 of the upper cascode FET 320; the upper collector-emitter 306; the upper base 302; the lower base 304; the lower collector-emitter 308; and the gate 316 of the lower cascode FET 310. To describe when each of these connections to driver 108 may be active, the specification turns to an example operation of the BDB BJT 300.

[0055] Figures 4A to 4F A partial cross-sectional view of a PNP-constructed instance BDB BJT 300 is shown in simplified form to illustrate several operating states. Specifically, Figures 4A to 4F This demonstrates six example states of a BDBBJT 300 arranged to carry the main load current across or through the N-type region. These six states are: passive shutdown (…). Figure 4A Active shutdown Figure 4B Passive connection ( Figure 4C Active connection ( ); Figure 4D Pre-shutdown Figure 4E ); and reverse recovery ( Figure 4F ).exist Figures 4A to 4F In this example, it is assumed that the hybrid switch 100 is forward biased (i.e., has a positive polarity associated with the upper terminal 102 relative to the lower terminal 104).

[0056] Figure 4B This demonstrates the passive shutdown configuration of the BDB BJT 300 example. Figure 4AThe upper terminal 102 and lower terminal 104 are shown. The BDB BJT 300 is electrically residing between the upper terminal 102 and the lower terminal 104. The upper base 302 is electrically floating via driver 108. The upper collector-emitter 306 is coupled to the upper terminal 102, for example, via an upper cascode FET 320 or its body diode 328. The lower base 304 is coupled to the lower terminal 104 via driver 108. The lower collector-emitter 308 is electrically floating, for example, disconnected via a lower cascode FET 310 and its body diode 318 is not conducting due to the applied voltage. Figure 4A In this arrangement, the BDB BJT 300 may have a breakdown voltage of 600 V or greater, and in some cases approximately 1200 V. Therefore, due to the blocking effect performed by the PN junction formed between the lower base 304 and the upper collector-emitter 306, no significant current flows through the BDB BJT 300. Figure 4A This state is called "passive shutdown" because the electrical arrangement can be implemented using purely passive components (such as diodes and resistors), and therefore the driver 108 does not need to have operating power to implement it. Figure 4A The arrangement is as follows. In the passive turn-off arrangement, the BDB BJT 300 blocks voltage and current, and therefore, the cascode FET 310 may experience a relatively small drain-to-source voltage when not in operation (e.g., 30 V or less for a 1200 V applied across the upper terminal 102 and the lower terminal 104).

[0057] Figure 4B This demonstrates the active shutdown arrangement of Example BDB BJT 300. Specifically, the upper base 302 is electrically floating via driver 108. The upper collector-emitter 306 is coupled to the upper terminal 102, for example, via an upper cascode FET 320 or its body diode 328. The lower base 304 is coupled to the lower terminal 104 via driver 108 via voltage source 400. The lower collector-emitter 308 is electrically floating, for example, turned off via a lower cascode FET 310 and its body diode 318 is not conducting due to the applied voltage. Voltage source 400 provides a negative bias to the lower base 304 relative to the lower collector-emitter 308. Figure 4B In this arrangement, the BDB BJT300 may have a breakdown voltage of 600 volts or greater, and in some cases approximately 1200 volts. Therefore, again in the active shutdown arrangement, no significant current flows through the BDB BJT 300 due to the blocking effect performed by the PN junction formed between the lower base 304 and the upper collector-emitter 306. Figure 4B The instance state is called "active shutdown" because... Figure 4B In the electrical arrangement, the driver 108 uses operating power to implement the arrangement (e.g., powering a voltage source 400). Figure 4BIn the active shutdown configuration, the BDB BJT 300 again blocks voltage and current, and therefore, the cascode FET 310 may experience a small drain-to-source voltage (e.g., 30 V or less) when not in operation.

[0058] Figure 4C This demonstrates the passive turn-on arrangement of Example BDB BJT 300. Specifically, the upper base 302 is electrically floated via driver 108. The upper collector-emitter 306 is coupled to the upper terminal 102, for example, via an upper cascode FET 320 or its body diode 328. The lower base 304 is electrically floated via driver 108. The lower collector-emitter 308 is coupled to the lower terminal 104 via a lower cascode FET 310. Figure 4C The voltage drop across the BDB BJT 300 in the arrangement is based on the substrate resistance (e.g., about 2 ohms for a 260 μm thick substrate). Figure 4C The instance state is called "passive ON" because the ON state does not involve injecting charge carriers to reduce the forward voltage drop V. CEON Charge carrier injection in Figure 4D The active connection setup is shown.

[0059] Figure 4D This example demonstrates an active-on arrangement of the BDB BJT 300, where the hybrid switch 100 is still forward biased. Specifically, the upper base 302 is coupled to the upper terminal 102 via a driver 108 through a voltage source 402. The upper collector-emitter 306 is coupled to the upper terminal 102, for example, via an upper cascode FET 320 or its body diode 328. The lower base 304 is electrically floated via the driver 108. The lower collector-emitter 308 is coupled to the lower terminal 104 via a lower cascode FET 310. The voltage source 402 provides a positive bias to the upper base 302 relative to the upper collector-emitter 306, and the voltage source 402 can provide any suitable bias voltage (e.g., 0.2 V to 2 V). Voltage source 402 injects charge carriers into the bulk substrate across the PN junction. For a main current flow of 30 amps (A), this will result in a forward voltage drop V measured from the upper collector-emitter 306 to the lower collector-emitter 308, compared to approximately 10 to 20 V without charge carrier injection (e.g., a passive-on arrangement). CEON It decreased to about 0.2 V.

[0060] Figure 4EThis demonstrates the pre-shutdown arrangement of Example BDB BJT 300. Specifically, the upper base 302 is coupled to the upper terminal 102 via driver 108. The upper collector-emitter 306 is coupled to the upper terminal 102, for example, via an upper cascode FET 320 or its body diode 328. The lower base 304 is coupled to the lower terminal 104 via driver 108. The lower collector-emitter 308 is coupled to the lower terminal 104 via a lower cascode FET 310. An equivalent arrangement could omit the coupling from the upper base 302 to the upper terminal 102. Figure 4E In the pre-shutdown arrangement, the BDB BJT 300 presents a resistance of approximately 2 ohms across terminals 102 and 104. Therefore, for the 30 A main load current of Example 30, Figure 4E In the pre-shutdown arrangement, there is a voltage drop of approximately 60 V from the upper terminal 102 to the lower terminal 104.

[0061] Figure 4F This demonstrates the reverse recovery arrangement of the example BDB BJT 300. Specifically, the upper collector-emitter 306 is coupled to the upper terminal 102. The lower base 304 is coupled to the lower terminal via a driver 108. The lower collector-emitter 308 is coupled to the lower terminal 104 via a voltage source 404 and a driver 108. The upper base 302 can be electrically floated via the driver 108. Figure 4F The reverse recovery arrangement can be used to shorten the diode reverse recovery time after the conduction period from the upper collector-emitter 306 to the lower collector-emitter 308 in the PN junction formed by the lower base 304 and the N-type substrate. This is because the PN junction formed by the lower base 304 becomes the main current / voltage blocking mechanism of the BDB BJT 300 when forward biased. That is, the positive voltage between the lower collector-emitter 308 and the lower base 304 pinches off the N+ / P region formed between the lower collector-emitter 308 and the lower base 304, thereby reducing the reverse recovery current between the upper collector-emitter 306 and the lower base 304.

[0062] Regarding the transition of the hybrid switch 100 from non-conducting to conducting, example BDB BJT 300 can be arranged to... Figure 4A Passive shutdown arrangement or Figure 4B The active shutdown arrangement is directly transformed into Figure 4D An active connection arrangement without the need for intermediate arrangements or states. However, Figure 4C Passive switching arrangements can find applications in some situations. Regarding the transition of the hybrid switch 100 from conducting to non-conducting, example BDB BJT 300 can be seen from... Figure 4D The active connection arrangement is directly transformed into Figure 4B Active shutdown arrangement or Figure 4AThe passive shutdown configuration can be implemented without the need for intermediate configurations or states. In other cases, the BDB BJT300 instance can shut down from [a specific location] within a predetermined time period (e.g., 400 nanoseconds or less). Figure 4D The active connection layout is transformed into Figure 4E The reverse recovery arrangement is then switched to a passive or active shutdown arrangement. However, Figure 4C Passive connection arrangement and Figure 4E Pre-shutdown arrangements can be useful in some situations.

[0063] Figures 4A to 4F The example is for a hybrid switch 100 that is forward biased. However, the example BDB BJT 300 is a symmetrical device, and since it is understood how the current through the BDB BJT is controlled when the hybrid switch 100 is forward biased, the current control when the hybrid switch 100 is reverse biased (i.e., having a more positive polarity relative to the upper terminal 102 and associated with the lower terminal 104) can be directly deduced by analogy. Furthermore, since it is understood that there are various operating states in which the main load current flows through the N-type region of the PNP configuration, those skilled in the art can deduce equivalent arrangements of the PNP configuration and NPN arrangement in which the main load current flows through the P-type region.

[0064] Return again Figure 1 In some instances, diode 114 has a SiC construction. The SiC construction of diode 114 allows it to quickly turn on when the hybrid switch is reverse biased. In other cases, specifically when the FET switch 110 implements a body diode, diode 114 may have a silicon construction to reduce cost. That is, when the hybrid switch 100 is reverse biased, reverse current can initially flow through the body diode of the FET branch 116, and then the current can be shared when the silicon-constructed diode 114 turns on.

[0065] Figure 5 A block diagram of example driver 108 is shown. Specifically, example driver 108 includes isolation circuitry 500, controller 502, driver circuitry 504, comparator 506, transformer 508, and AC-DC converter 510. The primary winding of transformer 508 is coupled to an input AC voltage. Transformer 508 is configured to generate an isolated AC voltage on its secondary winding based on the input AC voltage. In some embodiments, transformer 508 may include a core made of ferrous material and / or one or more taps on the secondary winding. Although in Figure 5 In this embodiment, a single transformer is depicted, but in other instances, multiple transformers may be used to provide different AC voltages to the AC-DC converter 510.

[0066] AC-DC converter 510 is configured to generate bus voltage 512. In some instances, bus voltage 512 may include multiple voltage levels (e.g., 3.3 V, 5 V, 12 V, etc.) for controller 502 to generate voltages for each of the control signals 514 applied to FET switch 110 via connection 122. Similarly, bus voltage may be used by driver circuitry 504 to generate voltages for each of the control signals 524 applied to BJT switch 112 via connection 124. AC-DC converter 510 may be implemented using rectifier circuitry, one or more capacitors, one or more power converter circuitry (e.g., buck converter), or any other suitable circuit components or sub-circuits.

[0067] The driver 108 can be in a different electrical domain than the circuit that generates the switching signal 516 applied to the control terminal 106. To account for this difference in electrical domains, an isolation circuit 500 is employed. The isolation circuit 500 is configured to generate a signal 518 based on the switching signal 516, such that the signal 518 is in a different electrical domain than the switching signal 516. The isolation circuit 500 can use an optocoupler, a capacitive isolation device, or any other circuit configured to switch the signal from one electrical domain to another.

[0068] Comparator 506 has a first input coupled to upper terminal 102, a second input coupled to lower terminal 104, and defines a comparison output. Comparator 506 is configured to generate a comparison signal 520 on the comparison output based on the corresponding voltage levels of terminals 102 and 104. The voltage level of comparison signal 520 indicates which of terminals 102 or 104 has a larger voltage, and thus indicates whether the hybrid switch 100 is forward-biased or reverse-biased. For example, an assertion state of comparison signal 520 may indicate forward bias, while a non-assertion state of comparison signal 520 may indicate reverse bias. Comparator 506 may be implemented using differential amplifier circuitry, a Schmitt trigger circuit, or any other suitable circuitry configured to generate an output signal whose voltage level is based on a comparison of the corresponding voltage levels of at least two input signals.

[0069] The controller 502 is configured to generate a signal 522 applied to the driver circuit 504 and a control signal 514 applied to the FET switch 110. In response to signal 522, the driver circuit 504 arranges the BJT switch 112 into various states, such as... Figures 4A to 4FAs described in the description. Controller 502 may be implemented using individual circuit components, application-specific integrated circuits (ASICs), microcontrollers configured to execute software or program instructions, reduced instruction set computers (RISCs), digital signal processor (DSP) circuitry, processors or processor cores configured to execute software or program instructions, programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), programmable system-on-a-chip (SoCs), or any suitable combination thereof.

[0070] Driver circuit 504 is configured to generate control signal 524 using one or more of the voltage levels contained in signal 522 and bus voltage 512. Driver circuit 504 can be used to place BJT switch 112 into various states, such as Figures 4A to 4F As described in the description. In various embodiments, the driver circuit 504 may be implemented using multiple switches, FETs, or any other suitable switching device.

[0071] Figure 6 This diagram illustrates the timing relationships between the forward-biased hybrid switch 100 and its transitions from non-conducting to conducting and from conducting to non-conducting. Specifically, Figure 6 The control signals associated with control terminal 106, the gate of FET switch 110, and BJT switch 112 are shown in the diagram. Figure 6 Further plotting the current through FET switch 110 and BJT switch 112 and the voltage drop across the hybrid switch – V CEON For ease of discussion, the control signal associated with BJT switch 112 is shown as a single representative signal asserted to be high or having a relatively high voltage; however, as per [the discussion]... Figures 4A to 4F The driver circuit 504 generates several control signals and uses these control signals to arrange the BDB BJT 300 in various on and off states.

[0072] In the example timing diagram, at time t0, control terminal 106 is asserted by an external device. In this example, control terminal 106 is asserted as high or has a high voltage. In response to the assertion of control terminal 106, the example driver 108 asserts the gate of FET switch 110. There may be a short time delay or propagation delay between the assertion of control terminal 106 and the assertion of the gate of FET switch 110, but... Figure 6 This delay is not reflected in the diagram to avoid making the figures or discussion overly complex. It is asserted that the gate of FET switch 110 turns FET switch 110 on, and therefore a forward current initially flows in FET switch 110, as shown by line 600 associated with the FET current. Therefore, the forward current flowing through FET switch 110 results in V... CEON The initial pressure drop between time t0 and t1.

[0073] After a predetermined turn-on delay “tdon”, the driver 108 arranges the BJT switch 112 to turn on, the arrangement being... Figure 6 The following is illustrated by asserting a representative control signal associated with BJT switch 112 at time t1. When BJT switch 112 turns on, the forward current is shared with BJT switch 112, as shown by line 602 associated with the BJT current. In steady state, BJT switch 112 carries most of the forward current, as shown by line 602, and FET switch 110 carries a smaller but non-zero portion of the forward current, as shown by line 600. Considering that FET switch 110 turns on faster than BJT switch 112, in some cases the predetermined turn-on delay "tdon" can be 0; however, when BJT switch 112 turns on, the forward current may initially flow only through FET switch 110, resulting in an equivalent relationship between the FET current and the BJT current, as shown in line 600. Figure 6 It is displayed in the middle.

[0074] Still referencing Figure 6 Considering the forward-biased hybrid switch 100, now consider the time t2 when the control terminal 106 is de-asserted by an external device, indicating that the hybrid switch 100 should be de-energized. In response to the de-assertion of control terminal 106, the driver 108 is designed and constructed to turn the BJT switch 112 non-energized, as demonstrated by the de-assertion of a representative control signal. There may be a short time delay or propagation delay between the de-assertion of control terminal 106 and the arrangement of various signals to de-energize the BJT switch 112, but... Figure 6 This delay is not shown to avoid making the diagrams or discussion overly complex. Therefore, when BJT switch 112 turns off, a portion of the positive current carried by BJT switch 112 slopes downwards, while simultaneously, a portion of the positive current carried by FET switch 110 slopes upwards, as illustrated by lines 600 and 602 between times t2 and t3. Example driver 108 is further designed and constructed to cancel the assertion of the gate of FET switch 112 at time t2 after a predetermined turn-off delay “tdoff”, thereby turning off hybrid switch 100.

[0075] return Figure 5Now consider the period when the hybrid switch 100 is reverse biased. Reverse current initially flows through one or more diodes, such as diode 114 associated with FET switch 110 and / or body diode 208. That is, driver 108, and specifically controller 502, does not need to take action to allow reverse current to initially flow through the diodes from lower terminal 104 to upper terminal 102. However, controller 502 receives a comparison signal 520 from comparator 506 and determines when the hybrid switch 100 is reverse biased. Once the reverse bias condition is sensed, controller 502 is designed and configured to turn on one or both of FET switch 110 and BJT switch 112. That is, in response to the comparison signal 520 indicating the reverse bias condition, in one example, controller 502 is designed and configured to command driver circuitry 504 to arrange BJT switch 112 to conduct reverse current from lower terminal 104 to upper terminal 102 (e.g., an active turn-on arrangement). Because the BJT switch 112 can have a voltage drop of approximately 0.2 V in an actively switched-on configuration, in some cases, the BJT switch 112 can carry the entire reverse current once fully turned on. In other words, the reverse current may initially flow through the diode (such as diode 114 or the body diode of FET switch 110), but because the voltage drop across the BDB BJT 300 can be driven to be lower than the forward voltage drop of the diode, the entire reverse current can flow through the BJT.

[0076] In an alternative configuration, controller 502 is designed and configured to arrange FET switch 110 to conduct reverse current from lower terminal 104 to upper terminal 102. That is, here, the reverse current initially flows again through one or more diodes, such as diode 114 and / or body diode 208. However, once controller 502 senses a reverse bias condition, controller 502 is designed and configured to turn on the instance SiC FET of FET switch 110. The drain-to-source voltage of a fully turned-on SiC FET 200 can be approximately 2.0 V, and therefore, even when SiC FET 200 110 is fully turned on, the reverse current can be shared between the diodes (e.g., diode 114 and / or body diode 208) and SiC FET 200.

[0077] In another configuration, controller 502 is designed and configured to arrange FET switch 110 and BJT switch 112 to conduct reverse current from lower terminal 104 to upper terminal 102. As previously described, the reverse current initially flows through one or more diodes, such as diode 114 and / or body diode 208. However, once controller 502 senses a reverse bias condition, controller 502 is designed and configured to turn on FET switch 110 and BJT switch 112. Because BJT switch 112 can have a voltage drop of approximately 0.2 V in an active-on configuration, once BJT switch 112 is fully turned on, the voltage drop across hybrid switch 100 is low enough that the diodes no longer participate in conducting the reverse current—the reverse current can be shared between FET switch 110 and BJT switch 112.

[0078] Figure 7 A schematic diagram of another example BJT switch 112 is shown. As previously mentioned, BJT switch 112 includes a BDB-BJT 300. However, in Figure 7 In the alternative arrangement, the upper collector-emitter 306 is directly coupled to the upper terminal 102. In other words, in Figure 7 In the alternative arrangement, the upper cascode FET is omitted. Without the upper cascode FET, implementation is not possible. Figure 4F The reverse recovery arrangement is omitted because the upper collector-emitter 306 cannot be electrically floated. Therefore, the electrical connection between the driver 108 and the lower collector-emitter 308 can be omitted, as shown. Although the example BJT switch 112 can still utilize reverse recovery after reverse current flow, the reverse recovery of the reverse current is not very important because the reverse current naturally ends when the voltage across the hybrid switch 100 decreases to 0. Therefore, the electrical connection between the driver 108 and the upper collector-emitter 306 can also be omitted. Figure 7 Examples of BJT switches in other aspects Figure 3 The same applies, and therefore, the various components will not be reintroduced here.

[0079] Figure 8An example method is illustrated. Specifically, the method begins (block 800) and includes sensing the voltage between the upper and lower terminals of a hybrid switch (block 802). For the purposes of this disclosure and the claims, the hybrid switch is considered to be forward biased when the upper terminal has a higher voltage and reverse biased when the lower terminal has a higher voltage; however, the designations of "forward" and "reverse" are arbitrarily assigned. When the hybrid switch is forward biased, the example method includes selectively conducting forward current from the upper terminal to the lower terminal by sharing forward current between the FET switch and the BJT switch, selectively conducting when the control terminal is asserted (block 804). When the hybrid switch is reverse biased, the example method includes non-selectively conducting reverse current from the lower terminal to the upper terminal (block 806). In some cases, non-selectively conducting reverse current may include: initially conducting reverse current through a first diode (block 808); and then conducting reverse current through the FET switch and / or the BJT switch (block 810). Thereafter, the method ends (block 812).

[0080] This disclosure contains references to "embodiments" or the group thereof. As used herein, an embodiment is a different implementation of an example of the disclosed concepts. References to "embodiments," "some embodiments," etc., do not necessarily refer to the same embodiment. Many embodiments are possible and are considered, including the specific disclosed embodiments as well as modifications or substitutions that fall within the spirit or scope of this disclosure.

[0081] The foregoing disclosure is intended to illustrate the principles of the disclosed concepts and various embodiments. Those skilled in the art will understand numerous variations and modifications upon fully understanding the foregoing disclosure. The appended claims are intended to be interpreted as encompassing all such variations and modifications.

Claims

1. A method for operating a hybrid switch, the method comprising: The voltage across the upper and lower terminals of the hybrid switch is sensed, wherein the hybrid switch is forward biased when the upper terminal has a higher voltage and reverse biased when the lower terminal has a higher voltage. When the hybrid switch is forward biased, the forward current is selectively conducted from the upper terminal to the lower terminal by sharing the forward current between the FET switch and the BJT switch, and the selective conduction is performed when the control terminal is asserted. and When the hybrid switch is reverse biased, it non-selectively conducts reverse current from the lower terminal to the upper terminal.

2. The method of claim 1, wherein conducting the reverse current further comprises: The reverse current is initially conducted through the first diode; And then The reverse current is conducted through the BJT switch.

3. The method of claim 2, wherein conducting the reverse current further comprises sharing the reverse current between the BJT switch and the FET switch.

4. The method of claim 2, wherein the first diode is the body diode of the FET switch.

5. The method according to claim 2, wherein the first diode is a discrete diode.

6. The method of claim 2, wherein the first diode is a silicon carbide diode having an anode coupled to the lower terminal and a cathode coupled to the upper terminal.

7. The method of claim 1, wherein selectively conducting the positive current further comprises responding to an assertion at the control terminal: The positive current is conducted through the FET switch; and then... The first portion of the positive current is conducted through the FET switch, and the second portion is conducted through the BJT switch.

8. The method of claim 7, wherein selectively conducting the positive current further comprises responding to a cancellation assertion at the control terminal: Turn off the BJT switch and conduct the positive current through the FET switch; and then Make the FET switch non-conducting.

9. The method of claim 1, further comprising at least one selected from the group consisting of: the FET switch comprising a plurality of FETs coupled in parallel; and the BJT switch comprising a plurality of BJTs coupled in parallel.

10. A hybrid switch comprising: Upper terminal, lower terminal and control terminal; BJT, which defines an upper base, a lower base, an upper collector-emitter junction coupled to the upper terminal, and a lower collector-emitter junction; A lower cascode FET, which defines a drain coupled to the lower collector-emitter, a source coupled to the lower terminal, and a gate; The main FET defines a drain coupled to the upper terminal, a source coupled to the lower terminal, and a gate. A diode having an anode coupled to the lower terminal and a cathode coupled to the upper terminal; A driver coupled to the upper terminal, the lower terminal, the control terminal, the upper base, the lower base, the gate of the lower cascode FET, and the gate of the main FET, the driver being configured to: Sensing the applied voltage across the upper terminal and the lower terminal; When the applied voltage is corrected on the upper terminal and the control terminal is de-asserted, the BJT and main FET are arranged to prevent current from flowing through the hybrid switch; When the applied voltage is corrected at the upper terminal and the control terminal is asserted, a positive current is allowed to flow from the upper terminal to the lower terminal, wherein the positive current is shared between the main FET and the BJT; and When the applied voltage is corrected at the lower terminal, reverse current is allowed to flow through the hybrid switch.

11. The hybrid switch of claim 10, wherein when the driver enables the reverse current to flow, the driver is configured to: Allow the reverse current to initially flow through the diode; and then The BJT is arranged such that the reverse current flows through the BJT.

12. The hybrid switch of claim 10, wherein when the driver enables the reverse current to flow, the driver is further configured to arrange the main FET such that the reverse current is shared between the BJT and the main FET.

13. The hybrid switch of claim 10, wherein the diode is the body diode of the main FET.

14. The hybrid switch of claim 10, wherein the diode is a discrete diode different from the main FET.

15. The hybrid switch of claim 10, wherein the diode is a silicon carbide diode.

16. The hybrid switch of claim 10, wherein when the driver enables the positive current to flow, the driver is configured to: Assert the gate of the main FET; and then The BJT is configured to be turned on in active turn-on mode.

17. The hybrid switch of claim 16, wherein when the applied voltage is corrected at the upper terminal and the control terminal becomes a canceled assertion, the driver is configured to: Turn the BJT off while maintaining the assertion state of the gate of the main FET; and then... Cancel the assertion of the gate of the main FET to make the main FET non-conductive.

18. The hybrid switch of claim 10, further comprising: An upper common-source cascode FET defines a drain coupled to the upper terminal, a source coupled to the upper collector-emitter junction, and a gate coupled to the driver. The driver is coupled to the lower collector-emitter junction; and When the applied voltage is corrected at the upper terminal and the control terminal changes from being asserted to being deasserted, the driver is further configured to: To disable the upper cascode FET; and The reverse recovery bias voltage is driven to the lower collector-emitter.

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