Semiconductor equipment and isolation switches

Abstract

To stabilize the potential of the semiconductor substrate in a semiconductor device. [Solution] The semiconductor device 10 includes a switch circuit chip 90 and a control circuit chip 80 mounted on a first die pad 101, a first conductive bonding material SD1 that bonds the first die pad 101 and the switch circuit chip 90, and a second conductive bonding material SD2 that bonds the first die pad 101 and the control circuit chip 80. The switch circuit chip 90 includes a first semiconductor substrate 91 bonded to the first die pad 101 by the first conductive bonding material SD1, and a first transistor 51 and a second transistor 52 whose sources are connected to each other. Both the first transistor 51 and the second transistor 52 are high electron mobility transistors containing nitride semiconductors. The sources of the first transistor 51 and the second transistor 52 are electrically connected to the first die pad 101 through the control circuit chip 80.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and an insulating switch.

Background Art

[0002] Patent Document 1 discloses a bidirectional switch in which the source of a first MOSFET and the source of a second MOSFET are connected. This bidirectional switch includes a first drain terminal connected to the drain electrode of the first MOSFET, a first gate terminal connected to the gate electrode of the first MOSFET, a second drain terminal connected to the drain electrode of the second MOSFET, a second gate terminal connected to the gate electrode of the second MOSFET, and a common source terminal to which the source electrode of the first MOSFET and the source electrode of the second MOSFET are connected.

Prior Art Document

Patent Document

[0003]

Patent Document 1

[0004] [Summary] By the way, when a high electron mobility transistor (HEMT) composed of a nitride semiconductor is used as the switch circuit of the bidirectional switch, stabilization of the potential of the semiconductor substrate in this HEMT is required.

[0005] A semiconductor device according to one aspect of the present disclosure comprises: a first die pad; a switch circuit chip mounted on the first die pad; a control circuit chip mounted on the first die pad and including a control circuit for controlling the drive of the switch circuit chip; a first conductive bonding material for bonding the first die pad and the switch circuit chip; a second conductive bonding material for bonding the first die pad and the control circuit chip; a first terminal and a second terminal disposed apart from the first die pad; and a sealing resin that at least seals the first conductive bonding material, the second conductive bonding material, the switch circuit chip, and the control circuit chip, while at least partially exposing both the first terminal and the second terminal, wherein the switch circuit The chip includes a first chip surface, a first chip back surface opposite to the first chip surface, a first semiconductor substrate constituting the first chip back surface and bonded to the first die pad by the first conductive bonding material, an insulating layer provided on the first semiconductor substrate, and a first transistor and a second transistor provided between the insulating layer and the first chip surface in the thickness direction of the switch circuit chip, with their sources connected to each other. Both the first and second transistors are high electron-mobility transistors containing nitride semiconductors, and the sources of the first transistor and the second transistor are electrically connected to the first die pad through the control circuit chip. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a schematic circuit diagram of an insulating switch comprising an exemplary semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view of the semiconductor device shown in Figure 1. [Figure 3] Figure 3 is a schematic cross-sectional view of the semiconductor device shown in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of an insulating chip in a semiconductor device. [Figure 5] Figure 5 is a schematic cross-sectional view of a portion of the insulating chip in a semiconductor device that differs from Figure 4. [Figure 6]Figure 6 is a schematic cross-sectional view illustrating the configuration of the control circuit chip shown in Figure 3. [Figure 7] Figure 7 is a schematic plan view showing an enlarged portion of the internal structure of the switch circuit chip shown in Figure 3. [Figure 8] Figure 8 is a schematic cross-sectional view obtained by cutting the switch circuit chip along the F8-F8 line in Figure 7. [Figure 9] Figure 9 is a schematic cross-sectional view showing an enlarged view of the control circuit chip, switch circuit chip, and surrounding area in the semiconductor device shown in Figure 3. [Figure 10] Figure 10 is a schematic plan view of an exemplary semiconductor device according to the second embodiment. [Figure 11] Figure 11 is a schematic cross-sectional view illustrating the configuration of the control circuit chip shown in Figure 10. [Figure 12] Figure 12 is a schematic circuit diagram of an insulating switch comprising an exemplary semiconductor device according to the third embodiment. [Figure 13] Figure 13 is a schematic plan view of the semiconductor device shown in Figure 12. [Figure 14] Figure 14 is a schematic cross-sectional view of the drive circuit chip in a modified semiconductor device. [Figure 15] Figure 15 is a schematic cross-sectional view of the insulating chip in the modified semiconductor device. [Figure 16] Figure 16 is a schematic plan view of the modified semiconductor device.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of this disclosure will be described with reference to the attached drawings. Note that, for the sake of simplicity and clarity, the components shown in the drawings are not necessarily drawn to a consistent scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The attached drawings are merely illustrative of embodiments of this disclosure and should not be considered as limiting this disclosure.

[0008] The following detailed description includes apparatus, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] The terms "First," "Second," "Third," etc., used in this disclosure are merely labels and are not necessarily intended to assign a sequence to the objects. As used in this disclosure, the phrase "at least one" means "one or more" of the desired options. For example, if there are two options, the phrase "at least one" means "only one option" or "both of the two options." As another example, if there are three or more options, the phrase "at least one" means "only one option" or "any combination of two or more options."

[0010] <First Embodiment> [Outline configuration of an insulated switch] Referring to Figure 1, the schematic configuration of the isolation switch 800 equipped with the semiconductor device 10 of the first embodiment will be described. Figure 1 shows the schematic configuration of the isolation switch 800.

[0011] The isolation switch 800 shown in Figure 1 may be mounted on a device such as a programmable logic controller (PLC). The isolation switch 800 may be used as a switch to turn on and off a circuit that supplies a drive voltage VD2 to a load 810. In one example, the isolation switch 800 includes a power supply circuit 821 and a signal generation circuit 822 electrically connected to the semiconductor device 10. The power supply circuit 821 is configured to supply an operating voltage VD1 to the semiconductor device 10. The operating voltage VD1 is, for example, a DC voltage. The signal generation circuit 822 is configured to output a control signal S1 for controlling the load 810 to the semiconductor device 10.

[0012] Note that the configuration of the insulation switch 800 is not limited to the example shown in FIG. 1 and can be arbitrarily changed. In one example, at least one of the power supply circuit 821 and the signal generation circuit 822 may be provided outside the insulation switch 800. In this case, the circuit provided outside the insulation switch 800 among the power supply circuit 821 and the signal generation circuit 822 is electrically connected to the insulation switch 800.

[0013] The semiconductor device 10 is configured to switch between a state where current flows through the load 810 (on state) and a state where no current flows through the load 810 (off state) in response to the control signal S1. The semiconductor device 10 includes first to sixth terminals 11 to 16.

[0014] The first terminal 11 and the second terminal 12 are terminals configured to be electrically connectable to the load 810. That is, the load 810 is connected to the first terminal 11 or the second terminal 12 according to the usage form of the load 810. In FIG. 1, a first load 811 and a second load 812 are shown as the load 810.

[0015] The semiconductor device 10 includes a switch circuit 50 connected between the first terminal 11 and the second terminal 12. The first load 811 shows, as an example of the usage form, a load connected to the insulation switch 800 so as to be driven in a sink form. The first load 811 is electrically connected between a high-potential terminal 831 that supplies the drive voltage VD2 to the first load 811 and the first terminal 11. The second terminal 12 is connected to a low-potential terminal 832 having a potential lower than the drive voltage VD2. The low-potential terminal 832 may be a reference terminal that becomes a reference potential with respect to the drive voltage VD2. The high-potential terminal 831 and the low-potential terminal 832 may be terminals or cables of a power supply that supplies power for operating the first load 811. The low-potential terminal 832 may be, for example, a ground terminal. The drive voltage VD2 is, for example, 36V. The reference voltage is, for example, 0V. Note that the drive voltage VD2 and the reference voltage may be appropriately changed respectively. When the switch circuit 50 is in the on state, current flows from the first terminal 11 toward the second terminal 12.

[0016] The second load 812, as an example of another usage configuration, is a load connected to the isolation switch 800 to be driven in source mode. The second load 812 is connected between the first terminal 11 and the low-potential terminal 832. The second terminal 12 is connected to the high-potential terminal 831, which supplies the drive voltage VD2. When the switch circuit 50 is ON, current flows from the second terminal 12 to the first terminal 11.

[0017] The third terminal 13 is, for example, electrically floating. The fourth terminal 14 and the fifth terminal 15 are terminals configured to be electrically connectable to the power supply circuit 821. The sixth terminal 16 is a terminal configured to be electrically connectable to the signal generation circuit 822.

[0018] The semiconductor device 10 includes a drive circuit 20, an isolation circuit 30, a control circuit 40, and the aforementioned switch circuit 50. The drive circuit 20 is electrically connected to the 4th to 6th terminals 14 to 16. In other words, the drive circuit 20 can be electrically connected to the power supply circuit 821 and the signal generation circuit 822. The drive circuit 20 is electrically connected to the isolation circuit 30. The drive circuit 20 is configured to generate a pulse signal SP for controlling the switch circuit 50. The drive circuit 20 is configured to output the pulse signal SP to the isolation circuit 30.

[0019] The drive circuit 20 may include, for example, a pulse signal generation circuit 21 and an oscillation circuit 22. The pulse signal generation circuit 21 is electrically connected to both the power supply circuit 821 and the signal generation circuit 822. The oscillation circuit 22 is electrically connected to both the power supply circuit 821 and the pulse signal generation circuit 21.

[0020] The oscillation circuit 22 is configured to output a clock signal CLK. The clock signal CLK may be, for example, a square wave. The clock signal CLK has a predetermined frequency and a predetermined duty cycle. The oscillation circuit 22 may be configured to change the frequency of the clock signal CLK. The oscillation circuit 22 may also be configured to output and stop the clock signal CLK by, for example, an enable signal. The pulse signal generation circuit 21 is configured to generate a pulse signal SP based on the clock signal CLK and the control signal S1 and output it to the isolation circuit 30. The clock signal CLK may be supplied from outside the isolation switch 800.

[0021] The isolation circuit 30 is electrically connected to the drive circuit 20 and the control circuit 40, respectively. The isolation circuit 30 includes a transformer 31. The transformer 31 includes a first coil 32 and a second coil 33. The first coil 32 is electrically connected to the pulse signal generation circuit 21 of the drive circuit 20. Therefore, the drive circuit 20 is configured to output a pulse signal to the first coil 32. The second coil 33 is electrically connected to the control circuit 40. The transformer 31 is configured to induce a current in the second coil 33 by the pulse signal SP supplied from the pulse signal generation circuit 21 to the first coil 32. Here, the first coil 32 is an example of a "first isolation element," and the second coil 33 is an example of a "second isolation element."

[0022] The control circuit 40 is electrically connected to the switch circuit 50. The control circuit 40 is configured to control the driving of the switch circuit 50. The control circuit 40 includes a rectifier circuit 41 and a gate voltage control circuit 42.

[0023] The rectifier circuit 41 is configured to rectify the induced current flowing through the second coil 33 of the transformer 31. The rectifier circuit 41 may include, for example, a plurality of diodes that rectify the induced current. Each of the plurality of diodes may be, for example, a diode-connected transistor.

[0024] The gate voltage control circuit 42 is electrically connected to the switch circuit 50. The gate voltage control circuit 42 is configured to generate a drive signal S2 that controls the switch circuit 50 based on the current from the rectifier circuit 41 and to output it to the switch circuit 50. In one example, the gate voltage control circuit 42 may include circuit elements such as transistors, capacitors, and resistors.

[0025] The switch circuit 50 is electrically connected individually to the first to third terminals 11 to 13. The switch circuit 50 may be configured as a bidirectional switch. In one example, the switch circuit 50 includes a configuration in which a first transistor 51 and a second transistor 52 are connected in series. These transistors 51 and 52 are high electron mobility transistors (HEMTs) containing nitride semiconductors. In one example, each of the first transistor 51 and the second transistor 52 is configured as a normally-off GaN HEMT.

[0026] Each of the first transistor 51 and the second transistor 52 includes a source, drain, and gate. The gates of each transistor 51 and 52 are electrically connected to the gate voltage control circuit 42. The sources of each transistor 51 and 52 are electrically connected to each other. The sources of each transistor 51 and 52 are electrically connected to the gate voltage control circuit 42. In other words, the gate voltage control circuit 42 is individually electrically connected to the gates of each transistor 51 and 52, and to the sources of each transistor 51 and 52. The drain of the first transistor 51 is electrically connected to the first terminal 11. The drain of the second transistor 52 is electrically connected to the second terminal 12. Therefore, the first transistor 51 and the second transistor 52 are connected in series between the first terminal 11 and the second terminal 12.

[0027] The first transistor 51 and the second transistor 52, which are configured as GaN HEMTs, include a substrate. The substrate for the first transistor 51 and the second transistor 52 may be, for example, a silicon (Si) substrate. The substrate for the first transistor 51 and the second transistor 52 may be a single integrated substrate. The source potentials of the first transistor 51 and the second transistor 52 may be supplied to the substrate. In one example, the substrate is electrically connected to the sources of the first transistor 51 and the second transistor 52.

[0028] In the isolation switch 800 with the above configuration, a pulse signal SP generated by the pulse signal generation circuit 21 is supplied to the first coil 32 of the isolation circuit 30 based on the control signal S1 from the signal generation circuit 822 and the clock signal CLK from the oscillation circuit 22. This generates an induced current in the second coil 33 of the isolation circuit 30 corresponding to the pulse signal SP. The rectifier circuit 41 rectifies the induced current of the second coil 33 to generate a DC voltage. The gate voltage control circuit 42 generates a drive signal S2 using the DC voltage from the rectifier circuit 41. In one example, the rectifier circuit 41 rectifies the induced current from the second coil 33 to generate a desired DC voltage. This DC voltage is, for example, 6V to 7V. The gate voltage control circuit 42 uses the DC voltage from the rectifier circuit 41 to generate a drive signal S2 with a voltage corresponding to the control of the first transistor 51 and the second transistor 52 of the switch circuit 50. The voltage of the drive signal S2 may be 5V to 5.5V, for example, 5.25V. This drive signal S2 is supplied to the gates of the first transistor 51 and the second transistor 52 of the switch circuit 50. Therefore, when the drive signal S2 becomes higher than the threshold voltage of the first transistor 51 and the second transistor 52, the first transistor 51 and the second transistor 52 are turned on. As a result, the switch circuit 50 becomes conductive. With the switch circuit 50 now conductive, current flows from the load 810 (load 811) through the switch circuit 50 to the low-potential terminal 832, thus driving the load 810 (load 811).

[0029] Furthermore, if the DC voltage obtained by the rectifier circuit 41 rectifying the induced current from the second coil 33 is less than the gate threshold voltage, the gate voltage control circuit 42 may include a boost circuit to increase the DC voltage. In other words, the gate voltage control circuit 42 may be configured to generate a drive signal S2 of the voltage necessary to turn on the first transistor 51 and the second transistor 52 by boosting the DC voltage from the rectifier circuit 41.

[0030] [Overall configuration of semiconductor device] The overall configuration of the semiconductor device 10 of the first embodiment will be described with reference to Figures 2 and 3. Figure 2 shows the schematic planar structure of the inside of the semiconductor device 10. Figure 3 shows the schematic cross-sectional structure of the semiconductor device 10 cut along the XZ plane. In Figure 2, the sealing resin 120, which will be described later, is shown by a dashed line for the purpose of explaining the internal structure of the semiconductor device 10.

[0031] In this disclosure, components may be described based on the mutually orthogonal XYZ axes shown in the figures. Here, the direction along the X axis is referred to as the "X direction," the direction along the Y axis as the "Y direction," and the direction along the Z axis as the "Z direction." Furthermore, the term "plan view" as used in this disclosure refers to viewing the semiconductor device 10 in the Z direction.

[0032] As shown in Figures 2 and 3, the semiconductor device 10 is a semiconductor device in which multiple semiconductor chips are packaged together. In the first embodiment, the semiconductor device 10 includes a drive circuit chip 60, an isolation chip 70, a control circuit chip 80, and a switch circuit chip 90 as semiconductor chips.

[0033] The package format of the semiconductor device 10 is SO (Small Outline) based, and in one example, it is SOP (Small Outline Package). The package format of the semiconductor device 10 can be changed as needed. The package format is not limited to SOP, and may include QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-leaded Package), or various similar package structures.

[0034] In the first embodiment, the semiconductor device 10 includes a first support member 100, a second support member 110, and a sealing resin 120. The drive circuit chip 60 is mounted on the second support member 110. In one example, the insulation chip 70 is mounted on the second support member 110. The control circuit chip 80 is mounted on the first support member 100. The switch circuit chip 90 is mounted on the first support member 100.

[0035] The sealing resin 120 is made of an electrically insulating resin material. This resin material may be, for example, an epoxy resin. This resin material may also be colored black or the like. The sealing resin 120 may be in the shape of a flat plate with the Z direction as the thickness direction. As shown in Figure 3, the sealing resin 120 includes a sealing upper surface 121 and a sealing lower surface 122 opposite to the sealing upper surface 121. The sealing upper surface 121 and the sealing lower surface 122 are located at positions separated from each other in the Z direction. The sealing resin 120 includes four sealing sides 123 to 126 (see Figure 2) that connect the sealing upper surface 121 and the sealing lower surface 122. The sealing sides 123 and 124 constitute both end faces in the X direction of the sealing resin 120. The sealing sides 125 and 126 constitute both end faces in the Y direction of the sealing resin 120.

[0036] Each of the first support member 100 and the second support member 110 is conductive. These support members 100 and 110 are made of materials including Cu (copper), Fe (iron), Al (aluminum), etc. The first support member 100 and the second support member 110 are provided both inside and outside the sealing resin 120. The first support member 100 and the second support member 110 are spaced apart in the X direction. The first support member 100 is positioned closer to the sealing side surface 124 relative to the second support member 110.

[0037] As shown in Figure 2, the first support member 100 includes a first die pad 101 placed inside the sealing resin 120, and a plurality of first to third terminals 102 to 104 arranged both inside and outside the sealing resin 120. The first terminal 102 constitutes the first terminal 11 in Figure 1, the second terminal 103 constitutes the second terminal 12 in Figure 1, and the third terminal 104 constitutes the third terminal 13 in Figure 1.

[0038] The first die pad 101 is equipped with both a control circuit chip 80 and a switch circuit chip 90. In one example, the first die pad 101 is not exposed from the sealing resin 120. The first die pad 101 is a flat plate with the Z direction as the thickness direction. In one example, the first die pad 101 is rectangular in shape with the X direction as the longer side and the Y direction as the shorter side when viewed from above.

[0039] The first to third terminals 102 to 104 are positioned in the X direction on the opposite side of the first die pad 101 from the second support member 110. The first to third terminals 102 to 104 are spaced apart from each other in the Y direction. The third terminal 104 is positioned on the side of the first die pad 101 where the first terminals 102 and 2 terminals 103 are positioned. The third terminal 104 is positioned between the first terminal 102 and 2 terminal 103 in the Y direction. Parts of the first to third terminals 102 to 104 protrude outward from the sealing side surface 124 toward the sealing resin 120. Each of the first terminal 102 and 2 terminal 103 is positioned away from the first die pad 101. The third terminal 104 is integrated with the first die pad 101.

[0040] The second support member 110 includes a second die pad 111 disposed within the sealing resin 120, and a plurality of fourth to sixth terminals 112 to 114 arranged both inside and outside the sealing resin 120. The fourth terminal 112 constitutes the fourth terminal 14 in Figure 1, the fifth terminal 113 constitutes the fifth terminal 15 in Figure 1, and the sixth terminal 114 constitutes the sixth terminal 16 in Figure 1.

[0041] The second die pad 111 is positioned at a distance from the first die pad 101 in the X direction. Both the drive circuit chip 60 and the insulating chip 70 are mounted on the second die pad 111. In one example, the second die pad 111 is not exposed from the sealing resin 120. The second die pad 111 is a flat plate with the Z direction as the thickness direction. In one example, the second die pad 111 is rectangular in shape with the X direction as the longer side and the Y direction as the shorter side in a plan view.

[0042] The fourth to sixth terminals 112 to 114 are positioned in the X direction on the opposite side of the second die pad 111 from the first support member 100. The fourth to sixth terminals 112 to 114 are spaced apart from each other in the Y direction. Parts of the fourth to sixth terminals 112 to 114 protrude outward from the sealing side surface 123 toward the sealing resin 120. The fourth terminal 112 and the sixth terminal 114 are each positioned away from the second die pad 111. The fifth terminal 113 is integrated with the second die pad 111. The fifth terminal 113 is positioned closer to the sealing side surface 126 than the fourth terminal 112 and the sixth terminal 114. The fourth terminal 112 is positioned between the fifth terminal 113 and the sixth terminal 114 in the Y direction.

[0043] As shown in Figures 2 and 3, the drive circuit chip 60, isolation chip 70, control circuit chip 80, and switch circuit chip 90 are arranged spaced apart from each other in the X direction. Both the isolation chip 70 and the control circuit chip 80 are positioned between the drive circuit chip 60 and the switch circuit chip 90 in the X direction. The isolation chip 70 is positioned between the drive circuit chip 60 and the control circuit chip 80 in the X direction.

[0044] The drive circuit chip 60 includes the drive circuit 20 shown in Figure 1. More specifically, the drive circuit chip 60 includes the pulse signal generation circuit 21 and the oscillation circuit 22 shown in Figure 1. The drive circuit chip 60 is a flat plate with the Z direction as the thickness direction. In plan view, the drive circuit chip 60 is rectangular with a short side and a long side. The drive circuit chip 60 is mounted on the second die pad 111 such that, for example, the long side is aligned with the Y direction and the short side is aligned with the X direction.

[0045] As shown in Figure 3, the drive circuit chip 60 is bonded to the second die pad 111 by a fourth conductive bonding material SD4. The drive circuit chip 60 includes a fourth chip surface 60S and a fourth chip back surface 60R opposite to the fourth chip surface 60S. The fourth chip back surface 60R is in contact with the fourth conductive bonding material SD4. As the fourth conductive bonding material SD4, at least one of solder paste, silver (Ag) paste, copper paste, and gold (Au) paste may be used.

[0046] The drive circuit chip 60 includes a fourth semiconductor substrate 61 and a fourth insulator 62 provided on the fourth semiconductor substrate 61. The fourth semiconductor substrate 61 includes the back surface 60R of the fourth chip. The fourth insulator 62 includes the front surface 60S of the fourth chip.

[0047] The fourth semiconductor substrate 61 is a flat plate with the Z direction as the thickness direction. The fourth semiconductor substrate 61 is made of a material containing, for example, Si. In one example, a Si substrate may be used for the fourth semiconductor substrate 61. Alternatively, a silicon carbide (SiC) substrate or a gallium nitride (GaN) substrate may be used for the fourth semiconductor substrate 61 instead of a Si substrate. A fourth semiconductor layer 61A, epitaxially grown from the fourth semiconductor substrate 61, is provided on the fourth semiconductor substrate 61. A drive circuit 20 (pulse signal generation circuit 21 and oscillation circuit 22) is provided on the fourth semiconductor layer 61A. The fourth insulator 62 is provided on the fourth semiconductor layer 61A. In other words, the fourth semiconductor layer 61A is provided between the fourth insulator 62 and the fourth semiconductor substrate 61.

[0048] The fourth insulator 62 is provided, for example, throughout the entire fourth semiconductor layer 61A in a plan view. The fourth insulator 62 may include an insulating layer containing at least one of silicon oxide (SiO2) and silicon nitride (SiN), and a protective layer provided on the insulating layer. The protective layer may be made of, for example, polyimide (PI).

[0049] As shown in Figure 2, the drive circuit chip 60 includes first to fifth pads 63A to 63E. The first to fifth pads 63A to 63E are provided on the fourth insulator 62 (see Figure 3). In a plan view, the first to fifth pads 63A to 63E are exposed from the fourth insulator 62. More specifically, the first to fifth pads 63A to 63E are provided on the insulating layer of the fourth insulator 62. The protective layer is provided so as to partially cover the first to fifth pads 63A to 63E. Therefore, in a plan view, the first to fifth pads 63A to 63E include portions exposed from the protective layer. The first pad 63A and the second pad 63B are electrically connected to the oscillation circuit 22. The third to fifth pads 63C to 63E are electrically connected to the pulse signal generation circuit 21. The first to third pads 63A to 63C are located on the fourth chip surface 60S, closer to the fourth to sixth terminals 112 to 116, in a plan view. The fourth pad 63D and the fifth pad 63E are located on the fourth chip surface 60S, closer to the insulating chip 70, in a plan view.

[0050] The insulating chip 70 includes the transformer 31 shown in Figure 1. The insulating chip 70 is a flat plate with the Z direction as the thickness direction. In a plan view, the insulating chip 70 is rectangular with a short side and a long side. The insulating chip 70 is mounted on the second die pad 111 such that, for example, the long side is aligned with the Y direction and the short side is aligned with the X direction.

[0051] As shown in Figure 3, the insulating chip 70 is bonded to the second die pad 111 by a third conductive bonding material SD3. The insulating chip 70 includes a third chip surface 70S and a third chip back surface 70R opposite to the third chip surface 70S. The third chip back surface 70R is in contact with the third conductive bonding material SD3. The third conductive bonding material SD3 may be at least one of solder paste, Ag paste, Cu paste, and Au paste.

[0052] The insulating chip 70 includes a third semiconductor substrate 71, a third insulator 72 provided on the third semiconductor substrate 71, and first to fourth pads 73A to 73D (see Figure 2). The third semiconductor substrate 71 includes the back surface 70R of the third chip. The third insulator 72 includes the front surface 70S of the third chip.

[0053] The third semiconductor substrate 71 is a flat plate with the Z direction as the thickness direction. The third semiconductor substrate 71 is made of a material containing, for example, Si. In one example, a Si substrate may be used for the third semiconductor substrate 71. Alternatively, a SiC substrate may be used for the third semiconductor substrate 71.

[0054] As shown in Figure 2, the first to fourth pads 73A to 73D are provided on the third insulator 72 (see Figure 3). The first to fourth pads 73A to 73D are exposed from the third insulator 72 in a plan view. The first pad 73A and the second pad 73B are electrically connected to the first coil 32 of the transformer 31. The first pad 73A and the second pad 73B are located on the third chip surface 70S closer to the drive circuit chip 60. The third pad 73C and the fourth pad 73D are electrically connected to the second coil 33 of the transformer 31. The third pad 73C and the fourth pad 73D are located in the center of the third chip surface 70S in the X direction.

[0055] The control circuit chip 80 includes the control circuit 40 shown in Figure 1. The control circuit 40 is configured to control the driving of the switch circuit chip 90. The control circuit chip 80 is a flat plate with the Z direction as the thickness direction. In plan view, the control circuit chip 80 is rectangular with a short side and a long side. The control circuit chip 80 is mounted on the first die pad 101 such that, for example, the long side is aligned with the Y direction and the short side is aligned with the X direction.

[0056] As shown in Figure 3, the control circuit chip 80 is bonded to the first die pad 101 by a second conductive bonding material SD2. The control circuit chip 80 includes a second chip surface 80S and a second chip back surface 80R opposite to the second chip surface 80S. The second chip back surface 80R is in contact with the second conductive bonding material SD2. The second conductive bonding material SD2 may be at least one of solder paste, Ag paste, Cu paste, and Au paste.

[0057] The control circuit chip 80 includes a second semiconductor substrate 81 and a second insulator 82 provided on the second semiconductor substrate 81. The second semiconductor substrate 81 includes a second chip back surface 80R. The second insulator 82 includes a second chip front surface 80S. The second semiconductor substrate 81 is electrically connected to the first die pad 101 by a second conductive bonding material SD2.

[0058] The second semiconductor substrate 81 is a flat plate with the Z direction as the thickness direction. The second semiconductor substrate 81 is made of a material containing Si, for example. In one example, a Si substrate may be used for the second semiconductor substrate 81. Alternatively, a SiC substrate may be used for the second semiconductor substrate 81. A second semiconductor layer 81A, epitaxially grown from the second semiconductor substrate 81, is provided on the second semiconductor substrate 81. A control circuit 40 (rectifier circuit 41 and gate voltage control circuit 42) is provided on the second semiconductor layer 81A. The second insulator 82 is provided on the second semiconductor layer 81A. In other words, the second semiconductor layer 81A is provided between the second insulator 82 and the second semiconductor substrate 81.

[0059] The second insulator 82 is provided, for example, over the entire second semiconductor layer 81A in a plan view. The second insulator 82 may include an insulating layer containing at least one of SiO2 and SiN, and a protective layer provided on the insulating layer. The protective layer may be made of, for example, PI.

[0060] As shown in Figure 2, the control circuit chip 80 includes first to fourth pads 83A to 83D. The first to fourth pads 83A to 83D are located on the second insulator 82 (see Figure 3). In a plan view, the first to fourth pads 83A to 83D are exposed from the second insulator 82. The first pad 73A and the second pad 73B are electrically connected to the rectifier circuit 41 of the control circuit 40. The first pad 83A and the second pad 83B are located on the second chip surface 80S closer to the insulating chip 70. The third pad 83C and the fourth pad 83D are electrically connected to the gate voltage control circuit 42 of the control circuit 40. The third pad 83C and the fourth pad 83D are located on the second chip surface 80S closer to the switch circuit chip 90.

[0061] The switch circuit chip 90 includes the switch circuit 50 shown in Figure 1. The switch circuit chip 90 is a flat plate with the Z direction as the thickness direction. In a plan view, the switch circuit chip 90 is rectangular in shape with a short side and a long side. The switch circuit chip 90 is mounted on the first die pad 101 such that, for example, the long side is aligned with the Y direction and the short side is aligned with the X direction.

[0062] As shown in Figure 3, the switch circuit chip 90 is bonded to the first die pad 101 by a first conductive bonding material SD1. The switch circuit chip 90 includes a first chip surface 90S and a first chip back surface 90R opposite to the first chip surface 90S. The first chip back surface 90R is in contact with the first conductive bonding material SD1. The first conductive bonding material SD1 may be at least one of solder paste, Ag paste, Cu paste, and Au paste.

[0063] The switch circuit chip 90 includes a first semiconductor substrate 91 corresponding to the substrates of the first transistor 51 and the second transistor 52 described above, a first insulator 98 provided on the first semiconductor substrate 91, and first to fourth pads 93A to 93D. The first semiconductor substrate 91 includes the back surface 90R of the first chip. The first insulator 98 includes the front surface 90S of the first chip. The first semiconductor substrate 91 is electrically connected to the first die pad 101 by a first conductive bonding material SD1. Therefore, the first semiconductor substrate 91 is electrically connected to the second semiconductor substrate 81 through the first conductive bonding material SD1, the first die pad 101, and the second conductive bonding material SD2.

[0064] The first semiconductor substrate 91 is a flat plate with the Z direction as the thickness direction. The first semiconductor substrate 91 is made of a material containing, for example, Si. In one example, a Si substrate may be used for the first semiconductor substrate 91. Alternatively, a SiC substrate may be used for the first semiconductor substrate 91 instead of a Si substrate.

[0065] The first to fourth pads 93A to 93D are located on the first insulator 98. In a plan view, the first to fourth pads 93A to 93D are exposed from the first insulator 98. The first pad 93A is electrically connected to the gates of the first transistor 51 and the second transistor 52 in Figure 1. The second pad 93B is electrically connected to node ND between the source of the first transistor 51 and the source of the second transistor 52, and to the substrates of the first transistor 51 and the second transistor 52. The first pad 93A and the second pad 93B are located on the first chip surface 90S closer to the control circuit chip 80. The third pad 93C is electrically connected to the drain of the first transistor 51. The fourth pad 93D is electrically connected to the source of the second transistor 52. The third pad 93C and the fourth pad 93D are located on the first chip surface 90S closer to the first to third terminals 102 to 104. The internal configuration of the switch circuit chip 90 will be described later.

[0066] Next, the electrical connection configuration of the drive circuit chip 60, isolation chip 70, control circuit chip 80, and switch circuit chip 90 will be described using Figure 2. As shown in Figure 2, the semiconductor device 10 includes first to eleventh wires W1 to W11 as an electrical connection configuration. The first to eleventh wires W1 to W11 are, for example, bonding wires and are made of materials including Au, Al, Cu, Ag, etc. The first to eleventh wires W1 to W11 are sealed by a sealing resin 120.

[0067] The first to third wires W1 to W3 individually connect the first to third pads 63A to 63C of the drive circuit chip 60 to the fourth to sixth terminals 112 to 114. The first wire W1 connects the first pad 63A to the fourth terminal 112, the second wire W2 connects the second pad 63B to the fifth terminal 113, and the third wire W3 connects the third pad 63C to the sixth terminal 114. As a result, the first pad 63A and the fourth terminal 112 are electrically connected, and the second pad 63B and the fifth terminal 113 are electrically connected. In other words, both the oscillation circuit 22 and the pulse signal generation circuit 21 (see Figure 1) are electrically connected to the fourth terminal 112 and the fifth terminal 113. Also, the third pad 63C and the sixth terminal 114 are electrically connected. In other words, the pulse signal generation circuit 21 and the sixth terminal 114 are electrically connected.

[0068] The fourth wire W4 and the fifth wire W5 electrically connect the drive circuit chip 60 and the isolation chip 70. More specifically, the fourth wire W4 and the fifth wire W5 individually connect the fourth pad 63D and the fifth pad 63E of the drive circuit chip 60 to the first pad 73A and the second pad 73B of the isolation chip 70. The fourth wire W4 connects the fourth pad 63D and the first pad 73A, and the fifth wire W5 connects the fifth pad 63E and the second pad 73B. As a result, the fourth pad 63D and the first pad 73A are electrically connected, and the fifth pad 63E and the second pad 73B are electrically connected. In other words, the pulse signal generation circuit 21 and the first coil 32 of the transformer 31 (see Figure 1) are electrically connected.

[0069] The sixth wire W6 and the seventh wire W7 electrically connect the insulating chip 70 and the control circuit chip 80. More specifically, the sixth wire W6 and the seventh wire W7 individually connect the third pad 73C and the fourth pad 73D of the insulating chip 70 to the first pad 83A and the second pad 83B of the control circuit chip 80. The sixth wire W6 connects the third pad 73C and the first pad 83A, and the seventh wire W7 connects the fourth pad 73D and the second pad 83B. As a result, the third pad 73C and the first pad 83A are electrically connected, and the fourth pad 73D and the second pad 83B are electrically connected. In other words, the second coil 33 of the transformer 31 and the rectifier circuit 41 (both shown in Figure 1) are electrically connected.

[0070] The eighth wire W8 and the ninth wire W9 individually connect the third pad 83C and the fourth pad 83D of the control circuit chip 80, and the first pad 93A and the second pad 93B of the switch circuit chip 90. The eighth wire W8 connects the third pad 83C and the first pad 93A, and the ninth wire W9 connects the fourth pad 83D and the second pad 93B. As a result, the third pad 83C and the first pad 93A are electrically connected, and the fourth pad 83D and the second pad 93B are electrically connected. In other words, the gate voltage control circuit 42 shown in Figure 1 is electrically connected to the gates of the first transistor 51 and the second transistor 52. Also, the gate voltage control circuit 42 is electrically connected to the source of the first transistor 51 and the source of the second transistor 52.

[0071] The 10th wire W10 and the 11th wire W11 connect the 3rd pad 93C and the 4th pad 93D of the switch circuit chip 90 to the 1st terminal 102 and the 2nd terminal 103, respectively. The 10th wire W10 connects the 3rd pad 93C to the 1st terminal 102, and the 11th wire W11 connects the 4th pad 93D to the 2nd terminal 103. As a result, the drain of the 1st transistor 51 is electrically connected to the 1st terminal 102, and the drain of the 2nd transistor 52 is electrically connected to the 2nd terminal 103.

[0072] Here, the first pad 93A of the switch circuit chip 90 corresponds to the "first input pad," the second pad 93B corresponds to the "second input pad," the third pad 93C corresponds to the "first power supply pad," and the fourth pad 93D corresponds to the "second power supply pad." The third pad 83C of the control circuit chip 80 corresponds to the "first output pad," and the fourth pad 83D corresponds to the "second output pad." The tenth wire W10 corresponds to the "first power supply connection member," and the eleventh wire W11 corresponds to the "second power supply connection member." The eighth wire W8 corresponds to the "first connection member," and the ninth wire W9 corresponds to the "second connection member." The sixth wire W6 and the seventh wire W7 correspond to the "relay connection members." The fourth wire W4 and the fifth wire W5 correspond to the "intermediate connection members." The fourth terminal 112 corresponds to the "power terminal," the fifth terminal 113 corresponds to the "ground terminal," and the sixth terminal 114 corresponds to the "signal terminal." The first wire W1 corresponds to the "power connection component," and the third wire W3 corresponds to the "signal connection component."

[0073] (Insulating tip) The internal structure of the insulating chip 70 will be described with reference to Figures 4 and 5. Figure 4 shows a schematic cross-sectional structure of the insulating chip 70 cut along the XZ plane passing through the first pad 73A and the third pad 73C in Figure 2, and Figure 5 shows a schematic cross-sectional structure of the insulating chip 70 cut along the XZ plane passing through the second pad 73B and the fourth pad 73D in Figure 2. For convenience, wires W4 to W7 from the fourth to the seventh wires are omitted in Figures 4 and 5. Also, for ease of understanding the drawings, the thickness of the third insulator 72 is shown to be greater than the thickness of the third semiconductor substrate 71. In reality, the thickness of the third semiconductor substrate 71 is greater than the thickness of the third insulator 72.

[0074] As shown in Figures 4 and 5, the third insulator 72 provided on the third semiconductor substrate 71 in the insulating chip 70 includes an upper surface 72S and a lower surface 72R opposite to the upper surface 72S. The lower surface 72R is in contact with the third semiconductor substrate 71.

[0075] The third insulator 72 includes a plurality of insulating films 72A stacked in the Z direction from the third semiconductor substrate 71. The insulating films 72A include a first insulating film 72AA and a second insulating film 72AB provided on the first insulating film 72AA. The first insulating film 72AA may be made of a material containing SiN, SiC, nitrogen-doped silicon carbide (SiCN), etc. The second insulating film 72AB is, for example, an interlayer insulating film. The second insulating film 72AB may be made of a material containing SiO2. The thickness of the second insulating film 72AB may be greater than the thickness of the first insulating film 72AA. Both the bottom insulating film 72AC in contact with the third semiconductor substrate 71 and the top insulating film 72AD may be made of the second insulating film 72AB.

[0076] As shown in Figure 4, the first coil 32 and the second coil 33 of the transformer 31 are provided on multiple insulating films 72A of the third insulator 72. The first coil 32 and the second coil 33 are arranged opposite each other while being spaced apart in the Z direction. The first coil 32 is positioned closer to the lower surface 72R of the third insulator 72 relative to the second coil 33. It can also be said that the first coil 32 is positioned closer to the third semiconductor substrate 71 relative to the second coil 33. Multiple insulating films 72A are interposed between the first coil 32 and the second coil 33 in the Z direction. Both the first coil 32 and the second coil 33 may be made of a material containing one or more of titanium (Ti), titanium nitride (TiN), Au, Ag, Cu, Al, and tungsten (W) as appropriate. In one example, both the first coil 32 and the second coil 33 are made of a material containing Cu. Both the first coil 32 and the second coil 33 may be circular spirals in shape, for example, when viewed from above.

[0077] The first coil 32 includes a first inner end 32A that constitutes the inner end in the winding direction of the circular spiral first coil 32, and a first outer end 32B (see Figure 5) that constitutes the outer end in the winding direction of the first coil 32.

[0078] As shown in Figures 4 and 5, the insulating tip 70 includes a first inner wiring 74 and a first outer wiring 75. Each of the first inner wiring 74 and the first outer wiring 75 may be made of a material containing one or more of Ti, TiN, Au, Ag, Cu, Al, and W, as appropriately selected.

[0079] As shown in Figure 4, the first inner wiring 74 connects the first inner end 32A of the first coil 32 to the first pad 73A. This electrically connects the first coil 32 and the first pad 73A. The first inner wiring 74 may include a first inner wiring portion extending in the Z direction so as to penetrate a plurality of insulating films 72A, and a second inner wiring portion extending in the X direction.

[0080] As shown in Figure 5, the first outer wiring 75 connects the first outer end 32B of the first coil 32 to the second pad 73B. This electrically connects the first coil 32 and the second pad 73B. The first outer wiring 75 may include a first outer wiring portion extending in the Z direction so as to penetrate a plurality of insulating films 72A, and a second outer wiring portion extending in the X direction. The first outer wiring 75 may also be electrically connected to, for example, the third semiconductor substrate 71.

[0081] The second coil 33 includes a second inner end 33A (see Figure 4) which constitutes the inner end of the circular spiral-shaped second coil 33 in the winding direction, and a second outer end 33B which constitutes the outer end of the second coil 33 in the winding direction.

[0082] As shown in Figures 4 and 5, the insulating tip 70 includes a second inner wiring 76 and a second outer wiring 77. Each of the second inner wiring 76 and the second outer wiring 77 may be made of a material containing one or more of Ti, TiN, Au, Ag, Cu, Al, and W, as appropriate.

[0083] As shown in Figure 4, the second inner wiring 76 connects the second inner end 33A of the second coil 33 to the third pad 73C. This electrically connects the second coil 33 and the third pad 73C. In a plan view, the second inner wiring 76 is positioned to overlap with both the third pad 73C and the second inner end 33A. The second inner wiring 76 may be a via that penetrates the uppermost insulating film 72AD in the Z direction.

[0084] As shown in Figure 5, the second outer wiring 77 connects the second outer end 33B of the second coil 33 to the fourth pad 73D. This electrically connects the second coil 33 and the fourth pad 73D. In a plan view, the second outer wiring 77 is positioned to overlap with both the fourth pad 73D and the second outer end 33B. The second outer wiring 77 may be a via that penetrates the uppermost insulating film 72AD in the Z direction.

[0085] As shown in Figures 4 and 5, the insulating tip 70 includes a dummy coil 78. The dummy coil 78 is provided on the third insulator 72. The dummy coil 78 is provided in the same position as the second coil 33 in the Z direction. The dummy coil 78 is provided so as to surround the second coil 33 in a plan view. The dummy coil 78 is provided around the second coil 33. The dummy coil 78 may be made of a material including one or more of Ti, TiN, Au, Ag, Cu, Al, and W, as appropriately selected. The dummy coil 78 can suppress electric field concentration with respect to the second coil 33. Note that the dummy coil 78 may be omitted.

[0086] The insulating chip 70 includes a passivation film 72B and a protective film 72C as a third insulator 72. The passivation film 72B is provided on the uppermost insulating film 72AC. The passivation film 72B is a protective film for the insulating film 72A. The passivation film 72B is made of a material including, for example, SiO2, SiN, SiCN, etc.

[0087] The first to fourth pads 73A to 73D are provided on the uppermost insulating film 72AC. The passivation film 72B covers each of the first to fourth pads 73A to 73D. On the other hand, the passivation film 72B includes openings that partially expose the first to fourth pads 73A to 73D in the Z direction.

[0088] The protective film 72C is provided on the passivation film 72B. The protective film 72C is made of a material including, for example, PI. The protective film 72C includes openings that communicate with openings in the passivation film 72B. As a result, the first to fourth pads 73A to 73D are partially exposed in the Z direction from the protective film 72C.

[0089] (Control circuit chip) Referring to Figure 6, the schematic internal configuration of the control circuit chip 80 will be described. Figure 6 shows a schematic cross-sectional structure of the control circuit chip 80 cut along the XZ plane passing through the second pad 83B and the fourth pad 83D in Figure 3.

[0090] As shown in Figure 6, the control circuit chip 80 includes a second semiconductor layer 81A epitaxially grown from the second semiconductor substrate 81, as described above. Both the rectifier circuit 41 and the gate voltage control circuit 42 are provided, for example, on the second semiconductor layer 81A. The first to fourth pads 83A to 83D (see Figure 3) are provided on the second semiconductor layer 81A. The second insulator 82 is provided on the second semiconductor layer 81A.

[0091] The control circuit chip 80 includes a plurality of first connection lines 84, a plurality of second connection lines 85, and a plurality of third connection lines 86. These first to third connection lines 84 to 86 are provided within the second semiconductor layer 81A. Each of the first to third connection lines 84 to 86 may be made of a material that includes one or more of Ti, TiN, Au, Ag, Cu, Al, and W, as appropriately selected.

[0092] Multiple first connection wires 84 connect the rectifier circuit 41 to the first pad 83A and the second pad 83B individually. Multiple second connection wires 85 connect the rectifier circuit 41 to the gate voltage control circuit 42. Multiple third connection wires 86 connect the gate voltage control circuit 42 to the third pad 83C and the fourth pad 83D individually. As shown in Figure 2, the multiple third connection wires 86 include wire 86A which connects the gate voltage control circuit 42 to the third pad 83C, and wire 86B which connects the gate voltage control circuit 42 to the fourth pad 83D. Wire 86B is electrically connected to the second semiconductor substrate 81. The gate voltage control circuit 42 is configured such that the third pad 83C, connected by wire 86A, has a desired potential difference with respect to the fourth pad 83D, which is connected by wire 86B. Furthermore, the gate voltage control circuit 42 is configured to generate a drive signal S2 whose drive voltage is the potential difference between the third pad 83C and the fourth pad 83D. The wiring 86B may include wiring connected to the circuit elements constituting the gate voltage control circuit 42, regions constituting the circuit elements, for example, the source region of an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). As a result, the gate voltage control circuit 42 and the fourth pad 83D are electrically connected to the second semiconductor substrate 81. On the other hand, among the multiple third connection wirings 86, the third connection wiring 86 connecting the gate voltage control circuit 42 and the third pad 83C is not connected to the second semiconductor substrate 81.

[0093] (Switch circuit chip) The schematic internal structure of the switch circuit chip 90 will be described with reference to Figures 7 and 8. Figure 7 shows a schematic plan view of a portion of the region of the switch circuit chip 90 where the first transistor 51 and the second transistor 52 are located. Figure 8 shows a schematic cross-sectional view of the switch circuit chip 90 cut along the line F8-F8 in Figure 7.

[0094] As shown in Figure 8, the switch circuit chip 90 includes an insulating layer 92 provided on the first semiconductor substrate 91 and a nitride semiconductor layer 94 provided on the insulating layer 92. The insulating layer 92 is a layer that insulates the first semiconductor substrate 91 from the nitride semiconductor layer 94. The insulating layer 92 is made of, for example, aluminum nitride (AlN). In one example, the thickness T2 of the insulating layer 92 may be thinner than the thickness T1 of the first semiconductor substrate 91. In one example, the thickness T2 of the insulating layer 92 may be thinner than the thickness T3 of the nitride semiconductor layer 94. In one example, the thickness T3 of the nitride semiconductor layer 94 may be thinner than the thickness T1 of the first semiconductor substrate 91.

[0095] The nitride semiconductor layer 94 includes a buffer layer 94A provided on the insulating layer 92, an electron transport layer 94B provided on the buffer layer 94A, and an electron supply layer 94C provided on the electron transport layer 94B.

[0096] The buffer layer 94A may be made of any material that can suppress wafer warping and cracking due to mismatch in thermal expansion coefficients between the first semiconductor substrate 91 and the electron transport layer 94B. The buffer layer 94A may include one or more nitride semiconductor layers. The buffer layer 94A is made of a material containing aluminum gallium nitride (AlGaN). The buffer layer 94A includes, for example, at least one of AlGaN layers and graded AlGaN layers having different Al compositions. For example, the buffer layer 94A may be made of a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. The buffer layer 94A may include multiple AlGaN layers with different compositions.

[0097] Furthermore, in order to suppress leakage current in the buffer layer 94A, an impurity may be introduced into a portion of the buffer layer 94A to make it semi-insulating. In this case, the impurity may be, for example, carbon (C) or Fe.

[0098] The electron transport layer 94B may be, for example, a GaN layer. The electron transport layer 94B may include one or more nitride semiconductor layers. Further, in order to suppress the leakage current in the electron transport layer 94B, a doped layer 94BA may be included in a part of the electron transport layer 94B by introducing acceptor-type impurities to make the region other than the surface layer region of the electron transport layer 94B semi-insulating. It can be said that the doped layer 94BA is composed of a material containing GaN doped with acceptor-type impurities. In this case, the acceptor-type impurity is, for example, C. The doped layer 94BA is provided on the buffer layer 94A. In one example, the doped layer 94BA is provided closer to the buffer layer 94A in the Z direction among the electron transport layers 94B. In one example, the doped layer 94BA is in contact with the buffer layer 94A.

[0099] The electron supply layer 94C is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 94B. The electron supply layer 94C may be, for example, an AlGaN layer. Since the larger the Al composition, the larger the bandgap, the electron supply layer 94C which is an AlGaN layer has a larger bandgap than the electron transport layer 94B which is a GaN layer. In one example, the electron supply layer 94C is composed of Al x Ga 1-x N. In this case, the Al composition ratio x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The thickness of the electron supply layer 94C may be thinner than the thickness of the electron transport layer 94B.

[0100] The electron transport layer 94B and the electron supply layer 94C have different lattice constants in the bulk region. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transport layer 94B and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 94C form a lattice-mismatched heterojunction. Due to the spontaneous polarization of the electron transport layer 94B and the electron supply layer 94C, and the piezoelectric polarization caused by the compressive stress on the heterojunction of the electron transport layer 94B, the energy level of the conduction band of the electron transport layer 94B near the heterojunction interface between the electron transport layer 94B and the electron supply layer 94C is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 95 is spread within the electron transport layer 94B at a position close to the heterojunction interface between the electron transport layer 94B and the electron supply layer 94C (e.g., a distance of a few nanometers from the interface).

[0101] The switch circuit chip 90 includes a gate layer 96 provided on a portion of the electron supply layer 94C, and a gate electrode 97G provided on the gate layer 96. Therefore, it can be said that the gate electrode 97G is provided on top of the electron supply layer 94C. It can also be said that the gate layer 96 is interposed between the gate electrode 97G and the electron supply layer 94C.

[0102] The gate layer 96 is made of a nitride semiconductor. In one example, the gate layer 96 is made of a nitride semiconductor having a smaller band gap than the electron supply layer 94C and containing acceptor-type impurities. In one example, the gate layer 96 is GaN (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), and carbon.

[0103] The gate electrode 97G comprises one or more metal layers. In one example, the gate electrode 97G may be a TiN layer. In another example, the gate electrode 97G may consist of a first metal layer made of Ti and a second metal layer made of TiN, provided on the first metal layer. The gate electrode 97G may be made of a material that has the property of forming a Schottky bond with, for example, the gate layer 96. An example of such a material is TiN.

[0104] A first insulator 98 is provided on the electron supply layer 94C. The first insulator 98 includes a passivation film 98A. The passivation film 98A covers the electron supply layer 94C, the gate layer 96, and the gate electrode 97G. The passivation film 98A may be composed of one or any combination of, for example, SiO2, SiN, silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). The passivation film 98A includes a source opening 98AA, a first drain opening 98AB, and a second drain opening 98AC, each exposing a portion of the upper surface of the electron supply layer 94C. The source opening 98AA is located between the first drain opening 98AB and the second drain opening 98AC in the Y direction.

[0105] The switch circuit chip 90 includes a source electrode 97S provided in a source opening 98AA, a first drain electrode 97DA provided in a first drain opening 98AB, and a second drain electrode 97DB provided in a second drain opening 98AC. The source electrode 97S includes a source contact portion that contacts the electron supply layer 94C via the source opening 98AA. The source contact portion is in ohmic contact with 2DEG 95 directly below the electron supply layer 94C. The first drain electrode 97DA includes a first drain contact portion that contacts the electron supply layer 94C via the first drain opening 98AB. The second drain electrode 97DB includes a second drain contact portion that contacts the electron supply layer 94C via the second drain opening 98AC. Both the first and second drain contact portions are in ohmic contact with 2DEG 95 directly below the electron supply layer 94C. Thus, the source electrode 97S, the first drain electrode 97DA, and the second drain electrode 97DB are located on the electron supply layer 94C.

[0106] The source electrode 97S, the first drain electrode 97DA, and the second drain electrode 97DB each include one or more metal layers. In one example, the source electrode 97S, the first drain electrode 97DA, and the second drain electrode 97DB may be composed of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu). In one example, the source electrode 97S, the first drain electrode 97DA, and the second drain electrode 97DB each consist of a first metal layer in contact with the electron supply layer 94C, a second metal layer laminated on the second metal layer, a third metal layer laminated on the second metal layer, and a fourth metal layer laminated on the third metal layer. The first metal layer is, for example, a Ti layer, the second metal layer is, for example, an Al layer, the third metal layer is, for example, a Ti layer, and the fourth metal layer is, for example, a TiN layer.

[0107] In a structure where the gate layer 96 is made of a nitride semiconductor containing acceptor-type impurities, when zero bias is applied and no voltage is applied to the gate electrode 97G, the 2DEG95 in the region directly beneath the gate layer 96 becomes depleted, blocking the conductive path (channel). This realizes a normally-off HEMT with a positive gate threshold voltage. Then, when a drive signal S2 of an appropriate voltage (on voltage) is applied to the gate electrode 97G, a channel formed by 2DEG95 is created in the region of the electron transport layer 94B directly beneath the gate layer 96, and the source-drain connection becomes conductive.

[0108] The first insulator 98 includes a first interlayer insulating film 98B. The first interlayer insulating film 98B is provided to cover the source electrode 97S, the first drain electrode 97DA, and the second drain electrode 97DB. The first interlayer insulating film 98B may be made of, for example, SiO2.

[0109] The switch circuit chip 90 includes a source wiring 99S, a first drain wiring 99DA, a second drain wiring 99DB, and a gate wiring 99G provided on a first interlayer insulating film 98B. The source wiring 99S, the first drain wiring 99DA, the second drain wiring 99DB, and the gate wiring 99G include one or more metal layers. The source wiring 99S, the first drain wiring 99DA, the second drain wiring 99DB, and the gate wiring 99G may be composed of one or any combination of Ti, TiN, Al, AlSiCu, and AlCu.

[0110] The source wiring 99S is connected to the source electrode 97S by a source via 99SP. Thus, the source wiring 99S is electrically connected to the source electrode 97S. The first drain wiring 99DA is connected to the first drain electrode 97DA by a first drain via 99DP. Thus, the first drain wiring 99DA is electrically connected to the first drain electrode 97DA. The second drain wiring 99DB is connected to the second drain electrode 97DB by a second drain via 99DQ. Thus, the second drain wiring 99DB is electrically connected to the second drain electrode 97DB. The gate wiring 99G is connected to the gate electrode 97G by a gate via 99GP. Thus, the gate wiring 99G is electrically connected to the gate electrode 97G. Each of the source via 99SP, the first drain via 99DP, the second drain via 99DQ, and the gate via 99GP is provided in the first interlayer insulating film 98B. Each of the source via 99SP, the first drain via 99DP, the second drain via 99DQ, and the gate via 99GP may be made of a material containing one or more of Ti, TiN, Au, Ag, Cu, Al, and W, as appropriately selected.

[0111] The first insulator 98 includes a second interlayer insulating film 98C. The second interlayer insulating film 98C is provided to cover the source wiring 99S, the first drain wiring 99DA, the second drain wiring 99DB, and the gate wiring 99G. The second interlayer insulating film 98C may be made of, for example, SiO2.

[0112] The first to fourth pads 93A to 93D (see Figure 3) are provided on the second interlayer insulating film 98C. The first pad 93A is connected to the gate wiring 99G by a gate connection wiring (not shown). Therefore, the first pad 93A is electrically connected to the gate electrode 97G through the gate connection wiring, the gate wiring 99G, and the gate via 99GP. The second pad 93B is connected to the source wiring 99S by a source connection wiring 99SQ. Therefore, the second pad 93B is electrically connected to the source electrode 97S through the source connection wiring 99SQ, the source wiring 99S, and the source via 99SP. The third pad 93C is connected to the first drain wiring 99DA by a first drain connection wiring (not shown). Therefore, the third pad 93C is electrically connected to the first drain electrode 97DA through the first drain connection wiring, the first drain wiring 99DA, and the first drain via 99DP. The fourth pad 93D is connected to the second drain wiring 99DB by a second drain connection wiring (not shown). Thus, the fourth pad 93D is electrically connected to the second drain electrode 97DB through the second drain connection wiring, the second drain wiring 99DB, and the second drain via 99DQ.

[0113] The first insulator 98 includes a protective film 98D. The protective film 98D is provided to cover the first to fourth pads 93A to 93D. The protective film 98D constitutes the first chip surface 90S. The protective film 98D is made of a material including, for example, PI. The protective film 98D includes openings corresponding to the first to fourth pads 93A to 93D. As a result, the first to fourth pads 93A to 93D are partially exposed in the Z direction from the protective film 98D. In this way, the first transistor 51 and the second transistor 52 are provided between the insulating layer 92 and the first chip surface 90S in the Z direction.

[0114] (Exemplary planar layout of a switch circuit chip) As shown in Figure 7, the switch circuit chip 90 includes a HEMT structure. For clarity, Figure 7 shows the schematic planar structure of the source electrode 97S, gate electrode 97G, drain electrodes 97DA, 97DB and their surroundings.

[0115] The switch circuit chip 90 includes multiple transistor elements having a HEMT structure. Figure 7 shows, for example, multiple transistor elements aligned in the Y direction, but in reality, the transistor elements are arranged in both the X and Y directions.

[0116] A first drain electrode 97DA is provided for each transistor element. A second drain electrode 97DB is also provided for each transistor element. The first drain electrode 97DA and the second drain electrode 97DB are spaced apart from each other in the Y direction. Each drain electrode 97DA, 97DB is a strip-shaped element extending along the X direction in a plan view.

[0117] The source electrode 97S is provided as a common electrode for the transistor element on which the first drain electrode 97DA is provided and the transistor element on which the second drain electrode 97DB is provided. The source electrode 97S is positioned between the first drain electrode 97DA and the second drain electrode 97DB in the Y direction. It can also be said that the first drain electrode 97DA and the second drain electrode 97DB are positioned spaced apart on both sides of the source electrode 97S. In a plan view, the source electrode 97S is a strip-shaped electrode extending along the X direction.

[0118] The gate layer 96 and gate electrode 97G are provided in common to multiple transistor elements. In a plan view, the gate layer 96 and gate electrode 97G are provided in a ring shape so as to individually surround the first drain electrode 97DA, the second drain electrode 97DB, and the source electrode 97S. In a plan view, the gate layer 96 and gate electrode 97G can also be said to be provided in a grid pattern. Therefore, in a plan view, the gate layer 96 and gate electrode 97G can also be said to be positioned between the source electrode 97S and the first drain electrode 97DA, and between the source electrode 97S and the second drain electrode 97DB.

[0119] Although not shown in the diagram, the source wiring 99S, the first drain wiring 99DA, the second drain wiring 99DB, and the gate wiring 99G may each extend in the X direction. The source wiring 99S, the first drain wiring 99DA, the second drain wiring 99DB, and the gate wiring 99G are spaced apart from each other in the Y direction.

[0120] The first drain wiring 99DA, the second drain wiring 99DB, and the gate wiring 99G may each extend in the Y direction. In this case, the source wiring 99S, the first drain wiring 99DA, the second drain wiring 99DB, and the gate wiring 99G are arranged spaced apart from each other in the X direction.

[0121] [Operation of the First Embodiment] The operation of the semiconductor device 10 of the first embodiment will be described with reference to Figure 9. Figure 9 shows the schematic cross-sectional structure of the control circuit chip 80, the switch circuit chip 90, and their surroundings as shown in Figure 3. For convenience, the second insulator 82, the protective film 98D, the seventh wire W7, and the eleventh wire W11 are omitted in Figure 9.

[0122] As shown in Figure 9, the sources of the first transistor 51 and the second transistor 52 are electrically connected to the second pad 93B of the switch circuit chip 90. The second pad 93B is electrically connected to the fourth pad 83D of the control circuit chip 80 by the ninth wire W9. The fourth pad 83D is electrically connected to the second semiconductor substrate 81 of the control circuit chip 80 by wiring 86B of the third connection wiring 86. The second semiconductor substrate 81 is electrically connected to the first die pad 101 by the second conductive bonding material SD2. The first semiconductor substrate 91 of the switch circuit chip 90 is electrically connected to the first die pad 101 by the first conductive bonding material SD1. Therefore, as shown by the dashed arrows in Figure 9, the sources of the first transistor 51 and the second transistor 52 are electrically connected to the first die pad 101 through the control circuit chip 80. Furthermore, the sources of the first transistor 51 and the second transistor 52 are electrically connected to the first semiconductor substrate 91 through the first die pad 101. As a result, the potential of the first semiconductor substrate 91 becomes equal to the potential of the second semiconductor substrate 81, and the potential of the first semiconductor substrate 91 becomes the source potential and stabilizes. Then, because the potential of the first semiconductor substrate 91 matches the source potential, the electrical characteristics of the switch circuit chip 90 stabilize.

[0123] Furthermore, it becomes unnecessary to provide a pad that is electrically connected to the source of the first transistor 51 and the source of the second transistor 52, and also electrically connected to the first die pad 101 by, for example, a wire, in addition to the second pad 93B. For this reason, the aforementioned wire can also be omitted.

[0124] [Effects of the First Embodiment] According to the semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 comprises a first die pad 101, a switch circuit chip 90 mounted on the first die pad 101, a control circuit chip 80 mounted on the first die pad 101 and including a control circuit 40 for controlling the drive of the switch circuit chip 90, a first conductive bonding material SD1 for bonding the first die pad 101 and the switch circuit chip 90, a second conductive bonding material SD2 for bonding the first die pad 101 and the control circuit chip 80, a first terminal 102 and a second terminal 103 arranged at a distance from the first die pad 101, and a sealing resin 120 that at least seals the first conductive bonding material SD1, the second conductive bonding material SD2, the switch circuit chip 90, and the control circuit chip 80, while at least partially exposing both the first terminal 102 and the second terminal 103. The switch circuit chip 90 includes a first chip surface 90S, a first chip back surface 90R opposite to the first chip surface 90S, a first semiconductor substrate 91 which constitutes the first chip back surface 90R and is bonded to the first die pad 101 by a first conductive bonding material SD1, an insulating layer 92 provided on the first semiconductor substrate 91, and a first transistor 51 and a second transistor 52 provided between the insulating layer 92 and the first chip surface 90S in the thickness direction (Z direction) of the switch circuit chip 90, with their sources connected to each other. Both the first transistor 51 and the second transistor 52 are high electron mobility transistors containing nitride semiconductors. The sources of the first transistor 51 and the second transistor 52 are electrically connected to the first die pad 101 through the control circuit chip 80.

[0125] In this configuration, the sources of the first transistor 51 and the second transistor 52 are electrically connected to the first semiconductor substrate 91 through the control circuit chip 80, the second conductive bonding material SD2, the first die pad 101, and the first conductive bonding material SD1. As a result, the source potential of each transistor 51 and 52 is equal to the potential of the first semiconductor substrate 91, thereby stabilizing the potential of the first semiconductor substrate 91. Consequently, the electrical characteristics of the switch circuit chip 90 can be stabilized.

[0126] (1-2) The control circuit chip 80 includes a second chip surface 80S, a second chip back surface 80R opposite to the second chip surface 80S, a second semiconductor substrate 81 which constitutes the second chip back surface 80R and is bonded to the first die pad 101 by a second conductive bonding material SD2, a third pad 83C exposed from the second chip surface 80S, and a fourth pad 83D which is electrically connected to the second semiconductor substrate 81 and exposed from the second chip surface 80S. The switch circuit chip 90 includes a first pad 93A exposed from the first chip surface 90S and electrically connected to both the gate of the first transistor 51 and the gate of the second transistor 52, and a second pad 93B exposed from the first chip surface 90S and electrically connected to the source of the first transistor 51 and the source of the second transistor 52. The semiconductor device 10 includes an eighth wire W8 connecting the third pad 83C and the first pad 93A, and a ninth wire W9 connecting the fourth pad 83D and the second pad 93B.

[0127] In this configuration, the source of the first transistor 51 and the source of the second transistor 52 are electrically connected to the second semiconductor substrate 81 of the control circuit chip 80 through the fourth pad 83D of the control circuit chip 80, the second pad 93B of the switch circuit chip 90, and the ninth wire W9. As a result, the source potential of each transistor 51 and 52 becomes equal to the potential of the second semiconductor substrate 81. Therefore, the electrical characteristics of the control circuit chip 80 and the switch circuit chip 90 can be stabilized.

[0128] In addition, by connecting the third pad 83C and the first die pad 101 with a wire, and connecting the second pad 93B and the first die pad 101 with a wire, the configuration of the semiconductor device 10 can be simplified compared to a configuration in which the sources of each transistor 51, 52, the first semiconductor substrate 91, and the second semiconductor substrate 81 are electrically connected.

[0129] (1-3) The semiconductor device 10 includes a third terminal 104 integrated with the first die pad 101. A portion of the third terminal 104 is exposed from the sealing resin 120. In this configuration, the third terminal 104 acts as a suspension lead for the first die pad 101. Therefore, the first die pad 101 can be stably supported during the manufacturing of the semiconductor device 10.

[0130] (1-4) The thickness T2 of the insulating layer 92 is thinner than the thickness T1 of the first semiconductor substrate 91. With this configuration, the thickness T2 of the insulating layer 92 can be reduced compared to the case where the thickness T1 of the first semiconductor substrate 91 is greater than or equal to the thickness T1 of the first semiconductor substrate 91.

[0131] (1-5) The insulating layer 92 is made of a material containing AlN. This configuration improves the heat dissipation performance of the insulating layer 92, making it easier to transfer heat from the first transistor 51 and the second transistor 52 to the first semiconductor substrate 91. Therefore, the heat dissipation performance of the switch circuit chip 90 can be improved.

[0132] (1-6) The semiconductor device 10 further comprises a second die pad 111 positioned spaced apart from the first die pad 101 in the X direction, an insulating chip 70 mounted on the second die pad 111, and a seventh wire W7 and an eighth wire W8 that electrically connect the insulating chip 70 and the control circuit chip 80. The sealing resin 120 seals the insulating chip 70, the seventh wire W7, and the eighth wire W8.

[0133] With this configuration, the semiconductor device 10 incorporates an insulating chip 70, which protects the control circuit chip 80 and the switch circuit chip 90 when static electricity or the like is applied to the semiconductor device 10. In addition, compared to the case where the insulating chip 70 is provided outside the semiconductor device 10, the distance of the path electrically connecting the insulating chip 70 and the control circuit chip 80 can be shortened. Therefore, the inductance caused by this path distance can be reduced.

[0134] (1-7) The semiconductor device 10 further comprises a drive circuit chip 60 mounted on a second die pad 111, and a fourth wire W4 and a fifth wire W5 connecting the insulating chip 70 and the drive circuit chip 60. The sealing resin 120 seals the drive circuit chip 60, the fourth wire W4, and the fifth wire W5.

[0135] This configuration allows for a shorter distance in the path between the drive circuit chip 60 and the insulating chip 70 compared to the case where the drive circuit chip 60 is located outside the semiconductor device 10. Therefore, the inductance caused by this path distance can be reduced.

[0136] (1-8) The semiconductor device 10 further comprises a fourth terminal 112 and a sixth terminal 114 arranged separately from the second die pad 111, and a fifth terminal 113 integrated with the second die pad 111. The fourth terminal 112, the sixth terminal 114, and the fifth terminal 113 are arranged on the opposite side of the second die pad 111 from the first die pad 101. The sixth terminal 114 is arranged on the side of the first die pad 101 from which the fourth terminal 112 and the fifth terminal 113 are arranged.

[0137] This configuration allows for a larger creepage distance between the third terminal 104 and the fourth to sixth terminals 112 to 114. Therefore, a decrease in the dielectric strength of the semiconductor device 10 can be suppressed.

[0138] <Second Embodiment> The semiconductor device 10 of the second embodiment will be described with reference to Figures 10 and 11. The semiconductor device 10 of the second embodiment differs from the semiconductor device 10 of the first embodiment mainly in that the insulating chip 70 is omitted and in the configuration of the control circuit chip 80. In the following, components common to the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0139] [Overall configuration of semiconductor device] Figure 10 shows a schematic planar structure of the semiconductor device 10 according to the second embodiment. As shown in Figure 10, the semiconductor device 10 of the second embodiment includes a drive circuit chip 60, a control circuit chip 80, and a switch circuit chip 90 as semiconductor chips. The configurations of the drive circuit chip 60 and the switch circuit chip 90 are the same as in the first embodiment.

[0140] The second die pad 111 is equipped with a drive circuit chip 60. On the other hand, in the second embodiment, since the insulating chip 70 is not equipped, the X-direction dimension of the second die pad 111 may be smaller than the X-direction dimension of the second die pad 111 in the first embodiment.

[0141] The semiconductor device 10 includes a 12th wire W12 and a 13th wire W13 in place of the 4th to 7th wires W4 to W7 of the first embodiment. The 12th wire W12 and the 13th wire W13 connect the drive circuit chip 60 and the control circuit chip 80. The 12th wire W12 connects the 4th pad 63D of the drive circuit chip 60 and the 1st pad 83A of the control circuit chip 80. The 13th wire W13 connects the 5th pad 63E of the drive circuit chip 60 and the 2nd pad 83B of the control circuit chip 80. The 12th wire W12 and the 13th wire W13 are sealed by a sealing resin 120 (see Figure 4). The 12th wire W12 and the 13th wire W13 are, for example, bonding wires and are made of a material including Au, Al, Cu, Ag, etc. Here, the 12th wire W12 and the 13th wire W13 are examples of "chip connecting members".

[0142] In the second embodiment, the X-direction dimension of the control circuit chip 80 is larger than that of the control circuit chip 80 in the first embodiment. Consequently, the X-direction dimension of the first die pad 101 on which the control circuit chip 80 is mounted is larger than that of the first die pad 101 in the first embodiment. The X-direction dimension of the first die pad 101 is larger than that of the second die pad 111.

[0143] [Outline configuration of the control circuit chip] Figure 11 schematically shows the cross-sectional structure of the control circuit chip 80 shown in Figure 10. For convenience, the 9th wire W9 and the 13th wire W13 are omitted in Figure 11.

[0144] As shown in Figure 11, the control circuit chip 80 includes a transformer 31, a rectifier circuit 41, and a gate voltage control circuit 42. The second insulator 82 of the control circuit chip 80 may include an insulating layer 82A containing at least one of SiO2 and SiN, and a protective layer 82B provided on the insulating layer 82A. The protective layer 82B may be made of, for example, PI.

[0145] Both the rectifier circuit 41 and the gate voltage control circuit 42 are provided within a second semiconductor layer 81A, which is provided on the second semiconductor substrate 81. The transformer 31 is provided within the insulating layer 82A. The first coil 32 and the second coil 33 of the transformer 31 are arranged opposite each other in the Z direction. The second coil 33 is positioned closer to the second semiconductor substrate 81 relative to the first coil 32. The first inner end 32A of the first coil 32 (see Figure 4) is connected to the first pad 83A (see Figure 2) by the first inner wiring 74 (see Figure 4). The first outer end 32B of the first coil 32 (see Figure 5) is connected to the second pad 83B by the first outer wiring 75. The second inner end 33A of the second coil 33 (see Figure 4) is connected to the rectifier circuit 41 by the second inner wiring 76 (see Figure 4). The second outer end 33B of the second coil 33 (see Figure 5) is connected to the rectifier circuit 41 by the second outer wiring 77.

[0146] The wiring 86A (see Figure 10) and wiring 86B of the third connecting wiring 86, which individually connects the third pad 83C and the fourth pad 83D to the gate voltage control circuit 42, extend through the insulating layer 82A in the Z direction. The wiring 86B that connects to the fourth pad 83D is electrically connected to the second semiconductor substrate 81, as in the first embodiment. The wiring 86A that connects to the third pad 83C is not electrically connected to the second semiconductor substrate 81, as in the first embodiment.

[0147] [Effects of the second embodiment] The semiconductor device 10 of the second embodiment provides the following advantages. (2-1) The semiconductor device 10 includes a second die pad 111 positioned at a distance from the first die pad 101, a drive circuit chip 60 mounted on the second die pad 111, and a 12th wire W12 and a 13th wire W13 connecting the control circuit chip 80 and the drive circuit chip 60. The drive circuit chip 60 includes a drive circuit 20 that outputs a signal to the control circuit chip 80. The control circuit chip 80 includes a rectifier circuit 41, a first coil 32 electrically connected to the drive circuit 20, a second coil 33 positioned opposite the first coil 32 and electrically connected to the rectifier circuit 41, and a gate voltage control circuit 42 electrically connected to the rectifier circuit 41. The sealing resin 120 seals the drive circuit chip 60, the 12th wire W12, and the 13th wire W13.

[0148] This configuration allows for a reduction in the number of semiconductor chips within the semiconductor device 10. In addition, it reduces the number of connecting members (wires) that connect the semiconductor chips. Therefore, the configuration of the semiconductor device 10 can be simplified. Furthermore, the inductance caused by the connecting members (wires) can be reduced.

[0149] <Third Embodiment> The semiconductor device 10 of the third embodiment will be described with reference to Figures 12 and 13. The main difference between the semiconductor device 10 of the third embodiment and the semiconductor device 10 of the first embodiment is that it includes a plurality of switch circuits 50. In the following, components common to the first embodiment will be denoted by the same reference numerals, and their descriptions will be omitted.

[0150] [Circuit configuration of an isolation switch] Referring to Figure 12, the circuit configuration of the isolation switch 800 equipped with the semiconductor device 10 of the third embodiment will be described. Figure 12 shows a schematic circuit configuration of the isolation switch 800.

[0151] As shown in Figure 12, the semiconductor device 10 has multiple switch circuits 50, including a first switch circuit 50A and a second switch circuit 50B. The control circuit 40 is configured to individually control the driving of the first switch circuit 50A and the second switch circuit 50B. The semiconductor device 10 includes first to third terminals 11A to 13A corresponding to the first switch circuit 50A, first to third terminals 11B to 13B corresponding to the second switch circuit 50B, a fourth terminal 14, a fifth terminal 15, a sixth terminal 16A corresponding to the first switch circuit 50A, and a sixth terminal 16B corresponding to the second switch circuit 50B.

[0152] The drive circuit 20 includes a first pulse signal generation circuit 21A, a second pulse signal generation circuit 21B, and an oscillator circuit 22. The oscillator circuit 22 is electrically connected individually to the first pulse signal generation circuit 21A and the second pulse signal generation circuit 21B. The power supply circuit 821 is electrically connected to the first pulse signal generation circuit 21A, the second pulse signal generation circuit 21B, and the oscillator circuit 22 through the fourth terminal 14 and the fifth terminal 15. The signal generation circuit 822 is electrically connected individually to the first pulse signal generation circuit 21A and the second pulse signal generation circuit 21B. More specifically, the signal generation circuit 822 is electrically connected to the first pulse signal generation circuit 21A through the sixth terminal 16A. The signal generation circuit 822 is electrically connected to the second pulse signal generation circuit 21B through the sixth terminal 16B.

[0153] The first pulse signal generation circuit 21A is configured to generate a first pulse signal for controlling the drive of the first switch circuit 50A based on the control signal S1A of the signal generation circuit 822 and the clock signal CLK of the oscillator circuit 22. The second pulse signal generation circuit 21B is configured to generate a second pulse signal for controlling the drive of the second switch circuit 50B based on the control signal S1B of the signal generation circuit 822 and the clock signal CLK of the oscillator circuit 22.

[0154] The isolation circuit 30 includes a first transformer 31A and a second transformer 31B. The configuration of these transformers 31A and 31B is the same as, for example, the transformer 31 of the first embodiment (see Figure 1). The first coil 32 of the first transformer 31A is electrically connected to the first pulse signal generation circuit 21A. The first coil 32 of the second transformer 31B is electrically connected to the second pulse signal generation circuit 21B.

[0155] The control circuit 40 includes a first control circuit 40A electrically connected to the first switch circuit 50A, and a second control circuit 40B electrically connected to the second switch circuit 50B. The first control circuit 40A includes a first rectifier circuit 41A and a first gate voltage control circuit 42A. The first rectifier circuit 41A is electrically connected to the second coil 33 of the first transformer 31A. The first rectifier circuit 41A is configured to rectify the induced current generated in the second coil 33 of the first transformer 31A. The first gate voltage control circuit 42A is electrically connected to the first rectifier circuit 41A. The first gate voltage control circuit 42A is configured to supply gate voltages to the first transistor 51 and the second transistor 52 of the first switch circuit chip 90A.

[0156] The second control circuit 40B includes a second rectifier circuit 41B and a second gate voltage control circuit 42B. The second rectifier circuit 41B is configured to rectify the induced current generated in the second coil 33 of the second transformer 31B. The second rectifier circuit 41B is electrically connected to the second coil 33 of the second transformer 31B. The second gate voltage control circuit 42B is electrically connected to the second rectifier circuit 41B. The second gate voltage control circuit 42B is configured to supply gate voltages to the first transistor 51 and the second transistor 52 of the second switch circuit chip 90B.

[0157] Both the first switch circuit 50A and the second switch circuit 50B include a first transistor 51 and a second transistor 52. The electrical connection configuration between the first transistor 51 and the second transistor 52 in each switch circuit 50A and 50B is the same as in the first embodiment. The first gate voltage control circuit 42A is individually electrically connected to the gates of each transistor 51 and 52 in the first switch circuit 50A and to the node ND between the sources of each transistor 51 and 52. The second gate voltage control circuit 42B is individually electrically connected to the gates of each transistor 51 and 52 in the second switch circuit 50B and to the node ND between the sources of each transistor 51 and 52.

[0158] In the first switch circuit 50A, the drain of the first transistor 51 is electrically connected to the first terminal 11A, and the drain of the second transistor 52 is electrically connected to the second terminal 12A. Node ND between the sources of each transistor 51 and 52 in the first switch circuit 50A is electrically connected to the third terminal 13A. In the second switch circuit 50B, the drain of the first transistor 51 is electrically connected to the first terminal 11B, and the drain of the second transistor 52 is electrically connected to the second terminal 12B. Node ND between the sources of each transistor 51 in the second switch circuit 50B is electrically connected to the third terminal 13B.

[0159] In the example shown in Figure 12, the first load 811A is electrically connected between the high-potential terminal 831 and the first terminal 11A. The second terminal 12A is electrically connected to the low-potential terminal 832. The first load 811B is electrically connected between the high-potential terminal 831 and the first terminal 11B. The second terminal 12B is electrically connected to the low-potential terminal 832. Alternatively, the second load 812 shown in Figure 1 may be connected to the first terminals 11A and 11B.

[0160] [Configuration of semiconductor device] The configuration of the semiconductor device 10 of the third embodiment will be described with reference to Figure 13. Figure 13 schematically shows the planar structure of the semiconductor device 10 of Figure 12. For the circuits included in each chip in the following description, please refer to Figure 12.

[0161] As shown in Figure 13, the semiconductor device 10 includes a plurality of control circuit chips 80 and a plurality of switch circuit chips 90. The multiple control circuit chips 80 include a first control circuit chip 80A which includes a first control circuit 40A, and a second control circuit chip 80B which includes a second control circuit 40B. The multiple switch circuit chips 90 include a first switch circuit chip 90A which includes a first switch circuit 50A, and a second switch circuit chip 90B which includes a second switch circuit 50B.

[0162] The first support member 100 includes first terminals 102A and 103A corresponding to the first switch circuit chip 90A, first terminals 102B and 103B corresponding to the second switch circuit chip 90B, and third terminals 104A and 104B. The first terminals 102A and 102B, the second terminals 103A and 103B, and the third terminals 104A and 104B are positioned in the X direction on the opposite side of the first die pad 101 from the second support member 110. The third terminals 104A and 104B are integrated with the first die pad 101. The third terminal 104A is positioned between the first terminal 102A and the second terminal 103A in the Y direction. The third terminal 104B is positioned between the first terminal 102B and the second terminal 103B in the Y direction.

[0163] The second support member 110 includes a fourth terminal 112 and a fifth terminal 113, a sixth terminal 114A corresponding to the first switch circuit chip 90A, and a sixth terminal 114B corresponding to the second switch circuit chip 90B. The fourth terminal 112, the fifth terminal 113, and the sixth terminals 114A and 114B are positioned in the X direction on the opposite side of the second die pad 111 from the first support member 100. The fifth terminal 113 is integrated with the second die pad 111.

[0164] The drive circuit chip 60 includes a first pad 63A and a second pad 63B, a third pad 63CA corresponding to the sixth terminal 114A, and a third pad 63CB corresponding to the sixth terminal 114B. The semiconductor device 10 includes a third wire W3A connecting the sixth terminal 114A and the third pad 63CA, and a third wire W3B connecting the sixth terminal 114B and the third pad 63CB. The first pad 63A, the second pad 63B, the third pad 63CA, the fourth pad 63DA, and the fifth pad 63EA are located on the fourth chip surface 60S closer to the sealing side 125 of the sealing resin 120. The third pad 63CB, the fourth pad 63DB, and the fifth pad 63EB are located on the fourth chip surface 60S closer to the sealing side 126 of the sealing resin 120.

[0165] The first pad 63A, the second pad 63B, and the third pad 63CA are electrically connected to the first pulse signal generation circuit 21A. The first pad 63A, the second pad 63B, and the third pad 63CB are electrically connected to the second pulse signal generation circuit 21B. The first pad 63A and the second pad 63B are electrically connected to the oscillation circuit 22.

[0166] The drive circuit chip 60 includes a fourth pad 63DA and a fifth pad 63EA electrically connected to the first pulse signal generation circuit 21A, and a fourth pad 63DB and a fifth pad 63EB electrically connected to the second pulse signal generation circuit 21B.

[0167] The insulating chip 70 includes a first transformer 31A and a second transformer 31B. The first transformer 31A and the second transformer 31B are arranged side by side in the Y direction, for example, in a plan view. The first transformer 31A is located on the third chip surface 70S closer to the sealing side surface 125 of the sealing resin 120. The second transformer 31B is located on the third chip surface 70S closer to the sealing side surface 126 of the sealing resin 120. The configuration of each transformer 31A, 31B may be the same as, for example, the transformer 31 of the first embodiment.

[0168] The insulating chip 70 includes first to fourth pads 73AA to 73DA and 73AB to 73DB. The first to fourth pads 73AA to 73DA correspond to the first transformer 31A, and the first to fourth pads 73AB to 73DB correspond to the second transformer 31B. The first to fourth pads 73AA to 73DA are located on the third chip surface 70S closer to the sealing side surface 125 of the sealing resin 120. The first to fourth pads 73AB to 73DB are located on the third chip surface 70S closer to the sealing side surface 126 of the sealing resin 120.

[0169] The first pad 73AA and the second pad 73BA are electrically connected to the first coil 32 of the first transformer 31A. The third pad 73CA and the fourth pad 73DA are electrically connected to the second coil 33 of the first transformer 31A. The first pad 73AB and the second pad 73BB are electrically connected to the first coil 32 of the second transformer 31B. The third pad 73CB and the fourth pad 73DB are electrically connected to the second coil 33 of the second transformer 31B.

[0170] The semiconductor device 10 includes fourth wires W4A, W4B and fifth wires W5A, W5B. The fourth wire W4A connects the fourth pad 63DA of the drive circuit chip 60 to the first pad 73AA of the isolation chip 70. The fifth wire W5A connects the fifth pad 63EA of the drive circuit chip 60 to the second pad 73BA of the isolation chip 70. The fourth wire W4B connects the fourth pad 63DB of the drive circuit chip 60 to the first pad 73AB of the isolation chip 70. The fifth wire W5B connects the fifth pad 63EB of the drive circuit chip 60 to the second pad 73BB of the isolation chip 70. As a result, the first pulse signal generation circuit 21A and the first coil 32 of the first transformer 31A are electrically connected, and the second pulse signal generation circuit 21B and the first coil 32 of the second transformer 31B are electrically connected.

[0171] Each of the first control circuit chip 80A and the second control circuit chip 80B has the same configuration as the control circuit chip 80 of the first embodiment. That is, each of the first control circuit chip 80A and the second control circuit chip 80B includes a second chip surface 80S and a second chip back surface 80R, a second semiconductor substrate 81, and a second insulator 82.

[0172] Both the first control circuit chip 80A and the second control circuit chip 80B are mounted on the first die pad 101. Both the first control circuit chip 80A and the second control circuit chip 80B are bonded to the first die pad 101 by a second conductive bonding material SD2 (see Figure 3). The first control circuit chip 80A and the second control circuit chip 80B are positioned at the same location in the X direction and spaced apart from each other in the Y direction.

[0173] The first control circuit chip 80A includes first to fourth pads 83AA to 83DA. The first pad 83AA and the second pad 83BA are electrically connected to the first rectifier circuit 41A. The third pad 83CA and the fourth pad 83DA are electrically connected to the first gate voltage control circuit 42A. The fourth pad 83DA is electrically connected to a second semiconductor substrate 81 (not shown) in the first control circuit chip 80A. The third pad 83CA is not electrically connected to the second semiconductor substrate 81 in the first control circuit chip 80A.

[0174] The second control circuit chip 80B includes first to fourth pads 83AB to 83DB. The first pad 83AB and the second pad 83BB are electrically connected to the second rectifier circuit 41B. The third pad 83CB and the fourth pad 83DB are electrically connected to the second gate voltage control circuit 42B. The fourth pad 83DB is electrically connected to a second semiconductor substrate 81 (not shown) in the second control circuit chip 80B. The third pad 83CB is not electrically connected to the second semiconductor substrate 81 in the second control circuit chip 80B.

[0175] The semiconductor device 10 includes sixth wires W6A, W6B and seventh wires W7A, W7B. The sixth wire W6A connects the third pad 73CA of the insulating chip 70 to the first pad 83AA of the first control circuit chip 80A. The seventh wire W7A connects the fourth pad 73DA of the insulating chip 70 to the second pad 83BA of the first control circuit chip 80A. The sixth wire W6B connects the third pad 73CB of the insulating chip 70 to the first pad 83AB of the second control circuit chip 80B. The seventh wire W7B connects the fourth pad 73DB of the insulating chip 70 to the second pad 83BB of the second control circuit chip 80B.

[0176] Each of the first switch circuit chip 90A and the second switch circuit chip 90B has the same configuration as the switch circuit chip 90 of the first embodiment. Both the first switch circuit chip 90A and the second switch circuit chip 90B are mounted on the first die pad 101. Both the first switch circuit chip 90A and the second switch circuit chip 90B are bonded to the first die pad 101 by a first conductive bonding material SD1 (see Figure 3). The first switch circuit chip 90A and the second switch circuit chip 90B are positioned at the same location in the X direction and spaced apart from each other in the Y direction.

[0177] The first switch circuit chip 90A includes first to fourth pads 93AA to 93DA. The first pad 93AA is electrically connected to the gate of the first transistor 51 and the gate of the second transistor 52 of the first switch circuit 50A. The second pad 93BA is electrically connected to node ND between the source of the first transistor 51 and the source of the second transistor 52 of the first switch circuit 50A. The third pad 93CA is electrically connected to the drain of the first transistor 51 of the first switch circuit 50A. The fourth pad 93DA is electrically connected to the drain of the second transistor 52 of the first switch circuit 50A.

[0178] The second switch circuit chip 90B includes first to fourth pads 93AB to 93DB. The first pad 93AB is electrically connected to the gate of the first transistor 51 and the gate of the second transistor 52 of the second switch circuit 50B. The second pad 93BB is electrically connected to node ND between the source of the first transistor 51 and the source of the second transistor 52 of the second switch circuit 50B. The third pad 93CB is electrically connected to the drain of the first transistor 51 of the second switch circuit 50B. The fourth pad 93DB is electrically connected to the drain of the second transistor 52 of the second switch circuit 50B.

[0179] The semiconductor device 10 includes eighth to eleventh wires W8A to W11A and W8B to W11B. The eighth wire W8A connects the third pad 83CA of the first control circuit chip 80A to the first pad 93AA of the first switch circuit chip 90A. The ninth wire W9A connects the fourth pad 83DA of the first control circuit chip 80A to the second pad 93BA of the first switch circuit chip 90A. The tenth wire W10A connects the third pad 93CA of the first switch circuit chip 90A to the first terminal 102A. The eleventh wire W11A connects the fourth pad 93DA of the first switch circuit chip 90A to the second terminal 103A. The eighth wire W8B connects the third pad 83CB of the second control circuit chip 80B to the first pad 93AB of the second switch circuit chip 90B. The ninth wire W9B connects the fourth pad 83DB of the second control circuit chip 80B to the second pad 93BB of the first switch circuit chip 90A. The tenth wire W10B connects the third pad 93CB of the second switch circuit chip 90B to the first terminal 102B. The eleventh wire W11B connects the fourth pad 93DA of the second switch circuit chip 90B to the second terminal 103B.

[0180] Here, the first pad 93AA of the first switch circuit chip 90A corresponds to the "first input pad," and the second pad 93BA corresponds to the "second input pad." The first pad 93AB of the second switch circuit chip 90B corresponds to the "third input pad," and the second pad 93BB corresponds to the "fourth input pad." The third pad 83CA of the first control circuit chip 80A corresponds to the "first output pad," and the fourth pad 83DA corresponds to the "second output pad." The third pad 83CB of the second control circuit chip 80B corresponds to the "third output pad," and the fourth pad 83DB corresponds to the "fourth output pad." The eighth wire W8A corresponds to the "first connecting component," the ninth wire W9A corresponds to the "second connecting component," the eighth wire W8B corresponds to the "third connecting component," and the ninth wire W9B corresponds to the "fourth connecting component." The sixth wires W6A, W6B and the seventh wires W7A, W7B correspond to "relay connection members". The fourth wires W4A, W4B and the fifth wires W5A, W5B correspond to "intermediate connection members". The fourth terminal 112 corresponds to the "power terminal", the fifth terminal 113 corresponds to the "ground terminal", and the sixth terminals 114A, 114B correspond to "signal terminals". The first wire W1 corresponds to the "power connection member", and the third wires W3A, W3B correspond to "signal connection members". The third pad 93CA of the first switch circuit chip 90A and the third pad 93CB of the second switch circuit chip 90B correspond to the "first power pad". The fourth pad 93DA of the first switch circuit chip 90A and the fourth pad 93DB of the second switch circuit chip 90B correspond to the "second power pad". The 10th wires W10A and W10B correspond to the "first power supply connection component," and the 11th wires W11A and W11B correspond to the "second power supply connection component."

[0181] [Effects of the third embodiment] According to the semiconductor device 10 of the third embodiment, the following effects can be obtained. (3-1) The semiconductor device 10 includes a first switch circuit chip 90A and a second switch circuit chip 90B as switch circuit chips. Each of the first switch circuit chip 90A and the second switch circuit chip 90B includes a first transistor 51 and a second transistor 52 whose sources are connected in series with each other. Both the first transistor 51 and the second transistor 52 are high electron mobility transistors containing nitride semiconductors. The sources of the first transistor 51 and the second transistor 52 of each of the first switch circuit chip 90A and the second switch circuit chip 90B are electrically connected to the first die pad 101 through the control circuit chip 80.

[0182] In this configuration, the sources of the first transistor 51 and the second transistor 52 of the first switch circuit chip 90A are electrically connected to the first semiconductor substrate 91 of the first switch circuit chip 90A through the control circuit chip 80, the second conductive bonding material SD2, the first die pad 101, and the first conductive bonding material SD1. As a result, the source potential of each transistor 51, 52 is equal to the potential of the first semiconductor substrate 91 of the first switch circuit chip 90A, thereby stabilizing the potential of the first semiconductor substrate 91 of the first switch circuit chip 90A. Consequently, the electrical characteristics of the first switch circuit chip 90A can be stabilized.

[0183] Furthermore, the sources of the first transistor 51 and the second transistor 52 of the second switch circuit chip 90B are electrically connected to the first semiconductor substrate 91 of the second switch circuit chip 90B through the control circuit chip 80, the second conductive bonding material SD2, the first die pad 101, and the first conductive bonding material SD1. As a result, the source potential of each transistor 51 and 52 is equal to the potential of the first semiconductor substrate 91 of the second switch circuit chip 90B, thereby stabilizing the potential of the first semiconductor substrate 91 of the second switch circuit chip 90B. Consequently, the electrical characteristics of the second switch circuit chip 90B can be stabilized.

[0184] <Example of changes> Each of the above embodiments can be implemented with the following modifications. Furthermore, each of the above embodiments and the following modifications can be combined with each other to the extent that they do not contradict each other technically.

[0185] The third embodiment may be combined with the second embodiment. In the first and second embodiments, the position of the third terminal 104 of the first support member 100 can be arbitrarily changed. For example, the third terminal 104 may be positioned closer to the sealing side surface 125 of the sealing resin 120 than the first terminal 102 in a plan view. For example, the third terminal 104 may be positioned closer to the sealing side surface 126 than the second terminal 103 in a plan view. For example, the third terminal 104 may be exposed from the sealing side surface 125 or the sealing side surface 126 instead of the sealing side surface 124. The arrangement of the first to third terminals 102A to 104A and the arrangement of the first to third terminals 102B to 104B of the first support member 100 in the third embodiment can also be changed in the same way.

[0186] In the first and second embodiments, the third terminal 104 of the first support member 100 may be provided in multiple locations. In the third embodiment, one of the third terminals 104A and 104B of the first support member 100 may be omitted.

[0187] In the first and second embodiments, the arrangement of the fourth to sixth terminals 112 to 114 of the second support member 110 can be arbitrarily changed. For example, the fifth terminal 113 may be positioned between the fourth terminal 112 and the sixth terminal 114 in the Y direction.

[0188] In the third embodiment, the arrangement of the fourth terminal 112, fifth terminal 113, and sixth terminals 114A, 114B of the second support member 110 can be arbitrarily changed. In each embodiment, the thickness T2 of the insulating layer 92 can be arbitrarily changed. For example, the thickness T2 of the insulating layer 92 may be greater than or equal to the thickness T1 of the first semiconductor substrate 91.

[0189] In each embodiment, the material constituting the insulating layer 92 can be arbitrarily changed as long as it is an insulating material. In each embodiment, the doping layer 94BA may be omitted from the switch circuit chip 90.

[0190] In each embodiment, the configuration of the insulating layer 92 and the nitride semiconductor layer 94 can be arbitrarily changed. In one example, the insulating layer 92 and the buffer layer 94A and doping layer 94BA of the nitride semiconductor layer 94 may be used as insulating layers to insulate the first semiconductor substrate 91 from the first transistor 51 and the second transistor 52. In this case, the nitride semiconductor layer 94 is composed of an electron transport layer 94B and an electron supply layer 94C. In another example, the buffer layer 94A may include the insulating layer 92. In this case, the buffer layer 94A may be used as an insulating layer to insulate the first semiconductor substrate 91 from the first transistor 51 and the second transistor 52. In yet another example, the doping layer 94BA may be omitted from the nitride semiconductor layer 94. In yet another example, the buffer layer 94A may be omitted from the switch circuit chip 90. In this case, the switch circuit chip 90 may include an insulating layer interposed between the first semiconductor substrate 91 and the electron transport layer 94B in the Z direction.

[0191] In each embodiment, the configuration of the switch circuit chip 90 (first switch circuit chip 90A and second switch circuit chip 90B) can be arbitrarily changed. In one example, a source electrode 97S may be provided for each transistor element. In this case, each source electrode 97S may be electrically connected to each other by source wiring 99S. In another example, the switch circuit chip 90 (first switch circuit chip 90A and second switch circuit chip 90B) may include, instead of the second pad 93B, a first source pad electrically connected to the source electrode 97S of the first transistor 51 and a second source pad electrically connected to the source electrode 97S of the second transistor 52. The first source pad may be connected to the fourth pad 83D of the control circuit chip 80 by a first source connection member such as a wire. The second source pad may be connected to the fourth pad 83D of the control circuit chip 80 by a second source connection member such as a wire. In this case, the ninth wire W9 may be omitted.

[0192] In the first embodiment, the configurations of the drive circuit chip 60 and the isolation chip 70 can be arbitrarily changed. For example, the semiconductor device 10 may have a configuration in which the transformer 31 of the isolation chip 70 is built into the drive circuit chip 60. In other words, the isolation chip 70 may be omitted. More specifically, as shown in Figure 14, the fourth insulator 62 of the drive circuit chip 60 includes an insulating layer 62A provided on the fourth semiconductor layer 61A and a protective layer 62B provided on the insulating layer 62A. The transformer 31 is provided on the insulating layer 62A. The first coil 32 of the transformer 31 is electrically connected to the pulse signal generation circuit 21. The second coil 33 is electrically connected to the third pad 63C and the fourth pad 63D.

[0193] In the second embodiment, the position of the transformer 31 in a plan view can be arbitrarily changed. In one example, the transformer 31 may be positioned so as to overlap with at least one of the rectifier circuit 41 and the gate voltage control circuit 42 in a plan view.

[0194] In each embodiment, the configuration of the first insulating element and the second insulating element of the insulating chip 70 is not limited to the transformer 31 and can be arbitrarily changed. In one example, as shown in Figure 15, the insulating chip 70 may include a capacitor 130 instead of the transformer 31. The capacitor 130 may include a first electrode plate 131 as the first insulating element and a second electrode plate 132 as the second insulating element. The first electrode plate 131 and the second electrode plate 132 are arranged opposite each other in the Z direction. The first electrode plate 131 is positioned closer to the first semiconductor substrate 91 relative to the second electrode plate 132 in the Z direction. The first electrode plate 131 is electrically connected to the first pad 73A by a first connecting wire 141. The configuration of the first connecting wire 141 may be the same as, for example, the first inner wiring 74 (see Figure 4). The second electrode plate 132 is electrically connected to the third pad 73C by a second connecting wire 142. The configuration of the second connection wiring 142 may be the same as, for example, the first outer wiring 75 (see Figure 4). In the first and second embodiments, the insulating chip 70 may omit the second pad 73B and the fourth pad 73D. Accordingly, the semiconductor device 10 may omit the fifth wire W5 and the seventh wire W7.

[0195] In each embodiment, the material constituting the fourth semiconductor substrate 61 of the drive circuit chip 60 can be arbitrarily changed. For example, the fourth semiconductor substrate 61 may be made of a nitride semiconductor. Alternatively, the drive circuit chip 60 may use a conductive substrate or an insulating substrate instead of the fourth semiconductor substrate 61.

[0196] In each embodiment, the material constituting the third semiconductor substrate 71 of the insulating chip 70 can be arbitrarily changed. For example, the third semiconductor substrate 71 may be made of a nitride semiconductor. Alternatively, the insulating chip 70 may use a conductive substrate or an insulating substrate instead of the third semiconductor substrate 71.

[0197] In each embodiment, the material constituting the second semiconductor substrate 81 of the control circuit chip 80 can be arbitrarily changed. For example, the second semiconductor substrate 81 may be made of a nitride semiconductor. Alternatively, the control circuit chip 80 may use a conductive substrate instead of the second semiconductor substrate 81.

[0198] In the first embodiment, the insulating chip 70 may be positioned adjacent to the drive circuit chip 60 in the Y direction. In the first embodiment, the insulating chip 70 may be mounted on the first die pad 101. In this case, the insulating chip 70 may be positioned adjacent to the control circuit chip 80 in the Y direction.

[0199] In the first embodiment, the drive circuit chip 60 may be omitted from the semiconductor device 10. Accordingly, the first to third wires W1 to W3 may be omitted. In this case, the sixth terminal 114 may be omitted from the second support member 110. The fourth wire W4 connects the fourth terminal 112 to the first pad 63A of the drive circuit chip 60. The fifth wire W5 connects the fifth terminal 113 to the second pad 63B of the drive circuit chip 60.

[0200] In each embodiment, the second support member 110, the drive circuit chip 60, and the insulating chip 70 may be omitted from the semiconductor device 10. That is, as shown in Figure 16, the semiconductor device 10 may include a first die pad 101, a control circuit chip 80 and a switch circuit chip 90 mounted on the first die pad 101, and a sealing resin 120 that seals the first die pad 101, the control circuit chip 80, and the switch circuit chip 90. In this case, the semiconductor device 10 may include first to third terminals 102 to 104, a fourth terminal 105, and a fifth terminal 106 as external terminals. The first to third terminals 102 to 104 are the same as in each embodiment. The fourth terminal 105 and the fifth terminal 106 are located on the opposite side of the first die pad 101 from the first to third terminals 102 to 104. The fourth terminal 105 and the fifth terminal 106 are located spaced apart from the first die pad 101. The fourth terminal 105 and the fifth terminal 106 are partially sealed by the sealing resin 120.

[0201] The semiconductor device 10 includes a 14th wire W14 and a 15th wire W15. The 14th wire W14 and the 15th wire W15 are, for example, bonding wires and are made of a material including Au, Al, Cu, Ag, etc. The 14th wire W14 and the 15th wire W15 are sealed by a sealing resin 120.

[0202] The 14th wire W14 connects the first pad 83A and the fourth terminal 105 of the control circuit chip 80. This electrically connects the first pad 83A and the fourth terminal 105. The 15th wire W15 connects the second pad 83B and the fifth terminal 106 of the control circuit chip 80. This electrically connects the second pad 83B and the fifth terminal 106. As a result, the fourth terminal 105 and the fifth terminal 106 are electrically connected to the rectifier circuit 41 (see Figure 1) of the control circuit 40.

[0203] In the modified example shown in Figure 16, the configuration of the control circuit chip 80 can be arbitrarily changed. For example, the control circuit chip 80 may include a transformer 31, as in the control circuit chip 80 of the second embodiment.

[0204] In each embodiment, the connecting members that connect semiconductor chips to each other, or to a semiconductor chip and a terminal, are not limited to wires and can be changed as desired. For example, the connecting member may be a clip.

[0205] One or more of the various examples described in this disclosure can be combined to the extent that they do not contradict the technical context. As used in this disclosure, the term “on” includes the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, for example, the expression “the first element is positioned on the second element” is intended to mean that in one embodiment the first element may be in contact with and directly positioned on the second element, while in other embodiments the first element may be positioned above the second element without contact. In other words, the term “on” does not preclude structures in which other elements are formed between the first and second elements.

[0206] The Z-direction used in this disclosure does not necessarily have to be vertical, nor does it have to perfectly coincide with the vertical. Therefore, the various structures described herein are not limited to the "up" and "down" in the Z-axis direction being the same as the "up" and "down" in the vertical direction. For example, the X-direction may be vertical, or the Y-direction may be vertical.

[0207] <Note> The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments described above. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0208] [Note 1] First die pad (101), A switch circuit chip (90) mounted on the first die pad (101), A control circuit chip (80) is mounted on the first die pad (101) and includes a control circuit (40) that controls the driving of the switch circuit chip (90), A first conductive bonding material (SD1) is used to bond the first die pad (101) and the switch circuit chip (90), A second conductive bonding material (SD2) is used to bond the first die pad (101) and the control circuit chip (80), A first terminal (102) and a second terminal (103) are arranged at a distance from the first die pad (101), A sealing resin (120) that at least seals the first conductive bonding material (SD1), the second conductive bonding material (SD2), the switch circuit chip (90), and the control circuit chip (80), while at least partially exposing both the first terminal (102) and the second terminal (103), Equipped with, The aforementioned switch circuit chip (90) is First chip surface (90S) and The back surface (90R) of the first chip, which is opposite to the front surface (90S) of the first chip, A first semiconductor substrate (91) which constitutes the back surface (90R) of the first chip and is bonded to the first die pad (101) by the first conductive bonding material (SD1), An insulating layer (92) provided on the first semiconductor substrate (91), A first transistor (51) and a second transistor (52) are provided between the insulating layer (92) and the first chip surface (90S) in the thickness direction (Z) of the switch circuit chip (90), and their sources are connected to each other. Includes, Both the first transistor (51) and the second transistor (52) are high electron-mobility transistors containing a nitride semiconductor. The source of the first transistor (51) and the source of the second transistor (52) are electrically connected to the first die pad (101) through the control circuit chip (80). Semiconductor device (10).

[0209] [Note 2] The aforementioned control circuit chip (80) The second chip surface (80S) and The back surface (80R) of the second chip, which is opposite to the front surface (80S) of the second chip, The second semiconductor substrate (81) constitutes the back surface (80R) of the second chip and is bonded to the first die pad (101) by the second conductive bonding material (SD2), The first output pad (83C) exposed from the second chip surface (80S), The second semiconductor substrate (81) is electrically connected to the second output pad (83D) exposed from the second chip surface (80S), Includes, The aforementioned switch circuit chip (90) is A first input pad (93A) is exposed from the surface (90S) of the first chip and is electrically connected to both the gate of the first transistor (51) and the gate of the second transistor (52), A second input pad (93B) is exposed from the surface (90S) of the first chip and electrically connected to the source of the first transistor (51) and the source of the second transistor (52), Includes, A first connecting member (W8) connects the first output pad (83C) and the first input pad (93A), A second connecting member (W9) connects the second output pad (83D) and the second input pad (93B), Equipped with The semiconductor device described in Appendix 1.

[0210] [Note 3] Including a third terminal (104) integrated with the first die pad (101), A portion of the third terminal (104) is exposed from the sealing resin (120). Semiconductor device as described in Appendix 1 or 2.

[0211] [Note 4] The third terminal (104) is positioned on the side of the first die pad (101) where the first terminal (102) and the second terminal (103) are located. Semiconductor device as described in Appendix 3.

[0212] [Note 5] The third terminal (104) is provided between the first terminal (102) and the second terminal (103). Semiconductor device as described in Appendix 4.

[0213] [Note 6] The thickness (T2) of the insulating layer (92) is thinner than the thickness (T1) of the first semiconductor substrate (91). A semiconductor device as described in any one of the appendices 1 to 5.

[0214] [Note 7] The insulating layer (92) is made of a material containing AlN. A semiconductor device as described in any one of the appendices 1 to 6.

[0215] [Note 8] The aforementioned switch circuit chip (90) is A buffer layer (94A) provided on the insulating layer (92), An electron transport layer (94B) provided on the buffer layer (94A), Includes, The buffer layer (94A) is made of a material containing AlGaN, The electron transport layer (94B) includes a doped layer (94BA) made of a material containing GaN doped with acceptor-type impurities. The doping layer (94BA) is provided in the electron transport layer (94B) closer to the buffer layer (94A). Semiconductor device as described in Appendix 7.

[0216] [Note 9] The aforementioned switch circuit chip (90) is An electron supply layer (94C) is provided on the electron transport layer (94B) and is made of a nitride semiconductor having a larger band gap than the electron transport layer (94B), A source electrode (97S) is provided on the electron supply layer (94C), A first drain electrode (97DA) and a second drain electrode (97DB) are provided on the electron supply layer (94C) and are spaced apart on both sides of the source electrode (97S), A gate electrode (97G) is provided on the electron supply layer (94C) and is positioned in a plan view between the source electrode (97S) and the first drain electrode (97DA), and between the source electrode (97S) and the second drain electrode (97DB), including Semiconductor device as described in Appendix 8.

[0217] [Note 10] The switch circuit chip (90) includes a gate layer (96) interposed between the gate electrode (97G) and the electron supply layer (94C). Semiconductor device as described in Appendix 9.

[0218] [Note 11] A second die pad (111) is positioned at a distance from the first die pad (101), The insulating chip (70) mounted on the second die pad (111), Intermediate connecting members (W6, W7) electrically connect the insulating chip (70) and the control circuit chip (80), Furthermore, The sealing resin (120) seals the insulating chip (70) and the relay connection members (W6, W7). A semiconductor device as described in any one of the appendices 1 to 10.

[0219] [Note 12] The drive circuit chip (60) mounted on the second die pad (111), Intermediate connecting members (W4, W5) that connect the insulating chip (70) and the drive circuit chip (60), Furthermore, The sealing resin (120) seals the drive circuit chip (60) and the intermediate connecting members (W4, W5). The semiconductor device described in Appendix 11.

[0220] [Note 13] The insulating chip (70) is positioned between the drive circuit chip (60) and the control circuit chip (80) in the arrangement direction (X) of the first die pad (101) and the second die pad (102). The semiconductor device described in Appendix 12.

[0221] [Note 14] The aforementioned insulating tip (70) is The third chip surface (70S) and The back surface (70R) of the third chip, which is opposite to the front surface (70S) of the third chip, The third semiconductor substrate (71) that constitutes the back surface (70R) of the third chip, A third insulator (72) provided on the third semiconductor substrate (71), The first insulating element (32 / 131) provided on the third insulator (72), A second insulating element (33 / 132) is provided on the third insulator (72) and is positioned opposite the first insulating element (32 / 131), including A semiconductor device as described in any one of the appendices 11 to 13.

[0222] [Note 15] A second die pad (111) is positioned at a distance from the first die pad (101), The drive circuit chip (60) mounted on the second die pad (111), A chip connecting member (W12, W13) connects the control circuit chip (80) and the drive circuit chip (60), Furthermore, The drive circuit chip (60) includes a drive circuit (20) that outputs a signal to the control circuit chip (80), The control circuit (40) is Rectifier circuit (41), A gate voltage control circuit (42) electrically connected to the rectifier circuit (41), Includes, The aforementioned control circuit chip (80) The first insulating element (32 / 131) is electrically connected to the drive circuit (20), A second insulating element (33 / 132) is positioned opposite the first insulating element (32 / 131) and is electrically connected to the rectifier circuit (41), Includes, The sealing resin (120) seals the drive circuit chip (60) and the chip connecting members (W12, W13). A semiconductor device as described in any one of the appendices 1 to 10.

[0223] [Note 16] A second die pad (111) is positioned at a distance from the first die pad (101), The drive circuit chip (60) mounted on the second die pad (111), A chip connecting member (W12, W13) connects the control circuit chip (80) and the drive circuit chip (60), Furthermore, The aforementioned drive circuit chip (60) First insulating element (32 / 131), A second insulating element (33 / 132) is positioned opposite the first insulating element (32 / 131), A drive circuit (20) that outputs a signal to the first insulating element (32 / 131), Includes, The control circuit chip (80) includes a gate voltage control circuit (42) and a rectifier circuit (41) as the control circuit (40), The sealing resin (120) seals the drive circuit chip (60) and the chip connecting members (W12, W13). A semiconductor device as described in any one of the appendices 1 to 10.

[0224] [Note 17] A power terminal (112) and a signal terminal (114) are located separately from the second die pad (111), The ground terminal (113) is integrated with the second die pad (111), A power connection member (W1) connects the drive circuit chip (60) and the power terminal (112), A signal connection member (W3) connects the drive circuit chip (60) and the signal terminal (114), Furthermore, The sealing resin (120) seals the power connection member (W1) and the signal connection member (W3), and also partially seals the power terminal (112), the signal terminal (114), and the ground terminal (113). Semiconductor device as described in Appendix 12 or 13.

[0225] [Note 18] The power terminal (112), the signal terminal (114), and the ground terminal (113) are located on the opposite side of the second die pad (111) from the first die pad (101). Semiconductor device as described in Appendix 17.

[0226] [Note 19] The aforementioned switch circuit chip (90) is A first power supply pad (93C) is exposed from the surface (90S) of the first chip and is electrically connected to the drain of the first transistor (51), A second power supply pad (93D) is exposed from the surface (90S) of the first chip and is electrically connected to the drain of the second transistor (52), Includes, A first power connection member (W10) connects the first power pad (93C) and the first terminal (102), A second power connection member (W11) that connects the second power pad (93D) and the second terminal (103); comprising The encapsulating resin (120) encapsulates both the first power connection member (W10) and the second power connection member (W11). The semiconductor device according to any one of Appendices 1 to 18.

[0227] [Appendix 20] The first semiconductor substrate (91) is made of a material containing Si. The semiconductor device according to any one of Appendices 1 to 19.

[0228] [Appendix 21] The second semiconductor substrate (81) is made of a material containing Si. The semiconductor device according to Appendix 2.

[0229] [Appendix 22] The third semiconductor substrate (71) is made of a material containing Si. The semiconductor device according to Appendix 14.

[0230] [Appendix 23] Both the first insulating element and the second insulating element are coils (32, 33). The semiconductor device according to any one of Appendices 14 to 16.

[0231] [Appendix 24] Both the first insulating element and the second insulating element are electrode plates (131, 132). The semiconductor device according to any one of Appendices 14 to 16.

[0232] [Appendix 25] The drive circuit chip (60) is a fourth chip surface (60S), a fourth chip back surface (60R) opposite to the fourth chip surface (60S), a fourth semiconductor substrate (61) constituting the fourth chip back surface (60R), Includes, The fourth semiconductor substrate (61) is made of a material containing Si. A semiconductor device as described in any one of the appendices 12, 13, and 15-18.

[0233] [Note 26] The semiconductor device (10) includes a first switch circuit chip (90A) and a second switch circuit chip (90B) as the switch circuit chips. Each of the first switch circuit chip (90A) and the second switch circuit chip (90B) includes the first transistor (51) and the second transistor (52) whose sources are connected in series with each other. The sources of the first transistor (51) and the second transistor (52) of the first switch circuit chip (90A) and the second switch circuit chip (90B) are electrically connected to the first die pad (101) through the control circuit chip (80). A semiconductor device as described in any one of the appendices 1 to 25.

[0234] [Note 27] The control circuit chip (80) includes a first control circuit chip (80A) and a second control circuit chip (80B), Each of the first control circuit chip (80A) and the second control circuit chip (80B) is: The second chip surface (80S) and The back surface (80R) of the second chip, which is opposite to the front surface (80S) of the second chip, The second semiconductor substrate (81) constitutes the back surface (80R) of the second chip and is bonded to the first die pad (101) by the second conductive bonding material (SD2), Includes, The first control circuit chip (80A) is, The first output pad (83CA) exposed from the second chip surface (80S) of the first control circuit chip (80A), The first control circuit chip (80A) is electrically connected to the second semiconductor substrate (81), and the second output pad (83DA) is exposed from the second chip surface (80S) of the first control circuit chip (80A), Includes, The second control circuit chip (80B) is, The third output pad (83CB) exposed from the second chip surface (80S) of the second control circuit chip (80B), The second control circuit chip (80B) is electrically connected to the second semiconductor substrate (81), and the fourth output pad (83DB) is exposed from the second chip surface (80S) of the second control circuit chip (80B), Includes, The first switch circuit chip (90A) is, A first input pad (93AA) is exposed from the surface of the first chip (90S) and is electrically connected to both the gate of the first transistor (51) and the gate of the second transistor (52) of the first switch circuit chip (90A), A second input pad (93BA) is exposed from the surface of the first chip (90S) and is electrically connected to the source of the first transistor (51) and the source of the second transistor (52) of the first switch circuit chip (90A), Includes, The second switch circuit chip (90B) is, A third input pad (93AB) is exposed from the surface of the first chip (90S) and electrically connected to both the gate of the first transistor (51) and the gate of the second transistor (52) of the second switch circuit chip (90B), A fourth input pad (93BB) is exposed from the surface of the first chip (90S) and electrically connected to the source of the first transistor (51) and the source of the second transistor (52) of the second switch circuit chip (90B), Includes, A first connecting member (W8A) connects the first output pad (83CA) and the first input pad (93AA), A second connection member (W9A) that connects the second output pad (83DA) and the second input pad (93BA); A third connection member (W8B) that connects the third output pad (83CB) and the third input pad (93AB); A fourth connection member (W9B) that connects the fourth output pad (83DB) and the fourth input pad (93BB); Comprising The semiconductor device according to Supplementary Note 26.

[0235] [Supplementary Note 28] The control circuit (40) includes a first control circuit (40A) and a second control circuit (40B), The first control circuit chip (80A) includes the first control circuit (40A), The second control circuit chip (80B) includes the second control circuit (40B), The first control circuit (40A) includes a first rectifier circuit (41A) and a first gate voltage control circuit (42A) electrically connected to the first switch circuit chip (90A), The second control circuit (40B) includes a second rectifier circuit (41B) and a second gate voltage control circuit (42B) electrically connected to the second switch circuit chip (90B). The semiconductor device according to Supplementary Note 27.

[0236] [Supplementary Note 29] The semiconductor device (10) according to any one of Supplementary Notes 1 to 28; A power supply circuit (821) electrically connected to the semiconductor device (10) and configured to supply an operating voltage to the semiconductor device (10); A signal generation circuit (822) electrically connected to the semiconductor device (10) and configured to output a control signal (S1) for controlling a load (810) electrically connected to the semiconductor device (10); Comprising an isolation switch (800).

[0237] The above description is for illustrative purposes only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims. [Explanation of symbols]

[0238] 10… Semiconductor equipment 11~16...1st~6th terminal 11A~13A, 11B~13B...1st~3rd terminal 16A,16B…6th terminal 20…Drive circuit 21...Pulse signal generation circuit 21A...First pulse signal generation circuit 21B...Second pulse signal generation circuit 22...Oscillator circuit 30…Isolated circuits 31…Trans 31A...First Transformer 31B... Second transformer 32...First coil 32A…First inner end 32B...First outer end 33... Second coil 33A…Second inner end 33B…Second outer end 40...Control circuit 40A...First control circuit 40B...Second control circuit 41... Rectifier circuit 41A…1st rectifier circuit 41B…Second rectifier circuit 42...Gate voltage control circuit 42A...First gate voltage control circuit 42B...Second gate voltage control circuit 50…Switch circuit 51…First transistor 52...2nd transistor 60…Driver circuit chip 60S…Fourth chip surface 60R…4th chip, back side 61…Fourth semiconductor substrate 61A...Fourth semiconductor layer 62...Fourth insulator 62A...Insulating layer 62B…Protective layer 63A~63E…Pads 1~5 63CA~63EA, 63CB~63EB…3rd to 5th pads 70…Insulating tip 70S…Third chip surface 70R…3rd chip back side 71…Third semiconductor substrate 71A...Third semiconductor layer 72...Third insulator 72A…Insulating film 72AA...First insulating film 72AB...Second insulating film 72AC... The bottommost insulating film 72AD... The outermost insulating film 72B... Passivation membrane 72C…Protective film 73A~73D, 73AA~73DA, 73AB~73DB…1st to 4th pads 74...1st inner wiring 75...1st outer wiring 76…Second inner wiring 77…Second outer wiring 78... Dummy coil 79...Connection wiring 80…Control circuit chip 80A…First control circuit chip 80B…Second control circuit chip 80S…Second chip surface 80R…Backside of the second chip 81...Second semiconductor substrate 81A...Second semiconductor layer 82...Second insulator 82A...Insulating layer 82B…Protective layer 83A~83D, 83AA~83DA, 83BA~83DB… 1st to 4th pads 84-86...1st-3rd connection wiring 86A, 86B… wiring 87...Fourth connection wiring 88... Fifth connection wiring 90…Switch circuit chip 90A…First switch circuit chip 90B…Second switch circuit chip 90S…First chip surface 90R…Back of the first chip 91...First semiconductor substrate 92...Insulating layer 93A~93D, 93AA~93DA, 93AB~93DB…1st to 4th pads 94… Nitride semiconductor layer 94A... Buffer layer 94B...Electron transport layer 94BA... Dope layer 94C…electron supply layer 95... Two-dimensional electron gas (2DEG) 96...Gate Layer 97DA...First drain electrode 97DB...Second drain electrode 97S…Source electrode 97G… TG 98...First insulator 98A... Passivation membrane 98AA…Source opening 98AB...First drain opening 98AC...Second drain opening 98B...First interlayer insulating film 98C...Second interlayer insulating film 98D…Protective film 99DA...First drain wiring 99DB...Second drain wiring 99DP...1st drain via 99DQ...2nd Drain Beer 99S... Source wiring 99SP... Source Beer 99SQ...Source connection wiring 99G...Gate wiring 99GP...Gate Beer 100...First support member 101...First die pad 102~104, 102A~104A, 102B~104B…1st to 3rd terminals 105…4th terminal 106...5th terminal 110...Second support member 111...Second die pad 112~114...4th~6th terminal 114A,114B…6th terminal 120…Sealing resin 121…Sealing top surface 122...Sealing bottom surface 123~126…Sealing side 800... Insulated switch 810... Load 811,811A,811B…1st load 812…Second load 821…Power circuit 822…Signal generation circuit 831... High-potential terminal 832…Low potential terminal CLK...clock signal ND...Node SD1...First conductive bonding material SD2…Second conductive bonding material SD3…Third conductive bonding material SD4... Fourth conductive bonding material S1, S1A, S1B... Control signals S2…Drive signal SP...Pulse signal W1~W15…Wires 1 to 15 W3A, W3B... Third wire W4A~W11A, W4B~W11B…4th to 11th wires T1...Thickness of the first semiconductor substrate T2...Thickness of the insulating layer T3...Thickness of the nitride semiconductor layer

Claims

1. First die pad and A switch circuit chip mounted on the first die pad, A control circuit chip mounted on the first die pad, which includes a control circuit for controlling the drive of the switch circuit chip, A first conductive bonding material for joining the first die pad and the switch circuit chip, A second conductive bonding material that joins the first die pad and the control circuit chip, A first terminal and a second terminal are arranged spaced apart from the first die pad, A sealing resin that at least seals the first conductive bonding material, the second conductive bonding material, the switch circuit chip, and the control circuit chip, while at least partially exposing both the first terminal and the second terminal, Equipped with, The aforementioned switch circuit chip is The first chip surface and The back surface of the first chip, which is opposite to the front surface of the first chip, A first semiconductor substrate which constitutes the back surface of the first chip and is bonded to the first die pad by the first conductive bonding material, An insulating layer provided on the first semiconductor substrate, A first transistor and a second transistor are provided between the insulating layer and the surface of the first chip in the thickness direction of the switch circuit chip, with their sources connected to each other. Includes, Both the first transistor and the second transistor are high electron-mobility transistors containing nitride semiconductors. The sources of the first transistor and the second transistor are electrically connected to the first die pad through the control circuit chip. Semiconductor equipment.

2. The aforementioned control circuit chip is The second chip surface and The back surface of the second chip, which is opposite to the front surface of the second chip, A second semiconductor substrate which constitutes the back surface of the second chip and is bonded to the first die pad by the second conductive bonding material, The first output pad exposed from the surface of the second chip, The second output pad is electrically connected to the second semiconductor substrate and is exposed from the surface of the second chip, Includes, The aforementioned switch circuit chip is A first input pad is exposed from the surface of the first chip and electrically connected to both the gate of the first transistor and the gate of the second transistor, A second input pad is exposed from the surface of the first chip and electrically connected to the source of the first transistor and the source of the second transistor, Includes, A first connecting member that connects the first output pad and the first input pad, A second connecting member that connects the second output pad and the second input pad, Equipped with The semiconductor device according to claim 1.

3. Including a third terminal integrated with the first die pad, A portion of the third terminal is exposed from the sealing resin. The semiconductor device according to claim 1.

4. The third terminal is positioned on the side of the first die pad where the first and second terminals are located. The semiconductor device according to claim 3.

5. The third terminal is provided between the first terminal and the second terminal. The semiconductor device according to claim 4.

6. The thickness of the insulating layer is thinner than the thickness of the first semiconductor substrate. The semiconductor device according to claim 1.

7. The insulating layer is made of a material containing AlN. The semiconductor device according to claim 1.

8. The aforementioned switch circuit chip is A buffer layer provided on the insulating layer, An electron transport layer provided on the buffer layer, Includes, The buffer layer is made of a material containing AlGaN, The electron transport layer includes a doped layer made of a material containing GaN doped with acceptor-type impurities, The doped layer is provided in the electron transport layer, closer to the buffer layer. The semiconductor device according to claim 7.

9. The aforementioned switch circuit chip is An electron supply layer provided on the electron transport layer and composed of a nitride semiconductor having a band gap larger than that of the electron transport layer, A source electrode provided on the electron supply layer, A first drain electrode and a second drain electrode are provided on the electron supply layer and are arranged spaced apart on both sides of the source electrode, A gate electrode is provided on the electron supply layer and, in a plan view, is positioned between the source electrode and the first drain electrode, and between the source electrode and the second drain electrode, including The semiconductor device according to claim 8.

10. The switch circuit chip includes a gate layer interposed between the gate electrode and the electron supply layer. The semiconductor device according to claim 9.

11. A second die pad is positioned at a distance from the first die pad, The insulating chip mounted on the second die pad, A relay connecting member that electrically connects the insulating chip and the control circuit chip, Furthermore, The sealing resin seals the insulating chip and the relay connection member. The semiconductor device according to claim 1.

12. The drive circuit chip mounted on the second die pad, An intermediate connecting member that connects the insulating chip and the drive circuit chip, Furthermore, The sealing resin seals the drive circuit chip and the intermediate connecting member. The semiconductor device according to claim 11.

13. The insulating chip is positioned between the drive circuit chip and the control circuit chip in the arrangement direction of the first die pad and the second die pad. The semiconductor device according to claim 12.

14. The aforementioned insulating chip is The third chip surface and The back surface of the third chip, opposite to the front surface of the third chip, The third semiconductor substrate that constitutes the back surface of the aforementioned third chip, A third insulator provided on the third semiconductor substrate, The first insulating element provided on the third insulator, A second insulating element is provided on the third insulating element and is positioned opposite the first insulating element, including The semiconductor device according to claim 11.

15. A second die pad is positioned at a distance from the first die pad, The drive circuit chip mounted on the second die pad, A chip connecting member that connects the control circuit chip and the drive circuit chip, Furthermore, The drive circuit chip includes a drive circuit that outputs a signal to the control circuit chip. The aforementioned control circuit is Rectifier circuit and A gate voltage control circuit electrically connected to the rectifier circuit, Includes, The aforementioned control circuit chip is A first insulating element electrically connected to the aforementioned drive circuit, A second insulating element is positioned opposite the first insulating element and electrically connected to the rectifier circuit, Includes, The sealing resin seals the drive circuit chip and the chip connecting member. The semiconductor device according to claim 1.

16. A second die pad is positioned at a distance from the first die pad, The drive circuit chip mounted on the second die pad, A chip connecting member that connects the control circuit chip and the drive circuit chip, Furthermore, The aforementioned drive circuit chip is First insulating element and A second insulating element is positioned opposite the first insulating element, A drive circuit that outputs a signal to the first insulating element, Includes, The control circuit chip includes a gate voltage control circuit and a rectifier circuit as the control circuit. The sealing resin seals the drive circuit chip and the chip connecting member. The semiconductor device according to claim 1.

17. Power terminals and signal terminals are arranged separately from the second die pad, The ground terminal integrated with the second die pad, A power connection member that connects the drive circuit chip and the power terminal, A signal connection member that connects the drive circuit chip and the signal terminal, Furthermore, The sealing resin seals the power connection member and the signal connection member, and partially seals the power terminal, the signal terminal, and the ground terminal. The semiconductor device according to claim 12.

18. The power terminal, the signal terminal, and the ground terminal are located on the opposite side of the second die pad from the first die pad. The semiconductor device according to claim 17.

19. The aforementioned switch circuit chip is A first power supply pad is exposed from the surface of the first chip and is electrically connected to the drain of the first transistor, A second power supply pad is exposed from the surface of the first chip and electrically connected to the drain of the second transistor, Includes, A first power connection member that connects the first power pad and the first terminal, A second power connection member that connects the second power pad and the second terminal, Equipped with, The sealing resin seals both the first power connection member and the second power connection member. The semiconductor device according to claim 1.

20. A semiconductor device according to any one of claims 1 to 19, A power supply circuit is electrically connected to the semiconductor device and configured to supply an operating voltage to the semiconductor device. A signal generation circuit is electrically connected to the semiconductor device and configured to output a control signal for controlling a load electrically connected to the semiconductor device. An insulated switch equipped with this feature.

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