Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can generate a correct over-temperature detection signal for the output transistor even when a reverse current is generated from the load towards the output transistor. [Solution] The temperature sensing diode 13 is formed on the semiconductor substrate adjacent to the power transistor 7 and generates a forward voltage Vf with a magnitude that reflects the temperature of the power transistor 7. The over-temperature detection circuit 62 detects over-temperature of the power transistor 7 by comparing the magnitude of the forward voltage Vf with a reference voltage VREF, and asserts an over-temperature detection signal OT1 in that case. The reverse current detection circuit 65 detects the occurrence of a reverse current Iinv in the power transistor 7 and asserts a reverse current detection signal INVD during the period in which it occurs. The semiconductor device 101 then uses the reverse current detection signal INVD to perform, for example, masking the over-temperature detection signal OT1.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that supplies power to an externally connected load. [Background technology]

[0002] Patent Document 1 describes a load drive circuit capable of detecting overcurrent and overtemperature and performing appropriate protective actions. The load drive circuit comprises an output transistor, an overcurrent detection circuit and an overtemperature detection circuit for detecting overcurrent and overtemperature in the output transistor, respectively, a cutoff circuit for controlling the output transistor to turn off in response to the detection of overcurrent or overtemperature, and a holding circuit. The holding circuit holds the overcurrent detection signal and then releases the holding of the overcurrent detection signal in response to an external signal. The overtemperature detection circuit detects overtemperature when the detected temperature is greater than the determination temperature and then releases the overtemperature detection state when the temperature becomes less than the determination temperature. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2014-60581 [Overview of the project] [Problems that the invention aims to solve]

[0004] For example, as shown in Patent Document 1, a semiconductor device equipped with an output transistor and an over-temperature detection circuit is known. The over-temperature detection circuit typically detects the temperature of the output transistor using a temperature sensing diode that generates a forward voltage corresponding to the temperature. The temperature sensing diode may be formed adjacent to the output transistor on the semiconductor substrate in order to detect the temperature of the output transistor with high accuracy.

[0005] On the other hand, when such a semiconductor device is used to intermittently supply power to a load, power supply fluctuations can cause a reverse current to flow from the load to the output transistor. This reverse current occurs, for example, when driving capacitive or inductive loads. Another example is the ripple current generated by rectification when the load is a generator, which can also be a reverse current. However, when a reverse current flows, the bias current to the temperature sensing diode located adjacent to the output transistor can change due to the parasitic current caused by the reverse current. As a result, the over-temperature detection circuit may generate an incorrect over-temperature detection signal.

[0006] The embodiments described later were made in view of these considerations, and other issues and novel features will become clear from the description and accompanying drawings of this specification. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment comprises an output transistor, a temperature sensing diode, a bias circuit, an over-temperature detection circuit, and a reverse current detection circuit. The output transistor is formed on a semiconductor substrate and connected between a power supply terminal and a power output terminal, supplying power to a load connected to the power output terminal when controlled to be ON. The temperature sensing diode is formed on the semiconductor substrate adjacent to the output transistor and generates a forward voltage whose magnitude reflects the temperature of the output transistor. The bias circuit supplies a bias current to the temperature sensing diode. The over-temperature detection circuit detects over-temperature of the output transistor by comparing the magnitude of the forward voltage with a threshold voltage and asserts an over-temperature detection signal when over-temperature is detected. The reverse current detection circuit detects the generation of a reverse current from the power output terminal to the power supply terminal and asserts a reverse current detection signal during the period in which the reverse current is generated. The semiconductor device then uses the reverse current detection signal to perform, for example, masking the over-temperature detection signal. [Effects of the Invention]

[0008] According to the above-described embodiment, even when a reverse current from a load toward the output transistor occurs, a correct overtemperature detection signal for the output transistor can be generated.

Brief Description of the Drawings

[0009] [Figure 1] FIG. 1 is a circuit diagram showing a configuration example of a main part of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a schematic diagram showing a layout configuration example of the semiconductor device in FIG. 1. [Figure 3] FIG. 3 is a cross-sectional view showing a configuration example between A-A' in FIG. 2. [Figure 4] FIG. 4 is a cross-sectional view showing a configuration example between C-C' in FIG. 2. [Figure 5A] FIG. 5A is a timing chart showing an operation example when the semiconductor device shown in FIG. 1 is in a non-overtemperature state and no reverse current is flowing. [Figure 5B] FIG. 5B is a timing chart showing an operation example when the semiconductor device shown in FIG. 1 is in a non-overtemperature state and a reverse current is flowing. ​​​​​​​​​​​​​​​​​​ [Figure 12] Figure 12 is a timing chart showing an example of operation in the semiconductor device shown in Figure 11 when it is not over-temperature and a reverse current is flowing. [Figure 13A] Figure 13A is a schematic diagram showing an example of the layout configuration of the semiconductor device in Figure 11. [Figure 13B] Figure 13B is a schematic diagram showing a different layout configuration example from Figure 13A. [Figure 13C] Figure 13C is a schematic diagram showing a different layout configuration example from Figure 13A. [Figure 13D] Figure 13D is a schematic diagram showing a different layout configuration example from Figure 13A. [Figure 14] Figure 14 is a cross-sectional view showing an example of the configuration between B and B' in Figure 13A. [Figure 15] Figure 15 is a circuit diagram showing an example configuration of a semiconductor device as a comparative example. [Figure 16] Figure 16 is a timing chart showing an example of operation in the semiconductor device shown in Figure 15 when it is not over-temperature and a reverse current is flowing. [Modes for carrying out the invention]

[0010] In the following embodiments, the description will be divided into multiple sections or embodiments where necessary for convenience. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, in the following embodiments, when referring to the number of elements (including number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that number.

[0011] Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless specifically stated or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of constituent elements, etc., it shall include those that substantially approximate or resemble such shapes, etc., unless specifically stated or considered to be not in principle. The same applies to the numerical values ​​and ranges mentioned above.

[0012] Furthermore, in the following embodiments, p-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and n-channel MOSFETs will be referred to as pMOS transistors and nMOS transistors, respectively. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all figures used to explain the embodiments, the same reference numerals will be used for identical components, and repeated explanations will be omitted.

[0013] (First Embodiment) <Circuit configuration of semiconductor device> Figure 1 is a circuit diagram showing an example of the main configuration of a semiconductor device 101 according to the first embodiment. The semiconductor device 101 shown in Figure 1 includes a power terminal 1, a power output terminal 2, a control input terminal 4, a power transistor (PT) 7, and various control circuits for controlling the power transistor (PT) 7. The various control circuits include an on / off control circuit 60, a charge pump circuit 61, control switches 12, 22, an over-temperature detection circuit 62, and a level shift circuit 63, as well as a mask circuit 64 and a reverse current detection circuit 65.

[0014] Power terminal 1 receives a battery voltage Vbat, such as 12V, from an external battery 6. This supplies the power supply voltage VCC to power terminal 1, i.e., power node N7. A load 8 is connected to power output terminal 2. Load 8 can be a capacitive or inductive load, and has a parallel-connected load 8a and a resistive load 8b. One end of load 8 is supplied with the ground power supply voltage PGND. Power output terminal 2 also generates an output voltage VOUT and an output current IOUT.

[0015] The power transistor (PT) 7 is also an output transistor connected between the power supply terminal 1 and the power output terminal 2. When controlled to be ON, the power transistor (PT) 7 supplies power to the load 8 connected to the power output terminal 2. In this example, the power transistor (PT) 7 is an nMOS transistor. The source and drain of the power transistor (PT) 7 are connected to the power output terminal 2 and the power supply terminal 1, respectively. The power transistor (PT) also has a body diode 7B with a commonly connected source and back gate as the anode and the drain as the cathode.

[0016] The control input terminal 4 receives an external on / off control signal IN. The on / off control circuit 60 exclusively controls the charge pump circuit 61 and the control switch 12 in response to the on / off control signal IN. The control switch 12 is, for example, an nMOS transistor. When the control switch 12 is controlled to be ON, it short-circuits the output node N3 of the charge pump circuit 61 and the power output terminal 2, i.e., the power output node N8.

[0017] For example, when the on / off control signal IN is at the on level, the on / off control circuit 60 activates the charge pump circuit 61. This causes the charge pump circuit 61 to generate a boosted voltage Vcp that is higher than the power supply voltage VCC. The boosted voltage Vcp is applied to the gate node N4 of the power transistor (PT) 7 via the gate resistor 11. On the other hand, when the on / off control signal IN is at the off level, the on / off control circuit 60 controls the control switch 12 to the on level. This controls the power transistor (PT) 7 to be turned off by short-circuiting the gate-source connection via the gate resistor 11 and the control switch 12.

[0018] The over-temperature detection circuit 62 protects the power transistor (PT) 7 from over-temperature, for example, in the event of a load short circuit. The over-temperature detection circuit 62 comprises a temperature sensing diode (Di) 13, a bias circuit, and a comparator 19. The temperature sensing diode (Di) 13 is positioned adjacent to the power transistor (PT) 7. As a result, the temperature sensing diode (Di) 13 generates a forward voltage Vf with a magnitude that reflects the temperature of the power transistor (PT) 7. The over-temperature detection circuit 62 basically detects over-temperature of the power transistor (PT) 7 by comparing the magnitude of the forward voltage Vf with a threshold voltage. When the over-temperature detection circuit 62 detects over-temperature, it asserts an over-temperature detection signal OT1.

[0019] In detail, the bias circuit within the over-temperature detection circuit 62 comprises nMOS transistors 20 and 21 that constitute a current mirror circuit, and a bias current source 18 that supplies a bias current Ibs to the original nMOS transistor 20. The temperature sensing diode (Di) 13 is connected in series with the mirrored nMOS transistor 21 between the power supply node N7 and the internal power supply node N9.

[0020] As a result, the bias circuit supplies a bias current Ibs to the temperature detection diode (Di) 13. That is, a diode current IDi equal to the bias current Ibs normally flows through the temperature detection diode (Di) 13. An internal power supply voltage VSS generated by a circuit not shown is supplied to the internal power supply node N9. The internal power supply voltage VSS is, for example, a voltage about 6V lower than the power supply voltage VCC of the power supply node N7.

[0021] The comparator 19 inputs, to one of its two inputs, a temperature detection voltage TSEN generated at the connection node N10 between the temperature detection diode (Di) 13 and the bias circuit. The comparator 19 inputs, to the other of its two inputs, a reference voltage VREF generated based on the power supply node N7 and representing a threshold voltage for over-temperature and, thus, a threshold temperature. Based on the negative temperature characteristic of the forward voltage Vf, the temperature detection voltage TSEN increases as the temperature rises and decreases as the temperature drops.

[0022] Therefore, when the junction temperature of the power transistor (PT) 7 is lower than the threshold temperature, that is, in a non-over-temperature state, "TSEN < VREF". Accordingly, the comparator 19 outputs a negative-level, here "H"-level, over-temperature detection signal OT1. On the other hand, when the junction temperature of the power transistor (PT) 7 is higher than the threshold temperature, that is, in an over-temperature state, "TSEN > VREF". Accordingly, the comparator 19 outputs an asserted level, here "L"-level, over-temperature detection signal OT1.

[0023] The over-temperature detection signal OT1 is output to the control switch 22 through logical inversion by the mask circuit 64 and level shift by the level shift circuit 63. The control switch 22 is, for example, an nMOS transistor and is connected in parallel to the control switch 12. When the control switch 22 is controlled to be on, it shorts the output node N3 of the charge pump circuit 61 and the power output node N8 to control the power transistor (PT) 7 to be off.

[0024] The level shift circuit 63 shifts the signal from the mask circuit 64, which is referenced to the internal power supply voltage VSS, to a signal referenced to the output voltage VOUT. The control switch 22, i.e., the nMOS transistor, receives the signal from the level shift circuit 63 as a discharge control voltage DCH between its gate and source. Details of the mask circuit 64 and the reverse current detection circuit 65 will be described later.

[0025] <Device configuration of semiconductor device> Figure 2 is a schematic diagram showing an example of the layout configuration of the semiconductor device 101 in Figure 1. The semiconductor device 101 shown in Figure 2 comprises a power transistor (PT) 7 formation region ARp and a various control circuit formation region ARc. The various control circuits are circuits for controlling the power transistor (PT) 7, as described in Figure 1. In addition, a guard ring (GR) 40 for isolation is provided between the formation region ARp and the formation region ARc.

[0026] The power transistor (PT) 7, i.e., the output transistor, is more specifically composed of multiple unit output transistors PTu connected in parallel to each other. The temperature sensing diode (Di) 13 is formed in a rectangular region ARd located inside the formation region ARp, adjacent to the unit output transistors PTu. Consequently, two or more sides constituting the rectangular region ARd are adjacent to one or more unit output transistors PTu. In this example, the temperature sensing diode (Di) 13 is formed in a rectangular region ARd located approximately in the center of the formation region ARp, from the viewpoint of detecting higher temperatures within the formation region ARp. Consequently, three sides constituting the rectangular region ARd are adjacent to one or more unit output transistors PTu.

[0027] Figure 3 is a cross-sectional view showing an example of the configuration between A and A' in Figure 2. Figure 3 illustrates the unit output transistor PTu and the temperature sensing diode (Di) 13 that constitute the power transistor (PT) 7. In Figure 3, an N-type epitaxial layer 502 is formed on an N-type semiconductor substrate 501. The unit output transistor PTu and the temperature sensing diode (Di) 13 are formed using a diffusion layer or the like placed on the surface of the epitaxial layer 502. The unit output transistor PTu and the temperature sensing diode (Di) 13 are arranged adjacent to each other and separated by a thick oxide film 503 (LOCOS).

[0028] The unit output transistor PTu is composed of a vertical nMOS transistor with the back surface of the semiconductor substrate 501 as the drain. Specifically, in the unit output transistor PTu, a Pbase diffusion layer 505, which serves as the back gate (BG), is formed on the surface of the epitaxial layer 502. Within the Pbase diffusion layer 505, N + A source (S) diffusion layer 510 and a P for supplying power to the back gate (BG) + A power supply diffusion layer 511 of the type is formed. The epitaxial layer 502 and the semiconductor substrate 501 become drains (D). The power supply voltage VCC is supplied to the drains (D), i.e., the back surface of the semiconductor substrate 501.

[0029] Furthermore, trenches 509 extending in the depth direction are formed in the epitaxial layer 502. A thin gate oxide film 506 and a polysilicon 508 that will serve as the gate (G) are embedded in the trenches 509. The source (S) diffusion layer 510 is formed in contact with the side wall of the trench 509. When a predetermined voltage is applied between the gate (G) and the source (S), a channel is formed in the Pbase diffusion layer 505 at the location of the side wall of the trench 509. As a result, a drive current flows from the back surface of the semiconductor substrate 501 towards the source (S) diffusion layer 510.

[0030] On the other hand, in the temperature sensing diode (Di) 13, the surface of the epitaxial layer 502 is P -A deep diffusion layer 504 of the P type is formed. - In the P-type diffusion layer 504, + a P-type diffusion layer 511 and an N - type shallow diffusion layer 513 are formed. In the N - type diffusion layer 513, + an N-type diffusion layer 510 and a P + type diffusion layer 511 are formed. Here, the P - type diffusion layer 511 formed within the P + type diffusion layer 504 and the N - type diffusion layer 510 formed within the N + type diffusion layer 513 are shorted by the upper metal layer. This shorted diffusion layer becomes the cathode of the temperature detection diode (Di) 13. On the other hand, the P - type diffusion layer 511 formed within the N + type diffusion layer 513 becomes the anode of the temperature detection diode (Di) 13.

[0031] Here, as shown in FIG. 3, when the unit output transistor PTu and the temperature detection diode (Di) 13 are arranged adjacent to each other, a PNP-type parasitic bipolar transistor 50 is formed therebetween. The parasitic bipolar transistor 50 operates with the back gate (BG) of the unit output transistor PTu as the emitter and the drain (D) as the base. Also, the parasitic bipolar transistor 50 uses a part of the cathode of the temperature detection diode (Di) 13, specifically, the P - type diffusion layer 511 within the P + type diffusion layer 504 as the collector.

[0032] On the premise that such a parasitic bipolar transistor 50 is formed, in the unit output transistor PTu, assume a case where an inverse current Iinv flows from the source (S) diffusion layer 510 toward the back surface of the semiconductor substrate 501, contrary to the driving current. More specifically, in FIG. 1, assume a case where, in the off state of the power transistor (PT) 7, the output voltage VOUT becomes higher than the power supply voltage VCC by, for example, 0.6V or more, and an inverse current Iinv flows through the body diode 7B.

[0033] In this case, the parasitic bipolar transistor 50 is turned on because a forward bias of 0.6V or more is applied between its base and emitter. As a result, a parasitic current Ipnp from the parasitic bipolar transistor 50 flows into the cathode of the temperature sensing diode (Di) 13. Consequently, the diode current IDi decreases by the amount of the increase in parasitic current Ipnp, causing the temperature sensing voltage TSEN to rise. For example, even if the junction temperature of the power transistor (PT) 7 is not in an over-temperature state, if the temperature sensing voltage TSEN rises above the reference voltage VREF, the comparator 19 will incorrectly assert the over-temperature detection signal OT1.

[0034] Figure 4 is a cross-sectional view showing an example configuration between C and C' in Figure 2. In addition to the unit output transistor PTu, which is the same as in Figure 3, Figure 4 shows low-voltage pMOS transistors MP-L and nMOS transistors MN-L, high-voltage pMOS transistors MP-H and nMOS transistors MN-H, and a guard ring GR. The pMOS transistors MP-L, MP-H and nMOS transistors MN-L, MN-H are included in various control circuits. The high-voltage pMOS transistors MP-H and nMOS transistors MN-H have a withstand voltage of approximately 40V, for example. On the other hand, the low-voltage pMOS transistors MP-L and nMOS transistors MN-L have a withstand voltage of approximately 6V, for example.

[0035] In the low-voltage pMOS transistor MP-L, the surface of the epitaxial layer 502 is P + The source (S) diffusion layer 511 and drain (D) diffusion layer 511 of the type, and N against the back gate. + A power supply diffusion layer 510 of the type is formed. On the epitaxial layer 502 located between the source (S) diffusion layer 511 and the drain (D) diffusion layer 511, polysilicon 508 which will serve as the gate (G) is formed via a thin gate oxide film 506.

[0036] In the low-voltage nMOS transistor MN-L, P is present on the surface of the epitaxial layer 502.- A deep diffusion layer 504 of the type, i.e., a p-well, is formed. - In the diffuse layer 504 of type N + A source (S) diffusion layer 510 and a drain (D) diffusion layer 510 of the type, and P for the back gate. + A power supply diffusion layer 511 of the type is formed. On the epitaxial layer 502 located between the source (S) diffusion layer 510 and the drain (D) diffusion layer 510, a polysilicon 508 that will serve as the gate (G) is formed via a thin gate oxide film 506.

[0037] In the high-voltage pMOS transistor MP-H, the surface of the epitaxial layer 502 is P + The source (S) diffusion layer 511 of type and N for the back gate + A power supply diffusion layer 510 of the type is formed. On the other hand, on the drain (D) side, P is released from the surface of the epitaxial layer 502. - A deep diffusion layer 512 of the type is formed. - In the type diffusion layer 512, P + A drain (D) diffusion layer 511 of type 511 is formed.

[0038] Furthermore, polysilicon 508, which forms the gate (G), is formed on the epitaxial layer 502 located between the source (S) diffusion layer 511 and the drain (D) diffusion layer 511, via a thin gate oxide film 506. However, unlike the low-voltage pMOS transistor MP-L, the gate oxide film 506 and polysilicon 508 near the drain (D) are superimposed on a thick oxide film 503 to achieve high breakdown voltage.

[0039] In the high-voltage nMOS transistor MN-H, P is present on the surface of the epitaxial layer 502. - A deep diffusion layer 504 of the type, i.e., a p-well, is formed. - In the diffuse layer 504 of type N + A source (S) diffusion layer 510 of type and P for the back gate +A power supply diffusion layer 511 of the type is formed. On the other hand, on the drain (D) side, N is emitted from the surface of the epitaxial layer 502. - A deep diffusion layer 513 of the N type is formed. - In the diffuse layer 513 of type N + A drain (D) diffusion layer 510 of type 510 is formed.

[0040] Furthermore, polysilicon 508, which will serve as the gate (G), is formed on the epitaxial layer 502 located between the source (S) diffusion layer 510 and the drain (D) diffusion layer 510, via a thin gate oxide film 506. However, unlike the low-voltage nMOS transistor MN-L, the gate oxide film 506 and polysilicon 508 near the drain (D) are superimposed on a thick oxide film 503 to achieve high breakdown voltage.

[0041] In Guard Ring GR, from the surface of the epitaxial layer 502, P - A deep diffusion layer 504 of the type, i.e., a p-well, is formed. - In the type diffusion layer 504, P + A power supply diffusion layer 511 of type P is formed. + For example, the ground power supply voltage is applied to the power supply diffusion layer 511 of this type.

[0042] As shown in Figure 4, for example, a PNP-type parasitic bipolar transistor 51 can be formed between the unit output transistor PTu and the nMOS transistor MN-H located near the unit output transistor PTu. Furthermore, by providing a guard ring GR, a PNP-type parasitic bipolar transistor 52 can also be formed between the unit output transistor PTu and the guard ring GR. The current path on the parasitic bipolar transistor 52 side has a low impedance. As a result, much of the parasitic current that could flow through the parasitic bipolar transistor 51 can be diverted to the guard ring GR.

[0043] For example, in Figure 3, if a guard ring GR as shown in Figure 4 is provided between the unit output transistor PTu and the temperature sensing diode (Di) 13, the parasitic current Ipnp flowing into the cathode of the temperature sensing diode (Di) 13 can be reduced. However, providing a guard ring GR may prevent high-precision detection of the temperature of the power transistor (PT) 7. Therefore, to eliminate the influence of the parasitic current Ipnp without providing a guard ring GR, the mask circuit 64 and reverse current detection circuit 65 shown in Figure 1 are provided.

[0044] <Details of the mask circuit and reverse current detection circuit> In Figure 1, the reverse current detection circuit 65 detects the occurrence of a reverse current Iinv from the power output terminal 2 toward the power supply terminal 1 and asserts a reverse current detection signal INVD during the period in which the reverse current Iinv is occurring. Specifically, the reverse current detection circuit 65 comprises pMOS transistors 23, 24 and nMOS transistors 25, 26 that constitute a source-input type differential amplifier circuit.

[0045] The gate of pMOS transistor 24 is connected to the drain and also to the gate of pMOS transistor 23. pMOS transistors 23 and 24 receive output voltage VOUT and power supply voltage VCC as sources, respectively. nMOS transistors 25 and 26 are supplied with an internal power supply voltage VSS as a source. nMOS transistors 25 and 26 each supply a common bias current based on a bias voltage Vbs from their drains to pMOS transistors 23 and 24.

[0046] With this configuration, the reverse current detection circuit 65 functions as a comparator that detects the relative magnitudes of the output voltage VOUT and the power supply voltage VCC, and consequently, whether or not a reverse current Iinv is present. When a reverse current Iinv is flowing, "VOUT > VCC", so the gate-source voltage of the pMOS transistor 23 becomes greater than that of the pMOS transistor 24. As a result, the reverse current detection circuit 65 outputs an assert level, in this case a "H" level reverse current detection signal INVD, to the output node N13. On the other hand, when no reverse current Iinv is flowing, the reverse current detection circuit 65 outputs a negate level, in this case a "L" level reverse current detection signal INVD.

[0047] The mask circuit 64 receives the reverse current detection signal INVD and the over-temperature detection signal (first over-temperature detection signal) OT1 from the over-temperature detection circuit 62. The mask circuit 64 then performs a predetermined logic operation to generate an over-temperature detection signal (second over-temperature detection signal) OT2, which is fixed at the negate level during the assertion period of the reverse current detection signal INVD, that is, fixed in a non-over-temperature state during the period when the reverse current Iinv is flowing.

[0048] In this example, the mask circuit 64 is composed of NOR gates. In this case, the mask circuit 64 outputs an over-temperature detection signal OT2 fixed to the negate level, in this case the "L" level, during the assertion period of the reverse current detection signal INVD, in this case the "H" level period. On the other hand, the mask circuit 64 inverts and outputs the input over-temperature detection signal OT1 during the negate period of the reverse current detection signal INVD, in this case the "L" level period. Therefore, in the over-temperature detection signal OT2, the assertion level and negate level are "H" level and "L" level, respectively, inversely to the over-temperature detection signal OT1.

[0049] The level shift circuit 63 shifts the over-temperature detection signal OT2 and outputs it to the control switch 22 as a discharge control voltage DCH. As a result, the control switch 22 is effectively turned off based on the reverse current detection signal INVD from the reverse current detection circuit 65 when the reverse current Iinv is flowing. On the other hand, when the reverse current Iinv is not flowing, the control switch 22 is effectively controlled on and off based on the over-temperature detection signal OT1 from the over-temperature detection circuit 62. For example, if an over-temperature is detected, the control switch 22 is turned on based on the asserted over-temperature detection signal OT1. This cuts off the drive current flowing through the power transistor (PT) 7, i.e., the output current IOUT to the load 8.

[0050] <Semiconductor device operation> Figure 5A is a timing chart showing an example of operation in the semiconductor device 101 shown in Figure 1 when it is not over-temperature and no reverse current Iinv is flowing. When supplying power to the load 8 as shown in Figure 1, an inrush current flows when the power transistor (PT) 7 is turned on to charge the load 8a. To suppress the inrush current, as shown in Figure 5A, an on / off control signal IN is usually used to periodically switch the device on and off. As a result, the semiconductor device 101 charges the load 8a in stages.

[0051] When the on / off control signal IN is at the "H" level, the charge pump circuit 61 performs a boost operation while the control switch 12 is turned off. As a result, the output node N3 of the charge pump circuit 61 and the gate node N4 of the power transistor (PT) 7 are boosted to a higher boost voltage Vcp than the power supply node N7. Consequently, the power transistor (PT) 7 turns on and charges the load 8a.

[0052] On the one hand, when the on-off control signal IN is at the "L" level, the control switch 12 is turned on while the charge pump circuit 61 stops its boosting operation. As a result, the voltage of the gate node N4 of the power transistor (PT) 7 is pulled down to the voltage of the power output node N8 which is the source node. Consequently, the power transistor (PT) 7 turns off and the charging of the load 8a stops. By repeating these operations, the load 8a is charged step by step while limiting the maximum value of the inrush current.

[0053] Here, in the case of a non-overtemperature state, in the overtemperature detection circuit 62, since the temperature detection voltage TSEN generated at the node N10 is lower than the reference voltage VREF, the comparator 19 outputs an overtemperature detection signal OT1 at a negative level, here the "H" level. Also, in the reverse current detection circuit 65, since "VOUT < VCC", the pMOS transistor 23 turns off through a differential amplification operation. As a result, the reverse current detection circuit 65 outputs a reverse current detection signal INVD at a negative level, here the "L" level, to the node N13.

[0054] The mask circuit 64 inputs the negative-level reverse current detection signal INVD and the negative-level overtemperature detection signal OT1, and outputs an overtemperature detection signal OT2 at a negative level, here the "L" level. In response to this, the level shift circuit 63 outputs a discharge control voltage DCH at the "L" level to the node N12 with reference to the voltage of the power output node N8. As a result, the control switch 22 maintains its off state.

[0055] On the other hand, although not shown in the diagram, in the case of an over-temperature condition, the temperature sensing voltage TSEN is higher than the reference voltage VREF, so the comparator 19 outputs an asserted level, in this case a "L" level over-temperature detection signal OT1. Also, the reverse current detection circuit 65 outputs a "L" level reverse current detection signal INVD, similar to the case of a non-over-temperature condition described above. The mask circuit 64 outputs an asserted level, in this case a "H" level over-temperature detection signal OT2, in response to the asserted level over-temperature detection signal OT1. Then, the control switch 22 is turned on based on the "H" level discharge control voltage DCH from the level shift circuit 63. As a result, the power transistor (PT) 7 is protected by being turned off.

[0056] Figure 5B is a timing chart showing an example of operation in the semiconductor device 101 shown in Figure 1 when it is not over-temperature and a reverse current Iinv is flowing. In Figure 5B, unlike in Figure 5A, at time t1, the power supply voltage VCC drops during the off period of the power transistor (PT) 7, resulting in the condition "VOUT>VCC". When the power transistor (PT) 7 is off, no channel is formed, so a reverse current Iinv can flow through the body diode 7B. In detail, the reverse current Iinv begins to flow, for example, from time t2 when "VOUT-VCC" exceeds the forward voltage of the body diode 7B, for example, about 0.6V.

[0057] When the reverse current Iinv begins to flow, the parasitic bipolar transistor 50 between the power transistor (PT) 7 and the temperature sensing diode (Di) 13 turns on because its base-emitter is forward-biased. This causes the parasitic current Ipnp to flow into the cathode of the temperature sensing diode (Di) 13. The diode current IDi is equal to the bias current Ibs when the parasitic current Ipnp is not flowing, but when the parasitic current Ipnp is flowing, it becomes "Ibs-Ipnp". The temperature sensing voltage TSEN generated at node N10 is determined based on the magnitude of this "Ibs-Ipnp".

[0058] Specifically, as the magnitude of the parasitic current Ipnp approaches the magnitude of the bias current Ibs, the diode current IDi decreases, and the value of the temperature sensing voltage TSEN approaches the value of the power supply voltage VCC. In particular, when the parasitic current Ipnp becomes larger than the bias current Ibs, the diode current IDi becomes zero, causing the temperature sensing voltage TSEN to rise significantly via the parasitic bipolar transistor 50. Due to the influence of this parasitic current Ipnp, when the temperature sensing voltage TSEN becomes higher than the reference voltage VREF of the comparator 19, the over-temperature detection signal OT1 is incorrectly asserted to the "L" level, even though it is not an over-temperature state.

[0059] In this example, the over-temperature detection signal OT1 is at an assert level from time t2 until time t3, when the power transistor (PT) 7 is turned on. When the power transistor (PT) 7 is turned on, the voltage difference between the output voltage VOUT and the power supply voltage VCC approaches zero via the power transistor (PT) 7, which is in the ON state.

[0060] In this operation, as described above, by providing the reverse current detection circuit 65 and the mask circuit 64, it is possible to control the system so that the erroneous over-temperature detection signal OT1 from the over-temperature detection circuit 62 is not transmitted to the control switch 22. Specifically, when the power supply voltage VCC becomes 0.6V or more lower than the output voltage VOUT, the reverse current detection circuit 65 outputs an assertion level, in this case an "H" level reverse current detection signal INVD, to node N13. In this example, the "H" level reverse current detection signal INVD is output during the period from time t2 to time t3.

[0061] The mask circuit 64 masks, or in other words disables, the over-temperature detection signal OT1 during the "H" level period of the reverse current detection signal INVD, so that the erroneous over-temperature detection signal OT1 is not transmitted to the control switch 22. That is, regardless of the level of the over-temperature detection signal OT1, the mask circuit 64 outputs an over-temperature detection signal OT2 that is fixed at a negate level, in this case, a "L" level. Accordingly, the control switch 22 receives a discharge control voltage DCH at a "L" level and remains in the off state.

[0062] <Regarding the differences from the semiconductor device (comparative example)> Figure 15 is a circuit diagram showing an example configuration of a comparative semiconductor device 301. Figure 16 is a timing chart showing an example of operation of the semiconductor device 301 shown in Figure 15 when it is not over-temperature and a reverse current Iinv is flowing. The comparative semiconductor device 301 shown in Figure 15 differs from the example configuration shown in Figure 1 in the following ways: First, the reverse current detection circuit 65 is not provided. Second, the mask circuit 64 is replaced by an inverter circuit 67.

[0063] In this configuration, as mentioned above, the over-temperature detection signal OT1 may be incorrectly asserted to the "L" level even when the system is not over-temperature, due to the influence of the parasitic current Ipnp associated with the reverse current Iinv. In particular, if the parasitic current Ipnp becomes larger than the bias current Ibs, the over-temperature detection signal OT1 will incorrectly become the "L" level.

[0064] As shown in Figure 16 from time t2 onwards, the over-temperature detection signal OT1 maintains an "L" level during the period when the reverse current Iinv is flowing. Consequently, the discharge control voltage DCH maintains an "H" level, and the control switch 22 remains on. As a result, the power transistor (PT) 7 remains off even when the on / off control signal IN switches to the on level, i.e., the "H" level. Consequently, as shown in Figure 16, the state in which the reverse current Iinv is flowing is prolonged, and the power transistor (PT) 7 cannot be turned on until the reverse current Iinv stops flowing.

[0065] On the other hand, using the configuration example in Figure 1, by detecting the presence of a reverse current Iinv and masking the over-temperature detection signal OT1 during the period when the reverse current Iinv is flowing, it becomes possible to control the power transistor (PT) 7 on and off based on the on / off control signal IN, even when the reverse current Iinv is flowing. Specifically, as shown from time t2 to time t3 in Figure 5B, the over-temperature detection signal OT1, which is incorrectly asserted, is masked by the mask circuit 64, so the control switch 22 remains off. As a result, at time t3, when the on / off control signal IN reaches the "H" level, the power transistor (PT) 7 turns on.

[0066] When the power transistor (PT) 7 is turned on at time t3, the reverse current Iinv that was flowing through the body diode 7B flows to the power transistor (PT) 7, which has a low channel resistance. As a result, "VOUT-VCC" becomes well below 0.6V, and the parasitic bipolar transistor 50 turns off. Accordingly, the parasitic current Ipnp becomes zero, and the over-temperature detection signal OT1 returns to the negate level. In parallel with this, the output voltage VOUT transitions to be approximately equal to the power supply voltage VCC. Also, since the charge on the load 8a is discharged through the resistive load 8b, the output voltage VOUT will eventually become lower than the power supply voltage VCC. As a result, the system returns to a normal state.

[0067] <Examples of application to electronic control units (ECUs)> Figure 6 is a circuit block diagram showing an example configuration of an electronic control unit (ECU) 401 to which the semiconductor device 101 shown in Figure 1 is applied. The electronic control unit (ECU) 401 shown in Figure 6 includes, in addition to the semiconductor device 101 shown in Figure 1, a power regulator 404 and a diode 403, and an ECU control device 402, in this case a microcontroller unit (MCU). The electronic control unit (ECU) 401 also has a power supply terminal 1A, a ground power supply terminal 5A, and a power output terminal 2A.

[0068] A battery 6 is connected between power terminal 1A and ground power terminal 5A. A load 8 is connected to power output terminal 2A. In this example, load 8 is another electronic control unit (ECU). The electronic control unit that is load 8 is equipped with load 8a, resistive load 8b, and power switch 8c, etc. Another load 80 is connected between the power output terminal of the electronic control unit, which is also the power output terminal of power switch 8c, and the ground power supply voltage PGND.

[0069] Power terminal 1A receives the battery voltage Vbat. Power regulator 404 receives the power voltage VCC obtained from power terminal 1A and generates a low-voltage power supply voltage for the ECU control device 402. The generated power supply voltage is supplied to the ECU control device 402 via diode 403. In addition, the ground power supply voltage SGND of the battery 6 is supplied to one end of the ECU control device 402 via ground power terminal 5A. Diode 403 is responsible for protecting the ECU control device 402 and prevents reverse current from flowing to the ECU control device 402 in the event of reverse connection of the battery 6, etc.

[0070] The output port of the ECU control device 402 is connected to the control input terminal 4 of the semiconductor device 101. The ECU control device 402 outputs an on / off control signal IN to the semiconductor device 101 to instruct the power transistor (PT) 7 to be turned on or off. The semiconductor device 101 controls the power supply to the load 8 based on the on / off control signal IN from the control input terminal 4. In this case, for example, even if a reverse current Iinv occurs due to a decrease in the battery voltage Vbat as described above, the power supply to the semiconductor device 101, and consequently to the load 8, can be controlled by the on / off control signal IN from the ECU control device 402.

[0071] The power supply terminal 1 of the semiconductor device 101 is supplied with a power supply voltage VCC from the power supply terminal 1A of the electronic control unit (ECU) 401. The power output terminal 2 of the semiconductor device 101 is connected to the power output terminal 2A of the electronic control unit (ECU) 401. The semiconductor device 101 also has a ground power supply terminal 5. The ground power supply voltage SGND is supplied to the ground power supply terminal 5 via the ground power supply terminal 5A of the electronic control unit (ECU) 401.

[0072] Figure 7 is a schematic diagram showing an example configuration of a vehicle 111 equipped with the electronic control unit (ECU) 401 shown in Figure 6. The vehicle 111 is, for example, an automobile. The vehicle 111 shown in Figure 7 is equipped with a battery 6, the electronic control unit 401, and loads 8 and 80, as shown in Figure 6. The electronic control unit 401 and load 8, and loads 8 and 80 are connected by wire harnesses. The ground power supply voltage PGND shown in Figure 6 is connected to, for example, the housing of the vehicle 111.

[0073] <Main effects of the first embodiment> As described above, the semiconductor device 101 according to the first embodiment has a reverse current detection circuit 65 and a mask circuit 64. This makes it possible to generate a correct over-temperature detection signal OT2 for the output transistor even when a reverse current Iinv is generated from the load 8 toward the power transistor (PT) 7, i.e., the output transistor. Furthermore, by generating a correct over-temperature detection signal OT2, malfunctions of the control switch 22 can be prevented, and situations in which the output transistor is fixed in the off position can be prevented.

[0074] (Second Embodiment) <Circuit configuration and operation of semiconductor devices> Figure 8 is a circuit diagram showing an example of the main configuration of the semiconductor device 102 according to the second embodiment. The method of the first embodiment was to generate the correct over-temperature detection signal OT2 by masking the erroneous over-temperature detection signal OT1 that may occur during the period when the reverse current Iinv is flowing. The method of the second embodiment is to generate the original over-temperature detection signal OT1 correctly.

[0075] The semiconductor device 102 shown in Figure 8 differs from the configuration example shown in Figure 1 in the following ways: First, a compensation circuit 66 is provided. Second, the mask circuit 64 is replaced with an inverter circuit 67 similar to that in Figure 15. Third, the output destination of the reverse current detection signal INVD from the reverse current detection circuit 65 is changed from the mask circuit 64 to the compensation circuit 66.

[0076] The compensation circuit 66 generates a compensation current Icps and, during the assertion period of the reverse current detection signal INVD, compensates the magnitude of the diode current IDi flowing through the temperature sensing diode (Di) 13 using the compensation current Icps. In other words, the compensation circuit 66 increases the diode current IDi, which has been reduced by the parasitic current Ipnp from the parasitic bipolar transistor 50, using the compensation current Icps.

[0077] In detail, the compensation circuit 66 has nMOS transistors 28 and 27. The nMOS transistors 28 and 27 are connected in series between the cathode of the temperature sensing diode (Di) 13, i.e., node N10, and node N9, which is supplied with the internal power supply voltage VSS. The nMOS transistor 27 is controlled by the reverse current detection signal INVD and turns on during the assertion period of the reverse current detection signal INVD, i.e., during the period when the reverse current Iinv is flowing.

[0078] The gate of nMOS transistor 28 is connected in common with the gate of nMOS transistor 20 in the over-temperature detection circuit 62. As a result, during the ON period of nMOS transistor 27, nMOS transistor 28 forms a current mirror circuit with nMOS transistor 20 as the mirror source and nMOS transistor 28 as the mirror destination. Consequently, the compensation circuit 66 can draw at least a portion of the parasitic current Ipnp to the internal power supply voltage VSS during the period when the reverse current Iinv is flowing, and thus during the period when the parasitic current Ipnp is flowing.

[0079] Figure 9 is a timing chart showing an example of operation in the semiconductor device 102 shown in Figure 8 when it is not over-temperature and a reverse current Iinv is flowing. Here, we will explain by focusing on the differences from Figure 5B. First, as in the case of Figure 5B, at time t1, the power supply voltage VCC drops during the off period of the power transistor (PT) 7, resulting in the condition "VOUT>VCC". At time t2, "VOUT-VCC" exceeds the forward voltage of the body diode 7B, for example, about 0.6V, and a reverse current Iinv begins to flow. Consequently, the parasitic bipolar transistor 50 turns on, and a parasitic current Ipnp flows into the cathode of the temperature sensing diode (Di) 13.

[0080] On the other hand, when a reverse current Iinv flows, the reverse current detection circuit 65 asserts the reverse current detection signal INVD to the "H" level. As a result, the compensation circuit 66 becomes active when the nMOS transistor 27 turns on. Here, the nMOS transistor 28 in the compensation circuit 66 forms a current mirror circuit with the nMOS transistor 20 in the over-temperature detection circuit 62, and has m times the transistor size, specifically the gate width. As a result, a compensation current Icps, which is m times the bias current Ibs, flows through the compensation circuit 66.

[0081] If the value of m is set so that the compensation current Icps is approximately the same as the parasitic current Ipnp, the compensation circuit 66 will function as a circuit that bypasses the parasitic current Ipnp. Generally, the magnitude of the bias current Ibs required to operate the temperature sensing diode (Di) 13 normally is, for example, on the order of a few uA. On the other hand, the parasitic current Ipnp can be well larger than a few uA. For this reason, the value of m can usually be well larger than 1.

[0082] By appropriately setting the value of m, the temperature sensing diode (Di) 13 will have a bias current Ibs flowing through it, even during periods when a parasitic current Ipnp is flowing. As a result, the temperature sensing voltage TSEN at node N10 will be approximately the same as the voltage obtained when neither the reverse current Iinv nor the parasitic current Ipnp is flowing. Consequently, in the non-over-temperature state, the comparator 19 outputs an over-temperature detection signal OT1 at the negate level, in this example, the "H" level, to node N11.

[0083] The "H" level over-temperature detection signal OT1 is inverted by the inverter circuit 67 and then transmitted to the control switch 22 as an "L" level discharge control voltage DCH by the level shift circuit 63. As a result, the control switch 22 remains in the off position. Consequently, as shown in Figure 15, even when a reverse current Iinv is flowing, it becomes possible to control the power transistor (PT) 7 on and off based on the on / off control signal IN.

[0084] In Figure 9, the magnitude of the diode current IDi from time t2 to time t3 is different compared to Figure 5B, and accordingly, the magnitude of the temperature detection voltage TSEN is also different. In Figure 5B, the magnitude of the temperature detection voltage TSEN exceeds the reference voltage VREF, whereas in Figure 9 it does not. This allows the over-temperature detection signal OT1 itself to be generated correctly. Furthermore, if the value of m mentioned above is ideal, the magnitude of the diode current IDi from time t2 to time t3 will be equal to the bias current Ibs.

[0085] <Regarding variations> Figure 10 is a circuit diagram showing an example of the main configuration of the semiconductor device 103 in the second embodiment, which is a modification of the configuration in Figure 8. In the configuration example shown in Figure 8, it is necessary to know the magnitude of the parasitic current Ipnp in advance in order to set the magnitude of the compensation current Icps. However, the magnitude of the parasitic current Ipnp can vary greatly due to process fluctuations. To address this, the semiconductor device 103 shown in Figure 10 is configured so that the magnitude of the compensation current Icps can be adjusted by testing the semiconductor device 103.

[0086] The semiconductor device 103 shown in Figure 10 differs from that in Figure 8 in the configuration of the compensation circuit 66B. In the compensation circuit 66B, the nMOS transistor 28 shown in Figure 8 is replaced by n nMOS transistors 28[1]-28[n] with fuses 29[1]-29[n] connected in series. Each fuse 29[1]-29[n] selects whether or not to connect the drains of the nMOS transistors 28[1]-28[n] to node N10. As a result, the compensation circuit 66B has a variable current source that can adjust the magnitude of the compensation current Icps. Note that the n nMOS transistors 28[1]-28[n] are, for example, 2 N The transistors may be configured to have different sizes within each unit.

[0087] Here, when testing the semiconductor device 103, the parasitic current Ipnp is measured first. Specifically, the bias current Ibs is set so that it does not flow through the nMOS transistor 21, and the current value flowing through node N10 is measured with an ammeter while an intentional reverse current is flowing through the power transistor (PT) 7. After that, the fuse 29[1]-29[n] is cut so that the value of the compensation current Icps is as close as possible to the current value obtained by measurement. This makes it possible to bring the diode current IDi from time t2 to time t3 closer to the bias current Ibs, for example, in Figure 9.

[0088] <Main effects of the second embodiment> As described above, the semiconductor devices 102 and 103 according to the second embodiment have a compensation circuit 66 that compensates for the magnitude of the diode current IDi by canceling out the parasitic current Ipnp with a compensation current Icps. As a result, similar to the first embodiment, even when a reverse current Iinv is generated from the load 8 toward the output transistor, a correct over-temperature detection signal OT1 for the output transistor can be generated. Furthermore, by generating a correct over-temperature detection signal OT1, malfunctions of the control switch 22 can be prevented, and situations in which the output transistor is fixed in the off position can be prevented.

[0089] Furthermore, in the second embodiment, unlike the first embodiment, the over-temperature detection signal OT1 is not masked during the period when the reverse current Iinv is flowing, and the over-temperature detection signal OT1, and consequently the temperature detection voltage TSEN, remains active. Therefore, over-temperature detection can be performed on the output transistor even during this period. Moreover, the more appropriately the compensation current Icps is set, the more accurately over-temperature detection can be performed.

[0090] (Third embodiment) <Circuit configuration and operation of semiconductor devices> Figure 11 is a circuit diagram showing an example of the main configuration of the semiconductor device 104 according to the third embodiment. The method of the third embodiment is similar to the method of the second embodiment in that it correctly generates the original over-temperature detection signal OT1 itself. However, the method of the third embodiment is capable of setting the compensation current Icps with higher precision than the method of the second embodiment.

[0091] The semiconductor device 104 shown in Figure 11 differs from those in Figures 8 and 10 in the configuration of the compensation circuit 66C. The compensation circuit 66C includes a dummy temperature sensing diode 13B. The dummy temperature sensing diode 13B is formed on the semiconductor substrate adjacent to the power transistor (PT) 7, similar to the temperature sensing diode (Di) 13.

[0092] As a result, a PNP-type parasitic bipolar transistor (second parasitic bipolar transistor) 50B, which is turned on by a reverse current Iinv, is formed between the power transistor (PT) 7 and the cathode of the dummy temperature sensing diode 13B. The compensation circuit 66C is configured to set the parasitic current (second parasitic current) Ipnp2 flowing through the parasitic bipolar transistor 50B as the compensation current Icps.

[0093] In detail, the compensation circuit 66C has nMOS transistors 27, 28B, and 30 in addition to a dummy temperature sensing diode 13B. As in Figure 8, nMOS transistor 27 is controlled to turn on and off by a reverse current sensing signal INVD. When nMOS transistor 27 is on, nMOS transistor 28B draws a compensation current Icps from the cathode of the temperature sensing diode (Di) 13 to the internal power supply voltage VSS. However, unlike in Figure 8, nMOS transistor 28B forms a current mirror circuit with nMOS transistor 30. The cathode of the dummy temperature sensing diode 13B is connected to the drain of nMOS transistor 30.

[0094] The dummy temperature sensing diode 13B is configured so that no current flows through it, and in this example, its anode and cathode are short-circuited. In other words, the dummy temperature sensing diode 13B is provided solely to allow the parasitic current Ipnp2 from the parasitic bipolar transistor 50B to flow through the nMOS transistor 30. When the parasitic current Ipnp2 flows through the parasitic bipolar transistor 50B in response to the reverse current Iinv, this parasitic current Ipnp2 flows as a compensation current Icps through the nMOS transistor 28B, which is the mirror target, with the nMOS transistor 30 as the mirror source.

[0095] Figure 12 is a timing chart showing an example of operation in the semiconductor device 104 shown in Figure 11 when it is not over-temperature and a reverse current Iinv is flowing. Here, we will explain focusing on the differences from Figure 9. Similar to the case in Figure 9, when a reverse current Iinv flows at time t2, the reverse current detection circuit 65 asserts the reverse current detection signal INVD to the "H" level. In addition, in response to the reverse current Iinv, the parasitic bipolar transistor (second parasitic bipolar transistor) 50B is also turned on in addition to the parasitic bipolar transistor (first parasitic bipolar transistor) 50.

[0096] As a result, a parasitic current (first parasitic current) Ipnp flows into the cathode of the temperature sensing diode (Di) 13. In addition, a parasitic current (second parasitic current) Ipnp2, of approximately the same magnitude as the parasitic current Ipnp, flows into the cathode of the dummy temperature sensing diode 13B. In response, a compensation current Icps, of the same magnitude as the parasitic current Ipnp2, is generated via the current mirror circuit consisting of nMOS transistors 28B and 30. Thus, the parasitic current Ipnp that flowed into the cathode of the temperature sensing diode (Di) 13 is bypassed to the compensation circuit 66C by the compensation current Icps, which is of a similar magnitude.

[0097] In Figure 12, unlike in Figure 9, the diode current IDi of the temperature sensing diode (Di) 13 is maintained at the bias current Ibs during the period from time t2 to time t3. That is, the effect of the parasitic current Ipnp is eliminated. As a result, the over-temperature detection circuit 62 can detect over-temperature with high accuracy even during the period from time t2 to time t3. For example, even if over-temperature occurs in the power transistor (PT) 7 during this period, the control switch 22 is immediately controlled to turn ON, thereby protecting the power transistor (PT) 7.

[0098] <Device configuration of semiconductor device> Figures 13A, 13B, 13C, and 13D are schematic diagrams showing different layout configurations of the semiconductor device 104 in Figure 11. The semiconductor devices 104a-104d shown in Figures 13A to 13D include a power transistor (PT) 7 formation region ARp, a various control circuit formation region ARc, and a guard ring (GR) 40, similar to the case in Figure 2. Furthermore, the semiconductor devices 104a-104d include a rectangular region (first rectangular region) ARd1 on which a temperature sensing diode (Di) 13 is formed, similar to the case in Figure 2, and also include a rectangular region (second rectangular region) ARd2 on which a dummy temperature sensing diode 13B is formed, unlike the case in Figure 2.

[0099] Figure 14 is a cross-sectional view showing an example configuration between B and B' in Figure 13A. In Figure 14, a dummy temperature sensing diode 13B having the same configuration as the temperature sensing diode (Di) 13 is added to the example configuration shown in Figure 3. In the example shown in Figure 14, the temperature sensing diode (Di) 13 and the dummy temperature sensing diode 13B are arranged adjacent to each other on both sides of the unit output transistor PTu that constitutes the power transistor (PT) 7.

[0100] Here, the semiconductor devices 104a-104d shown in Figures 13A to 13D differ in the arrangement of the dummy temperature sensing diodes 13B. The dummy temperature sensing diodes 13B are provided to obtain a parasitic current Ipnp2. For this reason, one or more sides constituting the rectangular region ARd2 must be adjacent to one or more unit output transistors PTu. Furthermore, it is desirable that the dummy temperature sensing diodes 13B obtain a parasitic current Ipnp2 that is the same magnitude as the parasitic current Ipnp flowing into the temperature sensing diode (Di) 13.

[0101] From this perspective, it is desirable that, like rectangular region ARd1, the three sides constituting rectangular region ARd2 are adjacent to one or more unit output transistors PTu. That is, from this perspective, the arrangements shown in Figures 13A and 13B are desirable. For example, one side constituting the formation region ARp, which is adjacent to the guard ring (GR) 40, is taken as the reference side. In this case, the distance between rectangular region ARd2 and the reference side is the same as that of rectangular region ARd1 in Figure 13A, and shorter than that of rectangular region ARd1 in Figure 13B. In particular, it is thought that using the arrangement shown in Figure 13A allows for highly accurate acquisition of a parasitic current Ipnp2 that is the same magnitude as the parasitic current Ipnp.

[0102] On the other hand, in Figure 13C, only two sides constituting the rectangular region ARd2 are adjacent to one or more unit output transistors PTu. Similarly, in Figure 13D, only one side constituting the rectangular region ARd2 is adjacent to one or more unit output transistors PTu. In such arrangements, the magnitude of the resulting parasitic current Ipnp2 may be smaller than the magnitude of the required parasitic current Ipnp. However, from the viewpoint of the area efficiency of the power transistor (PT) 7, the arrangements shown in Figures 13C and 13D are advantageous.

[0103] In other words, when rectangular regions ARd1 and ARd2 are placed inside the formation region ARp, a dead space may be created in the region extending from the rectangular regions ARd1 and ARd2 toward the reference edge where unit output transistors PTu are not formed, as shown in Figure 13A. As a result, the number of unit output transistors PTu constituting the power transistor (PT) 7 decreases, and the on-resistance of the power transistor (PT) 7 may increase accordingly. From this perspective, the arrangement shown in Figure 13B is more advantageous than that shown in Figure 13A.

[0104] <Main effects of the third embodiment> As described above, by using the method of the third embodiment, the same effects as those described in the second embodiment can be obtained. Furthermore, compared to the method of the second embodiment, a more accurate compensation current Icps can be obtained, thereby enabling the generation of a more accurate over-temperature detection signal OT1. For example, unlike the method shown in Figure 10, a highly accurate compensation current Icps can be obtained without depending on the current setting resolution in the compensation circuit 66B. In addition, even when the parasitic current Ipnp fluctuates depending on the operating environment of the semiconductor device, a compensation current Icps that follows these fluctuations can be obtained. Moreover, the compensation current Icps can be obtained without testing the semiconductor device.

[0105] The present invention has been described in detail above based on embodiments, but the present invention is not limited to the embodiments described above and can be modified in various ways without departing from its essence. For example, the embodiments described above are described in detail in order to explain the present invention in an easy-to-understand manner and are not necessarily limited to those having all the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add a configuration from another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with a configuration from another embodiment. [Explanation of symbols]

[0106] 1 Power terminal 2 Power output terminals 7. Power Transistors (Output Transistors) 8 loads 13. Temperature sensing diode 13B Dummy temperature sensing diode 19 Comparator 22 Control switches 50,50B Parasitic Bipolar Transistor 62 Over-temperature detection circuit 64 Mask Circuit 65 Reverse current detection circuit 66,66B Compensation circuit 101, 102, 103 Semiconductor equipment ARd,ARd1,ARd2 Rectangular area ARp, ARc formation region IDi diode current INVD Reverse Current Detection Signal Ibs bias current Icps compensation current Iinv reverse current Ipnp,Ipnp2 Parasitic current OT1 Over-temperature detection signal PTu (Unit Output Transistor) Vf (Forward Voltage)

Claims

1. An output transistor formed on a semiconductor substrate, connected between a power supply terminal and a power output terminal, and which supplies power to a load connected to the power output terminal when controlled to be ON, A temperature sensing diode is formed on the semiconductor substrate adjacent to the output transistor and generates a forward voltage of a magnitude that reflects the temperature of the output transistor, A bias circuit that supplies bias current to the temperature sensing diode, An over-temperature detection circuit that detects over-temperature of the output transistor by comparing the magnitude of the forward voltage with a threshold voltage, and asserts a first over-temperature detection signal when over-temperature is detected, A reverse current detection circuit that detects the occurrence of a reverse current from the power output terminal toward the power supply terminal and asserts a reverse current detection signal during the period in which the reverse current is occurring, A mask circuit that receives the reverse current detection signal and the first over-temperature detection signal and generates a second over-temperature detection signal fixed to the negate level during the assertion period of the reverse current detection signal, Equipped with, Semiconductor equipment.

2. In the semiconductor device described in claim 1, Furthermore, it includes a control switch that controls the output transistor to turn off during the assertion period of the second over-temperature detection signal. Semiconductor equipment.

3. In the semiconductor device described in claim 1, The output transistor is composed of a plurality of unit output transistors. The temperature sensing diode is formed in a rectangular region, Two or more sides constituting the rectangular region are adjacent to one or more unit output transistors among the plurality of unit output transistors. Semiconductor equipment.

4. In the semiconductor device described in claim 3, The output transistor is composed of a vertical n-channel MOSFET with the back surface of the semiconductor substrate as the drain. The source and drain of the output transistor are connected to the power output terminal and the power supply terminal, respectively. Between the output transistor and the temperature sensing diode, a PNP-type parasitic bipolar transistor is formed, with the back gate of the output transistor as the emitter and the drain as the base, and which is turned on by the reverse current. Semiconductor equipment.

5. In the semiconductor device described in claim 1, The aforementioned load is either a capacitive load or an inductive load. Semiconductor equipment.

6. An output transistor formed on a semiconductor substrate, connected between a power supply terminal and a power output terminal, and which supplies power to a load connected to the power output terminal when controlled to be ON, A temperature sensing diode is formed on the semiconductor substrate adjacent to the output transistor and generates a forward voltage of a magnitude that reflects the temperature of the output transistor, A bias circuit that supplies bias current to the temperature sensing diode, A reverse current detection circuit that detects the occurrence of a reverse current from the power output terminal toward the power supply terminal and asserts a reverse current detection signal during the period in which the reverse current is occurring, A compensation circuit that generates a compensation current and compensates the magnitude of the diode current flowing through the temperature sensing diode using the compensation current during the assertion period of the reverse current detection signal, An over-temperature detection circuit that detects over-temperature of the output transistor by comparing the magnitude of the forward voltage with a threshold voltage, and asserts an over-temperature detection signal when over-temperature is detected, Equipped with, Semiconductor equipment.

7. In the semiconductor device described in claim 6, Furthermore, it includes a control switch that controls the output transistor to turn off during the assertion period of the over-temperature detection signal. Semiconductor equipment.

8. In the semiconductor device described in claim 6, The output transistor is composed of a plurality of unit output transistors. The temperature sensing diode is formed in a first rectangular region, Two or more sides constituting the first rectangular region are adjacent to one or more unit output transistors among the plurality of unit output transistors. Semiconductor equipment.

9. In the semiconductor device described in claim 8, The output transistor is composed of a vertical n-channel MOSFET with the back surface of the semiconductor substrate as the drain. The source and drain of the output transistor are connected to the power output terminal and the power supply terminal, respectively. Between the output transistor and the cathode of the temperature sensing diode, a first parasitic PNP-type bipolar transistor is formed, with the back gate of the output transistor as the emitter and the drain as the base, and which is turned on by the reverse current. The magnitude of the compensation current is determined by reflecting the magnitude of the first parasitic current flowing through the first parasitic bipolar transistor. Semiconductor equipment.

10. In the semiconductor device described in claim 9, The compensation circuit increases the diode current, which has been reduced by the first parasitic current, by the compensation current. Semiconductor equipment.

11. In the semiconductor device described in claim 9, The compensation circuit includes a variable current source capable of adjusting the magnitude of the compensation current. The magnitude of the compensation current is determined during testing of the semiconductor device. Semiconductor equipment.

12. In the semiconductor device described in claim 9, The compensation circuit includes a dummy temperature sensing diode formed on the semiconductor substrate adjacent to the output transistor. A second parasitic bipolar transistor of type PNP, which is turned on by the reverse current, is formed between the output transistor and the cathode of the dummy temperature sensing diode. The compensation circuit is configured to set the second parasitic current flowing through the second parasitic bipolar transistor as the compensation current. Semiconductor equipment.

13. In the semiconductor device according to claim 12, The dummy temperature sensing diode is formed in a second rectangular region, One or more sides constituting the second rectangular region are adjacent to one or more unit output transistors among the plurality of unit output transistors. Semiconductor equipment.

14. In the semiconductor device described in claim 6, The aforementioned load is either a capacitive load or an inductive load. Semiconductor equipment.

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