Semiconductor device and method for manufacturing the same

Abstract

To improve the performance of semiconductor devices. [Solution] Chip mounting section TAB1 and chip mounting section TAB3 are electrically connected via resistor R1, and chip mounting section TAB2 and chip mounting section TAB3 are electrically connected via resistor R2.

Description

Technical Field

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[0005]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technique effective when applied to a semiconductor device and a method for manufacturing the same that enable signal transmission between different potentials.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2024-072440 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2023-181601 (Patent Document 2) describe a technique related to a transformer that enables non-contact signal transmission using inductively coupled lower and upper inductors.

[0003] [[ID=I5]] Japanese Patent Application Laid-Open No. 2010-016142 (Patent Document 3) describes a technique related to the structure of a transformer capable of dividing the breakdown voltage.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] There is a digital isolator that enables non-contact signal transmission from one circuit to another. In such a digital isolator, an improvement in the breakdown voltage is desired so that non-contact signal transmission between circuits with significantly different potentials can also be achieved.

Means for Solving the Problems

[0006] One embodiment of a semiconductor device includes a first chip mounting section to which a first potential is supplied, a first semiconductor chip disposed on the first chip mounting section, a second chip mounting section to which a second potential higher than the first potential is supplied, a second semiconductor chip disposed on the second chip mounting section, a third chip mounting section electrically connected to the first chip mounting section via a first resistive element and electrically connected to the second chip mounting section via a second resistive element, and an isolator chip disposed on the third chip mounting section. The isolator chip has a lower conductor section, a first upper conductor section formed above the lower conductor section via an insulating layer and electrically connected to the first semiconductor chip, and a second upper conductor section formed above the lower conductor section via an insulating layer, disposed separately from the first upper conductor section, and electrically connected to the second semiconductor chip.

[0007] A method for manufacturing a semiconductor device according to one embodiment includes: (a) a step of preparing a lead frame having a first chip mounting section, a second chip mounting section, and a third chip mounting section; (b) a step of placing a first semiconductor chip on the first chip mounting section via a first adhesive; (c) a step of placing a second semiconductor chip on the second chip mounting section via a second adhesive; (d) a step of placing an isolator chip on the third chip mounting section via a third adhesive; (e) a step of placing a first chip resistor via a fourth adhesive so as to span the first chip mounting section and the third chip mounting section; (f) a step of placing a second chip resistor via a fifth adhesive so as to span the second chip mounting section and the third chip mounting section; and (g) a step of performing a heat treatment on the lead frame to cure the first adhesive, second adhesive, third adhesive, fourth adhesive, and fifth adhesive after performing steps (b) to (e).

[0008] A method for manufacturing a semiconductor device according to one embodiment includes: (a) a step of preparing a lead frame having a first chip mounting section, a second chip mounting section and a third chip mounting section; (b) a step of placing a first semiconductor chip on the first chip mounting section via a first adhesive; (c) a step of placing a second semiconductor chip on the second chip mounting section via a second adhesive; (d) a step of placing an isolator chip on the third chip mounting section via a third adhesive; (e) a step of performing a first heat treatment on the lead frame to cure the first adhesive, the second adhesive and the third adhesive after performing steps (b) to (d); and (f) after step (e), The process includes: (g) connecting a semiconductor chip and a third semiconductor chip to each other electrically with a first bonding wire, and connecting a second semiconductor chip and a third semiconductor chip to each other electrically with a second bonding wire; (f) after step (f), arranging a first chip resistor via a fourth adhesive so as to span the first chip mounting portion and the third chip mounting portion; (h) arranging a second chip resistor via a fifth adhesive so as to span the second chip mounting portion and the third chip mounting portion; and (i) after performing steps (g) through (h), applying a second heat treatment to the lead frame to cure the fourth adhesive and the fifth adhesive. [Effects of the Invention]

[0009] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawing]

[0010] [Figure 1] This figure shows an example configuration of a drive control unit that drives a load circuit. [Figure 2] This is an explanatory diagram showing an example of signal transmission. [Figure 3] This diagram shows a 3-chip configuration. [Figure 4] This diagram illustrates areas for improvement. [Figure 5] This is a diagram explaining the basic concept. [Figure 6] This figure shows an example of a transformer layout configuration. [Figure 7]It is a diagram showing another example of the layout configuration of a transformer. [Figure 8A] It is a top view showing the mounting configuration of a semiconductor device. [Figure 8B] It is a cross-sectional view taken along the line A-A of FIG. 8A. [Figure 8C] It is a cross-sectional view taken along the line B-B of FIG. 8A. [Figure 9] It is a diagram showing an example of the manufacturing process of a semiconductor device in Embodiment 1. [Figure 10] It is a diagram showing an example of the manufacturing process of a semiconductor device following FIG. 9. [Figure 11] It is a diagram showing an example of the manufacturing process of a semiconductor device following FIG. 10. [Figure 12] It is a diagram showing an example of the manufacturing process of a semiconductor device following FIG. 11. [Figure 13] It is a diagram showing an example of the manufacturing process of a semiconductor device following FIG. 12. [Figure 14] It is a diagram showing an example of the manufacturing process of a semiconductor device following FIG. 13. [Figure 15] It is a diagram showing another example of the manufacturing process of a semiconductor device in Embodiment 1. [Figure 16] It is a diagram showing another example of the manufacturing process of a semiconductor device following FIG. 15. [Figure 17] It is a diagram schematically showing the "through-gate molding method". [Figure 18] It is a diagram showing the molding process in Embodiment 1. [Figure 19] It is a diagram showing the molding process following FIG. 18. [Figure 20] It is a diagram showing the molding process following FIG. 19. [Figure 21] It is a diagram showing the molding process following FIG. 20. [Figure 22A] It is a top view showing the mounting configuration of a semiconductor device. [Figure 22B] It is a cross-sectional view taken along the line A-A of FIG. 22A. [Figure 23A] It is a top view showing the mounting configuration of a semiconductor device. [Figure 23B]This is a cross-sectional view along line AA in Figure 23A. [Figure 24A] This is a top view showing the mounting configuration of a semiconductor device. [Figure 24B] This is a cross-sectional view along line AA in Figure 24A. [Modes for carrying out the invention]

[0011] In all the drawings illustrating the embodiments, the same reference numeral is used for identical components, and repeated explanations of them are omitted. Hatching may be used even in plan views to improve clarity.

[0012] The term "digital isolator" is used to broadly encompass devices that enable contactless signal transmission from one circuit to another. For example, digital isolators include transformers that utilize magnetic coupling and capacitors that utilize capacitive coupling. The technical concepts of this disclosure are broadly applicable to digital isolators, including transformers and capacitors. The following explanation will focus on transformers.

[0013] Furthermore, a chip on which a "digital isolator" is formed is called an "isolator chip." Similarly, a chip on which a "transformer" is formed is called a "transformer chip." Therefore, "isolator chip" is a broader term that includes "transformer chip."

[0014] <Circuit Configuration> Figure 1 shows an example of the configuration of a drive control unit that drives a load circuit such as a motor.

[0015] As shown in Figure 1, the drive control unit includes a control circuit CC, a transmitting circuit TX1, a receiving circuit RX1, a transmitting circuit TX2, a receiving circuit RX2, a transformer TR1, a transformer TR2, a drive circuit DR, and an inverter INV.

[0016] The transmitting circuit TX1 and the receiving circuit RX1 are circuits for transmitting control signals output from the control circuit CC to the drive circuit DR. On the other hand, the transmitting circuit TX2 and the receiving circuit RX2 are circuits for transmitting signals output from the drive circuit DR to the control circuit CC.

[0017] The control circuit CC is a circuit that controls the drive circuit DR. The drive circuit DR is a circuit that operates the inverter INV, which controls the load circuit LOD, based on the control from the control circuit CC. The inverter INV is electrically connected to the load circuit LOD.

[0018] The control circuit CC is supplied with the power supply potential VCC1. The control circuit CC is grounded by the ground potential GND1. On the other hand, the inverter INV is supplied with the power supply potential VCC2. The inverter INV is grounded by the ground potential GND2. For example, the power supply potential VCC1 is less than the power supply potential VCC2 supplied to the inverter INV. In other words, the power supply potential VCC2 supplied to the inverter INV is greater than the power supply potential VCC1.

[0019] A transformer TR1, consisting of inductively coupled (magnetically coupled) coils (inductors) CL1a and CL1b, is interposed between the transmitting circuit TX1 and the receiving circuit RX1. This allows signals to be transmitted from the transmitting circuit TX1 to the receiving circuit RX1 via the transformer TR1. As a result, the drive circuit DR can receive the control signal output from the control circuit CC via the transformer TR1.

[0020] By using inductive coupling to electrically isolate the transformer TR1, the transmission of electrical noise from the control circuit CC to the drive circuit DR can be suppressed while transmitting the control signal from the control circuit CC to the drive circuit DR. Therefore, malfunctions of the drive circuit DR caused by the superposition of electrical noise on the control signal can be suppressed. This improves the operational reliability of the semiconductor device.

[0021] The coils CL1a and CL1b that make up the transformer TR1 each function as inductors. The transformer TR1 functions as a magnetic coupling element consisting of inductively coupled coils CL1a and CL1b.

[0022] A transformer TR2, consisting of inductively coupled coils CL2b and CL2a, is interposed between the transmitting circuit TX2 and the receiving circuit RX2. This allows signals to be transmitted from the transmitting circuit TX2 to the receiving circuit RX2 via the transformer TR2. As a result, the control circuit CC can receive the signal output from the drive circuit DR via the transformer TR2.

[0023] By using inductive coupling to electrically isolate the transformer TR2, the transmission of electrical noise from the drive circuit DR to the control circuit CC can be suppressed while transmitting the signal from the drive circuit DR to the control circuit CC. Therefore, malfunctions of the control circuit CC caused by the superposition of electrical noise on the signal can be suppressed. This improves the operational reliability of the semiconductor device.

[0024] Transformer TR1 is composed of coils CL1a and CL1b. Coils CL1a and CL1b are not connected by a conductor but are magnetically coupled. Therefore, when current flows through coil CL1a, an induced electromotive force is generated in coil CL1b in response to the change in current, causing an induced current to flow. In this case, coil CL1a is the primary coil and coil CL1b is the secondary coil.

[0025] Transformer TR1 utilizes the electromagnetic induction phenomenon that occurs between coils CL1a and CL1b. Specifically, when a signal is sent from the transmitting circuit TX1 to coil CL1a of transformer TR1, a current flows, and as a result, the induced current generated in coil CL1b of transformer TR1 is detected by the receiving circuit RX1. In this way, the receiving circuit RX1 can receive a signal corresponding to the control signal output from the transmitting circuit TX1.

[0026] The transformer TR2 is composed of coils CL2a and CL2b. Coils CL2a and CL2b are not connected by a conductor, but are magnetically coupled. Therefore, when current flows through coil CL2b, an induced electromotive force is generated in coil CL2a in response to the change in that current, causing an induced current to flow.

[0027] By sending a signal from the transmitting circuit TX2 to the coil CL2b of the transformer TR2, which causes a current to flow, the receiving circuit RX2 detects the induced current generated in the coil CL2a of the transformer TR2. In this way, the receiving circuit RX2 can receive a signal corresponding to the control signal output from the transmitting circuit TX2.

[0028] Signal transmission and reception between the control circuit CC and the drive circuit DR are performed via two paths: one from the transmitting circuit TX1 through transformer TR1 to the receiving circuit RX1, and another from the transmitting circuit TX2 through transformer TR2 to the receiving circuit RX2.

[0029] In other words, the receiving circuit RX1 receives the signal transmitted by the transmitting circuit TX1, and the receiving circuit RX2 receives the signal transmitted by the transmitting circuit TX2, thereby enabling the transmission and reception of signals between the control circuit CC and the drive circuit DR.

[0030] Transformer TR1 is involved in the transmission of signals from the transmitting circuit TX1 to the receiving circuit RX1. On the other hand, transformer TR2 is involved in the transmission of signals from the transmitting circuit TX2 to the receiving circuit RX2. As a result, the drive circuit DR can drive the inverter INV to operate the load circuit LOD in response to the signal transmitted from the control circuit CC.

[0031] The control circuit CC and the drive circuit DR have different reference potential voltage levels. Specifically, in the control circuit CC, the reference potential is fixed to the ground potential GND1. On the other hand, as shown in Figure 1, the drive circuit DR is electrically connected to the inverter INV.

[0032] An inverter (INV) includes, for example, a high-side IGBT (Insulated Gate Bipolar Transistor) and a low-side IGBT. In the inverter (INV), the on / off control of the high-side IGBT and the on / off control of the low-side IGBT are performed by the drive circuit (DR), thereby enabling control of the load circuit (LOD) by the inverter (INV).

[0033] Specifically, the on / off control of the high-side IGBT is performed by controlling the potential applied to the gate electrode of the high-side IGBT with the drive circuit DR. The on / off control of the low-side IGBT is performed by controlling the potential applied to the gate electrode of the low-side IGBT with the drive circuit DR.

[0034] For example, the ON control of a low-side IGBT is achieved by applying "emitter potential (0V) + threshold voltage (15V)" to the gate electrode, with the emitter potential (0V) of the low-side IGBT connected to ground potential GND2 as the reference.

[0035] On the other hand, for example, the off-control of a low-side IGBT is achieved by applying the "emitter potential (0V)" to the gate electrode, using the emitter potential (0V) of the low-side IGBT connected to the ground potential GND2 as a reference.

[0036] Therefore, the on / off control of the low-side IGBT is performed by whether or not a threshold voltage (15V) is applied to the gate electrode, with 0V as the reference potential.

[0037] On the other hand, for example, the ON control of a high-side IGBT is also performed by using the emitter potential of the high-side IGBT as the reference potential, and applying "reference potential + threshold voltage (15V)" to the gate electrode relative to this reference potential.

[0038] However, the emitter potential of the high-side IGBT is not fixed to the ground potential GND2, unlike the emitter potential of the low-side IGBT. In other words, in the inverter INV, the high-side IGBT and the low-side IGBT are connected in series between the power supply potential VCC2 and the ground potential GND2.

[0039] In the inverter INV, when the high-side IGBT is turned on, the low-side IGBT is turned off, and when the high-side IGBT is turned off, the low-side IGBT is turned on. Therefore, when the high-side IGBT is off, the low-side IGBT is on. As a result, the emitter potential of the high-side IGBT becomes ground potential GND2 due to the on-up low-side IGBT.

[0040] On the other hand, when the high-side IGBT is ON, the low-side IGBT is OFF, so the emitter potential of the high-side IGBT becomes the IGBT bus voltage.

[0041] The on / off control of the high-side IGBT is performed by applying "reference potential + threshold voltage (15V)" to the gate electrode, using the emitter potential of the high-side IGBT as the reference potential. In this regard, the emitter potential of the high-side IGBT varies depending on whether the high-side IGBT is on or off.

[0042] In other words, the emitter potential of the high-side IGBT varies from the ground potential GND2 (0V) to the power supply potential VCC2 (e.g., 800V). Therefore, in order to turn on the high-side IGBT, it is necessary to apply "IGBT bus voltage (800V) + threshold voltage (15V)" to the gate electrode, using the emitter potential of the high-side IGBT as the reference potential.

[0043] Therefore, the drive circuit DR, which controls the on / off state of the high-side IGBT, needs to know the emitter potential of the high-side IGBT. For this reason, the drive circuit DR is configured to receive the emitter potential of the high-side IGBT as input. As a result, a reference potential of 800V is input to the drive circuit DR, and the drive circuit DR controls the high-side IGBT to turn on by applying a threshold voltage of 15V (15V) to the gate electrode of the high-side IGBT relative to this 800V reference potential. Consequently, a high potential of approximately 800V is applied to the drive circuit DR.

[0044] Thus, the drive control unit has a control circuit CC that handles low potentials (tens of volts) and a drive circuit DR that handles high potentials (hundreds of volts).

[0045] Therefore, signal transmission between the control circuit CC and the drive circuit DR requires signal transmission between circuits of different potentials. In this regard, since signal transmission between the control circuit CC and the drive circuit DR is carried out via transformers TR1 and TR2, signal transmission between circuits of different potentials is possible.

[0046] In transformers TR1 and TR2, a large potential difference may occur between the primary and secondary coils. Therefore, the primary and secondary coils are magnetically coupled rather than connected by a conductor, and these are used for signal transmission. Consequently, when forming transformer TR1, it is important to make the dielectric breakdown voltage between coil CL1a and coil CL1b as high as possible from the viewpoint of improving the operational reliability of the semiconductor device. When forming transformer TR2, it is important to make the dielectric breakdown voltage between coil CL2b and coil CL2a as high as possible from the viewpoint of improving the operational reliability of the semiconductor device.

[0047] <Example of signal transmission> Figure 2 is an explanatory diagram showing an example of signal transmission.

[0048] In Figure 2, the transmitting circuit TX1 extracts the edge portion of the square wave signal SG1 input to the transmitting circuit TX1 to generate a signal SG2 with a constant pulse width, and sends signal SG2 to the coil CL1a (primary coil) of the transformer TR1. When the current caused by this signal SG2 flows through the coil CL1a (primary coil) of the transformer TR1, a corresponding signal SG3 flows through the coil CL1b (secondary coil) of the transformer TR1 due to the induced electromotive force. This signal SG3 is amplified by the receiving circuit RX1 and further modulated into a square wave, so that the square wave signal SG4 is output from the receiving circuit RX1.

[0049] This allows the receiving circuit RX1 to output a signal SG4 corresponding to the signal SG1 input to the transmitting circuit TX1. In this way, signals can be transmitted from the transmitting circuit TX1 to the receiving circuit RX1. The same applies to the transmission of signals from the transmitting circuit TX2 to the receiving circuit RX2.

[0050] <The usefulness of a 3-chip configuration> The transmit / receive circuit section of the drive control unit can be implemented, for example, with a two-chip configuration using a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a transmit circuit TX1, a transformer TR1, and a receive circuit RX2. On the other hand, the second semiconductor chip has a receive circuit RX1, a drive circuit DR, a transmit circuit TX2, and a transformer TR2.

[0051] However, in a two-chip configuration, it is necessary to form the transformer TR1, the transmit circuit TX1, and the receive circuit RX2 on the first semiconductor chip. This complicates the manufacturing process of the first semiconductor chip. Alternatively, it is necessary to form the transformer TR2, the drive circuit DR, the receive circuit RX1, and the transmit circuit TX2 on the second semiconductor chip. This complicates the manufacturing process of the second semiconductor chip. As a result, the manufacturing costs of both the first and second semiconductor chips may increase.

[0052] Therefore, a 3-chip configuration is being considered instead of a 2-chip configuration.

[0053] Figure 3 shows a 3-chip configuration.

[0054] In Figure 3, semiconductor chip CHP1 has a transmit circuit TX1 and a receive circuit RX2. Semiconductor chip CHP2 has a drive circuit DR, a receive circuit RX1, and a transmit circuit TX2. In contrast, semiconductor chip CHP3 has transformers TR1 and TR2.

[0055] As a result, in the 3-chip configuration, semiconductor chip CHP3 has only transformers TR1 and TR2 formed on it. In other words, in the 3-chip configuration, semiconductor chip CHP3 can be used regardless of the configuration of semiconductor chips CHP1 and CHP2. Therefore, the 3-chip configuration can increase the variations of usable semiconductor chips CHP1 and CHP2. In other words, it can increase the versatility of semiconductor chip CHP3 on which transformers TR1 and TR2 are formed.

[0056] Furthermore, the semiconductor chip CHP3 on which transformers TR1 and TR2 are formed does not contain transistors. As a result, it can be formed using only a wiring process, thus simplifying the manufacturing process.

[0057] Therefore, a three-chip configuration makes it possible to reduce manufacturing costs.

[0058] In the following, the semiconductor chip CHP3 on which transformers TR1 and TR2 are formed may be referred to as the "transformer chip."

[0059] <Consideration of improvements> For example, Patent Documents 1 and 2, which are mentioned in the background technology section, describe a three-chip configuration including a "trans chip".

[0060] The "transformer chip" has a lower inductor located in the lower part of the multilayer wiring layer and an upper inductor located in the upper part of the multilayer wiring layer.

[0061] In recent years, in order to improve the performance of semiconductor devices including "transformer chips," high dielectric strength is required for "transformer chips." To ensure high dielectric strength, for example, increasing the thickness of the interlayer insulating film interposed between the lower layer inductor and the upper layer inductor is being considered. This is because increasing the thickness of the interlayer insulating film increases the distance between the opposing lower layer inductor and the upper layer inductor, thereby ensuring sufficient dielectric strength between the lower layer inductor and the upper layer inductor.

[0062] However, when a thick interlayer insulating film is formed on a semiconductor substrate, film stress is generated in the semiconductor substrate due to the thickness of the interlayer insulating film. As a result, the semiconductor substrate warps.

[0063] If warping occurs in the transformer chip, it may disrupt subsequent manufacturing processes. Therefore, it is desirable that the transformer chip can ensure high dielectric strength without causing warping.

[0064] In this regard, for example, there is Patent Document 3, which is mentioned in the background technology section. Patent Document 3 describes the structure of a transformer capable of dividing the dielectric strength.

[0065] The "transformer chip" described in Patent Document 3 has a lower inductor located in the lower part of the multilayer wiring layer, and a first upper inductor and a second upper inductor located in the upper part of the multilayer wiring layer. The first upper inductor and the second upper inductor are located apart from each other. As a result, the voltage applied to the "transformer chip" is divided into a first voltage applied between the lower inductor and the first upper inductor, and a second voltage applied between the lower inductor and the second upper inductor.

[0066] As a result, for example, if the thickness of the interlayer insulating film of the "transformer chip" described in Patent Document 3 is the same as the thickness of the interlayer insulating film of the "transformer chips" described in Patent Documents 1 and 2, the "transformer chip" described in Patent Document 3 can secure twice the dielectric strength of the "transformer chips" described in Patent Documents 1 and 2.

[0067] In other words, if the dielectric strength of the "transformer chip" described in Patent Document 3 is to be equivalent to that of the "transformer chips" described in Patent Documents 1 and 2, then the thickness of the interlayer insulating film of the "transformer chip" described in Patent Document 3 may be half the thickness of the interlayer insulating film of the "transformer chips" described in Patent Documents 1 and 2.

[0068] Thus, the technology described in Patent Document 3 can ensure dielectric strength without increasing the thickness of the interlayer insulating film, compared to the technologies described in Patent Documents 1 and 2.

[0069] However, the inventors have found that there is room for improvement in the technology described in Patent Document 3, and therefore, the areas for improvement will be explained below.

[0070] Figure 4 illustrates areas for improvement.

[0071] In Figure 4, the semiconductor device includes a chip mounting section TAB1, a chip mounting section TAB2, a chip mounting section TAB3, semiconductor chips CHP1, CHP2, and CHP3 (transformer chip).

[0072] A semiconductor chip CHP1 is placed on the chip mounting section TAB1. For example, "0V" is supplied to the chip mounting section TAB1.

[0073] The semiconductor chip CHP2 is placed on the chip mounting section TAB2. For example, "800V" is supplied to the chip mounting section TAB2.

[0074] A semiconductor chip CHP3 is placed on the chip mounting section TAB3. A transformer is formed on the semiconductor chip CHP3.

[0075] Specifically, as shown in Figure 4, the semiconductor chip CHP3 has a lower inductor BL, a first upper inductor UL1, and a second upper inductor UL2. The lower inductor BL, the first upper inductor UL1, and the second upper inductor UL2 are components of the transformer. The semiconductor chip CHP3 has a multilayer wiring layer. The lower inductor BL is located in the lower part of the multilayer wiring layer. The first upper inductor UL1 is located in the upper part of the multilayer wiring layer. The second upper inductor UL2 is located in the upper part of the multilayer wiring layer. Furthermore, the second upper inductor UL2 is located in the same wiring layer as the first upper inductor UL1 within the multilayer wiring layer.

[0076] For example, as shown in Figure 4, the distance between the lower inductor BL and the first upper inductor UL1 is "L1". The distance between the lower inductor BL and the second upper inductor UL2 is "L2". The distance between the lower inductor BL and the chip mounting area TAB3 is "L3". "L3" is smaller than "L1" and smaller than "L2". Also, "L2" is the same as "L1".

[0077] The first upper inductor UL1 is electrically connected to the semiconductor chip CHP1. 0V is supplied to the first upper inductor UL1. The second upper inductor UL2 is electrically connected to the semiconductor chip CHP2. 800V is supplied to the second upper inductor UL2. In contrast, the lower inductor BL is floating.

[0078] Here, let's assume that the chip mounting section TAB3 is floating. In this case, both the chip mounting section TAB3 and the lower inductor BL are floating. Even if both the chip mounting section TAB3 and the lower inductor BL are floating, they are capacitively coupled, but because both are floating, the potential of the lower inductor BL is unstable.

[0079] On the other hand, the first upper inductor UL1 is supplied with "0V" and is therefore not floating. The second upper inductor UL2 is supplied with "800V" and is therefore not floating. In addition, the lower inductor BL is capacitively coupled to the first upper inductor UL1 and also to the second upper inductor UL2. However, "L1" and "L2" are larger than "L3".

[0080] Therefore, the capacitive coupling between the lower inductor BL and the first upper inductor UL1 is very small. The capacitive coupling between the lower inductor BL and the second upper inductor UL2 is also very small. With such small capacitive coupling, the potential of the lower inductor BL is unstable. Therefore, from the viewpoint of stabilizing the potential of the lower inductor BL, it is undesirable to make the chip mounting section TAB3 floating.

[0081] Therefore, it is conceivable to supply an intermediate potential (400V) to the chip mounting section TAB3. In this case, the chip mounting section TAB3 is not floating. Also, the lower inductor BL is capacitively coupled to the chip mounting section TAB3. Here, "L3" is smaller than "L1" and "L2". Therefore, the capacitive coupling between the lower inductor BL and the chip mounting section TAB3 is larger than the capacitive coupling between the lower inductor BL and each upper inductor (first upper inductor UL1 and second upper inductor UL2). Furthermore, the planar area of ​​the chip mounting section TAB3 is larger than the planar area of ​​the first upper inductor UL1 and the planar area of ​​the second upper inductor UL2, respectively. From this, the capacitive coupling between the lower inductor BL and the chip mounting section TAB3 becomes very large. As a result, the potential of the lower inductor BL is stabilized.

[0082] Based on the above, it is desirable to supply an intermediate potential ("400V") to the chip mounting section TAB3 in order to stabilize the potential of the lower layer inductor BL. However, in order to supply an intermediate potential ("400V") to the chip mounting section TAB3, it is necessary to prepare a power supply circuit to generate the intermediate potential. In this case, the circuit configuration becomes complex. Therefore, it is desirable to realize a configuration that supplies an intermediate potential (400V) to the chip mounting section TAB3 without preparing a power supply circuit to generate the intermediate potential.

[0083] <Basic philosophy> Figure 5 is a diagram that explains the basic concept.

[0084] In Figure 5, the basic concept is that chip mounting sections TAB1 and TAB3 are electrically connected via a resistor R1, and chip mounting sections TAB2 and TAB3 are electrically connected via a resistor R2.

[0085] As a result, the potential applied to the chip mounting section TAB3 (third potential) is higher than the potential applied to the chip mounting section TAB1 (first potential) and lower than the potential applied to the chip mounting section TAB2 (second potential). For example, if "0V" is supplied to the chip mounting section TAB1 and "800V" is supplied to the chip mounting section TAB2, and assuming that the resistance values ​​of resistor element R1 and resistor element R2 are equal, then an intermediate potential of "400V" will be applied to the chip mounting section TAB3. In other words, according to the basic concept, an intermediate potential can be applied to the chip mounting section TAB3 without preparing a power supply circuit to generate the intermediate potential. That is, the basic concept applies an intermediate potential to the chip mounting section TAB3 by interposing a resistor element between "800V" and "0V". Therefore, according to the basic concept, a power supply circuit to supply an intermediate potential to the chip mounting section TAB3 is unnecessary. As a result, a semiconductor device adopting the basic concept can stabilize the potential of the lower layer inductor BL without configuring a complex circuit.

[0086] A semiconductor device that adopts this basic concept has the following configuration.

[0087] The semiconductor device comprises a chip mounting section TAB1 to which a first potential (0V) is supplied, a semiconductor chip CHP1 placed on the chip mounting section TAB1, a chip mounting section TAB2 to which a second potential (800V) higher than the first potential is supplied, a semiconductor chip CHP2 placed on the chip mounting section TAB2, a chip mounting section TAB3 electrically connected to the chip mounting section TAB1 via a resistive element R1 and electrically connected to the chip mounting section TAB2 via a resistive element R2, and a semiconductor chip CHP3 placed on the chip mounting section TAB3.

[0088] For example, resistor R1 can be made from a chip resistor. Resistor R2 can also be made from a chip resistor. The resistance values ​​of resistor R1 and resistor R2 can be appropriately set within a range of, for example, 5MΩ to 50MΩ, depending on the voltage to be applied to the chip mounting section TAB3.

[0089] The semiconductor chip CHP3 includes a lower inductor BL, a first upper inductor UL1 formed above the lower inductor BL via an insulating layer and electrically connected to the semiconductor chip CHP1, and a second upper inductor UL2 formed above the lower inductor BL via an insulating layer, positioned separately from the first upper inductor UL1, and electrically connected to the semiconductor chip CHP2.

[0090] The following describes embodiments that embody the basic concept.

[0091] <Embodiment 1> <<Transformer Layout Configuration>> Figure 6 shows an example of a transformer layout configuration.

[0092] In Figure 6, the semiconductor chip CHP3 is a "transformer chip." The semiconductor chip CHP3 has transformers TR1 and TR2.

[0093] Transformer TR1 has a lower layer inductor BLA, a first upper layer inductor UL1A, and a second upper layer inductor UL2A.

[0094] The first upper inductor UL1A and the second upper inductor UL2A are positioned above the lower inductor BLA. The lower inductor BLA and the first upper inductor UL1A are magnetically coupled. The lower inductor BLA and the second upper inductor UL2A are also magnetically coupled. As shown in Figure 6, the first upper inductor UL1A and the second upper inductor UL2A are positioned apart from each other and aligned in the X direction.

[0095] The planar arrangement direction of semiconductor chips CHP1, CHP3, and CHP2 is the X direction. Therefore, the planar arrangement direction of the first upper layer inductor UL1A and the second upper layer inductor UL2A is parallel to the planar arrangement direction of semiconductor chips CHP1, CHP3, and CHP2.

[0096] The transformer TR2 has a lower layer inductor BLB, a first upper layer inductor UL1B, and a second upper layer inductor UL2B.

[0097] The first upper inductor UL1B and the second upper inductor UL2B are positioned above the lower inductor BLB. The lower inductor BLB and the first upper inductor UL1B are magnetically coupled. The lower inductor BLB and the second upper inductor UL2B are also magnetically coupled. As shown in Figure 6, the first upper inductor UL1B and the second upper inductor UL2B are positioned apart from each other and aligned in the X direction.

[0098] The planar arrangement direction of semiconductor chips CHP1, CHP3, and CHP2 is the X direction. Therefore, the planar arrangement direction of the first upper layer inductor UL1B and the second upper layer inductor UL2B is parallel to the planar arrangement direction of semiconductor chips CHP1, CHP3, and CHP2.

[0099] Figure 7 shows another example of a transformer layout configuration.

[0100] In Figure 7, the semiconductor chip CHP3 is a "transformer chip." The semiconductor chip CHP3 has transformers TR1 and TR2.

[0101] Transformer TR1 has a lower layer inductor BLA, a first upper layer inductor UL1A, and a second upper layer inductor UL2A.

[0102] The first upper inductor UL1A and the second upper inductor UL2A are positioned above the lower inductor BLA. The lower inductor BLA and the first upper inductor UL1A are magnetically coupled. The lower inductor BLA and the second upper inductor UL2A are also magnetically coupled. As shown in Figure 7, the first upper inductor UL1A and the second upper inductor UL2A are positioned apart from each other and aligned in the Y direction.

[0103] The planar arrangement direction of semiconductor chips CHP1, CHP3, and CHP2 is the X direction. Therefore, the planar arrangement direction of the first upper layer inductor UL1A and the second upper layer inductor UL2A intersects with the planar arrangement direction of semiconductor chips CHP1, CHP3, and CHP2.

[0104] The transformer TR2 has a lower layer inductor BLB, a first upper layer inductor UL1B, and a second upper layer inductor UL2B.

[0105] The first upper inductor UL1B and the second upper inductor UL2B are positioned above the lower inductor BLB. The lower inductor BLB and the first upper inductor UL1B are magnetically coupled. The lower inductor BLB and the second upper inductor UL2B are also magnetically coupled. As shown in Figure 7, the first upper inductor UL1B and the second upper inductor UL2B are positioned apart from each other and aligned in the Y direction.

[0106] The planar arrangement direction of semiconductor chips CHP1, CHP3, and CHP2 is the X direction. Therefore, the planar arrangement direction of the first upper layer inductor UL1B and the second upper layer inductor UL2B intersects with the planar arrangement direction of semiconductor chips CHP1, CHP3, and CHP2.

[0107] For example, when adopting the transformer layout configuration shown in Figure 6, the length in the arrangement direction (X direction) of semiconductor chips CHP1, CHP3, and CHP2 is "X1". In contrast, when adopting the transformer layout configuration shown in Figure 7, the length in the arrangement direction (X direction) of semiconductor chips CHP1, CHP3, and CHP2 is "X2". "X2" is smaller than "X1". Therefore, a semiconductor device employing the transformer layout configuration shown in Figure 7 can be made smaller than a semiconductor device employing the transformer layout configuration shown in Figure 6.

[0108] <<Implementation configuration of semiconductor device>> Figure 8 is a diagram showing the mounting configuration of the semiconductor device 100 in Embodiment 1. Figure 8A is a top view showing the mounting configuration of the semiconductor device 100. Figure 8B is a cross-sectional view along line AA in Figure 8A. Figure 8C is a cross-sectional view along line BB in Figure 8A.

[0109] As shown in Figures 8A to 8C, the semiconductor device 100 includes a encapsulant MR, a chip mounting section TAB1, a chip mounting section TAB2, a chip mounting section TAB3, adhesives ADH1, ADH2, ADH3, ADH4, and ADH5, semiconductor chips CHP1, CHP2, and CHP3, and chip resistors CR1 and CR2. The semiconductor device 100 also includes multiple leads and multiple bonding wires as other components. The multiple bonding wires include bonding wire W1 that electrically connects semiconductor chips CHP1 and CHP3 to each other, and bonding wire W2 that electrically connects semiconductor chips CHP2 and CHP3 to each other.

[0110] Figures 8A to 8C show the internal structure of the MR sealant as seen through the glass.

[0111] The chip mounting sections TAB1, TAB3, and TAB2 are arranged in this order in the Y direction. In other words, in the Y direction, chip mounting section TAB3 is located between chip mounting sections TAB1 and TAB2.

[0112] A semiconductor chip CHP1 is placed on the chip mounting section TAB1 via an adhesive ADH1. The adhesive ADH1 is composed of, for example, silver paste or solder.

[0113] A semiconductor chip CHP2 is placed on the chip mounting section TAB2 via an adhesive ADH2. The adhesive ADH2 is composed of, for example, silver paste or solder.

[0114] A semiconductor chip CHP3 is placed on the chip mounting section TAB3 via an adhesive ADH3. The adhesive ADH3 is composed of, for example, silver paste or solder.

[0115] For example, the planar size of semiconductor chip CHP3 is larger than that of semiconductor chip CHP1, and smaller than that of semiconductor chip CHP2. In other words, among semiconductor chips CHP1, CHP2, and CHP3, semiconductor chip CHP1 has the smallest planar size, and semiconductor chip CHP2 has the largest planar size.

[0116] Semiconductor chip CHP1 is electrically connected to the leads via bonding wires. Furthermore, semiconductor chip CHP1 is electrically connected to semiconductor chip CHP3 via bonding wires.

[0117] The semiconductor chip CHP2 is electrically connected to the leads via bonding wires. Furthermore, the semiconductor chip CHP2 is electrically connected to the semiconductor chip CHP3 via bonding wires.

[0118] Semiconductor chip CHP3 is electrically connected to semiconductor chip CHP1 via bonding wires. Furthermore, semiconductor chip CHP3 is electrically connected to semiconductor chip CHP2 via bonding wires.

[0119] The chip mounting section TAB1 has a first surface FS1 and a first back surface BS1. The first surface FS1 is the surface on which the semiconductor chip CHP1 is placed. The first back surface BS1 is the surface opposite to the first surface FS1.

[0120] The chip mounting section TAB2 has a second front surface FS2 and a second back surface BS2. The second front surface FS2 is the surface on which the semiconductor chip CHP2 is placed. The second back surface BS2 is the surface opposite to the second front surface FS2.

[0121] The chip mounting section TAB3 has a third surface FS3 and a third back surface BS3. The third surface FS3 is the surface on which the semiconductor chip CHP3 is placed. The third back surface BS3 is the surface opposite to the third surface FS3.

[0122] The chip resistor CR1 is positioned across the first surface FS1 of the chip mounting section TAB1 and the third surface FS3 of the chip mounting section TAB3. The chip resistor CR1 is positioned on the first surface FS1 via the adhesive ADH4 and also on the third surface FS3 via the adhesive ADH4.

[0123] The chip resistor CR2 is positioned across the second surface FS2 of the chip mounting section TAB2 and the third surface FS3 of the chip mounting section TAB3. The chip resistor CR2 is positioned on the second surface FS2 via the adhesive ADH5 and also on the third surface FS3 via the adhesive ADH5.

[0124] In Figure 8A, the planar arrangement direction of semiconductor chips CHP1, CHP3, and CHP2 is the Y direction. The planar arrangement direction of chip resistors CR1 and CR2 is also the Y direction. Therefore, the planar arrangement directions of semiconductor chips CHP1, CHP3, and CHP2 and the planar arrangement directions of chip resistors CR1 and CR2 are parallel to each other.

[0125] Thus, when the planar arrangement directions of semiconductor chips CHP1, CHP3, and CHP2 are aligned with the planar arrangement directions of chip resistors CR1 and CR2, voids are less likely to occur in the resin material injected into the cavity during the molding process to form the encapsulant MR. In other words, the mounting configuration of the semiconductor device 100 in Embodiment 1 takes into consideration "void trap countermeasures" during the molding process.

[0126] In Embodiment 1, chip resistors CR1 and CR2 are mounted on the surface on which semiconductor chips CHP1, CHP2, and CHP3 are mounted (mounting surface, They are positioned on the same side as the placement surface. Therefore, there is no need to invert the lead frame to position chip resistors CR1 and CR2. Consequently, the ease of assembly in the assembly process (from die bonding to wire bonding) can be improved.

[0127] As shown in Figures 8B and 8C, the tip of the lead is bent upwards, for example.

[0128] <<Manufacturing Method for Semiconductor Devices>> Next, an example of a method for manufacturing a semiconductor device in Embodiment 1 will be described.

[0129] First, as shown in Figure 9, a chip mounting section TAB1, a chip mounting section TAB2, a chip mounting section TAB3, and a lead frame having multiple leads are prepared. Then, the semiconductor chip CHP1 is placed on the chip mounting section TAB1 via an adhesive ADH1.

[0130] Next, as shown in Figure 10, the semiconductor chip CHP3 is placed on the chip mounting section TAB3 via the adhesive ADH3. Then, as shown in Figure 11, the semiconductor chip CHP2 is placed on the chip mounting section TAB2 via the adhesive ADH2.

[0131] Next, as shown in Figure 12, chip resistor CR1 is placed across chip mounting sections TAB1 and TAB3 via adhesive ADH4, and chip resistor CR2 is placed across chip mounting sections TAB2 and TAB3 via adhesive ADH5. After that, a heat treatment is performed on the lead frame to cure adhesives ADH1, ADH2, ADH3, ADH4, and ADH5.

[0132] Next, as shown in Figure 13, the wire bonding process is carried out.

[0133] Specifically, semiconductor chip CHP1 and the lead are electrically connected to each other with bonding wires. Semiconductor chip CHP1 and semiconductor chip CHP3 are electrically connected to each other with bonding wire W1. Also, semiconductor chip CHP2 and the lead are electrically connected to each other with bonding wires. Semiconductor chip CHP2 and semiconductor chip CHP3 are electrically connected to each other with bonding wire W2.

[0134] More specifically, the first upper layer inductor UL1 provided on the semiconductor chip CHP3 is electrically connected to the semiconductor chip CHP1 via a bonding wire W1. The second upper layer inductor UL2 provided on the semiconductor chip CHP3 is electrically connected to the semiconductor chip CHP2 via a bonding wire W2.

[0135] Subsequently, as shown in Figure 14, a molding process is carried out. Specifically, the encapsulated body MR is formed by encapsulating at least semiconductor chips CHP1, CHP2, CHP3, chip resistors CR1 and CR2 with a resin material.

[0136] Next, after removing the burrs formed on the sealant MR, a plating film is formed on the portion of the lead exposed from the sealant MR. Then, a mark is formed on the surface of the sealant MR. After that, the leads exposed from the sealant MR are shaped. Next, the lead frame is cut. This allows for the manufacture of the semiconductor device according to Embodiment 1.

[0137] Each of the adhesives ADH1, ADH2, ADH3, ADH4, and ADH5 is composed of, for example, silver paste or solder.

[0138] In the example of semiconductor device manufacturing described above, the semiconductor chip CHP1 is placed on the chip mounting section TAB1 via adhesive ADH1, the semiconductor chip CHP3 is placed on the chip mounting section TAB3 via adhesive ADH3, the semiconductor chip CHP2 is placed on the chip mounting section TAB2 via adhesive ADH2, the chip resistor CR1 is placed across the chip mounting sections TAB1 and TAB3 via adhesive ADH4, and the chip resistor CR2 is placed across the chip mounting sections TAB2 and TAB3 via adhesive ADH5. After these steps are performed, baking (heat treatment) is carried out to cure the adhesives ADH1, ADH2, ADH3, ADH4, and ADH5 all at once. This reduces the number of steps and the time required for each step.

[0139] Here, for example, if silver paste is used as adhesive ADH1, ADH2, ADH3, ADH4, and ADH5, there is a risk that the first silver paste applied may dry out before the batch bake is performed if a batch bake is carried out. When it dries out, the likelihood of voids forming in the silver paste increases. As a result, there is a concern that the heat dissipation will decrease. Therefore, the semiconductor device manufacturing method described above incorporates the following measures.

[0140] In other words, focusing on semiconductor chips CHP1, CHP2, and CHP3, the planar size of semiconductor chip CHP1 is the smallest, and the planar size of semiconductor chip CHP2 is the largest. This means that semiconductor chip CHP1 generates the least heat, and semiconductor chip CHP2 generates the most heat. Therefore, it is important to ensure heat dissipation in the adhesive ADH2 that bonds semiconductor chip CHP2, which generates the most heat, to the chip mounting section TAB2. Accordingly, in the example of semiconductor device manufacturing method described above, for example, as shown in Figures 9 to 11, the steps of placing semiconductor chip CHP1 on the chip mounting section TAB1 via adhesive ADH1 and placing semiconductor chip CHP3 on the chip mounting section TAB3 via adhesive ADH3 are performed, followed by the step of placing semiconductor chip CHP2 on the chip mounting section TAB2 via adhesive ADH2. This shortens the time between applying the adhesive ADH2 and performing batch baking, thereby suppressing the drying of the adhesive ADH2 that bonds the heat-generating semiconductor chip CHP2 to the chip mounting area TAB2. As a result, the reduction in heat dissipation caused by drying is suppressed in the adhesive ADH2, which requires the highest level of heat dissipation.

[0141] Next, we will describe another example of a semiconductor device manufacturing method.

[0142] Figures 9 to 11 are similar to the example of semiconductor device manufacturing described above.

[0143] Subsequently, a heat treatment (first bake) is performed on the lead frame to cure adhesives ADH1, ADH2, and ADH3.

[0144] Next, as shown in Figure 15, the wire bonding process is carried out.

[0145] Specifically, semiconductor chip CHP1 and the lead are electrically connected to each other with bonding wires. Semiconductor chip CHP1 and semiconductor chip CHP3 are electrically connected to each other with bonding wire W1. Also, semiconductor chip CHP2 and the lead are electrically connected to each other with bonding wires. Semiconductor chip CHP2 and semiconductor chip CHP3 are electrically connected to each other with bonding wire W2.

[0146] More specifically, the first upper layer inductor UL1 provided on the semiconductor chip CHP3 is electrically connected to the semiconductor chip CHP1 via a bonding wire W1. The second upper layer inductor UL2 provided on the semiconductor chip CHP3 is electrically connected to the semiconductor chip CHP2 via a bonding wire W2.

[0147] Next, as shown in Figure 16, chip resistor CR1 is placed across chip mounting sections TAB1 and TAB3 via adhesive ADH4, and chip resistor CR2 is placed across chip mounting sections TAB2 and TAB3 via adhesive ADH5. After that, a heat treatment (second bake) is performed on the lead frame to cure adhesives ADH4 and ADH5.

[0148] The subsequent steps are the same as the example of semiconductor device manufacturing described above.

[0149] The wire bonding process is performed with the leads clamped using a lead-holding jig. However, when the leads are clamped with the lead-holding jig, there is a possibility that the chip resistor CR1, which is bonded with adhesive ADH4 across chip mounting sections TAB1 and TAB3, and the chip resistor CR2, which is bonded with adhesive ADH5 across chip mounting sections TAB2 and TAB3, may peel off. In other words, if the wire bonding process is performed after the chip resistors CR1 and CR2 have been mounted on the lead frame, the mounting reliability of the chip resistors CR1 and CR2 may be reduced.

[0150] In this regard, in another example of a semiconductor device manufacturing method, as shown in Figures 15 and 16, chip resistors CR1 and CR2 are mounted on the lead frame after the wire bonding process. This method, according to this other example of a semiconductor device manufacturing method, can suppress the peeling of chip resistors CR1 and CR2 from the lead frame caused by the wire bonding process. In other words, this method, according to this other example of a semiconductor device manufacturing method, can improve the mounting reliability of chip resistors CR1 and CR2.

[0151] <<<Improvements to the molding process>>> The molding process is a process of forming a encapsulated body MR by encapsulating at least semiconductor chips CHP1, CHP2, CHP3, chip resistors CR1 and CR2 with a resin material.

[0152] For example, the molding process employs a "through-gate molding method."

[0153] Figure 17 is a schematic diagram illustrating the "through-gate molding method".

[0154] In Figure 17, resin material is injected along the arrow. In Embodiment 1, chip resistors CR1 and CR2 are positioned. The heights of chip resistors CR1 and CR2 are higher than, for example, the heights of semiconductor chips CHP1, CHP2, and CHP3. Therefore, in the "through-gate molding method" shown in Figure 17, chip resistors CR1 and CR2 may become an obstacle, potentially resulting in insufficient filling of the resin material.

[0155] Therefore, in Embodiment 1, improvements have been made to the molding process. The molding process in Embodiment 1, with these improvements, will be described below.

[0156] First, as shown in Figure 18, the lead frame is sandwiched between the upper mold UM and the lower mold BM while forming the cavity CAV so that semiconductor chips CHP1, CHP2, CHP3, chip resistors CR1 and CR2 are arranged within the cavity CAV. Since Figure 18 is a cross-sectional view, semiconductor chips CHP2, CHP3 and chip resistor CR2 are not shown.

[0157] Subsequently, as shown in Figure 19, resin material 10 is injected into the cavity CAV from the gate G. Here, because the height of the chip resistor CR1 is high, the gap SP between the top surface of the chip resistor CR1 and the cavity CAV becomes narrowest. Therefore, in Embodiment 1, in order to suppress poor filling of the resin material 10 caused by the narrowest gap SP, a gate G is formed in the lower mold BM so that the resin material 10 is injected toward the narrowest gap SP in the cavity CAV. As a result, according to Embodiment 1, sufficient resin material 10 is injected even into the narrowest gap SP, thus suppressing poor filling of the resin material 10.

[0158] In other words, as shown in Figures 20 and 21, the resin material 10 is filled into the cavity CAV, resulting in the formation of a sealant MR without causing filling defects.

[0159] <Embodiment 2> Figure 22 is a diagram showing the mounting configuration of the semiconductor device 200 in Embodiment 2.

[0160] Figure 22A is a top view showing the mounting configuration of the semiconductor device 200. Figure 22B is a cross-sectional view along line AA in Figure 22A. Note that bonding wires are not shown in Figures 22A and 22B.

[0161] The chip mounting section TAB1 has a first surface FS1 and a first back surface BS1. The first surface FS1 is the surface on which the semiconductor chip CHP1 is placed. The first back surface BS1 is the surface opposite to the first surface FS1.

[0162] The chip mounting section TAB2 has a second front surface FS2 and a second back surface BS2. The second front surface FS2 is the surface on which the semiconductor chip CHP2 is placed. The second back surface BS2 is the surface opposite to the second front surface FS2.

[0163] The chip mounting section TAB3 has a third surface FS3 and a third back surface BS3. The third surface FS3 is the surface on which the semiconductor chip CHP3 is placed. The third back surface BS3 is the surface opposite to the third surface FS3.

[0164] Chip resistor CR1 is positioned across the first surface FS1 of chip mounting section TAB1 and the third surface FS3 of chip mounting section TAB3. Chip resistor CR2 is positioned across the second surface FS2 of chip mounting section TAB2 and the third surface FS3 of chip mounting section TAB3.

[0165] In Figure 22A, the planar alignment direction of semiconductor chips CHP1, CHP3, and CHP2 is the Y direction. The planar alignment direction of chip resistors CR1 and CR2 is in a direction intersecting the Y direction. Therefore, the planar alignment directions of semiconductor chips CHP1, CHP3, and CHP2, and the planar alignment directions of chip resistors CR1 and CR2, intersect each other.

[0166] In the semiconductor device 200 of Embodiment 2 configured in this way, the chip resistors CR1 and CR2 are arranged along the diagonal of the chip mounting section TAB3. This makes it easier to stabilize the potential of the chip mounting section TAB3. As a result, the potential of the lower layer inductor capacitively coupled to the chip mounting section TAB3 is also easier to stabilize.

[0167] <Embodiment 3> Figure 23 is a diagram showing the mounting configuration of the semiconductor device 300 in Embodiment 3.

[0168] Figure 23A is a top view showing the mounting configuration of the semiconductor device 300. Figure 23B is a cross-sectional view along line AA in Figure 23A. Note that bonding wires are not shown in Figures 23A and 23B.

[0169] The chip mounting section TAB1 has a first surface FS1 and a first back surface BS1. The first surface FS1 is the surface on which the semiconductor chip CHP1 is placed. The first back surface BS1 is the surface opposite to the first surface FS1.

[0170] The chip mounting section TAB2 has a second front surface FS2 and a second back surface BS2. The second front surface FS2 is the surface on which the semiconductor chip CHP2 is placed. The second back surface BS2 is the surface opposite to the second front surface FS2.

[0171] The chip mounting section TAB3 has a third surface FS3 and a third back surface BS3. The third surface FS3 is the surface on which the semiconductor chip CHP3 is placed. The third back surface BS3 is the surface opposite to the third surface FS3.

[0172] Chip resistor CR1 is positioned across the first back surface BS1 of chip mounting section TAB1 and the third back surface BS3 of chip mounting section TAB3. Chip resistor CR2 is positioned across the second back surface BS2 of chip mounting section TAB2 and the third back surface BS3 of chip mounting section TAB3.

[0173] In Figure 23A, the planar arrangement direction of semiconductor chips CHP1, CHP3, and CHP2 is the Y direction. The planar arrangement direction of chip resistors CR1 and CR2 is also the Y direction. Therefore, the planar arrangement directions of semiconductor chips CHP1, CHP3, and CHP2 and the planar arrangement directions of chip resistors CR1 and CR2 are parallel to each other.

[0174] According to Embodiment 3, the chip resistor CR1 is not placed on the first surface FS1 and the third surface FS3. The chip resistor CR2 is not placed on the second surface FS2 and the third surface FS3. This improves the layout flexibility of semiconductor chips CHP1, CHP2, and CHP3. In addition, the planar size of the chip mounting sections TAB1, TAB2, and TAB3 can be reduced.

[0175] <Embodiment 4> Figure 24 shows the mounting configuration of the semiconductor device 400 in Embodiment 4.

[0176] Figure 24A is a top view showing the mounting configuration of the semiconductor device 400. Figure 24B is a cross-sectional view along line AA in Figure 24A. Note that bonding wires are not shown in Figures 24A and 24B.

[0177] The chip mounting section TAB1 has a first surface FS1 and a first back surface BS1. The first surface FS1 is the surface on which the semiconductor chip CHP1 is placed. The first back surface BS1 is the surface opposite to the first surface FS1.

[0178] The chip mounting section TAB2 has a second front surface FS2 and a second back surface BS2. The second front surface FS2 is the surface on which the semiconductor chip CHP2 is placed. The second back surface BS2 is the surface opposite to the second front surface FS2.

[0179] The chip mounting section TAB3 has a third surface FS3 and a third back surface BS3. The third surface FS3 is the surface on which the semiconductor chip CHP3 is placed. The third back surface BS3 is the surface opposite to the third surface FS3.

[0180] Chip resistor CR1 is positioned across the first back surface BS1 of chip mounting section TAB1 and the third back surface BS3 of chip mounting section TAB3. Chip resistor CR2 is positioned across the second back surface BS2 of chip mounting section TAB2 and the third back surface BS3 of chip mounting section TAB3.

[0181] In Figure 24A, the planar alignment direction of semiconductor chips CHP1, CHP3, and CHP2 is the Y direction. The planar alignment direction of chip resistors CR1 and CR2 is in a direction intersecting the Y direction. Therefore, the planar alignment directions of semiconductor chips CHP1, CHP3, and CHP2, and the planar alignment directions of chip resistors CR1 and CR2, intersect each other.

[0182] In the semiconductor device 400 of Embodiment 4 configured in this way, the chip resistors CR1 and CR2 are arranged along the diagonal of the chip mounting section TAB3. This makes it easier to stabilize the potential of the chip mounting section TAB3. As a result, the potential of the lower layer inductor capacitively coupled to the chip mounting section TAB3 is also easier to stabilize.

[0183] According to Embodiment 4, the chip resistor CR1 is not placed on the first surface FS1 and the third surface FS3. The chip resistor CR2 is not placed on the second surface FS2 and the third surface FS3. This improves the layout flexibility of semiconductor chips CHP1, CHP2, and CHP3. In addition, the planar size of the chip mounting sections TAB1, TAB2, and TAB3 can be reduced.

[0184] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0185] For example, in the above embodiment, "transformer communication" between inductors was used as an example for explanation, but the basic concept in the above embodiment is not limited to this and can also be applied to "electrode-to-electrode communication" of a capacitor. In the case of a capacitor, the lower electrode is placed in the multilayer wiring layer instead of the lower inductor BL. The first upper electrode is placed in the multilayer wiring layer instead of the first upper inductor UL1. The second upper electrode is placed in the multilayer wiring layer instead of the second upper inductor UL2. The lower electrode, the first upper electrode, and the second upper electrode each consist of plate-shaped wiring. The first upper electrode and the lower electrode are provided so as to be capacitively coupled. The second upper electrode and the lower electrode are also provided so as to be capacitively coupled. The potential applied to the first upper electrode is the same as the potential applied to the first upper inductor UL1. The potential applied to the second upper electrode is the same as the potential applied to the second upper inductor UL2. The potential applied to the lower electrode is the same as the potential applied to the lower inductor BL. The relationship between the first upper electrode and other components is the same as the relationship between the first upper inductor UL1 and other components. The relationship between the second upper electrode and other components is the same as the relationship between the second upper inductor UL2 and other components. The relationship between the lower electrode and other components is the same as the relationship between the lower inductor BL and other components.

[0186] In the claims, the term "lower conductor section" is used to refer to a concept that includes the lower inductor and the lower electrode. The term "first upper conductor section" is used to refer to a concept that includes the first upper inductor and the first upper electrode. The term "second upper conductor section" is used to refer to a concept that includes the second upper inductor and the second upper electrode. [Explanation of symbols]

[0187] 10 Resin materials ADH1 adhesive ADH2 adhesive ADH3 adhesive ADH4 adhesive ADH5 adhesive BL lower layer inductor BLA Lower Layer Inductor BLB Lower Layer Inductor BM lower mold BS1 1st Reverse Side BS2 Second Backside BS3 3rd back CAV Cavity CC control circuit CHP1 semiconductor chip CHP2 semiconductor chip CHP3 semiconductor chip CL1a coil CL1b coil CL2a coil CL2 and Coil CR1 chip resistor CR2 chip resistor DR drive circuit FS1 First Surface FS2 2nd surface FS3 Third Surface G Gate GND1 Ground potential GND2 Ground potential INV Inverter LOD load circuit MR sealed body RX1 Receiver Circuit RX2 receiving circuit R1 Resistor R2 Resistor SG1 signal SG2 signal SG3 signal SG4 signal TAB1 Chip Mounting Section TAB2 Chip Mounting Section TAB3 Chip Mounting Section TR1 Transformer TR2 Transformers TX1 Transmitter Circuit TX2 Transmitter Circuit UL1 First Upper Layer Inductor UL1A First Upper Layer Inductor UL1B First Upper Layer Inductor UL2A Second Upper Layer Inductor UL2B Second Upper Layer Inductor UL2 Second Upper Inductor UM upper mold VCC1 power supply potential VCC2 power supply potential W1 bonding wire W2 bonding wire

Claims

1. A first chip mounting section to which a first potential is supplied, A first semiconductor chip disposed on the first chip mounting section, A second chip mounting section to which a second potential higher than the first potential is supplied, A second semiconductor chip is placed on the second chip mounting section, A third chip mounting section is electrically connected to the first chip mounting section via a first resistive element and electrically connected to the second chip mounting section via a second resistive element, An isolator chip positioned on the third chip mounting section, Equipped with, The isolator chip is Lower conductor section, A first upper conductor portion is formed above the lower conductor portion via an insulating layer and is electrically connected to the first semiconductor chip, A second upper conductor portion is formed above the lower conductor portion via the insulating layer, is arranged separately from the first upper conductor portion, and is electrically connected to the second semiconductor chip, A semiconductor device having the following features.

2. In the semiconductor device described in claim 1, The lower conductor portion and the first upper conductor portion are components of the first transformer. The lower conductor portion and the second upper conductor portion are components of the second transformer.

3. In the semiconductor device described in claim 1, The aforementioned lower conductor portion is the lower electrode, The first upper conductor portion is the first upper electrode, The second upper conductor portion is the second upper electrode.

4. In the semiconductor device described in claim 1, The first resistive element is a first chip resistor, The second resistive element is a second chip resistor.

5. In the semiconductor device according to claim 4, When the planar arrangement direction of the first semiconductor chip, the isolator chip, and the second semiconductor chip is defined as the first direction, and the planar arrangement direction of the first chip resistor and the second chip resistor is defined as the second direction, the first direction and the second direction are parallel to each other.

6. In the semiconductor device described in claim 5, The first chip mounting portion has a first surface on which the first semiconductor chip is placed, The second chip mounting portion has a second surface on which the second semiconductor chip is arranged. The third chip mounting portion has a third surface on which the isolator chip is arranged. The first chip resistor is arranged across the first surface and the third surface, The second chip resistor is arranged across the second surface and the third surface.

7. In the semiconductor device described in claim 5, The first chip mounting portion has a first back surface on which the first semiconductor chip is not placed. The second chip mounting portion has a second back surface on which the second semiconductor chip is not placed. The third chip mounting portion has a third back surface on which the isolator chip is not placed, The first chip resistor is positioned across the first back surface and the third back surface, The second chip resistor is positioned across the second back surface and the third back surface.

8. In the semiconductor device according to claim 4, When the planar arrangement direction of the first semiconductor chip, the isolator chip, and the second semiconductor chip is defined as the first direction, and the planar arrangement direction of the first chip resistor and the second chip resistor is defined as the third direction, the first direction and the third direction are directions that intersect each other.

9. In the semiconductor device described in claim 8, The first chip mounting portion has a first surface on which the first semiconductor chip is placed, The second chip mounting portion has a second surface on which the second semiconductor chip is arranged. The third chip mounting portion has a third surface on which the isolator chip is arranged. The first chip resistor is arranged across the first surface and the third surface, The second chip resistor is arranged across the second surface and the third surface.

10. In the semiconductor device described in claim 8, The first chip mounting portion has a first back surface on which the first semiconductor chip is not placed. The second chip mounting portion has a second back surface on which the second semiconductor chip is not placed. The third chip mounting portion has a third back surface on which the isolator chip is not placed, The first chip resistor is positioned across the first back surface and the third back surface, The second chip resistor is positioned across the second back surface and the third back surface.

11. In the semiconductor device according to claim 4, The resistance value of the first chip resistor is 5 MΩ to 50 MΩ. The resistance value of the second chip resistor is 5 MΩ to 50 MΩ.

12. In the semiconductor device described in claim 1, The third potential applied to the third chip mounting portion is higher than the first potential and lower than the second potential.

13. In the semiconductor device described in claim 1, The distance between the lower conductor portion and the first upper conductor portion is defined as the first distance. The distance between the lower conductor portion and the second upper conductor portion is defined as the second distance. When the distance between the lower conductor portion and the third chip mounting portion is defined as the third distance, The third distance is smaller than the first distance. The third distance is smaller than the second distance.

14. In the semiconductor device described in claim 1, When the planar arrangement direction of the first semiconductor chip, the isolator chip, and the second semiconductor chip is defined as the first direction, and the planar arrangement direction of the first upper conductor portion and the second upper conductor portion is defined as the fourth direction, the first direction and the fourth direction are directions that intersect each other.

15. (a) A step of preparing a lead frame having a first chip mounting section, a second chip mounting section and a third chip mounting section, (b) A step of placing the first semiconductor chip on the first chip mounting portion via a first adhesive, (c) A step of placing a second semiconductor chip on the second chip mounting portion via a second adhesive, (d) A step of placing an isolator chip on the third chip mounting portion via a third adhesive, (e) A step of arranging the first chip resistor via a fourth adhesive so as to span the first chip mounting portion and the third chip mounting portion, (f) A step of arranging a second chip resistor via a fifth adhesive so as to span the second chip mounting portion and the third chip mounting portion, (g) After performing steps (b) through (e), the lead frame is subjected to a heat treatment to cure the first adhesive, the second adhesive, the third adhesive, the fourth adhesive and the fifth adhesive. A method for manufacturing a semiconductor device, comprising:

16. In the method for manufacturing a semiconductor device according to claim 15, (h) After step (g), the process includes a step of forming a encapsulant that encapsulates the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor, The aforementioned (h) step is, (h1) A step of sandwiching the lead frame between an upper mold and a lower mold while forming the cavity such that the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor are arranged in the cavity. (h2) A step of injecting resin material into the cavity from the gate, Includes, The gate is formed in the upper or lower mold such that the resin material is injected into the narrowest gap in the cavity where the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor are arranged.

17. (a) A step of preparing a lead frame having a first chip mounting section, a second chip mounting section and a third chip mounting section, (b) A step of placing the first semiconductor chip on the first chip mounting portion via a first adhesive, (c) A step of placing a second semiconductor chip on the second chip mounting portion via a second adhesive, (d) A step of placing an isolator chip on the third chip mounting portion via a third adhesive, (e) After performing steps (b) through (d), a first heat treatment is applied to the lead frame to cure the first adhesive, the second adhesive and the third adhesive. (f) After step (e), the first semiconductor chip and the third semiconductor chip are electrically connected to each other with a first bonding wire, and the second semiconductor chip and the third semiconductor chip are electrically connected to each other with a second bonding wire. (g) After step (f), a step of arranging the first chip resistor via a fourth adhesive so as to span the first chip mounting portion and the third chip mounting portion, (h) A step of arranging the second chip resistor via a fifth adhesive so as to span the second chip mounting portion and the third chip mounting portion, (i) After performing steps (g) through (h), a second heat treatment is applied to the lead frame to cure the fourth adhesive and the fifth adhesive. A method for manufacturing a semiconductor device, comprising:

18. In the method for manufacturing a semiconductor device according to claim 17, (j) After step (i), the process includes a step of forming a encapsulant that encapsulates the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor, The above step (j) is, (j1) A step of sandwiching the lead frame between an upper mold and a lower mold while forming the cavity such that the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor are arranged in the cavity. (j2) A step of injecting resin material into the cavity from the gate, Includes, The gate is formed in the upper or lower mold such that the resin material is injected into the narrowest gap in the cavity where the first semiconductor chip, the second semiconductor chip, the isolator chip, the first chip resistor, and the second chip resistor are arranged.

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