Wiring board, semiconductor device, and method for manufacturing a wiring board

Abstract

The present invention provides a wiring board, a semiconductor device, and a method for manufacturing a wiring board that can improve the adhesion between the insulating layer and the dam member. [Solution] The wiring board has a wiring layer, an insulating layer 30 provided on the wiring layer, and a frame-shaped dam member 40 provided on the insulating layer and containing resin and filler dispersed in the resin, wherein the dam member has a first region 46 that contacts the insulating layer and a second region 47 located above the first region, and the volume ratio of the resin in the first region is higher than the volume ratio of the resin in the second region.

Description

Technical Field

[0001] The present disclosure relates to a wiring board, a semiconductor device, and a method for manufacturing a wiring board.

Background Art

[0002] There is a semiconductor device in which an electronic component is mounted on a wiring board and an underfill is provided between the wiring board and the electronic component. When providing the underfill, a fluid underfill is poured, but the underfill may flow out to an unnecessary portion. Therefore, a wiring board having a dam member surrounding the mounting area of the electronic component for suppressing the outflow of the underfill has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, there has been an increasing demand for improving the adhesion between an insulating layer such as a solder resist layer included in a wiring board and a dam member.

[0005] An object of the present disclosure is to provide a wiring board, a semiconductor device, and a method for manufacturing a wiring board that can improve the adhesion between an insulating layer and a dam member.

Means for Solving the Problems

[0006] According to one embodiment of the present disclosure, a wiring substrate is provided, comprising: a wiring layer; an insulating layer provided on the wiring layer; and a frame-shaped dam member provided on the insulating layer and containing a resin and a filler dispersed in the resin, wherein the dam member has a first region in contact with the insulating layer and a second region located above the first region, and the volume ratio of the resin in the first region is higher than the volume ratio of the resin in the second region. [Effects of the Invention]

[0007] According to the disclosed technology, the adhesion between the insulating layer and the dam member can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This figure illustrates a wiring board according to the first embodiment. [Figure 2] This is a cross-sectional view illustrating a dam component. [Figure 3] This is a cross-sectional view (part 1) illustrating a method for manufacturing a wiring board according to the first embodiment. [Figure 4] This is a cross-sectional view (part 2) illustrating a method for manufacturing a wiring board according to the first embodiment. [Figure 5] This is a cross-sectional view illustrating a filler-containing layer that has undergone planarization pressing. [Figure 6] This figure illustrates a cross-sectional scanning electron microscope image. [Figure 7] This is a cross-sectional view illustrating a semiconductor device according to the second embodiment. [Figure 8] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0009] The embodiments will be described in detail below with reference to the attached drawings. In this specification and the drawings, components having substantially the same functional configuration will be denoted by the same reference numerals to avoid redundant descriptions.

[0010] (First Embodiment) A first embodiment will be described. The first embodiment relates to a wiring board.

[0011] [Structure of the wiring board according to the first embodiment] The structure of the wiring board according to the first embodiment will now be described. Figure 1 is a diagram illustrating the wiring board according to the first embodiment. Figure 1(a) is a plan view, and Figure 1(b) is a cross-sectional view. Figure 1(b) corresponds to a cross-sectional view along the line Ib-Ib in Figure 1(a).

[0012] The wiring board 1 according to the first embodiment is, for example, a build-up board. As shown in Figure 1, the wiring board 1 has a substrate 10, a wiring layer 20, a solder resist layer 30, a dam member 40, a barrier layer 51, and connecting bumps 52.

[0013] The substrate 10 is, for example, a resin substrate having multiple wiring layers (not shown) and multiple insulating resin layers (not shown). The substrate 10 may or may not have a core layer.

[0014] The wiring layer 20 is provided on one side of the substrate 10. The wiring layer 20 is electrically connected to the wiring layer within the substrate 10. The wiring layer 20 includes electrode pads 21. The wiring layer 20 includes, for example, copper (Cu).

[0015] In this embodiment, for convenience, the substrate 10 is used as the reference, with the wiring layer 20 side being the upper side or one side, and the opposite side being the lower side or the other side. Also, the upper surface of each part is referred to as one surface or top surface, and the lower surface is referred to as the other surface or bottom surface. However, the wiring board 1 can be used upside down or arranged at any angle. Furthermore, a plan view refers to viewing the object from the direction normal to one surface of the substrate 10, and a planar shape refers to the shape of the object when viewed from the direction normal to one surface of the substrate 10.

[0016] The solder resist layer 30 is formed to cover the wiring layer 20 on one surface of the substrate 10. An opening 31 is formed in the solder resist layer 30. The opening 31 penetrates the solder resist layer 30. The opening 31 overlaps with the electrode pad 21 which is a part of the wiring layer 20 in plan view and reaches the electrode pad 21. The solder resist layer 30 is an example of an insulating layer.

[0017] The barrier layer 51 is provided on one surface of the electrode pad 21 within the opening 31. The connection bump 52 is provided on the barrier layer 51 and the solder resist layer 30. The connection bump 52 has a portion within the opening 31 and is electrically connected to the electrode pad 21 of the wiring layer 20. The barrier layer 51 has, for example, a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) layer formed in order from the side of the electrode pad 21. The connection bump 52 contains, for example, copper (Cu).

[0018] The dam member 40 is provided on the solder resist layer 30. The thickness of the dam member 40 is, for example, about 10 μm to 50 μm, preferably 15 μm to 40 μm, and more preferably 20 μm to 30 μm. The dam member 40 has a frame-like shape in plan view. In plan view, the opening 31, the barrier layer 51, and the connection bump 52 are located inside the dam member 40. FIG. 2 is a cross-sectional view illustrating the dam member. As shown in FIG. 2, the dam member 40 contains a resin 41 and a filler 42. The filler 42 is dispersed in the resin 41. The resin 41 contains, for example, an epoxy resin, a polyimide resin, or an acrylic resin. The resin 41 may contain two or more of these. The filler 42 contains, for example, silica (SiO2). The particle size of the filler 42 is, for example, about 3 μm to 4 μm. The ratio of the mass of the filler 42 to the mass of the dam member 40 is, for example, about 30% to 70%. Also, the dam member 40 has a first region 46 and a second region 47. The first region 46 contacts the solder resist layer 30. The second region 47 is located above the first region 46. The first region 46 is between the solder resist layer 30 and the second region 47. The volume ratio of the resin 41 in the first region 46 is higher than the volume ratio of the resin 41 in the second region 47.

[0019] As described below, electronic components are mounted inside the dam member 40 in a plan view, and an underfill is provided between the electronic components and the solder resist layer 30. At this time, the uncured and fluid underfill is blocked inside the dam member 40.

[0020] In the wiring board 1, the dam member 40 has a first region 46 and a second region 47, and the volume ratio of the resin 41 in the first region 46 is higher than the volume ratio of the resin 41 in the second region 47. For this reason, the adhesion between the dam member 40 and the solder resist layer 30 can be improved.

[0021] [Manufacturing Method of Wiring Board According to First Embodiment] The manufacturing method of the wiring board according to the first embodiment will be described. FIGS. 3 to 4 are cross-sectional views illustrating the manufacturing method of the wiring board according to the first embodiment.

[0022] First, as shown in FIG. 3(a), a wiring layer 20 and a solder resist layer 30 are formed on one surface of the substrate 10.

[0023] As the substrate 10, a large-sized substrate on which a plurality of wiring boards 1 can be taken is used. That is, the substrate 10 has a plurality of regions in which structures corresponding to the wiring boards 1 are formed. Then, after collectively manufacturing members that will become the plurality of wiring boards 1, the members are separated into individual wiring boards 1 by cutting along the cutting line CL. For convenience of explanation, parts that will finally become each component of the wiring board 1 are described with reference numerals of the final components.

[0024] The substrate 10 has a cutting region 11 that is cut off during the individualization process. When forming the wiring layer 20, the wiring layer 20 includes electrode pads 21 and alignment marks 25 within the cutting region 11. The solder resist layer 30 has openings 31 and openings 32 in which the alignment marks 25 are exposed within the cutting region 11. In forming the solder resist layer 30, for example, a photosensitive filler-containing layer that will become the solder resist layer 30 is attached and flattened by a vacuum lamination method, and then the filler-containing layer is exposed and developed. After forming the openings 31 and 32, a process may be performed to remove the native oxide film present on the surfaces of the electrode pads 21 and alignment marks 25.

[0025] Next, as shown in Figure 3(b), a filler-containing layer 45 is provided on the solder resist layer 30. The filler-containing layer 45 is a layer that will later become a dam member 40 and contains resin 41 and filler 42 (see Figure 3). At this stage, the resin 41 is photosensitive. The filler-containing layer 45 can be provided by a vacuum lamination method. For example, the temperature of the substrate 10 when providing the filler-containing layer 45 is set to about 60°C to 90°C, and the filler-containing layer 45 is attached to the solder resist layer 30 at a pressure of about 0.3 MPa to 2 MPa. In the filler-containing layer 45 provided on the solder resist layer 30 by the vacuum lamination method, the resin 41 flows towards the solder resist layer 30 due to the pressure during lamination, and therefore has a first region 46 and a second region 47. However, the openings 31 and 32 are not filled by the filler-containing layer 45, and voids exist inside.

[0026] Subsequently, as shown in Figure 4(a), the filler-containing layer 45 is processed into a frame-shaped dam member 40 while having a first region 46 and a second region 47. During the processing of the filler-containing layer 45, the position of the alignment marks 25 is confirmed by looking through the filler-containing layer 45, and the filler-containing layer 45 is exposed to light while being aligned with the alignment marks 25 as a reference, and then developed.

[0027] Next, as shown in Figure 4(b), a barrier layer 51 is formed on one side of the electrode pad 21 within the opening 31, and a connecting bump 52 is formed on the barrier layer 51.

[0028] Next, the structure shown in Figure 4(b) is cut along the cutting line CL. As a result, the cutting region 11 and the alignment marks 25 and solder resist layer 30 above it are cut off. In this way, the wiring board 1 can be manufactured.

[0029] Furthermore, it is conceivable to perform a flattening press on the filler-containing layer 45 after it has been formed by the vacuum lamination method and before it has been processed into a frame-shaped dam member 40. However, if a flattening press is performed under general conditions, the filler 42 will be dispersed throughout the filler-containing layer 45, and the first region 46 will disappear from the filler-containing layer 45. As a result, it will not be possible to improve the adhesion between the dam member 40 and the solder resist layer 30. Also, if a flattening press is performed under general conditions, as shown in Figure 5, the filler-containing layer 45 will move into the opening 32, causing the filler-containing layer 45 to become thicker above the alignment mark 25. As a result, depending on the thickness of the filler-containing layer 45, the visibility of the alignment mark 25 may decrease, and it may become impossible to confirm the position of the alignment mark 25. Therefore, it is preferable not to perform a flattening press on the filler-containing layer 45. The filler-containing layer 45 may be flattened by pressing, but in order to improve adhesion, the filler-containing layer 45 should be flattened to the extent that the first region 46 and the second region 47 remain. Figure 5 is a cross-sectional view illustrating a filler-containing layer 45 that has been flattened by pressing.

[0030] Figure 6 illustrates cross-sectional scanning electron microscope (SEM) images. Figure 6(a) shows a cross-sectional SEM image of a sample in which a filler-containing layer 45A was attached to a solder resist layer 30A by vacuum lamination, and no planarization press was performed afterward. Figure 6(b) shows a cross-sectional SEM image of a sample in which a filler-containing layer 45A was attached to a solder resist layer 30A by vacuum lamination, and then a planarization press was performed. In the sample in which no planarization press was performed, as shown in Figure 6(a), there is a region 41A with a low volume ratio of filler near the interface between the filler-containing layer 45A and the solder resist layer 30A. On the other hand, in the sample in which a planarization press was performed, as shown in Figure 6(b), the filler is dispersed almost uniformly within the filler-containing layer 45A, and there is no region with a low volume ratio of filler near the interface with the solder resist layer 30A.

[0031] For example, the ratio of the volume of filler 42 in the first region 46 to the volume of filler 42 in the second region 47 is 60% or less. If this ratio is greater than 60%, the effect of improving adhesion by the first region 46 may be reduced. This ratio is preferably 50% or less, and more preferably 40% or less.

[0032] For example, the thickness of the first region 46 is 1 μm or more and 3 μm or less. If the thickness of the first region 46 is less than 1 μm, the effect of improving adhesion by the first region 46 may be reduced. If the thickness of the first region 46 is greater than 3 μm, the strength of the dam member 40 may be reduced. The thickness of the first region 46 is preferably 1 μm or more and 2.5 μm or less, and more preferably 1 μm or more and 2 μm or less.

[0033] The relative volume ratios of filler 42 between the first region 46 and the second region 47 can be substituted with the relative area ratios of filler 42 observed in the cross-section. Alternatively, the volume ratio can be calculated by raising the ratio of area ratios to the power of 3 / 2. For example, if the ratio of the area ratio of filler 42 in the first region 46 to the area ratio of filler 42 in the second region 47 is 64%, then the ratio of the volume ratio of filler 42 in the first region 46 to the volume ratio of filler 42 in the second region 47 can be calculated as 51.2%.

[0034] (Second Embodiment) A second embodiment will now be described. The second embodiment relates to a semiconductor device having a wiring board 1 according to the first embodiment.

[0035] [Structure of the semiconductor device according to the second embodiment] The structure of a semiconductor device according to the second embodiment will now be described. Figure 7 is a cross-sectional view illustrating a semiconductor device according to the second embodiment.

[0036] As shown in Figure 7, the semiconductor device 2 according to the second embodiment includes a wiring board 1, electronic components 60, and underfill 70.

[0037] The electronic component 60 is electrically connected to the connecting bump 52. The electronic component 60 has an interposer 61 and a die 62. The interposer 61 is, for example, a silicon (Si) interposer. The interposer 61 may also be an interposer made of resin or the like. The interposer 61 has electrodes that are joined to the connecting bump 52 using, for example, solder. The die 62 is, for example, a semiconductor chip and is mounted on the interposer 61.

[0038] The underfill 70 is provided between the solder resist layer 30 and the electronic component 60. The underfill 70 covers the sides of the connection bump 52 and protects the connection bump 52. The underfill 70 contains, for example, epoxy resin.

[0039] [Manufacturing method for a semiconductor device according to the second embodiment] A method for manufacturing a semiconductor device according to the second embodiment will now be described. Figure 8 is a cross-sectional view illustrating the method for manufacturing a semiconductor device according to the second embodiment.

[0040] First, as shown in Figure 8(a), a wiring board 1 is prepared, and electronic components 60 are mounted on the wiring board 1. At this time, the electrodes of the interposer 61 are joined to the connection bumps 52 using, for example, solder.

[0041] Next, as shown in Figure 8(b), the uncured and fluid underfill 71 is poured between the electronic component 60 and the solder resist layer 30. Since the dam member 40 is provided on top of the solder resist layer 30, the underfill 71 is dammed up inside the dam member 40.

[0042] Subsequently, the underfill 71 is cured to form underfill 70 (see Figure 7). The sides of the connecting bump 52 are covered by the underfill 70, and the connecting bump 52 is protected by the underfill 70.

[0043] In this way, the semiconductor device 2 can be manufactured.

[0044] Furthermore, the electronic component 60 does not need to include the interposer 61, and the semiconductor chip may be flip-chip connected to the connection bump 52.

[0045] Although preferred embodiments have been described in detail above, this disclosure is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of Symbols]

[0046] 1 Wiring board 2 Semiconductor devices 10 circuit boards 20 wiring layer 21 Electrode Pads 25 Alignment Marks 30 Solder Resist Layers 40 Dam components 41 Resin 42 Filler 45 Filler-containing layer 46 First area 47 Second area 60 Electronic Components 61 Interposer 62 Dies 70, 71 Underfill

Claims

1. Wiring layer and An insulating layer provided on the aforementioned wiring layer, A frame-shaped dam member provided on the insulating layer, containing a resin and a filler dispersed in the resin, It has, The aforementioned dam member is A first region in contact with the insulating layer, A second region located above the first region, It has, A wiring board in which the volume ratio of the resin in the first region is higher than the volume ratio of the resin in the second region.

2. The wiring board according to claim 1, wherein the ratio of the volume ratio of the filler in the first region to the volume ratio of the filler in the second region is 60% or less.

3. The wiring substrate according to claim 1 or 2, wherein the thickness of the first region is 1 μm or more and 3 μm or less.

4. In a plan view, an opening is formed in the insulating layer on the inside of the dam member. The wiring board according to claim 1 or 2, having a portion within the opening and a connecting bump electrically connected to the wiring layer.

5. The wiring board according to claim 4, An electronic component electrically connected to the aforementioned connecting bump, An underfill provided between the insulating layer and the electronic component, Semiconductor device.

6. A process of forming an insulating layer on top of a wiring layer, A step of providing a filler-containing layer containing a resin and a filler dispersed in the resin on the insulating layer by a vacuum lamination method, The process of processing the filler-containing layer into a frame-shaped dam member, It has, The filler-containing layer is A first region in contact with the insulating layer, A second region located above the first region, It has, The volume ratio of the resin in the first region is higher than the volume ratio of the resin in the second region. A method for manufacturing a wiring board, wherein the filler-containing layer is processed into the dam member having the first region and the second region.

7. The method for manufacturing a wiring substrate according to claim 6, wherein the step of processing the filler-containing layer is a step of exposure and development of the filler-containing layer.

8. A method for manufacturing a wiring board according to claim 6 or 7, wherein a flattening press of the filler-containing layer is not performed between the step of providing the filler-containing layer and the step of processing the filler-containing layer.

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