Oxide semiconductor thin-film transistor

Abstract

This controls the threshold voltage of an oxide semiconductor thin-film transistor. [Solution] The oxide semiconductor thin-film transistor includes a gate electrode, a source electrode, and a drain electrode, an oxide semiconductor layer connected to the source electrode and the drain electrode, respectively, and a gate insulating film between the gate electrode and the oxide semiconductor layer in the stacking direction. The oxide semiconductor layer includes a channel region. The gate insulating film includes a first insulating film made of silicon nitride and / or silicon oxynitride, and a metal oxide film. A portion of the first insulating film is disposed between the metal oxide film and the oxide semiconductor layer. At least a portion of the first end of the metal oxide film overlaps the channel region in a plan view and faces one of the source electrode and the drain electrode.

Description

Technical Field

[0001] The present disclosure relates to an oxide semiconductor thin film transistor.

Background Art

[0002] Thin film transistors (TFTs) are used in various fields such as display devices and radiation sensors. A TFT having an oxide semiconductor typified by IGZO (InGaZnO) as an active layer can obtain high mobility despite having an amorphous structure. However, since it is difficult to control the Fermi energy by adding donors and acceptors, it has been difficult to control the threshold voltage of the TFT.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] A technique capable of controlling the threshold voltage of an oxide semiconductor TFT is desired.

Means for Solving the Problems

[0005] An oxide semiconductor thin-film transistor according to one aspect of the present disclosure includes a gate electrode, a source electrode, and a drain electrode; an oxide semiconductor layer connected to the source electrode and the drain electrode, respectively; and a gate insulating film between the gate electrode and the oxide semiconductor layer in the stacking direction. The oxide semiconductor layer includes a channel region. The gate insulating film includes a first insulating film made of silicon nitride and / or silicon oxynitride, and a metal oxide film. A portion of the first insulating film is disposed between the metal oxide film and the oxide semiconductor layer. At least a portion of the first end of the metal oxide film overlaps the channel region in a plan view and faces either the source electrode or the drain electrode. [Effects of the Invention]

[0006] According to one aspect of this disclosure, the threshold voltage of an oxide semiconductor TFT can be controlled. [Brief explanation of the drawing]

[0007] [Figure 1] This shows an X-ray sensor. [Figure 2] This shows the cross-sectional structure of a pixel in an X-ray sensor. [Figure 3] This is a schematic cross-sectional view showing an example of the configuration of an oxide semiconductor thin TFT in which the gate insulating film is composed of a SiNx / SiOx / SiNx multilayer film. [Figure 4A] A band diagram is shown to explain the carrier movement during X-ray irradiation of an oxide semiconductor TFT. [Figure 4B] A band diagram is shown to explain the carrier movement during X-ray irradiation of an oxide semiconductor TFT. [Figure 5] This is a schematic cross-sectional view showing the configuration of an oxide semiconductor TFT according to one embodiment of the present disclosure. [Figure 6] This is a schematic plan view showing the positional relationship between the silicon oxide film, the channel region, and several other components in an oxide semiconductor TFT. [Figure 7A]Figures 5 and 6 schematically show the charge state generated when radiation is applied to an oxide semiconductor TFT according to one embodiment, with a gate bias applied. [Figure 7B] This graph schematically illustrates the change in the threshold voltage in the negative direction. [Figure 8A] Figures 5 and 6 schematically show the charge state generated when radiation is applied to an oxide semiconductor TFT according to one embodiment, with a gate bias applied. [Figure 8B] This graph schematically shows the change in the positive direction of the threshold voltage. [Figure 9] This graph shows the relationship between the electric field strength generated by planar charges of different areas and the distance from the planar charges. [Figure 10] This is a schematic cross-sectional view showing the configuration of an oxide semiconductor TFT according to one embodiment of the present disclosure. [Figure 11] Figure 10 is a schematic plan view showing the positional relationship between the silicon oxide film, the channel region, and several other components in an oxide semiconductor TFT. [Figure 12] This is a schematic cross-sectional view showing the configuration of an oxide semiconductor TFT according to one embodiment of the present disclosure. [Figure 13] Figure 12 is a schematic plan view showing the positional relationship between the silicon oxide film, the channel region, and several other components in an oxide semiconductor TFT. [Figure 14A] This exhibits a planar charge that extends infinitely in both the positive and negative directions along the Y-axis, and infinitely in the positive direction along the X-axis. [Figure 14B] Figure 14A shows the value of the Z-axis component of the electric field strength created by the planar charge at coordinate (x,z). [Figure 15] This is a schematic cross-sectional view showing the configuration of an oxide semiconductor TFT according to one embodiment of the present disclosure. [Figure 16] Figure 15 is a schematic plan view showing the positional relationship between the silicon oxide film, the channel region, and several other components in an oxide semiconductor TFT. [Figure 17]It is a plan view schematically showing the configuration of an oxide semiconductor TFT according to an embodiment of the present disclosure. [Figure 18] It is a cross-sectional view schematically showing the configuration of an oxide semiconductor TFT according to an embodiment of the present disclosure. [Figure 19] It is a cross-sectional view schematically showing the configuration of an oxide semiconductor TFT according to an embodiment of the present disclosure. [Figure 20A] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 20B] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 20C] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 20D] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 20E] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 20F] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 20G] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 20H] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 20I] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 20J] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 21A] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 21B] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 21C] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 21D] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 21E] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 21F] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 21G] It shows the steps in the manufacturing method of an oxide semiconductor TFT. [Figure 21H] This shows the process for manufacturing oxide semiconductor TFTs. [Figure 21I] This shows the process for manufacturing oxide semiconductor TFTs. [Figure 21J] This shows the process for manufacturing oxide semiconductor TFTs. [Modes for carrying out the invention]

[0008] The embodiments will be described below with reference to the attached drawings. These embodiments are merely examples for realizing the present disclosure and do not limit the technical scope of the present disclosure. For the sake of clarity, the dimensions and shapes of the illustrated objects may be exaggerated in some cases.

[0009] The oxide semiconductor thin-film transistors (TFTs) according to the embodiments of this disclosure can be applied to various devices such as display devices and radiation sensors. Figure 1 shows an X-ray sensor 10 as an example of a device to which an oxide semiconductor TFT according to the embodiments of this disclosure is applied. The X-ray sensor 10 is an image sensor used, for example, for capturing X-ray transmission images.

[0010] The X-ray sensor 10 includes a pixel matrix 101, a scanning circuit 170, and a detection circuit 150. The pixel matrix 101 includes pixels 102 arranged in a matrix. The pixel matrix 101 is formed on a substrate 100. The substrate 100 is an insulating substrate, such as a glass substrate or a resin substrate.

[0011] Pixel 102 is located at each intersection of multiple signal lines 106 extending vertically and arranged horizontally in Figure 1, and multiple gate lines (scan lines) 105 extending horizontally and arranged vertically. Each pixel 102 is connected to a bias line 107 extending vertically and arranged horizontally in Figure 1. In Figure 1, only one pixel, one signal line, one gate line, and one bias line are indicated by the symbols 102, 106, 105, and 107, respectively.

[0012] Each signal line 106 is connected to a different pixel row. Each gate line 105 is connected to a different pixel row. The signal lines 106 are connected to the detection circuit 150, and the gate lines 105 are connected to the scanning circuit 170. The bias line 107 is connected to the common bias line 108. A bias potential is applied to the pad 109 of the common bias line 108.

[0013] Pixel 102 includes a photodiode 103, which is a photoelectric conversion element, and a TFT 104, which is a switching element. The gate of the TFT 104 is connected to the gate line 105, one source / drain is connected to the signal line 106, and the other source / drain is connected to the cathode of the photodiode 103. In the example in Figure 1, the anode of the photodiode 103 is connected to the bias line 107.

[0014] In the configuration example shown in Figure 1, TFT104 is an n-type conductivity type. The TFT may have other conductivity types. In this embodiment, TFT104 is an oxide semiconductor TFT. Oxide semiconductor TFTs exhibit excellent switching characteristics.

[0015] The X-ray sensor 10 reads out a signal by making the signal charge accumulated in the photodiode 103 in accordance with the amount of X-ray irradiation, conduction through the TFT 104 located in its pixel 102, and extracting it to the outside. Specifically, when light is incident on the photodiode 103, a signal charge is generated and accumulated in the photodiode 103.

[0016] The scanning circuit 170 sequentially selects gate lines 105 and applies pulses that cause the TFT 104 to conduct. The anode terminal of the photodiode 103 is connected to the bias line 107, and the signal line 106 is supplied with a reference potential by the detection circuit 150. As a result, the photodiode 103 is charged with the difference voltage between the bias potential of the bias line 107 and the reference potential. This difference voltage is set to a reverse bias voltage where the cathode potential is higher than the anode potential.

[0017] The charge required to recharge the photodiode 103 to this reverse bias voltage depends on the amount of light irradiated onto the photodiode 103. The detection circuit 150 reads the signal charge by integrating the current that flows when the photodiode 103 is recharged to the reverse bias.

[0018] The charge stored in the photodiode 103 inevitably decreases due to the reduction in charge caused by the irradiated light and the dark leakage current that flows even when the photodiode 103 is not irradiated with light. Therefore, when reading the signal charge, the voltage at the terminal connected to the signal line 106 of the TFT 104 is greater than or equal to the voltage at the terminal connected to the photodiode 103. In other words, when detecting the signal charge, the terminal connected to the signal line 106 of the TFT 104 is the drain, and the terminal connected to the photodiode 103 is the source.

[0019] Figure 2 shows the cross-sectional structure of a pixel. In the following explanation, the side of the X-ray sensor 10 on which the object to be measured is placed is referred to as the front side. In the example in Figure 2, the side opposite the photodiode 103 on the substrate 100 is the front side. Also, in terms of the positional relationship of the pixel components, the side with the substrate 100 is referred to as the bottom side, and the opposite side is referred to as the top side.

[0020] The TFT 104 and photodiode 103 contained in the pixel each have a stacked structure. The TFT 104 includes a gate electrode 202 formed on an insulating substrate 100, a gate insulating film 203 on the gate electrode 202, and an oxide semiconductor layer 204 on the gate insulating film 203. As will be described later, the gate insulating film 203 includes multiple insulating films of different materials.

[0021] The TFT 104 shown in Figure 2 has a bottom gate structure, and the gate electrode 202 is located on the underside of the oxide semiconductor layer 204. The TFT 104 further includes source / drain electrodes 205 and 206 on the gate insulating film 203. The source / drain electrodes 205 and 206 are each connected to the oxide semiconductor layer 204. The source / drain electrodes 205 and 206 are formed so as to be in contact with the side and part of the top surface of the island-shaped oxide semiconductor layer 204.

[0022] Depending on the carrier flow, one of the source / drain electrodes 205 and 206 is the source electrode and the other is the drain electrode. In detecting the charge of the photodiode 103, electrode 205 is the drain electrode and electrode 206 is the source electrode. Therefore, in the following, electrode 205 is assumed to be the drain electrode and electrode 206 is assumed to be the source electrode.

[0023] The gate insulating film 203 is formed to cover the entire surface of the gate electrode 202. The gate insulating film 203 is formed between the gate electrode 202 and the oxide semiconductor layer 204, and between the gate electrode 202 and the drain electrode 25 and the source electrode 206, respectively.

[0024] The first interlayer insulating layer 207 covers the entire TFT 104. Specifically, the first interlayer insulating layer 207 covers the upper surface of the oxide semiconductor layer 204, as well as the upper surfaces of the drain electrode 205 and the source electrode 206.

[0025] The substrate 100 is formed of, for example, glass or resin. The gate electrode 202 is a conductor and can be formed of metal or impurity-doped silicon. The gate insulating film 203 has a multilayer structure. The gate insulating film 203 may include an insulating film made of oxide and an insulating film made of nitride or oxynitride. Details of the gate insulating film 203 will be described later.

[0026] The oxide semiconductor constituting the oxide semiconductor layer 204 is an oxide semiconductor containing at least one of In, Ga, and Zn, and examples include amorphous InGaZnO (a-InGaZnO) and microcrystalline InGaZnO. In addition, oxide semiconductors such as a-InSnZnO and a-InGaZnSnO can be used. In the examples described below, amorphous or microcrystalline InGaZnO (hereinafter also referred to as IGZO) will be mainly used.

[0027] The drain electrode 205 and the source electrode 206 are conductors and can be formed from metals such as Mo, Ti, Al, and Cr, their alloys, or laminates thereof. The first interlayer insulating layer 207 is an inorganic or organic insulator. The TFT 104 shown in Figure 2 has a bottom gate structure, but the TFT 104 may have a top gate structure, or a double gate structure including both a top gate and a bottom gate.

[0028] A photodiode 103 is formed on the first interlayer insulating layer 207. An example of the photodiode 103 shown in Figure 2 is a PIN diode. The PIN diode can efficiently detect light by forming a wide depletion layer in the film thickness direction. The photodiode 103 includes a semiconductor laminate sandwiched between a lower electrode 208 and an upper electrode 212 on the first interlayer insulating layer 207. The lower electrode 208 is connected to the source electrode 206 of the TFT 104 via the interconnection portion of the via hole 221 in the first interlayer insulating layer 207.

[0029] The lower electrode 208 is a conductor and can be formed from, for example, a metal such as Cr, Mo, or Al, an alloy thereof, or a laminate thereof. The upper electrode 212 is a transparent electrode to light from the scintillator 216 and is, for example, ITO.

[0030] The photodiode 103 includes an n-type amorphous silicon layer 209 on the lower electrode 208, an intrinsic amorphous silicon layer 210 on the n-type amorphous silicon layer 209, and a p-type amorphous silicon layer 211 on the intrinsic amorphous silicon layer 210. The upper electrode 212 is formed on the p-type amorphous silicon layer 211. The light to be detected is incident on the photodiode 103 from the upper electrode 212 side (p-type amorphous silicon layer 211 side).

[0031] The second interlayer insulating layer 213 is formed to cover the photodiode 103. Specifically, the second interlayer insulating layer 213 is formed on a part of the first interlayer insulating layer 207 and on the upper electrode 212. The second interlayer insulating layer 213 is an inorganic or organic insulator.

[0032] A bias wire 107 is formed on the second interlayer insulating layer 213. The bias wire 107 is connected to the upper electrode 212 by interconnects formed in via holes 222 of the second interlayer insulating layer 213. The bias wire 107 is a conductor and can be formed from, for example, metals such as Mo, Ti, Al, alloys thereof, or laminates thereof.

[0033] A passivation layer 215 is formed to cover the bias line 107 and the second interlayer insulating layer 213. The passivation layer 215 covers the entire pixel matrix 101. The passivation layer 215 is an inorganic or organic insulator. A scintillator 216 is placed on the passivation layer 215.

[0034] The scintillator 216 covers the entire area of ​​the pixel matrix 101. The scintillator 216 emits light when excited by radiation. Specifically, the scintillator 216 converts incident X-rays into light of a wavelength that the photodiode 103 can detect. The photodiode 103 accumulates a signal charge in response to the light from the scintillator 216.

[0035] The configuration of an oxide semiconductor TFT according to one embodiment of this disclosure will be described below. The oxide semiconductor TFT according to one embodiment of this disclosure can be applied to devices different from the X-ray sensor described above, such as a display device.

[0036] TFTs using oxide semiconductors such as IGZO (InGaZnO) as the active layer can achieve high mobility despite their amorphous structure. However, controlling the Fermi energy by adding donors and acceptors is difficult, making it challenging to control the threshold by adding impurities to the TFT channel.

[0037] In response, the inventors investigated a method to control the threshold of a TFT by constructing the gate insulating film as a SiNx / SiOx / SiNx multilayer film, applying a voltage to the gate of an oxide semiconductor TFT, and irradiating it with light having an energy greater than the band gap of the gate insulating film, thereby accumulating a desired charge at the interface of the three layers, and controlling the potential of the oxide semiconductor interface with the electric field generated by this charge (see, for example, Japanese Patent Application No. 2023-123799).

[0038] Specifically, when an oxide semiconductor is irradiated with high-energy light such as X-rays, h (hole) and e (electron) pairs are photoexcited and generated. Furthermore, when a negative voltage is applied to the source-gate voltage of the TFT, the h in the oxide semiconductor hops to the interface with the gate insulating film SiNx and is trapped in the interface state, causing a threshold voltage fluctuation. Conversely, when a positive voltage is applied between the source and gate, the e induced in the channel is trapped in the interface state with the gate insulating film SiNx, causing a threshold voltage fluctuation.

[0039] These methods for reducing threshold voltage fluctuations involve using a three-layer structure of SiNx / SiOx / SiNx for the gate insulating film. Depending on the polarity of the voltage applied between the source and gate, charges of different polarities are accumulated at two of these interfaces. The electric field created by these accumulated charges cancels out the electric field created by charges trapped at the gate insulating film interface.

[0040] Figure 3 is a schematic cross-sectional view showing an example of the configuration of an oxide semiconductor TFT in which the gate insulating film is composed of a SiNx / SiOx / SiNx multilayer film. The oxide semiconductor TFT 500 includes a gate electrode 502, a gate insulating film 503 on the gate electrode 502, and an oxide semiconductor layer 504 on the gate insulating film 503. An interlayer insulating layer 507 covers the entire oxide semiconductor TFT 500.

[0041] The gate insulating film 503 has a three-layer structure and is composed of a lower silicon nitride film (SiNx) 511, a silicon oxide film (SiOx) 512 on the lower silicon nitride film 511, and an upper silicon nitride film 513 on the silicon oxide film 512. These are the lower region, upper region, and intermediate region of the gate insulating film 503.

[0042] The intermediate insulating layer, silicon oxide film 512, contacts the lower silicon nitride film 511 and the upper silicon nitride film 513 to form an interface. In the gate insulating film 503, the lower silicon nitride film 511 forms an interface with the gate electrode 502, and the upper silicon nitride film 513 forms an interface with the oxide semiconductor layer 504.

[0043] The oxide semiconductor TFT 500 has a bottom gate structure, with the gate electrode 502 located beneath the oxide semiconductor layer 504. The oxide semiconductor TFT 500 further includes source / drain electrodes 505 and 506 on the gate insulating film 503. The source / drain electrodes 505 and 506 are each connected to the oxide semiconductor layer 504.

[0044] Figures 4A and 4B show band diagrams to explain the carrier movement in an oxide semiconductor thin-film transistor during X-ray irradiation. The band diagram 592 shown in Figure 4A shows the electron energy levels in the gate electrode 502, lower silicon nitride film 511, silicon oxide film 512, upper silicon nitride film 513, and oxide semiconductor layer 504 when a positive gate voltage is applied to the oxide semiconductor thin-film transistor under X-ray irradiation. Ec represents the lower end of the conduction band level of the oxide semiconductor layer 504, lower silicon nitride film 511, silicon oxide film 512, and upper silicon nitride film 513, Ev represents the upper end of the valence band level of the oxide semiconductor layer 504, lower silicon nitride film 511, silicon oxide film 512, and upper silicon nitride film 513, and Ef represents the Fermi level of the gate electrode 502 (metal layer).

[0045] Electrons (e) generated by X-rays in the lower silicon nitride film 511 are trapped in electron trap levels within the lower silicon nitride film 511. Similarly, holes (h) generated in the lower silicon nitride film 511 are trapped in hole trap levels within the lower silicon nitride film 511.

[0046] Similarly, electrons (e) generated by X-rays in the upper silicon nitride film 513 are trapped in electron trap levels within the upper silicon nitride film 513. Furthermore, holes (h) generated in the upper silicon nitride film 513 are trapped in hole trap levels within the upper silicon nitride film 513.

[0047] Electrons (e) generated by X-rays in the silicon oxide film 512 move to the lower silicon nitride film 511, which has a lower energy level, and are trapped in the electron trap level of the lower silicon nitride film 511. Holes (h) generated in the silicon oxide film 512 are trapped in the hole trap level within the silicon oxide film 512. As a result, positive charges accumulate near the interface between the silicon oxide film 512 and the upper silicon nitride film 513.

[0048] Furthermore, electrons (e) generated by X-rays in the oxide semiconductor layer 504 are moved to the vicinity of the interface between the upper silicon nitride film 513 and the oxide semiconductor layer 504 and trapped by the positive gate voltage. The negative charge from these trapped electrons cancels out with the positive charge accumulated near the interface between the silicon oxide film 512 and the upper silicon nitride film 513, reducing the change in the potential of the oxide semiconductor layer 504 and suppressing the shift in the Vg-Id characteristics of the thin-film transistor 1010.

[0049] The band diagram 593 shown in Figure 4B shows the electron energy levels in the gate electrode 502, lower silicon nitride film 511, silicon oxide film 512, upper silicon nitride film 513, and oxide semiconductor layer 504 when a negative gate voltage is applied to the oxide semiconductor thin-film transistor 500 under X-ray irradiation. The band gaps for Ec, Ev, Ef, silicon oxide, silicon nitride, and oxide semiconductor are the same as in band diagram 592.

[0050] Electrons (e) and holes (h) generated by X-rays in the lower silicon nitride film 511 are trapped in electron trap levels and hole trap levels within the lower silicon nitride film 511, respectively.

[0051] Similarly, electrons (e) generated by X-rays in the upper silicon nitride film 513 are trapped in electron trap levels within the upper silicon nitride film 513. Furthermore, holes (h) generated in the upper silicon nitride film 513 are trapped in hole trap levels within the upper silicon nitride film 513.

[0052] Electrons (e) generated by X-rays in the silicon oxide film 512 move to the upper silicon nitride film 513, which has a lower energy level, and are trapped in the electron trap level of the upper silicon nitride film 513. As a result, negative charges accumulate near the interface between the silicon oxide film 512 and the upper silicon nitride film 513. In addition, holes (h) generated in the silicon oxide film 512 are trapped in the hole trap level within the silicon oxide film 512.

[0053] Furthermore, holes (h) generated by X-rays in the oxide semiconductor layer 504 are moved to the vicinity of the interface between the upper silicon nitride film 513 and the oxide semiconductor layer 504 and trapped by the negative gate voltage. The positive charge from these trapped holes cancels out the negative charge accumulated near the interface between the silicon oxide film 512 and the upper silicon nitride film 513, reducing the change in the potential of the oxide semiconductor layer 504 and suppressing the shift in the Vg-Id characteristics of the oxide semiconductor thin-film transistor 500.

[0054] Further investigations by the inventors revealed a more effective method for controlling the threshold voltage of an oxide semiconductor thin-film transistor. This method involves reducing the area of ​​the silicon oxide film separated from the oxide semiconductor layer in the stacking direction within a gate insulating film having a multilayer structure. This increases the distance dependence of the electric field strength due to trapped charges, thereby increasing the difference between the electric field strength due to positive charges and the strength due to negative charges at the location of the oxide semiconductor layer.

[0055] One embodiment of the present disclosure involves forming a portion of the gate insulating film (first insulating film) of an oxide semiconductor thin-film transistor with silicon nitride and / or silicon oxynitride, and embedding small island-like (isolated) metal oxide films (insulating films) within the gate insulating film at positions overlapping with the channel region in the stacking direction. The metal oxide films may be formed, for example, with silicon oxide and / or aluminum oxide.

[0056] The electric charge is distributed at the interface between the metal oxide film and the silicon nitride or silicon oxynitride film. Therefore, by reducing the area of ​​the metal oxide film, a small area of ​​planar charge can be formed. This increases the difference between the electric field strength created by charges close to the oxide semiconductor layer and the electric field strength created by charges farther away from it.

[0057] Therefore, for example, to control the threshold voltage in the positive direction, a voltage is applied between the source and gate so that the polarity of the charge near the oxide semiconductor layer becomes negative (a negative voltage relative to the source potential is applied to the gate), and high-energy light (e.g., X-rays) with an energy greater than the band gap of the metal oxide film is irradiated. To control the threshold voltage to shift it to the negative side, a positive voltage relative to the source potential is applied to the gate of the thin-film transistor, and the above high-energy light is irradiated.

[0058] Figure 5 is a schematic cross-sectional view showing the configuration of an oxide semiconductor thin-film transistor (TFT) 300 according to one embodiment of the present disclosure. The oxide semiconductor thin-film transistor 300 can be used as the thin-film transistor 104 shown in Figures 1 and 2. The descriptions of the components with the same reference numerals shown in Figure 2 can also be applied to the components shown in Figure 5.

[0059] The oxide semiconductor thin-film transistor 300 includes a gate electrode 302, a gate insulating film 303 on the gate electrode 302, and an oxide semiconductor layer 304 on the gate insulating film 303. An interlayer insulating layer 307 covers the entire oxide semiconductor thin-film transistor 300.

[0060] The gate insulating film 303 has a layered structure and is composed of a silicon nitride film (SiNx) 311 and isolated island-shaped silicon oxide films (SiOx) 312 embedded within the silicon nitride film 311. The entire outer surface of the silicon oxide film 312 is surrounded by the silicon nitride film 311 and forms an interface in contact with the silicon nitride film 311. A portion of the silicon nitride film 311 exists between the silicon oxide film 312 and the oxide semiconductor layer 304, and the silicon oxide film 312 is separated from the oxide semiconductor layer 304. A portion of the silicon nitride film 311 exists between the silicon oxide film 312 and the gate electrode 302, and the silicon oxide film 312 is separated from the gate electrode 302.

[0061] The oxide semiconductor layer 304 includes a channel region 341 between the drain region 342 and the source region 343. The resistance of the drain region 342 and the source region 343 is lower than the resistance of the channel region 341. The drain region 342 and the source region 343 can be formed by reducing the resistance of the oxide semiconductor layer, for example, by exposing it to a hydrogen plasma or a fluorine plasma. At least a portion of the drain region 342 is in contact with the drain electrode 305. At least a portion of the source region 343 is in contact with the source electrode 306.

[0062] The size of the channel region 341 can be defined by the channel width and the channel length. The channel length is the distance between the boundaries of the source region 343 and the drain region 342 and the channel region 341, respectively, and the channel width is the length perpendicular to the channel length.

[0063] In the configuration example shown in Figure 5, the entire area of ​​the silicon oxide film 312 overlaps with the channel region 341 in a plan view. Furthermore, the area of ​​the silicon oxide film 312 in a plan view is smaller than the area of ​​the channel region 341.

[0064] Figure 6 is a schematic plan view showing the positional relationship between the silicon oxide film 312, the channel region 341, and several other components. The silicon nitride film 311 fills the entire area of ​​Figure 6. In Figure 6, the source region 343, the drain region 342, and the channel region 341 between them are indicated by arrows. The direction of the arrows is the channel length direction, and the direction perpendicular to them is the channel width direction.

[0065] As shown in Figure 6, in a plan view, the area of ​​the silicon oxide film 312 is smaller than the area of ​​the channel region 341, and the entire area of ​​the silicon oxide film 312 overlaps with (is included in) the channel region 341. In Figure 6, the entire portions of the left and right edges and the top and bottom edges of the silicon oxide film 312 overlap with (are included in) the channel region 341 in a plan view. The left and right edges are opposite edges in the channel length direction (left-right direction), and the top and bottom edges are opposite edges in the channel width direction (up-down direction).

[0066] The right end of the silicon oxide film 312 is the end facing the source electrode 306 (and source region 343). The left end of the silicon oxide film 312 is the end facing the drain electrode 305 (and drain region 342). The entire right end of the silicon oxide film 312 facing the source electrode 306 (and source region 343) overlaps with the channel region 341. The entire left end of the silicon oxide film 312 facing the drain electrode 305 (and drain region 342) overlaps with the channel region 341. At least a portion of either the right end or the left end may be located outside the channel region 341 (i.e., it may not overlap with the channel region 341).

[0067] In the configuration example shown in Figure 6, the distance (minimum distance) LR between the right end of the silicon oxide film 312 and the end of the source electrode 306 is the same as the distance (minimum distance) LL between the left end of the silicon oxide film 312 and the end of the drain electrode 305. In other configuration examples, these distances may be different. Also, the centroid position of the silicon oxide film 312 coincides with the centroid position of the channel region 341. In other configuration examples, these do not have to coincide. The example shape of the silicon oxide film 312 shown in Figures 5 and 6 is a rectangular parallelepiped, but its shape is not particularly limited.

[0068] Figures 7A and 8A schematically show the charge state generated when radiation is applied to an oxide semiconductor thin-film transistor 300 according to one embodiment shown in Figures 5 and 6 while a gate bias is applied. Figures 7A and 8A schematically show the charge state generated when radiation (for example, X-rays of 500 Gy or more) is applied while a voltage is applied between the gate electrode 302 and the source electrode 306.

[0069] Figure 7A shows that a positive voltage is applied to the gate electrode 302 with the potential of the source electrode 306 as a reference. Electrons (-) and holes (+) are excited in the silicon oxide film 312 by radiation. Due to the electric field between the gate electrode 302 and the source electrode 306, holes accumulate at the interface between the upper surface of the silicon oxide film 312 (the surface facing the oxide semiconductor layer 304) and the silicon nitride film 311, and electrons accumulate at the interface between the lower surface of the silicon oxide film 312 (the surface facing the gate electrode 302) and the silicon nitride film 311.

[0070] Figure 8A shows that a negative voltage is applied to the gate electrode 302 with the potential of the source electrode 306 as the reference. Electrons (-) and holes (+) are excited in the silicon oxide film 312 by radiation. Due to the electric field between the gate electrode 302 and the source electrode 306, electrons accumulate at the interface between the upper surface of the silicon oxide film 312 (the surface facing the oxide semiconductor layer 304) and the silicon nitride film 311, and holes accumulate at the interface between the lower surface of the silicon oxide film 312 (the surface facing the gate electrode 302) and the silicon nitride film 311.

[0071] In the states shown in Figures 7A and 8A, the distance between the electron and the oxide semiconductor layer 304 is different from the distance between the hole and the oxide semiconductor layer 304. Specifically, in the state shown in Figure 7A, the distance between the hole and the oxide semiconductor layer 304 is smaller than the distance between the electron and the oxide semiconductor layer 304. In the state shown in Figure 8A, the distance between the electron and the oxide semiconductor layer 304 is smaller than the distance between the hole and the oxide semiconductor layer 304.

[0072] In the state shown in Figure 7A, since holes are concentrated closer to the oxide semiconductor layer 304 than electrons, a positive electric field is generated at the interface of the oxide semiconductor layer 304, and the threshold voltage fluctuates in the negative direction. Figure 7B is a schematic graph showing the change in the negative direction of the threshold voltage. The horizontal axis represents the gate-source voltage, and the vertical axis represents the drain current. In the state shown in Figure 8A, since electrons are concentrated closer to the oxide semiconductor layer 304 than holes, a negative electric field is generated at the interface of the oxide semiconductor layer 304, and the threshold voltage fluctuates in the positive direction. Figure 8B is a schematic graph showing the change in the positive direction of the threshold voltage. The horizontal axis represents the gate-source voltage, and the vertical axis represents the drain current.

[0073] After radiation irradiation and voltage application are stopped, the charge states in Figures 7A and 8A can be maintained. The charge state of the oxide semiconductor layer 304 allows for control of the threshold voltage of the oxide semiconductor layer 304 in the positive or negative direction. To effectively control the threshold voltage of the oxide semiconductor layer 304, it is important to generate a strong positive or negative electric field at the interface between the oxide semiconductor layer 304 and the silicon nitride film 311.

[0074] The electric field in the oxide semiconductor layer 304 is due to the difference in distance between electrons and holes and the oxide semiconductor layer 304. As explained with reference to Figures 5 and 6, the silicon oxide film 312 in one embodiment of the present disclosure has a small area. This increases the difference in intensity between the electric field due to electrons and the electric field due to holes, and allows an effective electric field for controlling the threshold voltage to be applied to the oxide semiconductor layer 304. This point will be explained below.

[0075] According to electromagnetism theory, the magnitude of the electric field strength created by a charge distributed across a surface, along a perpendicular to the surface, depends more strongly on the distance from the surface as the surface size decreases. For example, the electric field strength created by a charge on an infinitely large surface does not depend on the distance from the surface, but the electric field strength created by a surface small enough to be considered a point charge depends on the distance z from the surface. -2 This can be understood if you consider the dependence on it.

[0076] Since the charge is distributed at the interface between the silicon oxide film 312 and the silicon nitride film 311, reducing the size of the silicon oxide film 312 allows for the formation of small-area planar charges. This increases the difference between the electric field strength created by charges close to the oxide semiconductor layer 304 and those created by charges farther away. Therefore, for example, to control the threshold in the positive direction, the threshold can be controlled by applying a voltage between the source and gate such that the polarity of charges close to the oxide semiconductor layer becomes negative, and then irradiating with high-energy light. Conversely, to control the threshold in the negative direction, the threshold can be controlled by applying a voltage between the source and gate such that the polarity of charges close to the oxide semiconductor layer becomes positive, and then irradiating with high-energy light.

[0077] The effect of reducing the area of ​​the oxide semiconductor layer 304 will be explained with reference to Figure 9. Figure 9 shows a graph illustrating the relationship between the electric field strength generated by planar charges of different areas and the distance from the planar charges. The planar shape is assumed to be a circle, and the relationship is based on theoretical calculations. The horizontal axis of the graph shows the distance from the planar charge (nm), and the vertical axis shows the electric field strength (AU).

[0078] Line 205 shows the relationship between electric field strength and distance due to a circular planar charge with a radius of 100 μm. Line 206 shows the relationship between electric field strength and distance due to a circular planar charge with a radius of 10 μm. Line 207 shows the relationship between electric field strength and distance due to a circular planar charge with a radius of 5 μm. Line 208 shows the relationship between electric field strength and distance due to a circular planar charge with a radius of 2 μm.

[0079] As can be seen from the graph in Figure 9, the smaller the area of ​​the planar charge, the greater the difference in electric field strength due to the difference in distance from the planar charge. For example, suppose the thickness of the silicon oxide film 312 is about 400 nm, and the distance between the top surface of the silicon oxide film 312 and the bottom surface of the oxide semiconductor layer 304 is about 10 nm. The difference in electric field strength in the silicon oxide film 312 due to electrons and holes caused by a silicon oxide film 312 with a radius of 100 μm is small. On the other hand, the difference in electric field strength in the silicon oxide film 312 due to electrons and holes caused by a silicon oxide film 312 with a radius of 2 μm is larger, and a larger electric field can be applied to the silicon oxide film 312 due to charges closer to the oxide semiconductor layer.

[0080] The configurations of oxide semiconductor thin-film transistors according to several embodiments of this disclosure will be described below. Figure 10 is a schematic cross-sectional view showing the configuration of an oxide semiconductor thin-film transistor 400 according to one embodiment of this disclosure. Figure 11 is a schematic plan view showing the positional relationship between the silicon oxide film 402, the channel region 341, and several other components in the oxide semiconductor thin-film transistor 400 shown in Figure 10.

[0081] The following will mainly explain the differences from the configuration examples shown in Figures 5 and 6. Note that the explanation of the oxide semiconductor thin-film transistor 300, referring to Figures 5 and 6, may apply to components with the same reference numerals as those described in Figures 5 and 6. Compared to the silicon oxide film 312 of the oxide semiconductor thin-film transistor 300, the silicon oxide film 402 is positioned closer to the source electrode 306 than to the drain electrode 305.

[0082] Referring to Figure 6, the distance (minimum distance) LR between the right end of the silicon oxide film 402 and the end of the source electrode 306 is smaller than the distance (minimum distance) LL between the left end of the silicon oxide film 402 and the end of the drain electrode 305. Also, the distance (minimum distance) between the centroid of the silicon oxide film 402 and the end of the source electrode 306 in a plan view is smaller than the distance (minimum distance) between the centroid and the end of the drain electrode 305.

[0083] The silicon oxide film 402 is an isolated island within the silicon nitride film 311, and its entire area in a plan view overlaps with the channel region 341. In other words, the area of ​​the silicon oxide film 402 in a plan view is smaller than the area of ​​the channel region 341. As shown in Figure 10, the region between the silicon oxide film 402 and the oxide semiconductor layer 304, and the region between the silicon oxide film 402 and the gate electrode 302, are each filled with a portion of the silicon nitride film 311.

[0084] The threshold voltage of an oxide semiconductor is more strongly dependent on the potential in the region closer to the source electrode. Therefore, by positioning the silicon oxide film 402 closer to the source electrode 306 than to the drain electrode 305, a larger variation in the threshold voltage can be obtained.

[0085] Figure 12 is a schematic cross-sectional view showing the configuration of an oxide semiconductor thin-film transistor 420 according to one embodiment of the present disclosure. Figure 13 is a schematic plan view showing the positional relationship between the silicon oxide film 422, the channel region 341, and several other components in the oxide semiconductor thin-film transistor 420 shown in Figure 12.

[0086] The following mainly describes the differences from the configuration examples shown in Figures 5 and 6. Note that the explanation of the oxide semiconductor thin-film transistor 300, referring to Figures 5 and 6, can be applied to components with the same reference numerals as those described in Figures 5 and 6. Compared to the silicon oxide film 312 of the oxide semiconductor thin-film transistor 300, a portion of the silicon oxide film 422 is located outside the channel region 341 in a plan view. Specifically, the source-side portion of the silicon oxide film 422 does not overlap with the channel region 341 in a plan view. A portion of the source-side portion of the silicon oxide film 422 overlaps with the source region 343 and / or the source electrode 306 in a plan view.

[0087] Referring to Figure 13, the drain end 423 of the silicon oxide film 422 faces the drain electrode 305 in a plan view. The entire drain end 423 overlaps with the channel region 341 in a plan view. The distance LS1 between the drain end 423 and the end of the source electrode 306 is smaller than the distance LD1 between the drain end 423 and the end of the drain electrode 305.

[0088] By positioning the drain end 423 of the silicon oxide film 422 closer to the source electrode 306 than the drain electrode 305, a larger threshold voltage variation can be obtained. This point will be explained with reference to Figures 14A and 14B.

[0089] Figure 14A shows a planar charge 580 that extends infinitely in both the positive and negative directions along the Y-axis and infinitely in the positive direction along the X-axis. Figure 14B shows the Z-axis component of the electric field strength created by the planar charge 580 shown in Figure 14A at the coordinate (x,z). The horizontal axis represents the distance from the edge of the planar charge towards the center along the X-axis (value of the X-coordinate), and the vertical axis represents the Z-axis component of the electric field strength. Points with a value of 0 on the horizontal axis correspond to the positions of the edges of the planar charge 580.

[0090] Line 581 shows the change in electric field strength at a Z coordinate of 10 nm, and line 582 shows the change in electric field strength at a Z coordinate of 500 nm. As can be seen from the comparison of lines 581 and 582, the difference in electric field strength between different Z coordinate values ​​is larger the closer you are to the edge of the planar charge. In other words, because the position of the edge 423 of the silicon oxide film 422 is closer to the position of the source electrode 306 than the position of the drain electrode 305, the difference in electric field strength relative to the region near the source electrode in the oxide semiconductor layer due to electrons and holes separated vertically in the stacking direction becomes larger, and the threshold voltage can be effectively controlled.

[0091] Figure 15 is a schematic cross-sectional view showing the configuration of an oxide semiconductor thin-film transistor 440 according to one embodiment of the present disclosure. Figure 16 is a schematic plan view showing the positional relationship between the silicon oxide film 442, the channel region 341, and several other components in the oxide semiconductor thin-film transistor 440 shown in Figure 15.

[0092] The following mainly describes the differences from the configuration examples shown in Figures 5 and 6. Note that the explanation of the oxide semiconductor thin-film transistor 300 with reference to Figures 5 and 6 may apply to components with the same reference numerals as those described in Figures 5 and 6. Compared to the silicon oxide film 312 of the oxide semiconductor thin-film transistor 300, a portion of the silicon oxide film 442 is located outside the channel region 341 in a plan view. Specifically, the drain-side portion of the silicon oxide film 442 does not overlap with the channel region 341 in a plan view. A portion of the drain-side portion of the silicon oxide film 442 overlaps with the drain region 342 and / or the drain electrode 305 in a plan view.

[0093] Referring to Figure 16, the source end 443 of the silicon oxide film 442 faces the source electrode 306 in a plan view. The entire source end 443 overlaps with the channel region 341 in a plan view. The distance LS2 between the source end 443 and the end of the source electrode 306 is smaller than the distance LD2 between the source end 443 and the end of the drain electrode 305. As explained with reference to Figures 14A and 14B, by positioning the source end 443 of the silicon oxide film 442 closer to the source electrode 306 than to the drain electrode 305, a larger threshold voltage variation can be obtained.

[0094] In the structure of the oxide semiconductor transistor described with reference to Figure 13, the distance LS1 between the drain end 423 and the end of the source electrode 306 may be greater than or equal to the distance LD1 between the drain end 423 and the end of the drain electrode 305. Also, in the structure of the oxide semiconductor transistor described with reference to Figure 16, the distance LS2 between the source end 443 and the end of the source electrode 306 may be greater than or equal to the distance LD2 between the source end 443 and the end of the drain electrode 305.

[0095] Figure 17 is a schematic plan view showing the configuration of an oxide semiconductor thin-film transistor 460 according to one embodiment of the present disclosure. The differences from the configuration example shown in Figure 6 will be explained in detail. A portion of the silicon oxide film 462 does not overlap with the channel region 341 in a plan view and is located outside of it. Both ends of the silicon oxide film 462 in the channel width direction, that is, the upper end 463 and the lower end 464 in Figure 17, are located outside the channel region 341 in a plan view.

[0096] Therefore, a portion of the source end 465 of the silicon oxide film 462 overlaps with the channel region 341, while the other portion lies outside the channel region 341. Similarly, a portion of the drain end 466 of the silicon oxide film 462 overlaps with the channel region 341, while the other portion lies outside the channel region 341. The oxide semiconductor thin-film transistor 460, like oxide semiconductor thin-film transistors of other embodiments, can effectively control the threshold voltage.

[0097] Similar to the oxide semiconductor thin-film transistor 300 described with reference to Figures 5 and 6, the region between the silicon oxide film 462 and the oxide semiconductor layer 304, and the region between the silicon oxide film 462 and the gate electrode 302 are filled with a portion of the silicon nitride film.

[0098] The silicon oxide film 462 has both ends in the channel width direction located outside the channel region 341 in a plan view, but one end may overlap with the channel region 341 in a plan view, while the other end is located outside the channel region 341. The configuration described with reference to Figure 17, that is, the configuration in which the ends of the silicon oxide film in the channel width direction are located outside the channel region 341 in a plan view, can be applied to each of the configuration examples described with reference to Figures 10 to 13, 15, and 16.

[0099] Thus, in the oxide semiconductor thin-film transistor described with reference to Figures 5 to 17, at least a portion of the end of the silicon oxide film that faces one of the source electrode and drain electrode in a plan view overlaps with the channel region in a plan view.

[0100] Figures 18 and 19 are schematic cross-sectional views showing the configuration of an oxide semiconductor thin-film transistor 480 according to one embodiment of the present disclosure. Compared to the oxide semiconductor thin-film transistor 300 described with reference to Figures 5 and 6, the position of the silicon oxide film in the stacking direction is different, but the other components are the same. Specifically, the silicon oxide film 482 is in direct contact with the gate electrode 302, and the silicon oxide film 482 and the gate electrode 302 form an interface.

[0101] Figures 18 and 19 schematically show the charge state generated when radiation is applied to an oxide semiconductor thin-film transistor 480 with a gate bias applied. Figure 18 shows a positive voltage applied to the gate electrode 302 with the potential of the source electrode 306 as the reference. Figure 19 shows a negative voltage applied to the gate electrode 302 with the potential of the source electrode 306 as the reference. In either state, an electric field of charges trapped at the interface between the silicon oxide film 482 facing the oxide semiconductor layer 304 and the silicon nitride film 311 can be applied to the oxide semiconductor layer 304. Note that in the oxide semiconductor thin-film transistor described with reference to Figures 10 to 17, the silicon oxide film may also be in direct contact with the gate electrode.

[0102] In the oxide semiconductor thin-film transistor described with reference to Figures 5 to 19, the metal oxide film in the gate insulating film can be formed from a material different from that of the silicon oxide film. For example, aluminum oxide can be used instead of silicon oxide. Furthermore, the material of the insulating film, such as the silicon nitride film 311, is not particularly limited, and for example, silicon oxynitride can be used. For example, a laminated film of silicon nitride film and silicon oxynitride film may be used, and the silicon nitride film 311 can be composed of multiple silicon nitride layers.

[0103] For example, a lower layer of silicon nitride or silicon oxynitride may exist between the metal oxide film and the bottom gate electrode, and an upper layer of silicon nitride or silicon oxynitride may exist between the metal oxide film and the oxide semiconductor layer. The number of layers constituting the insulating film surrounding the metal oxide film is not particularly limited. The metal oxide film may also have a single-layer structure or a multilayer structure.

[0104] An oxide semiconductor thin-film transistor of one embodiment of the present disclosure may include a top gate electrode instead of the bottom gate electrode described with reference to Figures 5 to 19. The gate insulating film between the top gate electrode and the oxide semiconductor layer can have various structures, as described with reference to Figures 5 to 19.

[0105] Other embodiments of oxide semiconductor thin-film transistors may include both a top gate electrode and a bottom gate electrode. The top gate insulating film between the top gate electrode and the oxide semiconductor layer, and / or the bottom gate insulating film between the bottom gate electrode and the oxide semiconductor layer, may have the gate insulating film structure of any of the embodiments described above.

[0106] In the oxide semiconductor thin-film transistor described with reference to Figures 5 to 19, the source electrode and drain electrode are formed on the oxide semiconductor layer (on the upper layer side). In other configurations, the source electrode and drain electrode may be formed below the oxide semiconductor layer (on the lower layer side).

[0107] The following describes an example of a manufacturing method for oxide semiconductor thin-film transistors. More specifically, a method for producing the gate insulating film of an oxide semiconductor thin-film transistor is described. The manufacturing example described produces a gate insulating film having a structure in which an isolated silicon oxide film is embedded in a silicon nitride insulating film. The production of other components can be done using widely known methods, so their description is omitted here. Furthermore, any widely known method can be used for film deposition, patterning, etching, and removal of each component.

[0108] First, the first manufacturing method will be described with reference to Figures 20A to 20J. Referring to Figure 20A, the manufacturing method involves depositing and patterning gate metal 602 on a substrate 601, depositing silicon nitride 603 on top of it, and then patterning photoresist 604. Next, referring to Figure 20B, the silicon nitride 603 in the openings of the photoresist 604 is etched to a desired depth. Next, referring to Figure 20C, the photoresist 604 is removed.

[0109] Next, referring to Figure 20D, silicon oxide 605 is deposited to pattern the photoresist 606. Next, referring to Figure 20E, the silicon oxide 609 in the openings of the photoresist 606 is etched. Next, referring to Figure 20F, the photoresist 606 is removed. Next, referring to Figure 20G, silicon nitride 607 is deposited over the entire upper surface of the silicon oxide 605.

[0110] Next, referring to Figure 20H, an oxide semiconductor 609 is deposited to pattern the photoresist 610. The stacking of silicon nitride 603 and silicon nitride 607 is indicated by reference numeral 608. Next, referring to Figure 20I, the oxide semiconductor 609 is etched. Next, referring to Figure 20J, the photoresist 610 is removed.

[0111] Next, the second manufacturing method will be described with reference to Figures 21A to 20J. This method is more complex than the first method, but it can improve the uniformity of the gate insulating film thickness. Referring to Figure 21A, a gate metal 632 is deposited and patterned on a substrate 631, then silicon nitride 633 and an etch stop layer 634 are deposited thereon, and then a photoresist 635 is patterned.

[0112] Next, referring to Figure 21B, the etch stop layer 634 is etched. Next, referring to Figure 21C, the silicon nitride 633 is etched using the etch stop layer 634 as a mask. Next, referring to Figure 21D, silicon oxide 636 is deposited over the entire upper surface of the etch stop layer 634.

[0113] Next, referring to Figure 21E, the silicon oxide 636 is etched until the silicon oxide on top of the etch stop layer 634 is removed. At this time, the etch stop layer 634 prevents over-etching of the silicon nitride 633. Next, referring to Figure 21F, the etch stop layer 634 is removed. Next, referring to Figure 21G, silicon nitride 637 is deposited over the entire upper surface of the silicon oxide 636.

[0114] Next, referring to Figure 21H, the stacking of silicon nitride 633 and silicon nitride 637 is indicated by reference numeral 638. An oxide semiconductor 639 is deposited on the silicon nitride 638, and then a photoresist 640 is deposited and patterned on top of it. Next, referring to Figure 21I, the oxide semiconductor 639 is etched. Next, referring to Figure 21J, the photoresist 640 is removed.

[0115] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. Those skilled in the art can easily modify, add to, and transform each element of the above embodiments within the scope of the present disclosure. It is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of Symbols]

[0116] 300, 400, 420, 440, 460, 480 Oxide semiconductor thin-film transistors 302 Terminal 304 oxide semiconductor layer 311 Silicon Nitride Film 312, 402, 422, 442, 462, 482 Silicon oxide film 341 channel area

Claims

1. Oxide semiconductor thin-film transistor, An electrode, a source electrode, and a drain electrode, An oxide semiconductor layer connected to the source electrode and the drain electrode, respectively, In the stacking direction, the gate insulating film between the gate electrode and the oxide semiconductor layer, Includes, The oxide semiconductor layer includes a channel region, The gate insulating film is Metal oxide film and A first insulating film made of silicon nitride and / or silicon oxynitride, A portion of the first insulating film is disposed between the metal oxide film and the oxide semiconductor layer. At least a portion of the first end of the metal oxide film overlaps with the channel region in a plan view and faces either the source electrode or the drain electrode. Oxide semiconductor thin-film transistor.

2. An oxide semiconductor thin-film transistor according to claim 1, The minimum distance between the first end and the source electrode is smaller than the minimum distance between the first end and the drain electrode. Oxide semiconductor thin-film transistor.

3. An oxide semiconductor thin-film transistor according to claim 2, The first end faces the source electrode in a plan view, The metal oxide film includes a second end that faces the drain electrode in a plan view, At least a portion of the second end overlaps the channel region in a plan view. Oxide semiconductor thin-film transistor.

4. An oxide semiconductor thin-film transistor according to claim 1, The aforementioned metal oxide film is in the form of islands, In a plan view, the area of ​​the metal oxide film is smaller than the area of ​​the channel region. In a plan view, the entire area of ​​the metal oxide film overlaps with the channel region. Oxide semiconductor thin-film transistor.

5. An oxide semiconductor thin-film transistor according to claim 1 or 4, The entire outer surface of the metal oxide film is surrounded by the first insulating film. Oxide semiconductor thin-film transistor.

6. The oxide semiconductor thin-film transistor according to claim 5, The minimum distance in a plan view between the centroid of the metal oxide film and the source electrode is smaller than the minimum distance in a plan view between the centroid of the metal oxide film and the drain electrode. Oxide semiconductor thin-film transistor.

7. An oxide semiconductor thin-film transistor according to claim 1, The metal oxide film and the gate electrode form an interface. Oxide semiconductor thin-film transistor.

8. An oxide semiconductor thin-film transistor according to claim 1, The metal oxide film is composed of silicon oxide, and the first insulating film is composed of silicon nitride. Oxide semiconductor thin-film transistor.

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