Printed circuit board

Abstract

The present invention provides a printed circuit board that facilitates the formation of fine circuits, reduces the number of layers and thus the overall package thickness, and exhibits excellent power characteristics and / or die-to-die fine connectivity. [Solution] This disclosure relates to a printed circuit board 100A comprising a first insulating body 111 and a plurality of first wiring layers 112, wherein the uppermost first wiring layer 112 is embedded on the upper side of the first insulating body 111 and a portion of its upper surface is exposed from the upper surface of the first insulating body 111; a second wiring section 120 comprising a second insulating body 121 and a plurality of second wiring layers 122 respectively arranged within the second insulating body 121; and an electronic component embedded on the upper side of the first insulating body 111 such that at least a portion of its upper surface is exposed from the upper surface of the first insulating body 111, wherein the plurality of first and second wiring layers are electrically connected to each other, and the first wiring section 110 includes a wiring area with a relatively higher density than the second wiring section 120.

Description

Technical Field

[0001] The present disclosure relates to a printed circuit board.

Background Art

[0002] Due to the high performance improvement of semiconductor chips such as the AP (Application Processor) of smartphones, the CPU (Central Processing Unit) for servers, and AI (Artificial Intelligence) accelerators, the demand for package substrates including high-density circuits is expanding. As a result, the bump pitch is decreasing, and higher multi-layer and larger area are required. Also, in order to cope with the increasing input / output terminals, technology for realizing fine circuits is becoming important.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objectives of the present disclosure is to provide a printed circuit board that can facilitate the formation of fine circuits, reduce the number of layers and the thickness of the overall package, and is excellent in power characteristics and / or die-to-die fine connectivity.

Means for Solving the Problems

[0004] One of the various solutions proposed in the present disclosure is to form a first wiring portion including a fine circuit on a carrier, form a coreless second wiring portion on the first wiring portion, and further embed an electronic component in the first layer of the first wiring portion. <B

[0005] For example, a printed circuit board according to one example includes a first insulating body and a plurality of first wiring layers, each arranged within the first insulating body, wherein the uppermost of the plurality of first wiring layers is embedded above the first insulating body, and at least a portion of the upper surface of the uppermost first wiring layer is exposed from the upper surface of the first insulating body; a second wiring section, located below the first wiring section, includes a second insulating body and a plurality of second wiring layers, each arranged within the second insulating body; and an electronic component embedded above the first insulating body such that at least a portion of its upper surface is exposed from the upper surface of the first insulating body. The plurality of first wiring layers and the plurality of second wiring layers are electrically connected to each other, and the minimum pitch of the wiring included in each of the plurality of first wiring layers may be smaller than the minimum pitch of the wiring included in each of the plurality of second wiring layers.

[0006] For example, a printed circuit board according to one example includes a first insulating body and a plurality of first wiring layers, each arranged within the first insulating body, wherein the uppermost of the plurality of first wiring layers is embedded above the first insulating body, and at least a portion of the upper surface of the uppermost first wiring layer is exposed from the upper surface of the first insulating body; a second wiring section, located below the first wiring section, includes a second insulating body and a plurality of second wiring layers, each arranged within the second insulating body; and an electronic component embedded above the first insulating body such that at least a portion of its upper surface is exposed from the upper surface of the first insulating body. The plurality of first wiring layers and the plurality of second wiring layers are electrically connected to each other, and the minimum insulating distance between the plurality of first wiring layers may be smaller than the minimum insulating distance between the plurality of second wiring layers. [Effects of the Invention]

[0007] One of the various effects of this disclosure is that it is possible to facilitate the formation of fine circuits, reduce the number of layers and the overall package thickness, and provide a printed circuit board with excellent power characteristics and / or die-to-die fine connectivity. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2] This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 3] This is a schematic cross-sectional view showing another example of a printed circuit board. [Modes for carrying out the invention]

[0009] The disclosure will be described below with reference to the attached drawings. The shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation.

[0010] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0011] Referring to the drawing, the electronic device 1000 houses a main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also coupled with other electronic components, which will be described later, to form various signal lines 1090.

[0012] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM (Dynamic Random Access Memory)), non-volatile memory (e.g., ROM (Read Only Memory)), and flash memory; application processor chips such as central processors (e.g., CPU (Central Processing Unit)), graphics processors (e.g., GPU (Graphics Processing Unit)), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (Application Specific Integrated Circuits). Furthermore, these chip-related components 1020 can be combined with each other. The chip-related components 1020 may also be in the form of a package containing the aforementioned chips and electronic components.

[0013] Network-related components 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (Long Term Evolution), Ev-DO (Evolution Data Only), HSPA+ (High Speed ​​Packet Access Plus), HSDPA+ (High Speed ​​Downlink Packet Access Plus), HSUPA+ (High Speed ​​Uplink Packet Access Plus), EDGE (Enhanced Data GSM (Global System for Mobile communications) Environment), GSM (Global System for Mobile Communications), GPS (Global Positioning System), GPRS (General Packet Radio Service), CDMA (Code Division Multiple Access), TDMA (Time Division Multiple Access), DECT (Digital Enhanced Cordless Telecommunications), Bluetooth (registered trademark), and 3G (3rd Generation Mobile Communication). This includes, but is not limited to, any other wireless and wired protocols designated as System (third-generation mobile communication system), 4G (4th Generation Mobile Communication System), 5G (5th Generation Mobile Communication System), and later. It may also include any of many other wireless or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with the chip-related component 1020.

[0014] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, and MLCCs (multi-layer ceramic capacitors). However, they are not limited to these, and may also include passive elements in the form of chip components used for various other applications. Furthermore, other components 1040 can be combined with chip-related components 1020 and / or network-related components 1030.

[0015] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the main board 1010, or not connected. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. However, it is not limited to these, and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. In addition to these, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0016] The electronic device 1000 may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, automobile, server, etc. However, it is not limited to these, and may be any other electronic device that processes data.

[0017] Figure 2 is a schematic cross-sectional view showing an example of a printed circuit board.

[0018] Referring to the drawings, an example printed circuit board 100A includes a first insulating body 111 and a plurality of first wiring layers 112 disposed within the first insulating body 111, wherein the uppermost of the plurality of first wiring layers 112 is embedded above the first insulating body 111, and at least a portion of the upper surface of the uppermost first wiring layer 112 is exposed from the upper surface of the first insulating body 111, a second wiring section 120 disposed below the first wiring section 110 and including a second insulating body 121 and a plurality of second wiring layers 122 disposed within the second insulating body 121, and electronic components, such as a plurality of chip capacitors 151, 152, embedded above the first insulating body 111 such that at least a portion of their upper surfaces is exposed from the upper surface of the first insulating body 111. The plurality of first wiring layers 112 and second wiring layers 122 may be electrically connected to each other. Multiple chip capacitors 151 and 152 may be electrically connected to multiple first wiring layers 112.

[0019] In this case, the first wiring section 110 may include a wiring area with a relatively higher density than the second wiring section 120. For example, the minimum pitch of the wiring included in each of the multiple first wiring layers 112 may be smaller than the minimum pitch of the wiring included in each of the multiple second wiring layers 122. Also, the line width and minimum pitch of the wiring included in each of the multiple first wiring layers 112 may be smaller than the minimum pitch of the wiring included in each of the multiple second wiring layers 122. Furthermore, the minimum insulation distance between the multiple first wiring layers 112 may be smaller than the minimum insulation distance between the multiple second wiring layers 122. Also, the thickness of each of the multiple first wiring layers 112 may be thinner than the thickness of each of the multiple second wiring layers 122. Furthermore, the overall thickness of the first insulating body 111 may be thinner than the overall thickness of the second insulating body 121.

[0020] As described above, the printed circuit board 100A, as an example, can have an ETS (Embedded Trace Substrate) structure in the first wiring section 110, which includes a relatively high-density wiring area. For example, the first wiring section 110 can be formed using the ETS method on a carrier with excellent flatness, such as glass, silicon, or metal, making it easier to form fine circuits. In this case, when forming the M1 layer of the ETS structure, electronic components, such as multiple chip capacitors 151 and 152, can be placed and embedded, so that the distance between the chip capacitors 151 and 152, which are positioned on the outermost edge of the first wiring section 110, and the die mounted on the substrate can be minimized. Therefore, power characteristics can be improved. Furthermore, since the second wiring section 120 can be formed on the first wiring section 110 using a coreless method, the number of layers can be reduced, and the overall package thickness can be reduced, making it easy to accommodate high multilayer and large area designs. As a result, die-to-die linking at the substrate level becomes possible without using 2.5D or 2.3D interposers or other similar technologies, reducing process difficulty and costs, and also lowering the difficulty of embedding electronic components.

[0021] On the one hand, the wiring included in each of the plurality of first wiring layers 112 may have a minimum line width greater than 0 μm and less than or equal to 2 μm, and a minimum spacing between wirings greater than 0 μm and less than or equal to 2 μm. Also, the wiring included in each of the plurality of second wiring layers 122 may have a minimum line width greater than 2 μm and less than or equal to 5 μm, and a minimum spacing between wirings greater than 2 μm and less than or equal to 5 μm. In this case, the printed circuit board 100A according to an example can more easily replace the role of a conventional interposer.

[0022] On the one hand, the first wiring portion 110 can be respectively disposed within the first insulating body 111 and further include a plurality of first via layers 113 each connected to one or more of the plurality of first wiring layers 112. Also, the second wiring portion 120 can be respectively disposed within the second insulating body 121 and further include a plurality of second via layers 123 each connected to one or more of the plurality of second wiring layers 122. At this time, the connection vias included in each of the plurality of first via layers 113 and second via layers 123 can have side surfaces that are substantially tapered in the same direction as each other in cross-section. For example, the connection vias included in each of the plurality of first via layers 113 and second via layers 123 can have substantially tapered side surfaces where the width of the upper end portion is narrower than the width of the lower end portion in cross-section. As described above, since the first wiring portion 110 can be formed on the carrier by the ETS method and the second wiring portion 120 can be formed on the first wiring portion 110 by the coreless method, the plurality of first via layers 113 and second via layers 123 can have such a tapered structure.

[0023] On the other hand, in the first wiring section 110, the upper surface of the uppermost first wiring layer 112 protrudes above the upper surface of the first insulating body 111, and a part of the side surface of the uppermost first wiring layer 112 can protrude from the first insulating body 111. For example, a part of the upper side of the first insulating body 111 can be removed by plasma treatment or the like so that the side surface of the uppermost first wiring layer 112, which is the M1 layer, is exposed after carrier detachment. In this case, a part of the uppermost first wiring layer 112 can protrude, which can make connection with the die easier. At this time, the upper surfaces of the electronic components, such as a plurality of chip capacitors 151 and 152, can also protrude above the upper surface of the first insulating body 111, and as a result, a part of the side surface of the electronic components, such as a plurality of chip capacitors 151 and 152, can be exposed from the first insulating body 111.

[0024] Referring to the drawings, an example printed circuit board 100A may further include a third wiring section 130 located below the second wiring section 120, comprising a third insulating body 131, one or more third wiring layers 132 located on or within the third insulating body 131, and one or more third via layers 133 located within the third insulating body 131 and each connected to one of the one or more third wiring layers 132. The multiple second wiring layers 122 and the one or more third wiring layers 132 may be electrically connected to one another. The third wiring section 130 may be formed on the second wiring section 120 using a coreless molding method. The first wiring section 110 may include a wiring area with a relatively higher density than the third wiring section 130. The connecting vias included in the one or more third via layers 133 may also have sides that are substantially tapered in the same direction as the connecting vias included in each of the multiple first via layers 113 and second via layers 123.

[0025] On the other hand, the third insulating body 131 can include an insulating material different from the insulating materials included in one or more of the first insulating body 111 and the second insulating body 121. For example, the third insulating body 131 can include an insulating material having a higher elastic modulus (elastic modulus) than the insulating materials included in one or more of the first insulating body 111 and the second insulating body 121. For example, the third insulating body 131 can include an insulating material, such as a prepreg, that further includes glass fibers in addition to an insulating resin and an inorganic filler. In this case, it can be more effective in terms of warpage control.

[0026] Referring to the drawings, a printed circuit board 100A according to an example includes a first semiconductor chip 161 and a second semiconductor chip 162 that are respectively disposed above the first wiring portion 110 and connected to the uppermost first wiring layer 112 via a first connection member 163 and a second connection member 164, a passivation layer 141 that is disposed below the third wiring portion 130 and has a plurality of openings that respectively expose at least a part of the lowermost third wiring layer 132 among one or more third wiring layers 132, and / or a plurality of electrical connection metals 170 that are respectively disposed on the plurality of openings and connected to at least a part of the lowermost third wiring layer 132. For example, the printed circuit board 100A according to an example may be a semiconductor package substrate or an interposer substrate capable of fine connection between the first semiconductor chip 161 and the second semiconductor chip 162, and may be mounted on a main board or another package substrate via the plurality of electrical connection metals 170.

[0027] Hereinafter, components of the printed circuit board 100A according to an example will be described in more detail with reference to the drawings.

[0028] The first insulating body 111, the second insulating body 121, and the third insulating body 131 may each contain an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain inorganic fillers, organic fillers, and / or glass fibers together with these insulating resins. For example, the first insulating body 111 and the second insulating body 121 may contain an insulating material containing an insulating resin and an inorganic filler, such as Ajinomoto Build up Film (ABF) (registered trademark), but are not limited to these, and may also contain photosensitive insulating material (PID). The third insulating body 131 may contain an insulating material containing an insulating resin, an inorganic filler, and glass fibers, such as a prepreg, but are not limited to these. The first insulating body 111 and the second insulating body 121 may contain substantially the same insulating material, but may also contain different insulating materials. The first insulating body 111, the second insulating body 121, and the third insulating body 131 may each include one or more insulating layers or multiple insulating layers, and these insulating layers may have distinct boundaries between them, or they may be integrated with each other with indistinct boundaries.

[0029] The first wiring layer 112, the second wiring layer 122, and the third wiring layer 132 can each contain a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first wiring layer 112, the second wiring layer 122, and the third wiring layer 132 can each contain chemical copper formed by electroless plating as a seed layer, and electrocopper formed by electroplating based on this as a pattern plating layer. However, it is not limited to these, and the first wiring layer 112, the second wiring layer 122, and the third wiring layer 132 may each contain a titanium (Ti) layer and a copper (Cu) layer formed by sputtering as seed layers. The first wiring layer 112, the second wiring layer 122, and the third wiring layer 132 can each perform various functions depending on the design. For example, the first wiring layer 112, the second wiring layer 122, and the third wiring layer 132 may each include signal transmission wiring, power transmission wiring, ground transmission wiring, etc. On the other hand, these wirings can have various pattern forms such as lines, traces, planes, pads, and lands. The first wiring layer 112, the second wiring layer 122, and the third wiring layer 132 may each consist of one or more layers.

[0030] The first via layer 113, the second via layer 123, and the third via layer 133 can each contain a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first via layer 113, the second via layer 123, and the third via layer 133 can each contain chemical copper formed by electroless plating as a seed layer, and based on this, electrocopper formed by electroplating can be included as a pattern plating layer. However, it is not limited to these, and the first via layer 113, the second via layer 123, and the third via layer 133 may each contain a titanium (Ti) layer and a copper (Cu) layer formed by sputtering as seed layers. The first via layer 113, the second via layer 123, and the third via layer 133 can each perform various functions depending on the design. For example, the first via layer 113, the second via layer 123, and the third via layer 133 may each include signal transmission vias, power transmission vias, ground transmission vias, etc. On the other hand, the connecting vias included in each of the first via layer 113, the second via layer 123, and the third via layer 133 may have substantially tapered sides in cross-section, where the width of the upper end is narrower than the width of the lower end. There may be multiple connecting vias included in each of the first via layer 113, the second via layer 123, and the third via layer 133. The connecting vias included in each of the first via layer 113, the second via layer 123, and the third via layer 133 may have a fill-plated via structure, but are not limited to these, and may also have a conformally plated via structure.

[0031] The passivation layer 141 may include an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may include an inorganic filler and / or organic filler together with the resin. For example, the organic insulating material may be, but is not limited to, Ajinomoto Build-Up Film (ABF) (registered trademark), photosensitive insulating material (PID), or solder resist (SR). The passivation layer 141 may have a plurality of openings that each expose at least a portion of the bottommost third wiring layer 132. At least a portion of the bottommost third wiring layer 132 exposed through each of the plurality of openings may be of the SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined) type.

[0032] The chip capacitors 151 and 152 may, but are not limited to, MLCCs (Multi-Layer Ceramic Capacitors). On the other hand, the electronic components are not necessarily limited to chip capacitors 151 and 152, and may include various other types of active and / or passive components. For example, active components may include various types of semiconductor chips, and passive components may include various types of chip-type components other than chip capacitors, such as chip inductors. Such electronic components may be embedded on the uppermost side of the first wiring section 110 as described above.

[0033] The semiconductor chips 161 and 162 may each include an integrated circuit (IC) die in which hundreds to millions or more elements are integrated within a single chip. In this case, the integrated circuit may be, but is not limited to, a logic chip such as a central processor (e.g., CPU), graphics processor (e.g., GPU), field programmable gate array (FPGA), digital signal processor, cryptographic processor, microprocessor, microcontroller, application processor (e.g., AP), analog-to-digital converter, or ASIC. It may also be a different type such as a memory chip such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, HBM (High Bandwidth Memory), or a PMIC (Power Management Integrated Circuit).

[0034] The connecting members 163, 164 and the electrical connecting metal 170 may each be formed from a low-melting-point metal, such as a tin (Sn)-aluminum (Al)-copper (Cu) solder, but these are merely examples and the materials are not particularly limited to these. The connecting members 163, 164 and the electrical connecting metal 170 may each be balls, pins, etc. The connecting members 163, 164 and the electrical connecting metal 170 may each be formed from multiple layers or a single layer. When formed from multiple layers, copper columns and solder may be included, and when formed from a single layer, tin-silver solder may be included, but are not limited to these. There may be multiple connecting members 163, 164 and the electrical connecting metal 170.

[0035] Figure 3 is a schematic cross-sectional view showing another example of a printed circuit board.

[0036] Referring to the drawing, in another example, printed circuit board 100B may have an interconnect bridge 155 embedded as an electronic component on the uppermost side of the first wiring section 110 in printed circuit board 100A described above. The interconnect bridge 155 may be electrically connected to the first semiconductor chip 161 and the second semiconductor chip 162, respectively. By arranging the interconnect bridge 155, it becomes possible to achieve high-density die-to-die connections locally, for example, with L (line) / S (space) of 2 / 2 μm or less. In particular, as described above, when forming the first wiring section 110 using the ETS method, by arranging and embedding the interconnect bridge 155 when forming the M1 layer of the ETS structure, the distance between the embedded interconnect bridge 155 and the first semiconductor chip 161 and the second semiconductor chip 162 mounted on the first wiring section 110 can be minimized. Therefore, signal loss can be minimized and signal characteristics can be improved. Furthermore, the difficulty of embedding can also be reduced. The interconnect bridge 155 may be a silicon-type bridge and / or an organic-type bridge, and may include high-density circuits.

[0037] Other explanations may be substantially the same as those described for printed circuit board 100A in the example described above. Furthermore, the technical effects described for printed circuit board 100A in the example described above can be applied substantially similarly to printed circuit board 100B in the other example.

[0038] In this disclosure, the expression "cover" can include not only covering the entire surface but also covering at least a portion of it, and can include not only direct covering but also indirect covering. Similarly, the expression "fill" can include not only completely filling the surface but also filling at least a portion of it, and can also include roughly filling the surface. For example, this can include cases where there are some gaps or voids. Furthermore, the expression "enclose" can include not only completely enclosing the surface but also partially enclosing or roughly enclosing it. Moreover, "expose" can include not only completely exposing the surface but also partially exposing it, and exposure can mean exposing the relevant component from being embedded. For example, an opening exposing a pad may mean exposing the pad from the resist layer, and a surface treatment layer or the like may be further placed on the exposed pad.

[0039] In this disclosure, the determination can be made including process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, substantially coplane means not only when it is perfectly coplane, but also when it is approximately coplane. Similarly, substantially having a specific shape means not only when it is exactly that shape, but also when it is approximately that shape. Furthermore, substantially identical insulating materials may mean not only when they are completely identical insulating materials, but also when they include insulating materials of the same type. Therefore, the composition of the insulating materials may be substantially the same, but their specific composition ratios may differ slightly.

[0040] In this disclosure, "cross-sectional" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. "Planar" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0041] In this disclosure, terms such as "lower side," "bottom," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section of the drawing, while terms such as "upper side," "top," and "top surface" are used to mean the opposite direction. However, this is merely a definition of direction for explanatory purposes, and the scope of the claims is not specifically limited by such descriptions of direction, and the concepts of "upper" and "lower" can change at any time.

[0042] In this disclosure, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physically connected and unconnected cases. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of those components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0043] In this disclosure, thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness, etc., can be measured using a scanning microscope or optical microscope, based on a cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section may be a vertical or horizontal cross-section, and the values ​​can be measured based on the required cut cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section obtained by cutting the central axis of the via. In this case, if the values ​​are not constant, the values ​​can be determined by taking the average of the values ​​measured at any five points.

[0044] The expression "example" as used in this disclosure does not mean that each embodiment is identical to another, but is provided to highlight and illustrate the unique features of each embodiment that are distinct from one another. However, the examples presented do not preclude their realization in combination with features of other examples. For example, even if a matter described in one example is not described in another example, it can be understood as a description related to the other example unless there is a description in the other example that contradicts or inconsistes with that matter.

[0045] The terms used in this disclosure are for illustrative purposes only and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of Symbols]

[0046] 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related components 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 signal line 100A, 100B Printed Circuit Boards 110, 120, 130 wiring section 111, 121, 131 Insulation body 112, 122, 132 wiring layer 113, 123, 123 via layer 141 Passivation Layer 151, 152 Chip Capacitors 155 Interconnect Bridge 161, 162 Semiconductor chips 163, 164 Connecting members 170 Electrically connected metals

Claims

1. A first wiring section comprising a first insulating body and a plurality of first wiring layers, each disposed within the first insulating body, wherein the uppermost of the plurality of first wiring layers is embedded above the first insulating body, and at least a portion of the upper surface of the uppermost first wiring layer is exposed from the upper surface of the first insulating body, A second wiring section is located below the first wiring section and includes a second insulating body and a plurality of second wiring layers, each of which are located within the second insulating body. Includes an electronic component embedded above the first insulating body such that at least a portion of its upper surface is exposed from the upper surface of the first insulating body, The plurality of first wiring layers and the plurality of second wiring layers are electrically connected to each other. A printed circuit board in which the minimum pitch of the wiring included in each of the plurality of first wiring layers is smaller than the minimum pitch of the wiring included in each of the plurality of second wiring layers.

2. The printed circuit board according to claim 1, wherein the minimum line width of the wiring included in each of the plurality of first wiring layers and the minimum spacing between wirings are smaller than the minimum line width of the wiring included in each of the plurality of second wiring layers.

3. Each of the plurality of first wiring layers has a minimum line width greater than 0 μm and less than or equal to 2 μm, and a minimum spacing between wirings greater than 0 μm and less than or equal to 2 μm. The printed circuit board according to claim 2, wherein each of the plurality of second wiring layers has a minimum line width of more than 2 μm and 5 μm or less, and the minimum spacing between wirings is more than 2 μm and 5 μm or less.

4. The first wiring section further includes a plurality of first via layers, each of which is arranged within the first insulating body and connected to one or more of the plurality of first wiring layers. The second wiring section further includes a plurality of second via layers, each of which is arranged within the second insulating body and connected to one or more of the plurality of second wiring layers. The printed circuit board according to claim 1, wherein the connecting vias included in each of the plurality of first via layers and the plurality of second via layers have sides that are tapered in the same direction in cross-section.

5. The printed circuit board according to claim 4, wherein each of the connecting vias included in the plurality of first via layers and the plurality of second via layers has a tapered side surface in cross-section, where the width of the upper end is narrower than the width of the lower end.

6. The printed circuit board according to claim 1, wherein the upper surface of the uppermost first wiring layer protrudes above the upper surface of the first insulating body, and a part of the side surface of the uppermost first wiring layer is exposed from the first insulating body.

7. The printed circuit board according to claim 6, wherein the upper surface of the electronic component protrudes above the upper surface of the first insulating body, and a part of the side surface of the electronic component is exposed from the first insulating body.

8. The printed circuit board according to claim 1, wherein the electronic component includes one or more chip capacitors.

9. The printed circuit board according to claim 1, wherein the electronic component includes one or more interconnect bridges.

10. The third wiring section is located below the second wiring section and further includes a third insulating body and one or more layers of third wiring sections, each of which is located on or inside the third insulating body. The plurality of second wiring layers and the one or more third wiring layers are electrically connected to each other. The printed circuit board according to claim 1, wherein the third insulating body includes an insulating material different from one or more of the first insulating body and the second insulating body.

11. The printed circuit board according to claim 10, wherein the third insulating body includes an insulating material with a higher elastic modulus than the insulating material contained in one or more of the first insulating body and the second insulating body.

12. A first semiconductor chip and a second semiconductor chip are respectively positioned above the first wiring section and connected to the uppermost first wiring layer via a first connecting member and a second connecting member, A passivation layer having multiple openings located below the third wiring section, each exposing at least a portion of the third wiring layer located at the bottom of the one or more third wiring layers, The printed circuit board according to claim 10, further comprising a plurality of electrically connecting metals, each arranged on the plurality of openings and each connected to at least a portion of the third wiring layer located at the bottom.

13. A first wiring section comprising a first insulating body and a plurality of first wiring layers, each disposed within the first insulating body, wherein the uppermost of the plurality of first wiring layers is embedded above the first insulating body, and at least a portion of the upper surface of the uppermost first wiring layer is exposed from the upper surface of the first insulating body, A second wiring section is located below the first wiring section and includes a second insulating body and a plurality of second wiring layers, each of which are located within the second insulating body. Includes an electronic component embedded above the first insulating body such that at least a portion of its upper surface is exposed from the upper surface of the first insulating body, The plurality of first wiring layers and the plurality of second wiring layers are electrically connected to each other. A printed circuit board in which the minimum insulation distance between the plurality of first wiring layers is smaller than the minimum insulation distance between the plurality of second wiring layers.

14. The printed circuit board according to claim 13, wherein the thickness of each of the plurality of first wiring layers is thinner than the thickness of each of the plurality of second wiring layers.

15. The printed circuit board according to claim 13, wherein the overall thickness of the first insulating body is thinner than the overall thickness of the second insulating body.

Images