Gate drive control system for SiC and IGBT power devices for controlling unsaturated or short-circuit faults

Abstract

The present invention provides a gate drive control device that quickly turns on power semiconductor devices without generating high-voltage ringing. [Solution] The gate drive control device includes a master control unit (MCU) 402 and one or more comparators 406 that compare the output signal of a power semiconductor device 408 with a reference value generated by the MCU. In response to a turn-off trigger signal, the MCU generates a first intermediate drive signal for the power semiconductor device and a second intermediate drive signal different from the first drive signal if the DSAT (de-saturated) signal indicates that the power semiconductor device is experiencing de-saturation. If the output signals of one or more comparators indicate that the output signal of the power semiconductor device has changed relative to the reference value, the MCU generates a final drive signal for the power semiconductor. The control device also includes a timer that changes the drive signal at predetermined intervals if one or more comparators do not indicate a change.

Description

Technical Field

[0001] This application claims the benefit of priority of U.S. Provisional Patent Application No. 62 / 244,325, filed on October 21, 2015, and U.S. Provisional Patent Application No. 62 / 393,859, filed on September 13, 2016, and this application is also a partial continuation of U.S. Patent Application No. 15 / 074,364, filed on March 18, 2016, the contents of these applications are incorporated herein by reference.

Background Art

[0002] Power semiconductor devices, insulated gate bipolar transistors (IGBTs), or field effect transistors (FETs) based on silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and other wide bandgap materials (WBG) such as diamond, aluminum nitride (AlN), and boron nitride (BN) are used in high-power inverters, motor control, battery control systems, etc. SiC and GaN FETs are becoming common choices for high-power systems. These wide bandgap devices have faster switching speeds and are more efficient than Si IGBTs. The improvement in efficiency is a result of faster switching speeds. Faster switching reduces switching losses and also allows the use of inductors and capacitors that are smaller than those used in devices with slower switching speeds by switching at higher frequencies. The combination of low losses and smaller external filter components makes SiC devices an attractive alternative to IGBTs.

Summary of the Invention

Means for Solving the Problems

[0003] In one embodiment, a gate drive control device for a power semiconductor device includes a master control unit (MCU) and a comparator that compares the output signal of the power semiconductor device with a reference value. In response to a turn-off trigger signal, the MCU generates a reference value and a first intermediate drive signal for the power semiconductor device. If the desaturated (DSAT) signal indicates that the power semiconductor device is experiencing desaturation, the MCU generates a different reference value and a different intermediate drive signal. If the comparator indicates that the output signal from the power semiconductor device is below the reference value, the MCU generates a final drive signal for the power semiconductor.

[0004] In another embodiment, the gate drive control device includes an MCU which generates a first drive signal for a power semiconductor device when a trigger signal indicates that the power semiconductor device should be turned off, holds this first drive signal for a first predetermined time interval, provides a second drive signal different from the first drive signal at the end of the first predetermined time interval, holds this second drive signal for a second predetermined time, and provides a third drive signal different from the first and second drive signals at the end of the second predetermined time interval.

[0005] In yet another embodiment, the MCU receives a trigger pulse having a rising edge and a falling edge. In response to the detection of the rising edge of the trigger pulse, the MCU generates a first reference value and a first drive signal to partially turn on the power semiconductor device. When the state of the comparator output signal changes, the MCU generates a second drive signal to fully turn on the power semiconductor device. In response to the falling edge of the trigger pulse, the MCU generates a second reference value and a third drive signal for the power semiconductor device to partially turn off the power semiconductor device. When the comparator output signal returns to its original state, the MCU generates a fourth drive signal to fully turn off the power semiconductor device.

[0006] In further embodiments, the MCU monitors Vce or Vds depending on the type of device being controlled to determine when to proceed to the next voltage level in a multi-level turn-off (MLTO) sequence. The MCU uses two comparators to determine when an overvoltage spike exceeds a first predetermined voltage VCHK1 and falls below a second predetermined voltage VCHK2. These voltage values ​​change with each step. If the two comparators indicate that Vce / Vds is within the voltage range, the next step in the turn-off process can proceed. Knowing when to proceed to the next voltage level based on the Vce / Vds values ​​allows for optimization of the MLTO process, enabling the power device to shut down as quickly as possible to minimize potential damage. The MCU can also monitor timers set at each step to proceed to the next step at the time indicated by the timer, even if the comparators do not indicate that it is time to perform the next step. [Brief explanation of the drawing]

[0007] [Figure 1A] This is a schematic diagram of a bridge circuit containing four power FETs. [Figure 1B] This graph shows voltage-to-time and current-to-time waveforms, which are useful for explaining the operation of the circuit shown in Figure 1A. [Figure 2-3] This graph shows voltage-to-time and current-to-time waveforms, which are useful for illustrating an exemplary control circuit. [Figure 4] This is a schematic diagram of an exemplary control circuit that controls switching based on Vce. [Figure 5] This is a schematic diagram of an exemplary control circuit that controls switching based on Ic. [Figure 6] This is a schematic diagram of an exemplary control circuit that controls switching based on Vce and includes a Vce overshoot monitoring device. [Figure 7-8] These flowcharts are useful for explaining the operation of the circuits shown in Figures 4, 5, and 6. [Figure 9]This graph, showing voltage-time waveforms, is useful for explaining the control circuit that controls switching when a non-saturation phenomenon is detected. [Figure 10-11] This flowchart is useful for explaining the operation of a control circuit that controls switching when a non-saturation phenomenon is detected. [Figure 12] This is a partially schematic block diagram of an exemplary circuit that controls switching when a non-saturation phenomenon is detected. [Modes for carrying out the invention]

[0008] Faster switching speeds in SiC devices can lead to control problems. Fast turn-on and turn-off times coupled with the system's stray inductance can result in relatively high-voltage switching spikes when the device is turned off, and ringing of the output voltage signal when the device is turned on. These spikes and ringing are directly related to the inductance L in the system (V = L * dI / dt). For example, a power semiconductor device switching 200 amperes in 50 ns with an inductance of only 50 nH may generate a 200 V spike. This large spike can limit the usefulness of the SiC device.

[0009] Figures 1A and 1B show the turn-on ringing and turn-off spikes across the load in a bridge circuit. The circuit 100 shown in Figure 1A includes four power FETs 102, 104, 106, and 108 arranged as a bridge circuit to power a load illustrated as a resistor 110. FETs 102 and 104 are controlled by voltage gate control 1, while FETs 106 and 108 are controlled by voltage gate control 2. Figure 1B is a graph showing gate control 1 (112), gate control 2 (114), the voltage across the load (116), and the current flowing through the load (118). At time T1, gate control 2 transitions to high, turning on FETs 106 and 108. This allows current to flow through the load from terminal 1 to terminal 2. As illustrated, rapid switching causes ringing 120 in the voltage across the load. This ringing is caused by parasitic inductance in the circuit. At time T2, gate control 2 transitions to low and gate control 1 transitions to high. This switches FETs 106 and 108 off and FETs 102 and 104 on, allowing current to flow in the reverse direction, from terminal 2 to terminal 1, through the load. This switching also generates a ringing 120 in the voltage across the load at time 2. At time T3, gate control 1 transitions to low, switching off FETs 102 and 104 and switching off the current to load 110. Switching off the current causes a spike 122 in the voltage across load 110.

[0010] Existing systems use resistors to reduce gate charging current, thus slowing down the switching time of SiC devices and reducing spikes and ringing. Unfortunately, slowing down the switching time throughout the entire switching period dramatically reduces system efficiency. A solution is needed to control and optimize the switching speed to reduce turn-off voltage spikes and turn-on ringing while maintaining efficiency.

[0011] While exemplary control circuits are shown using SiC power FETs, it is intended that these control circuits may be used with other types of power FETs or IGBT power semiconductors. Consequently, as used herein, the term Vce refers to the voltage across a power semiconductor device, which refers to the collector-emitter voltage of an IGBT or the source-drain voltage of a power FET. Similarly, the term Ic refers to the current flowing through the conductive channel of the device, which may be the collector current of an IGBT or the source current of a power FET. This current can be measured at the collector or emitter of an IGBT, or at the source or drain of a power FET.

[0012] One method for managing high-voltage turn-off spikes is to turn off the device in two stages. This is referred to herein as two-stage turn-off (2LTOff). A system implementing 2LTOff first drives the gate of a power semiconductor device to an intermediate voltage level, and then, after a predetermined interval or when a predetermined Vce or Ic value is measured, drives the gate to the final off-voltage state. The purpose of this function is to increase the dynamic on-resistance of the FET, thereby reducing the current flowing through the device and, consequently, reducing dI / dt and the magnitude of the spike. The use of 2LTOff allows users to improve switching characteristics to achieve an optimal trade-off between efficiency and voltage turn-off spikes.

[0013] Figure 2 shows an exemplary waveform that occurs during 2LTOff operation. Before time T1, the gate voltage 204 is high, and the device is on. The current Ic 206 flowing through the device is high, and the voltage Vce 202 across the device is low. At time T1, the gate voltage 204 drops to the midpoint 2LTO, which increases the device's dynamic on-resistance. The 2LTO voltage level is held on the gate for the duration of the 2LTO time, which ends at T3. At time T3, the gate voltage 204 transitions to its low value. Immediately after time T2, the FET turns off, resulting in a voltage spike in the Vce signal 202. At T2, before the end of the 2LTO time, Vce begins to rise (Vce bend). As described below, this rise in Vce can be detected by a comparator, causing the MCU to apply a turn-off gate voltage before the end of the 2LTO time.

[0014] As an alternative to two-stage turn-off or turn-on, multi-stage turn-on and / or turn-off (MLTO) can provide even better spike and ring suppression. In the multi-stage method, the gate voltage is changed in three or more steps, as shown in Figure 3. In this example, the gate voltage 304 controls the device as shown by the graphs of Vce 302 and Ic 306. As shown, before time T0, the gate voltage 304 is low and the device is off (Vce 302 is high and Ic 306 is low). At time T0, the gate voltage transitions to high, turning the device on. At time T1, the gate voltage drops to a first intermediate level, resulting in a voltage spike 302A on the Vce signal 302. This first intermediate level is held for a first time interval from T1 to T2, and at T2, the gate voltage is reduced to a second intermediate level. This results in a second voltage spike 302B after time T2. After a second holding time between times T2 and T3, the gate voltage transitions to low, and the device turns off. There is no voltage spike after time T3. Furthermore, the voltage spikes 302A and 302B are much smaller than if the gate voltage had transitioned from high to low in a single step.

[0015] When a power semiconductor (FET, other wide-bandgap device, or IGBT) device conducts current and the voltage VDS across the device increases beyond a predetermined level, a desaturated state (DSAT) occurs within the device, resulting in a sudden power outage that can lead to a failure. In a DSAT state, the current flowing through the device can be much larger than during normal operation. When this overcurrent within the device quickly turns off, any inductance in the system generates a voltage spike according to the equation V = L*dI / dt. In SiC power FETs, the turn-off time is less than 50 ns. This short turn-off time can lead to a very large voltage spike. For example, in a circuit with a stray inductance of 15 nH during a 3000 A DSAT state, the turn-off voltage spike is 15 nH × 3000 A / 50 ns = 900 V. When added to the DC voltage across the device (typically 700V for a 1200V rated device), this voltage causes an overvoltage spike of 1600V, significantly exceeding the maximum withstand voltage of 1200V.

[0016] Two solutions can be used to suppress DSAT. One is to further increase the gate resistance to try to manage the voltage spike, and the other is to shut down the device using 2LTOff. However, increasing the gate resistance further reduces the power efficiency of the device during normal operation. If 2LTOff is already used to control the turn-off spike during normal operation, 2LTOff may not be effective in controlling the spike in the DSAT condition. One solution may be to use gate resistance to control the turn-off voltage spike during normal operation and use 2LTOff to turn off the device when the DSAT condition is detected. The exemplary apparatus and method described below enable two types of turn-off functionality, where one set of parameters (intermediate voltage and time) may be used during normal operation, and a second set of parameters (for higher voltage and time) may be used when the DSAT condition is detected.

[0017] The third solution is to use two sets of multi-level turn-off (MLTO) parameters for both normal operation and the DSAT state. Note that 2LTOff is a subset of multi-level turn-off that uses two or more intermediate levels during the turn-off operation. The devices described below can be used to implement a solution that uses two sets of multi-level turn-off parameters. During DSAT, a multi-level solution using more than two levels may be the optimal solution to effectively manage the magnitude of dI / dt and thus the magnitude of the voltage spike. An exemplary system for performing switching after the DSAT state is detected will be described below with reference to FIGS. 9-12.

[0018] Two-level turn-on (2LTOn) is similar to 2LTOff and enables the power semiconductor device to turn on quickly without generating high-voltage ringing. The FET gate signal is first turned on to an intermediate level, and this signal remains at this level for a time interval and then changes to the final voltage level at which the device is fully on.

[0019] Some of the systems and methods described below also add real-time monitoring of Vce to manage the timing with respect to the switching characteristics of SiC or IGBT devices for both 2LTOff and 2LTOn (as used herein, the term 2LTO can refer to either 2LTOn or 2LTOff). Two-level turn-on (2LTOn) is similar to 2LTOff except that it is used during turn-on. Other systems and methods monitor the current or detect an overshoot of Vce.

[0020] Vce Monitoring The main purpose of the 2LTO function is to allow the FET to gradually change its on / off resistance at the start of the switching cycle in order to reduce or manage dV / dt and dI / dt. As seen in Figure 2, Vce begins to rise slightly during the 2LTO period (the resistance of the FET increases). This is shown in Figure 2 as the "Vce bend". This initial gentle change makes it possible to further gradually change the number of amperes of stray inductance, and as a result, the turn-off spike is reduced.

[0021] One way to control the 2LTO function for monitoring the Vce of the FET using the comparator 406 is shown in Figure 4. In this system, the master control unit (MCU) 402 receives the input signal IN, which goes high when the FET is to be turned on and low when the FET is to be turned off. The signal IN can be either a digital signal or an analog signal. Further, the MCU receives a Boolean signal from the comparator 406 and generates the 2LTO analog voltage level applied to the operational amplifier (op-amp) driver 404, and the operational amplifier driver 404 then supplies the gate voltage to the SiC FET 408. The MCU 402 also generates the reference analog voltage level Vce Compare, which is applied to one input terminal of the comparator 406. The other input terminal of the comparator is coupled to the source terminal of the FET 408 to monitor the Vce level. As shown in Figure 4, the source terminal of the FET 408 is connected to the load 410, and the load 410 receives the operating power from the voltage source V. When the Vce level is equal to or exceeds the Vce Compare value, the comparator 406 generates a Boolean output signal that transitions from low to high. This Boolean signal is applied to the MCU 402, and the MCU 402 controls the gate voltage to complete the 2LTO operation. As will be described below, instead of monitoring Vce, the comparator 406 can be configured to monitor Ic or a voltage proportional to Ic. To ensure appropriate voltage levels, both the MCU 402 and the FET 408 are coupled to a common source of the reference potential (e.g., ground).

[0022] The circuit shown in Figure 4 uses a single comparator that monitors either Vce or Ic, but it is intended that multiple comparators (not shown) may be used, one for each voltage or current level being monitored. This may be desirable when the DAC used by the MCU cannot change the comparator's reference voltage without delay for the next transition. As mentioned above, it is also possible to detect the DSAT state by monitoring Vce using a separate comparator (not shown). This comparator detects voltage levels greater than the normal on-level. The MCU can detect the DSAT state when the MCU turns on the power semiconductor device and the output signal of the comparator shows a voltage value greater than or equal to the DSAT voltage value.

[0023] In the examples described below, the MCU may be a programmable control unit including an internal analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) (not shown) that enable the reception and provision of analog output signals. Alternatively, the MCU may be implemented as an application-specific integrated circuit (ASIC), coupled programmable logic circuit (CPLD), field-programmable gate array (FPGA), or discrete control logic, each having or coupled with an ADC and DAC, to receive and provide analog signals and simultaneously perform the operations described below with reference to Figures 7, 8, 10, and 11. Alternatively, the MCU 402 and driver 404 may include circuits such as an MCU, interface board, and driver board of a system described in U.S. Patent No. 8,984,197, entitled "POWER STACK CONTROL SYSTEMS" by Charpentier et al., which is incorporated herein by reference.

[0024] In Figure 4, the MCU 402 supplies the VCE compare voltage to the comparator 406. This level is set by performing a system characterization to determine the optimal level for controlling the size of the turn-off spike or turn-on dI / dt for a specific application. Since the inductance of each design may differ, it is desirable to determine this value for each circuit design. For example, the MCU may set the Vce turn-off level to 10V. Once the Vce level of 10V is achieved, the 2LTOff time stops, and the MCU applies a low (off) signal to the gate of the FET, causing the FET to turn off. As another example, in the case of 2LTOn, the MCU may set the Vce compare level to VCC-10V. Once Vce falls below that level, 2LTOn stops, and the MCU transitions the signal applied to the gate of the FET to an on (high) level. Considering that the voltage level to the power system can be as high as 800V or more, it may be desirable to monitor the 2LTOff and 2LTOn states separately using a separate comparator or level shift circuit (not shown). This allows the comparator to monitor, for example, VCC-10V 2LTOn using its separated comparator output to the MCU.

[0025] Ic monitoring In certain IGBT and SiC devices, the manufacturer provides a secondary output pin proportional to the main output current. This output pin may be, for example, the drain electrode of a smaller FET (not shown) having source and gate electrodes connected in parallel with the source and gate electrodes of the power FET in a current mirror configuration. This output pin allows the system to shunt the secondary current to a low-ohm resistor (not shown) coupled between the drain and ground of the smaller FET to generate a monitoring voltage that is a function of the total current flowing through the FET. In some systems, a shunt resistor within the main current output may be used to generate a measurable voltage that can be used instead of a current mirror configuration. The voltage output across the low-ohm resistor or shunt resistor is monitored by a comparator, and when the voltage reaches a level applied by the MCU (e.g., 2LTOff or 2LTOn), the MCU drives the FET completely off or on.

[0026] An exemplary Ice monitoring system is shown in Figure 5. This system includes an MCU 502, which may be the same as the MCU 402 shown in Figure 4. The exemplary system also includes an operational amplifier driver circuit 540 and comparator 506, which may be the same as the operational amplifier 404 and comparator 406 shown in Figure 4. The output signal of the driver 540 is coupled to the gate of the SiC FET 508. In this embodiment, the TLTOn and TLTOff values ​​and times are set by the MCU based on the monitored current signal from the current mirror output CM of the FET or IGBT 508 and the circuit design, in the same manner as described above with reference to Figure 4. Figure 5 also includes a comparator 512 (shown by dashed lines) coupled to receive Vce from the FET 508 and a second reference value from the MCU 502. When comparator 512 is added to the control unit, the control unit can perform TLTOn, TLTOff, or both based on Ic, Vce, or both.

[0027] Real-time 2LTOff and 2LTOn adjustment This function utilizes the amount of time required for Vce or Ice to reach a level that activates the comparator. This time is monitored by the MCU using its internal clock (digital timer set, counting down to zero). The timer's "set" value is based on the characterization of the IGBT or SiC FET device obtained by a dual-pulse test or other form of dynamic test on the circuit containing the IGBT or SiC FET.

[0028] An exemplary system for performing this adjustment is shown in Figure 6. This system includes an MCU 602, op-amp 604, and comparator 606, which operate in the same manner as the MCU 402, op-amp 404, and comparator 406 shown in Figure 4, except that the MCU monitors ringing and Vce voltage spikes on the Vce signal to determine whether the value or time of TLTOn or TLTOff should be adjusted. The monitoring circuit includes a Zener diode 610 and a resistor 612. If the time is too long or too short, the MCU can adjust the 2LTOff or 2LTOn level and / or time to cause the FET to change state at different voltage levels or at different speeds, and thus optimize the efficiency of the overshoot, dI / dt, and switching characteristics.

[0029] This function first determines that Vce has exceeded the level defined by the breakdown of the Zener diode 610, using the Zener diode 610. The Zener diode is selected to have a breakdown voltage greater than Vce by an acceptable overshoot (spike or ringing) value. When the diode breaks down, a voltage is generated across resistor 612. This voltage indicates that the overshoot is too high, and the MCU increases or decreases the 2LTOff level or increases the hold time. This change is made in stages to reduce the Vce overshoot to a level below the diode's breakdown level.

[0030] The circuits shown in Figures 4-6 include an operational amplifier configured as a unity-gain amplifier as a gate driver circuit, but this driver circuit is intended to be omitted or implemented using different techniques. For example, the driver circuit may be implemented inside the MCU so that the signal provided by the MCU transmits enough current to quickly switch the gate of the FET or IGBT. Alternatively, the operational amplifier can be replaced with another buffer amplifier, such as a push-pull amplifier.

[0031] In any of the circuits described above, the best 2LTOn and 2LTOff potentials to be used for a particular device may vary based on the age or temperature of the FET or IGBT. To compensate for these variations, the MCU may include an internal clock that measures how long each power semiconductor device has been in use, and may also be coupled with a temperature sensor (e.g., a thermistor or thermocouple (not shown)) to determine the instantaneous temperature of the device. These values ​​can be applied to formulas to adjust the 2LTOn and / or 2LTOff gate voltage values ​​and delay times to compensate for aging and / or temperature. The specific formula used depends on the structure and configuration of the power semiconductor device and can be determined empirically.

[0032] Figures 7 and 8 are flowcharts illustrating examples of the operation of MCU402, 502, or 602 in the circuits shown in Figures 4, 5, and 6, respectively. Figure 7 shows the system operation in 2LTO mode (both 2LTOff and 2LTOn), while Figure 8 shows the system operation when a DSAT fault condition is detected. A DSAT condition can be detected by monitoring Ic in Figure 5 to determine if the current flowing through the FET or IGBT becomes excessive or experiences a sudden increase, or by monitoring Vce for on-state values ​​higher than the on-state Vce value when the device is saturated, or by monitoring Vce when the on-state Vce value shows a sudden increase. Other systems and methods for handling DSAT conditions are described below with reference to Figures 9-12.

[0033] In block 702, the MCU detects the rising edge of an input trigger on the input terminal IN. This signal indicates that the FET should be turned on. Upon detecting this trigger, in block 702, the MCU initiates 2LTOn operation by selecting a 2LTOn level and a 2LTOn timer value. The MCU then applies the 2LTOn level to the gate electrode of the FET via the driver circuit. The MCU also sets the reference value supplied to the comparator to an intermediate Vce (or Ic) level, which indicates that the FET can be turned on. In block 706, the MCU starts the 2LTOn timer. In block 706, when the timer expires (e.g., counts down to zero) or when the comparator indicates that the Vce (or Ic) value has reached the reference level, the MCU sets the gate potential to a fully on (high) level.

[0034] In block 710, the MCU detects the falling edge of the input trigger IN and initiates the turn-off operation. Also in block 710, the MCU selects an appropriate reference level and delay time for the 2LTOff operation. In block 712, the MCU ensures that the 2LTOff level is applied to the gate electrode of the FET and sets the reference value applied to the comparator to an intermediate value of Vce (or Ic) indicating that the FET can be turned off. In block 714, the MCU starts the 2LTOff timer. In block 716, if the timer expires or the comparator indicates that the Vce (or Ic) value has reached the reference level, the MCU sets the gate potential to completely off (low).

[0035] Figure 8 shows an exemplary operation when a DSAT fault condition is detected. The algorithm shown in Figure 8 can be used in conjunction with the algorithm shown in Figure 7 to provide a more aggressive turn-off operation when a DSAT condition is detected. In block 802, when a DSAT condition is detected, the MCU sets a DSAT condition indicator so that, in this example, a set of multi-stage turn-off (MLTO) gate voltage value and corresponding delay time is selected. In block 804, the MCU sets the signal applied to the gate electrode to a first turn-off gate voltage level, and in block 806, a timer is started to count down the first delay time. In block 808, when the timer expires, the MCU sets the gate potential to a second (next) off voltage level. As indicated by arrow 807, blocks 806 and 808 can be repeated once or more times to address multiple intervening levels. Arrow 807 is shown with a dashed line because only a single intermediate level may exist (e.g., 2LTOff). For each level i, the i-th timer is started in block 806. When this timer counts down, block 806 sets the (i+1)th output level and delay value, and then branches back to block 806. When the (i+1)th level is equal to the nth level, control is transferred to block 810. In block 810, once the MCU has selected the nth (last) off-voltage level, the timer starts with the last delay value. In block 812, when the timer has counted down the last delay value, the MCU sets the gate potential of the FET or IGBT to the full off-voltage level.

[0036] When a DSAT state is detected (in this example, for a SiC FET), there are two methods that can be used to manage the turn-off characteristics: fixed multi-stage power semiconductor turn-off and Vce (or Vds) feedback-controlled multi-stage turn-off.

[0037] Fixed multi-level turn-off In a fixed multilevel turn-off, the gate signal to the FET is advanced via a fixed set of voltages. Each voltage is held for a predetermined (and possibly different) time interval. In one embodiment, the level and time steps are programmable and can be optimized through a characterization procedure. Figure 9 shows a typical time and voltage sequence for gate signal 902 and Vds 904. In Figure 9, the values ​​from T0 to T4 represent continuous time intervals. The left vertical axis in Figure 9 corresponds to the gate signal, and the right vertical axis corresponds to Vds in response to the detection of the DSAT state during time interval T1 (e.g., Vds increases to 12V within 2μs). Table 1 provides details for each event.

[0038] [Table 1]

[0039] Figure 10 shows the sequence of events for the MLTO operation shown in Figure 9 and Table 1. In block 1002, the DSAT state is detected. As described above, the DSAT can be detected by the MCU as a Vds value greater than the allowable value (e.g., 12V) when the power semiconductor is ON. Alternatively, the DSAT can be detected by the MCU as a rapid change in the Vds value. In this method, the MCU may include or be coupled to an analog-to-digital converter (ADC), which is described below with reference to Figure 12, and which samples the Vds signal at periodic intervals, the sampling interval may be between 10 ns and 500 ns. The DSAT state can be detected when a series of samples specify a rate of change greater than the threshold.

[0040] Next, in block 1004, the MCU sets the gate signal to a first reduced level (e.g., 14V) and loads a first time interval (T2) into a watchdog timer that may be built into the MCU. As shown in the example in Table 1, this time value is 500ns. Blocks 1006, 1008, 1010, 1012, and 1014 form a loop that is executed for each interval and each step of the gate voltage. In this example, T2 is the current interval for the first time through the loop.

[0041] In block 1006, the MCU starts a timer for the current interval and transfers control to block 1008, which monitors the timer and transfers control to block 1010 when the timer counts down to zero. Block 1010 selects a gate signal that will be applied at the end of the current interval. In block 1012, the MCU determines whether the gate signal level selected in block 1010 is the last level in the sequence. If not, block 1014 loads the interval corresponding to the selected level into the timer and transfers control to block 1006 to hold the gate signal at a specified voltage for the new time interval that becomes the current time interval. The loop defined by blocks 1006-1014 is repeated until block 1010 determines that the selected gate level signal is the last level (e.g., off). When this occurs, block 1016 holds the gate signal at the off level.

[0042] The loop formed by blocks 1006-1014 in Figure 10 sequentially advances the gate voltage from an on-voltage of 18V to a first step of 14V (during period T2), a second step of 9V (during period T3), a third step of 4V (during period T4), and finally to an off-voltage of -4V. This flowchart shows that a single counter is loaded at the end of each interval, but it is intended that a separate counter (not shown) may be pre-loaded and started for each interval, or that two counters (not shown) may be used in a ping-pong manner, with one counter counting down the current interval while the other counter is loaded for the next time interval.

[0043] VCE / DS Feedback Control Multi-Stage Turn-Off Figure 11 is a flowchart showing how Vce / Vds can be monitored to determine when to proceed to the next voltage level in the MLTO sequence. The exemplary system described below, with reference to Figure 12, uses two comparators to determine when an overvoltage spike exceeds a predetermined voltage VCHK1 and falls below another predetermined voltage VCHK2. This decreasing voltage change indicates that the voltage spike caused by the previous step has subsided and that the next step in the turn-off process can proceed. By switching to the next voltage level based on the system state, rather than waiting for a fixed set of time, the MLTO process can be optimized, allowing power devices to shut down as quickly as possible to reduce potential damage.

[0044] Prior to block 1102, the power semiconductor device is turned on (for example, the gate voltage is set to 18V). In block 1102, the MCU detects the DSAT state. The MCU can detect the DSAT state in the same manner as described above with reference to block 1002. As soon as the DSAT state is detected, the MCU initiates MLTO operation by setting the gate signal to a first level (for example, 14V) and, if applicable, loading a first countdown value (for example, T2) into the watchdog timer. If a watchdog timer is used, the MCU starts the timer in block 1106.

[0045] If a timer is not used, or if a timer is used, in parallel with the timer's countdown, block 1112 determines whether Vds is greater than VCHK1. As described above, a decrease in gate voltage increases the channel resistance of the power semiconductor device, increasing Vds. Immediately after a decrease in gate voltage, Vds may exhibit a voltage spike. VCHK1 is a Vds voltage that is a predetermined amount (e.g., 1-10 percent) greater than the Vds voltage before the gate voltage changed. VCHK2 is a voltage value that is greater than VCHK1 but less than the voltage that adds the expected voltage spike to VCHK1. Thus, VCHK2 represents the upper limit target level for Vds after the voltage spike has subsided. In block 1114, the MCU determines whether Vds is less than VCHK2. Although the comparisons are described as "greater than" in block 1112 and "less than" in block 1114, it is intended that these comparisons may also be "greater than or equal to" or "less than or equal to," respectively.

[0046] If a watchdog timer is used, block 1112 determines that Vds is less than or equal to VCHK1, and block 1114 determines that Vds is greater than or equal to VCHK2, then control is transferred to block 1106, which continues to decrement the timer. If the timer is not used, blocks 1112 and 1114 continuously test the value of Vds until the conditions are met. This operation is indicated by dashed lines 1113 and 1115.

[0047] After block 1114 determines that Vds is less than VCHK2, block 1110 sets the gate signal to the next level. If the watchdog timer is used and block 1112 determines that Vds is greater than VCHK1 and / or before block 1114 determines that Vds is less than VCHK2, the timer expires and control is transferred to block 1110.

[0048] In block 1116, the MCU determines whether the level set in block 1110 is an off voltage. If so, control is transferred to block 1120, which holds the gate signal applied to the power semiconductor device at an off level. If block 1116 determines that the level applied in block 1110 is not the last level, block 1116 transfers control to block 1118 to load values ​​for VCHK1 and VCHK2 for the next step. If a watchdog timer is used, the next time interval (e.g., T3, T4, etc.) is loaded into the timer in block 1118.

[0049] A watchdog timer can be used to prevent malfunctions in the comparator sequence. If the rising edge Vds does not reach VCHK1, or if the subsequent falling edge Vds does not reach VCHK2, the watchdog timer times out and advances the gate signals sequentially to the next voltage level. This condition may occur in block 1112 if L*dI / dt does not produce a voltage spike high enough to reach voltage VCHK1, or in block 1114 if VDS does not drop low enough to reach voltage VCHK2.

[0050] Figure 12 is a partially schematic block diagram of an exemplary MCU that can be used to perform the operations described in Figures 10 and 11. The control logic 1202 includes an internal timer 1203, registers (not shown), memory (not shown), and a state machine (not shown) that performs the operations described in Figures 10 and / or 11. As described above, the control logic may be implemented as a standalone or embedded microprocessor, microcontroller, or DSP. Alternatively, the control logic may be implemented as an ASIC, FPGA, or CPLD. In another alternative, the control logic may be implemented using discrete logic circuits. In one embodiment, the control logic may include circuits such as an MCU 402, and the driver 404 may include circuits such as an MCU, interface board, and driver board of the system referred to above in U.S. Patent No. 8,984,197.

[0051] The control logic is configured to receive Boolean output signals supplied by comparators 1204 and 1206. One input to these comparators is a voltage proportional to either Vce or Vds, supplied by a voltage divider including resistors R3 and R4. Resistors R3 and R4 are selected to have a coupled high impedance (e.g., greater than 1 megaohm) and to scale the expected range of the Vce / Vds signal to a range that matches the input signal range of comparators 1204 and 1206. The signal supplied by the voltage divider is also applied to the ADC 1205 to generate a digitized value monitored by the MCU 1202 as described above, which can be used to determine the occurrence of a DSAT condition.

[0052] The expected range of the Vce / Vds signal should ideally include the worst-case voltage spike that may occur when switching power semiconductor devices. Therefore, the values ​​of R3 and R4 depend on the expected value of Vce / Vds when the device is turned off, the input range of comparators 1204 and 1206, the parasitic inductance of the circuit including the power semiconductor device, and the expected value of dv / dt with respect to Vds.

[0053] The other inputs to comparators 1204 and 1206 are supplied by digital-to-analog converters (DACs) 1208 and 1210, respectively. DAC 1208 converts the digital value for VCHK1 supplied by control logic 1202 to an analog value and applies this analog value to comparator 1204 so that it can be compared with the scaled Vce / Vds signals across R4. Similarly, DAC 1210 converts the digital value for VCHK2 supplied by control logic 1202 to an analog value and applies this analog value to comparator 1206 so that it can be compared with the scaled Vce / Vds signals. DACs 1208 and 1210, along with comparators 1204 and 1206, are used to implement blocks 1112 and 1114 in Figure 11.

[0054] In addition to implementing block 1112, the DSAT state can be detected using comparator 1204. In this embodiment, the value supplied to DAC 1208 may be a Vce / Vds threshold indicating the occurrence of a DSAT state when the semiconductor device is turned on. Thus, upon receiving a trigger signal to turn on the semiconductor device, control logic 1202 may apply the DSAT threshold to DAC 1208 and monitor the output signal of comparator 1204 while the ON voltage (e.g., 18V) is applied to the gate of the semiconductor device.

[0055] The exemplary circuit shown in Figure 12 also includes five DACs 1222, 1224, 1226, 1228, and 1230. These DACs receive digital values ​​from the MCU 1202 corresponding to their respective gate voltages used in MLTO operation. The DACs convert these digital values ​​into analog signals, which are applied to the analog multiplexer 1232. The multiplexer is controlled by the MUX SELECT signal supplied by the MCU 1202. The output signal of the multiplexer 1232 is applied to a high-speed operational amplifier 1234, which has a gain determined by two gain control resistors R1 and R2. The output signal of the amplifier 1234 is applied to a buffer amplifier 1236 connected to the gate electrode of a power semiconductor device. The operational amplifier 1234 and the buffer circuit 1236 operate in the same manner as the operational amplifiers 404 and 504 described above with reference to Figures 4 and 5.

[0056] The exemplary configuration shown in Figure 12 uses five DACs, each coupled to its own programmable register (not shown) within the control logic 1202. The values ​​stored in these registers are determined when the power semiconductor device is characterized to determine the range of scaled values ​​for Vce / Vds and the specific gate voltages that will be used at various stages of the MLTO. These values ​​can be set when the device is first turned on and can also be changed during the operation of the power semiconductor device, for example, based on the device's temperature and age. By applying separate values ​​to the analog multiplexer 1232, the system can rapidly change the gate voltage of the device. The delay between the control logic 1202 supplying the MUX SELECT signal and the applied gate voltage is only the propagation delay in the high-speed operational amplifier 1234 and buffer 1236.

[0057] Figure 12 shows DACs 1208, 1210, 1222, 1224, 1226, 1228, and 1230 as being outside the MCU control logic 1202, but it is intended that one or more of these DACs may be inside the MCU control logic 1202, and as a result the MCU may directly supply drive signals to the analog multiplexer 1232.

[0058] The exemplary apparatus and method embodiments outlined above can be embodied by programming in the form of software, firmware, or microcode executable by, for example, a user computer system, a server computer, or other programmable device. Programmable embodiments of the technology can typically be considered “products” or “manufactured articles” in the form of executable code and / or associated data carried or embodied on some kind of machine-readable medium. “Storage” type media include any or all of the tangible memories of computers, processors, etc., or their associated modules, such as various semiconductor memories, tape drives, and disk drives, which can at any time provide non-temporary storage for software programming. All or part of the software can sometimes be communicated via the Internet or various other telecommunication networks. Such communication can, for example, allow software to be loaded from one computer or processor to another. Therefore, other types of media on which software elements can be carried include optical, electrical, and electromagnetic waves, such as those used between physical interfaces between local devices, via wired optical terrestrial communication line networks, and via various air links. Physical elements that transmit such waves, such as wired or wireless links and optical links, can also be considered media for carrying software. As used herein, unless limited to one or more “non-transient,” “tangible,” or “storage” media, terms such as “computer or machine-readable medium” refer to any medium involved in providing instructions to a processor for execution.

[0059] Therefore, machine-readable media can take many forms, including but not limited to tangible storage media, carrier media, or physical transmission media. Non-temporary storage media include optical disks or magnetic disks, such as any storage device in any computer. Non-temporary storage media also include storage media such as dynamic memory, such as the main memory of a computer platform. Tangible transmission media include coaxial cables and copper wires and optical fibers, including wires that make up buses inside computer systems. Carrier media can take the form of electrical signals or electromagnetic signals, or acoustic waves or light waves, such as those generated during radio frequency (RF) and optical-based data communications. Therefore, common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tapes, any other magnetic media, CD-ROMs, DVDs or DVD-ROMs, any other optical media, punched card paper tapes, any other physical storage media having a pattern of holes, RAM, PROMs and EPROMs, FLASH-EPROMs, any other memory chips or cartridges, carriers for transmitting data or instructions, cables or links for transmitting such carriers, or any other media from which a computer can read programming code and / or data. Many of these forms of computer-readable media may be involved in transmitting one or more sequences of one or more instructions to a processor for execution.

[0060] Program instructions may include software or firmware implementations encoded in any desired language. When programme instructions are incorporated into a machine-readable medium accessible to the processor of a computer system or device, they transform the computer system or device into a specialized machine customized to perform the actions specified in the program.

[0061] Notwithstanding the foregoing, terms and expressions used herein have their ordinary meanings, consistent with such terms and expressions in their respective fields of study and research, unless otherwise specified herein. Terms indicating relationships, such as "First" and "Second," may be used simply to distinguish one element or action from another, and do not necessarily imply or require any actual relationship or order between such elements or actions. The terms "comprises," "comprising," "includes," "including," or any other variation thereof are intended to include non-exclusive inclusion, so that a process, method, article, or apparatus that includes an enumeration of elements may not only include those elements but may also include other elements that are not expressly enumerated or are specific to such process, method, article, or apparatus. An element preceded by "a" or "an" does not, unless further constraints, preclude the existence of additional identical or similar elements in a process, method, article, or apparatus that includes that element.

[0062] As used herein, the term “combined” refers to any logical, physical, or electrical connection, link, etc., that transmits a signal generated by one system element to another “combined” element. Unless otherwise specified, coupled elements or devices do not necessarily have to be directly connected to one another and may be separated by intermediate components, elements, or communication media that can modify, manipulate, or transmit signals. Each of the various couplings can be considered a separate communication channel.

[0063] While we have described above what we consider to be the best mode and / or other examples, please understand that various modifications are possible therein, that the subject matter of the invention disclosed herein can be implemented in various forms and examples, and that they can be applied to numerous uses, only a portion of which have been described herein. Any and all modifications and variations that fall within the true scope of the concept of the present invention are intended to be claimed by the following claims.

Claims

1. A gate drive control device for power semiconductor devices, A master control unit (MCU) having an input terminal configured to receive a trigger signal and an output terminal that supplies a drive signal for the power semiconductor device, A comparator having an output terminal coupled to the MCU and first and second input terminals, wherein the first input terminal is coupled to receive a signal representing the output signal of the semiconductor device, the second input terminal is coupled to the MCU to receive a target value representing the expected value of the output signal of the power semiconductor device, and the output terminal is coupled to supply a Boolean output signal having a first value when the signal representing the output signal of the power semiconductor device is greater than the target value, and a second value when the signal representing the output signal of the power semiconductor is less than or equal to the target value, The MCU includes program instructions, and the program instructions allow the MCU to... When the trigger signal indicates that the power semiconductor device should be changed from a first state to a second state, a first drive signal for the power semiconductor device and a first target value for the comparator are generated. The first drive signal is held until the Boolean signal shows a first transition between the first value and the second value. In response to the first transition between the first and second values ​​of the Boolean signal, a second drive signal different from the first drive signal and a second target value are supplied to the comparator. The second drive signal is held until the Boolean signal shows a second transition between the first value and the second value. A gate drive control device that, in response to a second transition of the Boolean signal, supplies a third drive signal different from the first and second drive signals.

2. The gate drive control device according to claim 1, wherein the first state is an ON state in which current flows through the power semiconductor device, and the second state is an OFF state in which current does not flow through the power semiconductor device.

3. The gate drive control device according to claim 1, wherein the first state is an off state in which no current flows through the power semiconductor device, and the second state is an on state in which current flows through the power semiconductor device.

4. The gate drive control device according to claim 1, wherein the power semiconductor device is selected from the group consisting of silicon IGBT, SiC FET, GaN FET, AlN FET, and BN FET.

5. A further comparator having an output terminal coupled to the MCU and first and second input terminals, wherein the first input terminal of the further comparator is coupled to receive a signal representing the output signal of the power semiconductor device, and the second input terminal of the further comparator is coupled to receive a first further target value representing a further expected value of the output signal of the power semiconductor device after power fluctuations in the output signal of the power semiconductor device have subsided, the power fluctuations resulting from a change in the drive signal, and the output terminal is configured to supply a further Boolean output signal having a first value when the signal representing the output signal of the power semiconductor device is less than the first further target value, and a second value when the signal representing the output signal of the power semiconductor is greater than or equal to the first further target value, The program instruction causing the MCU to hold the first drive signal until the Boolean signal indicates the first transition between the first value and the second value further causes the MCU to hold the first drive signal until both the Boolean signal and the further Boolean signal indicate the respective first transitions between the first value and the second value. The program instruction that causes the MCU to supply a second drive signal different from the first drive signal and a second target value to the comparator in response to the first transition between the first and second values ​​of the Boolean signal, further causes the MCU to supply a second further target signal to the further comparator, The gate drive control device according to claim 1, wherein the program instruction causing the MCU to hold the second drive signal until the Boolean signal indicates a second transition between the first value and the second value, further causes the MCU to hold the second drive signal until both the Boolean signal and the further Boolean signal indicate their respective second transitions between the first value and the second value.

6. The MCU includes first, second, and third drive output terminals, the first drive output terminal supplies the first drive signal, the second drive output terminal supplies the second drive signal, and the third drive output terminal supplies the third drive signal. The gate drive control device further comprises a multiplexer, the multiplexer having first, second, and third input terminals coupled to the first, second, and third drive output terminals of the MCU, respectively, an output terminal coupled to supply the drive signal to the power semiconductor device, and a control terminal coupled to the MCU for receiving control signals. The aforementioned program instruction is performed by the MCU, In response to the MCU receiving the trigger signal, the multiplexer controls to supply the first drive signal. When the Boolean signal indicates the first transition between the first value and the second value, the multiplexer is controlled to supply the second drive signal. The gate drive control device according to claim 1, which controls the multiplexer to supply the third drive signal in response to the transition between the first and second values ​​of the Boolean signal.

7. A timer configured to be set to a countdown value by the MCU, further comprising a timer that supplies a signal to the MCU when the countdown value has counted down to zero, The program instruction causing the MCU to generate the first drive signal and the first target value further causes the MCU to supply a first countdown value to the timer. The program instruction causing the MCU to hold the first drive signal until the Boolean signal indicates the first transition between the first value and the second value further causes the MCU to hold the first drive signal until the timer value counts down to the first countdown value to zero, or the Boolean signal indicates the first transition between the first value and the second value, whichever occurs first. The program instruction causing the MCU to supply the second drive signal and the second target value further causes the MCU to supply a second countdown value to the timer, The gate drive control device according to claim 1, wherein the program instruction causing the MCU to hold the second drive signal until the Boolean signal indicates a second transition between the first value and the second value further causes the MCU to hold the second drive signal until the timer value counts down to the second countdown value to zero, or the Boolean signal indicates a second transition between the first value and the second value, whichever occurs first.

8. A gate drive control device for power semiconductor devices, A master control unit (MCU) having a first input terminal configured to receive a DSAT signal indicating that the power semiconductor device is experiencing a desaturated state (DSAT), and an output terminal for supplying a drive signal for the power semiconductor device, A comparator having an output terminal coupled to the MCU and first and second input terminals, wherein the first input terminal is coupled to receive a signal representing the output signal of the power semiconductor device, and the second input terminal is coupled to receive a target value from the MCU representing the expected value of the output signal of the power semiconductor device, and to supply a Boolean output signal at the output terminal having a first value when the signal representing the output signal of the power semiconductor device is greater than the target value, and a second value when the signal representing the output signal of the power semiconductor is less than or equal to the target value, The MCU includes program instructions, and the program instructions allow the MCU to... When the DSAT signal indicates that the power semiconductor device is experiencing a DSAT state, a first drive signal for the power semiconductor device and a first target value for the comparator are generated. The first drive signal is held until the Boolean signal shows a first transition between the first value and the second value. In response to the first transition between the first and second values ​​of the Boolean signal, a second drive signal different from the first drive signal and a second target value are supplied to the comparator. The second drive signal is held until the Boolean signal shows a second transition between the first value and the second value. A gate drive control device that, in response to a second transition of the Boolean signal, supplies a third drive signal different from the first and second drive signals.

9. The gate drive control device according to claim 8, wherein the power semiconductor device is selected from the group consisting of silicon IGBT, SiC FET, GaN FET, AlN FET, and BN FET.

10. A further comparator, the further comparator is coupled to receive a first further target value from the MCU, the first further target value representing a first further expected value of the output signal of the power semiconductor device after power fluctuations in the output signal of the power semiconductor device have subsided, the power fluctuations resulting from a change in the drive signal, and the further comparator is coupled to supply a further Boolean output signal having a first value when the output signal of the power semiconductor device is less than the further expected value, and a second value when the output signal of the power semiconductor is greater than or equal to the further expected value, The program instruction causing the MCU to hold the first drive signal until the Boolean signal indicates the first transition between the first value and the second value further causes the MCU to hold the first drive signal until both the Boolean signal and the further Boolean signal indicate the respective first transitions between the first value and the second value. The program instruction that causes the MCU to supply a second drive signal different from the first drive signal and a second target value to the comparator in response to the first transition between the first and second values ​​of the Boolean signal, further causes the MCU to supply a second further target signal to the further comparator, The gate drive control device according to claim 8, wherein the program instruction causing the MCU to hold the second drive signal until the Boolean signal indicates a second transition between the first value and the second value, further causes the MCU to hold the second drive signal until both the Boolean signal and the further Boolean signal indicate their respective second transitions between the first value and the second value.

11. The MCU includes first, second, and third drive output terminals, the first drive output terminal supplies the first drive signal, the second drive output terminal supplies the second drive signal, and the third drive output terminal supplies the third drive signal. The gate drive control device further comprises a multiplexer, the multiplexer having a control input terminal, first, second, and third signal input terminals coupled to the first, second, and third drive output terminals of the MCU, respectively, and an output terminal coupled to supply a selected signal from the first, second, and third drive signals to the power semiconductor device in response to a selection control signal applied to the control terminal of the multiplexer, The aforementioned program instruction is, When the MCU responds to receiving the DSAT signal, the MCU controls the multiplexer to select the first drive signal. When the Boolean signal indicates the first transition between the first value and the second value, the MCU controls the multiplexer to select the second drive signal. The gate drive control device according to claim 8, wherein when the Boolean signal indicates a second transition between a first value and a second value, the MCU controls the multiplexer to select the third drive signal.

12. A timer configured to be set to a countdown value by the MCU, further comprising a timer that supplies a signal to the MCU when the countdown value has counted down to zero, The program instruction causing the MCU to generate the first drive signal and the first target value further causes the MCU to supply a first countdown value to the timer. The program instruction causing the MCU to hold the first drive signal until the Boolean signal indicates the first transition between the first value and the second value further causes the MCU to hold the first drive signal until the timer value counts down to the first countdown value to zero, or the Boolean signal indicates the first transition between the first value and the second value, whichever occurs first. The program instruction causing the MCU to supply the second drive signal and the second target value further causes the MCU to supply a second countdown value to the timer, The gate drive control device according to claim 8, wherein the program instruction causing the MCU to hold the second drive signal until the Boolean signal indicates a second transition between the first value and the second value further causes the MCU to hold the second drive signal until the timer value counts down to the second countdown value to zero, or the Boolean signal indicates a second transition between the first value and the second value, whichever occurs first.

13. A gate drive control device for power semiconductor devices, A master control unit (MCU) having a non-saturated (DSAT) input terminal configured to receive a non-saturated (DSAT) signal, an output terminal configured to provide a DSAT comparison value, and an output terminal to supply a drive signal for the power semiconductor device, The system comprises a DSAT detector coupled to the power semiconductor device for determining the occurrence of a DSAT state, The MCU includes program instructions, and the program instructions allow the MCU to... When a DSAT state occurs, a first drive signal for the power semiconductor device is generated. The first drive signal is held for a first predetermined time interval, At the end of the first predetermined time interval, a second drive signal different from the first drive signal is supplied. The second drive signal is held for a second predetermined time, A gate drive control device that supplies a third drive signal different from the first and second drive signals at the end of the second predetermined time interval.

14. The gate drive control device according to claim 13, wherein the DSAT detector comprises a comparator having a first input terminal coupled to receive a signal representing the output signal of the power semiconductor device, a second input terminal coupled to the MCU for receiving a DSAT comparison value, and an output terminal coupled to the DSAT input terminal of the MCU.

15. The gate drive control device according to claim 13, wherein the DSAT detector includes an analog-to-digital converter (ADC) coupled to supply a series of digital samples of a signal representing the output signal of the power semiconductor device, and the program instruction causes the MCU to calculate the rate of change of the series of samples and indicate a DSAT state if the calculated rate of change is greater than a threshold.

16. The gate drive control device according to claim 13, wherein the power semiconductor device is selected from the group consisting of silicon IGBT, SiC FET, GaN FET, AlN FET, and BN FET.

17. A gate drive control device for power semiconductor devices, A comparator having a reference input terminal, a signal input terminal coupled to receive the output signal of the power semiconductor device, and an output terminal, wherein the comparator supplies a Boolean output signal that enters a first state when the value of the signal applied to the signal input terminal is less than a reference value applied to the reference input terminal, and enters a second state when the value of the signal applied to the signal input terminal is equal to or greater than the reference value applied to the reference input terminal, A master control unit (MCU) comprising: a first input terminal configured to receive a turn-off trigger signal; a second input terminal configured to receive the Boolean signal supplied by the comparator; a third input terminal configured to receive a non-saturated (DSAT) signal; a first output terminal configured to supply a drive signal for the power semiconductor device; and a second output terminal configured to supply the reference value to the reference input terminal of the comparator, The MCU includes program instructions, and the program instructions allow the MCU to... If the trigger signal indicates that the power semiconductor device should be turned off, a first intermediate drive signal for the power semiconductor device is generated. If the DSAT signal indicates that the power semiconductor device is experiencing non-saturation, a second intermediate drive signal different from the first drive signal is generated. A gate drive control device that generates a final drive signal for the power semiconductor when the Boolean signal indicates that the output signal from the power semiconductor device has changed.

18. The gate drive control device according to claim 17, wherein the signal input terminal of the comparator is coupled to receive a voltage signal representing the voltage across the power semiconductor device, and the program instruction causes the MCU to generate the final drive signal when the output signal of the power semiconductor is greater than the reference value.

19. The gate drive control device according to claim 17, wherein the signal input terminal of the comparator is coupled to receive a voltage signal representing the current flowing through the power semiconductor device, and the program instruction causes the MCU to generate the final drive signal when the output signal of the power semiconductor is smaller than the reference value.

20. A further comparator having a further reference input terminal, a further signal input terminal coupled to receive a voltage signal representing the voltage across the power semiconductor device, and a further output terminal, further comprising a further comparator that supplies a further Boolean output signal that changes its state from a first value to a second value when the voltage across the semiconductor device becomes smaller than the value applied to the further reference input terminal, The gate drive control device according to claim 19, wherein if the Boolean signal indicates that the signal applied to the input terminal of the comparator is less than the reference value, or if the further signal applied to the further input terminal of the further comparator is greater than the further reference value, the program instruction further causes the MCU to generate the final drive signal.

21. The gate drive control device according to claim 17, wherein the program instruction further causes the MCU to set a timer to a first value when the first intermediate drive signal is generated, and to set a timer to a second value when the second intermediate drive signal is generated, and also causes the MCU to generate the final drive signal when the timer expires, regardless of the state of the Boolean signal.

22. The MCU further comprises a temperature sensor coupled to supply a signal representing the temperature of the power semiconductor device, The gate drive control device according to claim 17, further comprising a program instruction causing the MCU to change the reference value in response to a change in the temperature of the power semiconductor device.

23. The gate drive control device according to claim 17, wherein the power semiconductor device is selected from the group consisting of silicon IGBT, SiC FET, GaN FET, AlN FET, and BN FET.

24. A gate drive control device for power semiconductor devices, A comparator having a reference input terminal, a signal input terminal coupled to receive the output signal of the power semiconductor device, and an output terminal, wherein the comparator supplies a Boolean output signal that enters a first state when the value of the signal applied to the signal input terminal is less than a reference value applied to the reference input terminal, and enters a second state when the value of the signal applied to the signal input terminal is equal to or greater than the reference value applied to the reference input terminal, A master control unit (MCU) comprises: a first input terminal configured to receive a trigger pulse having rising and falling edges; a second input terminal configured to receive the Boolean signal supplied by the comparator; a first output terminal configured to supply a drive signal for the power semiconductor device; and a second output terminal configured to supply the reference value to the comparator. The MCU includes program instructions, and the program instructions allow the MCU to... In response to the detection of the rising edge of the trigger pulse, a first reference value and a first drive signal for the power semiconductor device are generated, the first drive signal tends to partially turn on the power semiconductor device. When the Boolean signal changes between the first state and the second state, a second drive signal for the power semiconductor device is generated, and the second drive signal tends to fully turn on the power semiconductor device. In response to the falling edge of the trigger pulse, a second reference value and a third drive signal for the power semiconductor device are generated, the third drive signal tends to partially turn off the power semiconductor device. A gate drive control device that generates a fourth drive signal for the power semiconductor device when the Boolean signal changes between the second state and the first state, the fourth drive signal tends to completely turn off the power semiconductor device.

25. The gate drive control device according to claim 24, wherein the signal input terminal of the comparator is coupled to receive a voltage signal representing the voltage across the power semiconductor device, and the program instruction causes the MCU to generate the fourth drive signal when the output signal of the power semiconductor is greater than the reference value.

26. The gate drive control device according to claim 24, wherein the signal input terminal of the comparator is configured to receive a voltage signal representing the current flowing through the power semiconductor device, and the program instruction causes the MCU to generate the fourth drive signal when the output signal of the power semiconductor is smaller than the reference value.

27. A further comparator having a further reference input terminal and a further signal input terminal coupled to receive a voltage signal representing the voltage across the power semiconductor device, wherein the further comparator supplies a further Boolean output signal that enters a first state if the value of the voltage signal applied to the further signal input terminal is less than a further value applied to the further reference input terminal, and enters a second state if the value of the voltage signal applied to the signal input terminal is greater than or equal to the further value applied to the further reference input terminal, The aforementioned program instruction further states that the MCU will If either the Boolean signal or the further Boolean signal changes between the first state and the second state, the second drive signal is generated. The gate drive control device according to claim 26, which generates the fourth drive signal when either the Boolean signal or the further Boolean signal changes between the second state and the first state.

28. The aforementioned program instruction further states that the MCU will When the first drive signal is generated, the timer is set to a first value. Regardless of the state of the Boolean signal, when the timer expires, the second drive signal is generated. When the third drive signal is generated, the timer is set to the second value. The gate drive control device according to claim 24, which generates the fourth drive signal when the timer expires, regardless of the state of the Boolean signal.

29. The MCU further comprises a temperature sensor coupled to supply a signal representing the temperature of the power semiconductor device, The gate drive control device according to claim 24, wherein the program instruction further causes the MCU to change at least one of the first and second reference values ​​in response to a change in the temperature of the power semiconductor device.

30. The gate drive control device according to claim 24, wherein the power semiconductor device is selected from the group consisting of silicon IGBT, SiC FET, GaN FET, AlN FET, and BN FET.

31. A further comparator having a further reference input terminal, a further signal input terminal coupled to receive the output signal of the power semiconductor device, and a further output terminal, further comprising a further comparator that supplies a further Boolean output signal which enters a first state when the value of the signal applied to the further signal input terminal is less than a reference value applied to the further reference input terminal, and enters a second state when the value of the signal applied to the further signal input terminal is greater than or equal to the reference value applied to the further reference input terminal, The gate drive control device according to claim 24, wherein the program instruction causes the MCU to apply the first reference value to the comparator, apply the second reference value to the further comparator, and generate the fourth drive signal when the further Boolean signal changes between the second state and the first state.

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