Nitride semiconductor transistor and method for manufacturing nitride semiconductor transistor

Abstract

The present invention provides a nitride semiconductor transistor capable of reducing sheet resistance and a method for manufacturing a nitride semiconductor transistor. [Solution] The nitride semiconductor transistor has a channel layer and a first barrier layer that overlap each other, the first barrier layer contains a rare earth group III element, aluminum and nitrogen, the first barrier layer has a first region having a first oxygen concentration of 20 atomic% or less and a second region having a second oxygen concentration higher than 20 atomic%, the first region is located between the channel layer and the second region, the first region is thicker than the second region, and the maximum value of the second oxygen concentration is 50 atomic% or less.

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor transistor and a method for manufacturing the nitride semiconductor transistor.

Background Art

[0002] Conventionally, a high electron mobility transistor (HEMT) having a barrier layer containing scandium has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, there has been an increasing demand for further reduction of sheet resistance.

[0006] This disclosure aims to provide a nitride semiconductor transistor capable of reducing sheet resistance and a method for manufacturing a nitride semiconductor transistor. [Means for solving the problem]

[0007] The nitride semiconductor transistor of this disclosure has a channel layer and a first barrier layer that overlap each other, wherein the first barrier layer contains a rare earth group III element, aluminum, and nitrogen, and the first barrier layer has a first region having a first oxygen concentration of 20 atomic% or less and a second region having a second oxygen concentration higher than 20 atomic%, wherein the first region is located between the channel layer and the second region, the first region is thicker than the second region, and the maximum value of the second oxygen concentration is 50 atomic% or less. [Effects of the Invention]

[0008] According to this disclosure, sheet resistance can be reduced. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a cross-sectional view showing a nitride semiconductor transistor according to an embodiment. [Figure 2] Figure 2 is a cross-sectional view (part 1) showing a method for manufacturing a nitride semiconductor transistor according to the embodiment. [Figure 3] Figure 3 is a cross-sectional view (part 2) showing a method for manufacturing a nitride semiconductor transistor according to the embodiment. [Figure 4] Figure 4 is a cross-sectional view (part 3) showing a method for manufacturing a nitride semiconductor transistor according to the embodiment. [Figure 5] Figure 5 is a cross-sectional view (part 4) showing a method for manufacturing a nitride semiconductor transistor according to the embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 5) showing a method for manufacturing a nitride semiconductor transistor according to the embodiment. [Figure 7]FIG. 7 is a cross-sectional view (part 6) showing a method for manufacturing a nitride semiconductor transistor according to an embodiment. [Figure 8] FIG. 8 is a diagram showing the temperature dependence of the Hall effect before annealing. [Figure 9] FIG. 9 is a diagram showing the temperature dependence of the Hall effect after annealing. [Figure 10] FIG. 10 is a diagram showing the band structure before annealing. [Figure 11] FIG. 11 is a diagram showing the band structure after annealing. [Figure 12] FIG. 12 is a diagram showing the ADF image before annealing. [Figure 13] FIG. 13 is a diagram showing the BF image before annealing. [Figure 14] FIG. 14 is a diagram showing the results of EDX analysis before annealing. [Figure 15] FIG. 15 is a diagram showing the ADF image after annealing. [Figure 16] FIG. 16 is a diagram showing the BF image after annealing. [Figure 17] FIG. 17 is a diagram showing the results of EDX analysis after annealing. [Figure 18] FIG. 18 is a diagram showing the TEM observation image before annealing. [Figure 19] FIG. 19 is a diagram showing the TEM observation image after annealing. [Figure 20] FIG. 20 is a schematic diagram (part 1) showing the change in the structure in the crystalline region before and after annealing. [Figure 21] FIG. 21 is a schematic diagram (part 2) showing the change in the structure in the crystalline region before and after annealing. [Figure 22] FIG. 22 is a diagram showing the relationship between the annealing atmosphere, the sheet carrier concentration, and the mobility.

Mode for Carrying Out the Invention

[0010] [Description of Embodiments of the Present Disclosure] First, the embodiments of this disclosure will be listed and described.

[0011] [1] A nitride semiconductor transistor according to one aspect of the present disclosure has a channel layer and a first barrier layer that overlap each other, wherein the first barrier layer contains a rare earth group III element, aluminum and nitrogen, and the first barrier layer has a first region having a first oxygen concentration of 20 atomic% or less and a second region having a second oxygen concentration higher than 20 atomic%, wherein the first region is located between the channel layer and the second region, the first region is thicker than the second region, and the maximum value of the second oxygen concentration is 50 atomic% or less.

[0012] The first barrier layer is formed, for example, by a sputtering method, and inevitably has a first region having a first oxygen concentration of 20 atomic percent or less, and a second region having a second oxygen concentration higher than 20 atomic percent, with the first region being thicker than the second region. Here, by having a maximum second oxygen concentration of 50 atomic percent or less, the negative fixed charge contained in the first barrier layer is small, and the sheet resistance can be reduced.

[0013] [2] In [1], the maximum value of the second oxygen concentration may be 40 atomic percent or less. In this case, the sheet resistance is particularly easy to reduce.

[0014] [3] In [1] or [2], a second barrier layer is provided between the channel layer and the first barrier layer, wherein the second barrier layer may contain gallium, aluminum, and nitrogen. In this case, the concentration of the two-dimensional electron gas is increased, making it easier to reduce the sheet resistance.

[0015] [4] In any of [1] to [3], the first barrier layer may contain scandium as a rare earth group III element. Scandium has a relatively small ionic radius among the rare earth group III elements, and the nitride of scandium and aluminum can reduce the degree of lattice mismatch with gallium nitride compared to when other rare earth group III elements are included. For this reason, when the first barrier layer contains scandium as a rare earth group III element, the crystallinity of the channel layer and the first barrier layer can be improved, for example.

[0016] [5] A method for manufacturing a nitride semiconductor transistor according to another aspect of the present disclosure comprises the steps of forming an overlapping channel layer and a semiconductor layer, and forming a first barrier layer by annealing the semiconductor layer to reduce the oxygen concentration in the semiconductor layer, wherein the semiconductor layer is formed by sputtering, and the semiconductor layer contains a rare earth group III element, aluminum, and nitrogen.

[0017] The first barrier layer, formed by sputtering and containing rare earth group III elements, aluminum, and nitrogen, inevitably contains oxygen. By annealing the semiconductor layer, the oxygen concentration in the semiconductor layer is reduced, thereby forming the first barrier layer. This reduces the negative fixed charges contained in the first barrier layer and lowers the sheet resistance.

[0018] [6] In [5], the semiconductor layer may be formed at a temperature of 700°C or lower. In this case, the semiconductor layer is likely to have a wurtzite-type crystal structure.

[0019] [7] In [5] or [6], the annealing temperature may be higher than the temperature at which the semiconductor layer is formed. In this case, it is easier to lower the oxygen concentration in the semiconductor layer.

[0020] [8] In [7], the annealing temperature may be 1000°C or lower. In this case, phase separation of the semiconductor layer due to annealing can be made less likely.

[0021] [9] In any of [5] to [8], the annealing may be carried out in an atmosphere containing at least one gas selected from nitrogen gas, hydrogen gas, and ammonia gas. In this case, it is easier to lower the oxygen concentration in the semiconductor layer.

[0022] [Details of the embodiments of this disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant descriptions. In this disclosure, "plan view" means viewing the object from above. In this disclosure, the direction in which the nitride semiconductor layer is located relative to the substrate is defined as "up".

[0023] Embodiments of this disclosure relate to nitride semiconductor transistors. Nitride semiconductor transistors are, for example, gallium nitride-based high electron mobility transistors (HEMTs). Figure 1 is a cross-sectional view showing a nitride semiconductor transistor according to an embodiment.

[0024] As shown in Figure 1, the nitride semiconductor transistor 1 according to the embodiment includes a substrate 10, a nitride semiconductor layer 20, an insulating film 30, a regrowth layer 41S, a regrowth layer 41D, a gate electrode 43, a source electrode 42S, and a drain electrode 42D.

[0025] The substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. If the substrate 10 is a SiC substrate, the upper surface of the substrate 10 is the silicon (Si) polar surface.

[0026] The nitride semiconductor layer 20 includes a nucleation layer 21, a buffer layer 22, a channel layer 23, a spacer layer 24, a second barrier layer 25, and a first barrier layer 26. For example, the buffer layer 22 is formed on the nucleation layer 21, and the channel layer 23 is formed on the buffer layer 22. The direction in which each layer is formed is also called the stacking direction. The "planar view" described above includes viewing the object along the stacking direction.

[0027] The nucleation layer 21 is located on the substrate 10. The nucleation layer 21 is, for example, an aluminum nitride (AlN) layer. The thickness of the nucleation layer 21 is, for example, between 5 nm and 40 nm.

[0028] The buffer layer 22 is located on top of the nucleation layer 21. The buffer layer 22 is, for example, a gallium nitride (GaN) layer. The buffer layer 22 may contain iron (Fe) as an impurity. The thickness of the buffer layer 22 is, for example, 100 nm to 1000 nm.

[0029] The channel layer 23 is located on top of the buffer layer 22. The channel layer 23 is, for example, a gallium nitride (GaN) layer. The thickness of the channel layer 23 is, for example, between 10 nm and 1000 nm. The conductivity type of the channel layer 23 is, for example, n-type or undoped (i-type). It is not necessary to distinguish between the buffer layer 22 and the channel layer 23.

[0030] The spacer layer 24 is located on top of the channel layer 23. The spacer layer 24 is, for example, an aluminum nitride (AlN) layer. The thickness of the spacer layer 24 is, for example, between 0.5 nm and 3 nm.

[0031] The second barrier layer 25 is located on the spacer layer 24. The channel layer 23 and the second barrier layer 25 overlap each other. The second barrier layer 25 is, for example, an aluminum gallium nitride (AlGaN) layer. The electron affinity of the second barrier layer 25 is smaller than that of the channel layer 23. The band gap of the second barrier layer 25 is larger than that of the channel layer 23. The thickness of the second barrier layer 25 is, for example, between 1 nm and 20 nm. The composition of the second barrier layer 25 is, for example, Al Y Ga 1-Y N(0.15≦Y≦0.55). That is, in the AlGaN layer, the ratio of the number of Al atoms to the total number of Al atoms and Ga atoms (Al composition ratio) is between 15% and 55%. The conductivity type of the second barrier layer 25 is, for example, n-type or undoped (i-type).

[0032] The first barrier layer 26 is located on top of the second barrier layer 25. The channel layer 23, the second barrier layer 25, and the first barrier layer 26 overlap each other. The first barrier layer 26 contains rare earth group III elements, aluminum, and nitrogen. The first barrier layer 26 is, for example, a scandium aluminum nitride (ScAlN) layer. The electron affinity of the first barrier layer 26 is smaller than that of the channel layer 23. The band gap of the first barrier layer 26 is larger than that of the channel layer 23. The thickness of the first barrier layer 26 is, for example, between 5 nm and 80 nm. The composition of the first barrier layer 26 is, for example, Sc X Al 1-X N(0.05≦X≦0.45). That is, in the ScAlN layer, the ratio of the number of Sc atoms to the total number of Al atoms and Sc atoms (Sc composition ratio) is between 5% and 45%. The first barrier layer 26 has a wurtzite-type crystal structure, and the crystal orientation perpendicular to the upper surface 27 of the first barrier layer 26 is

[0001] (c axis). The conductivity type of the first barrier layer 26 is, for example, n-type or undoped (i-type).

[0033] The first barrier layer 26 has a first region 261 having a first oxygen concentration and a second region 262 having a second oxygen concentration in the stacking direction. The first region 261 is located between the channel layer 23 and the second region 262. The first region 261 is thicker than the second region 262. The upper surface 27 of the first barrier layer 26 is located in the second region 262. The first barrier layer 26 inevitably contains oxygen (O), and the second oxygen concentration is higher than the first oxygen concentration. The first oxygen concentration is 20 atomic percent or less, and the second oxygen concentration is higher than 20 atomic percent. The maximum value of the second oxygen concentration is 50 atomic percent or less. For example, the thickness of the first region 261 is 3 nm to 75 nm, and the thickness of the second region 262 is 2 nm to 5 nm.

[0034] A source recess 40S and a drain recess 40D are formed in the nitride semiconductor layer 20. The recesses 40S and 40D penetrate the first barrier layer 26, the second barrier layer 25, and the spacer layer 24. The recesses 40S and 40D may further penetrate the channel layer 23. The bottoms of the recesses 40S and 40D may be in the channel layer 23 or in the buffer layer 22.

[0035] The insulating film 30 is located on the first barrier layer 26. The insulating film 30 is, for example, a silicon nitride (SiN) film. The thickness of the insulating film 30 is, for example, 20 nm to 700 nm. An opening 30S for the source, an opening 30D for the drain, and an opening 30G for the gate are formed in the insulating film 30. The opening 30S connects to a recess 40S, and the opening 30D connects to a recess 40D. In a plan view, the opening 30G is located between the openings 30S and 30D. The opening 30G reaches the first barrier layer 26.

[0036] The regrowth layer 41S is located within the recess 40S on top of the channel layer 23 or buffer layer 22. The regrowth layer 41D is located within the recess 40D on top of the channel layer 23 or buffer layer 22. The regrowth layers 41S and 41D are, for example, n-type GaN layers. The regrowth layers 41S and 41D contain germanium (Ge) or silicon (Si) as n-type impurities.

[0037] The source electrode 42S is on the regrowth layer 41S, and the drain electrode 42D is on the regrowth layer 41D. The source electrode 42S is in contact with the regrowth layer 41S, and the drain electrode 42D is in contact with the regrowth layer 41D. The source electrode 42S is in ohmic contact with the regrowth layer 41S, and the drain electrode 42D is in ohmic contact with the regrowth layer 41D.

[0038] In a plan view, the gate electrode 43 is located between the source electrode 42S and the drain electrode 42D. The gate electrode 43 is on the insulating film 30 and contacts the first barrier layer 26 through the opening 30G.

[0039] In the nitride semiconductor transistor 1, due to the action of the second barrier layer 25 and the first barrier layer 26, a two-dimensional electron gas (2DEG) 50 is generated near the upper surface of the channel layer 23, as shown in Figure 1.

[0040] Next, a method for manufacturing a nitride semiconductor transistor according to an embodiment will be described. Figures 2 to 7 are cross-sectional views showing a method for manufacturing a nitride semiconductor transistor 1 according to an embodiment.

[0041] First, as shown in Figure 2, a nucleation layer 21, a buffer layer 22, a channel layer 23, a spacer layer 24, and a second barrier layer 25 are sequentially formed on the substrate 10, for example, by metal-organic vapor phase epitaxy (MOVPE). The nucleation layer 21, buffer layer 22, channel layer 23, spacer layer 24, and second barrier layer 25 may also be formed by electron beam epitaxy (MBE).

[0042] For the formation of the nucleating layer 21, for example, trimethylaluminum (TMA) and ammonia (NH3) are used as raw material gases, with a growth temperature (formation temperature) of approximately 1000°C and a growth pressure (formation pressure) of approximately 5 kPa. For the formation of the buffer layer 22, for example, trimethylgallium (TMG) and ammonia (NH3) are used as raw material gases, with a growth temperature of approximately 1000°C and a growth pressure of approximately 40 kPa. When iron (Fe) is added to the buffer layer 22, for example, cyclopentanedienyl iron (CP2Fe) is used as the raw material for iron. For the formation of the channel layer 23, for example, trimethylgallium (TMG) and ammonia (NH3) are used as raw material gases, with a growth temperature of approximately 1000°C and a growth pressure of approximately 20 kPa. When forming the spacer layer 24, for example, trimethylaluminum (TMA) and ammonia (NH3) are used as raw material gases, and the growth temperature is set to about 1000°C and the growth pressure to about 5kPa. When forming the second barrier layer 25, for example, trimethylgallium (TMG), trimethylaluminum (TMA), and ammonia (NH3) are used as raw material gases, and the growth temperature is set to about 1000°C and the growth pressure to about 5kPa. As the second barrier layer 25 is formed, a two-dimensional electron gas 50X is generated near the upper surface of the channel layer 23.

[0043] Next, as shown in Figure 3, a semiconductor layer 26X, which will later become the first barrier layer 26, is formed on the second barrier layer 25 by sputtering. The semiconductor layer 26X contains rare earth group III elements, aluminum, and nitrogen. When forming the semiconductor layer 26X, for example, a scandium (Sc) target and an aluminum (Al) target are used, and the growth temperature is set to about 650°C and the growth pressure to about 10 Pa in a mixed gas atmosphere of nitrogen (N2) and argon (Ar). In the stacking direction, the semiconductor layer 26X has a third region 263 having a third oxygen concentration and a fourth region 264 having a fourth oxygen concentration. The third region 263 is located between the channel layer 23 and the fourth region 264. The semiconductor layer 26X inevitably contains oxygen (O), and the fourth oxygen concentration is higher than the third oxygen concentration. The third oxygen concentration is 30 atomic percent or less, and the fourth oxygen concentration is higher than 30 atomic percent. For example, the fourth oxygen concentration is higher than 30 atomic percent and 70 atomic percent or less. The maximum value of the fourth oxygen concentration may be higher than 50 atomic percent. The fourth region 264 is an amorphous region. The thickness of the third region 263 does not need to match the thickness of the first region 261, and the thickness of the fourth region 264 does not need to match the thickness of the second region 262. With the formation of the semiconductor layer 26X, a two-dimensional electron gas 50Y with a higher concentration than the two-dimensional electron gas 50X is generated near the upper surface of the channel layer 23.

[0044] Next, the semiconductor layer 26X is annealed to lower the oxygen concentration in the semiconductor layer 26X compared to before annealing. The annealing is performed, for example, in a MOVPE furnace. The annealing atmosphere gas includes, for example, nitrogen (N2) gas, hydrogen (H2) gas, or ammonia (NH3) gas. The annealing atmosphere may also be a mixed atmosphere containing two or more of these gases. For example, the annealing temperature is about 800°C and the time is about 60 minutes. Rapid thermal annealing (RTA) of about 10 minutes is repeated six times.

[0045] Annealing of the semiconductor layer 26X promotes its crystallization. As a result, some of the oxygen atoms contained in the fourth region 264 are expelled to the outside. In addition, some of the oxygen atoms contained in the third region 263 diffuse into the fourth region 264 or are further expelled to the outside. As a result, as shown in Figure 4, a first barrier layer 26 is obtained from the semiconductor layer 26X. The first barrier layer 26 has a first region 261 and a second region 262. Due to the expulsion of oxygen atoms, the oxygen concentration in the first barrier layer 26 becomes lower than the oxygen concentration in the semiconductor layer 26X. The maximum value of the second oxygen concentration in the second region 262 is 50 atomic percent or less. With the formation of the first barrier layer 26, a two-dimensional electron gas 50 with a higher concentration than the two-dimensional electron gas 50Y is generated near the upper surface of the channel layer 23.

[0046] Next, as shown in Figure 5, an insulating film 30 is formed on the first barrier layer 26. Then, an opening 30S for the source and an opening 30D for the drain are formed in the insulating film 30. The openings 30S and 30D can be formed, for example, by reactive ion etching (RIE) using a mask (not shown). In RIE, a reactive gas containing fluorine, such as carbon tetrafluoride (CF4), is used.

[0047] Next, as shown in Figure 6, a source recess 40S and a drain recess 40D are formed in the nitride semiconductor layer 20. The recesses 40S and 40D can be formed, for example, by argon (Ar)-based ion milling using the insulating film 30 as a mask. Subsequently, the disordered crystals created by ion milling are removed by wet etching, chlorine-based dry etching, or both.

[0048] Next, as shown in Figure 7, a regrowth layer 41S is formed on the channel layer 23 or buffer layer 22 within the recess 40S, and a regrowth layer 41D is formed on the channel layer 23 or buffer layer 22 within the recess 40D. The regrowth layers 41S and 41D can be formed, for example, by the MOVPE method. When forming the regrowth layers 41S and 41D, for example, trimethylgallium (TMG) and ammonia (NH3) are used as raw material gases, and the growth temperature is set to about 850°C and the growth pressure to about 20kPa.

[0049] Next, a source electrode 42S is formed on the regrowth layer 41S, and a drain electrode 42D is formed on the regrowth layer 41D. When forming the source electrode 42S and the drain electrode 42D, for example, a metal layer (not shown) is deposited using a growth mask (not shown) with openings formed in the regions where the source electrode 42S and the drain electrode 42D are to be formed, and then the growth mask is removed together with the metal layer (not shown) formed thereon. In other words, a lift-off is performed.

[0050] Next, an opening 30G for the gate is formed in the insulating film 30 (see Figure 1). The opening 30G can be formed, for example, by RIE using a mask (not shown). Next, a gate electrode 43 that contacts the first barrier layer 26 through the opening 30G is formed on the insulating film 30 (see Figure 1). When forming the gate electrode 43, a metal layer (not shown) is deposited using, for example, a growth mask (not shown) with an opening formed in the region where the gate electrode 43 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed on it. In other words, a lift-off is performed.

[0051] In this way, nitride semiconductor transistor 1 can be manufactured.

[0052] Here, we will describe various tests conducted by the inventors of this application in relation to the change from the semiconductor layer 26X to the first barrier layer 26 due to annealing.

[0053] (First Exam) In the first experiment, the temperature dependence of the Hall effect before and after annealing was investigated. In the first experiment, a sample was first prepared as follows: a nucleation layer was formed on the substrate, gallium nitride layers were formed on the nucleation layer as a buffer layer and a channel layer, a spacer layer was formed on the gallium nitride layer, a second barrier layer was formed on the spacer layer, and a first barrier layer was formed on the second barrier layer. The buffer layer, channel layer, spacer layer, and second barrier layer were formed by the MOVPE method, and the first barrier layer was formed by the sputtering method. As the spacer layer, an aluminum nitride layer with a thickness of 1 nm was formed, as the second barrier layer, an aluminum gallium nitride layer with a thickness of 3 nm and an Al composition ratio of 20% was formed, and as the first barrier layer, an aluminum scandium nitride layer with a thickness of 10 nm and an Sc composition ratio of 10% was formed. The shape of the sample in plan view was a square with sides of 10 mm in length. Then, the carrier mobility was measured before and after annealing. The annealing temperature was 800°C and the duration was 60 minutes. These results are shown in Figures 8 and 9. Figure 8 shows the temperature dependence of the Hall effect before annealing, and Figure 9 shows the temperature dependence of the Hall effect after annealing.

[0054] Before annealing, as shown in Figure 8, mobility decreased at extremely low temperatures below 100K. On the other hand, after annealing, as shown in Figure 9, there was no decrease in mobility at extremely low temperatures below 100K, and mobility was rate-limited by interfacial roughness scattering. From this, it can be inferred that before annealing, carrier scattering occurred due to ionized impurities, whereas after annealing, the number of ionized impurities decreased, making carrier scattering less likely.

[0055] Furthermore, ionized impurities act as negative fixed charges, and it is thought that the band structure changes as follows. Figure 10 shows the band structure before annealing, and Figure 11 shows the band structure after annealing. Figures 10 and 11 show the Fermi level E F and the lower end E of the conduction band C This is shown. Figures 10 and 11 also show the electron concentration.

[0056] Before annealing, the first barrier layer has a negative fixed charge, and the two-dimensional electron gas is remotely scattered by this negative fixed charge. Also, due to the negative fixed charge, the band of the first barrier layer rises, as shown in Figure 10. On the other hand, after annealing, the negative fixed charge in the first barrier layer decreases, and the two-dimensional electron gas is less likely to be remotely scattered by Coulomb. Also, as shown in Figure 11, the band of the first barrier layer is pushed down, and the concentration of the two-dimensional electron gas increases.

[0057] (Second Exam) In the second experiment, cross-sectional observation using scanning transmission electron microscopy (STEM) and analysis using energy dispersive X-ray spectroscopy (EDX) were performed before and after annealing. The same sample preparation method was used for the second experiment as for the first experiment. Next, a carbon film was formed on the second barrier layer as a protective layer by sputtering. Then, the laminate was processed using a focused ion beam processing apparatus so that a cross-section perpendicular to the lamination direction of the sample and carbon film was visible. For cross-sectional observation using STEM, annular dark field (ADF) and bright field (BF) images were obtained. The results of the second experiment are shown in Figures 12 to 17. Figure 12 shows the ADF image before annealing, Figure 13 shows the BF image before annealing, and Figure 14 shows the results of the EDX analysis before annealing. Figure 15 shows the ADF image after annealing, Figure 16 shows the BF image after annealing, and Figure 17 shows the results of EDX analysis after annealing. In Figures 14 and 17, the position 33 nm from the outermost surface of the aluminum scandium nitride layer, which serves as the first barrier layer, is defined as 0 nm.

[0058] As shown in Figures 12 and 13, before annealing, the first barrier layer contains an amorphous region 71 and a crystalline region 72. Region 72 is located below region 71. Also, as shown in Figure 14, the maximum oxygen concentration in the amorphous region 72 is high, at approximately 60 atomic percent.

[0059] On the other hand, as shown in Figures 15 and 16, after annealing, the amorphous region 71 changes into a crystalline region 72. Also, as shown in Figure 17, there is a region in region 72 where the oxygen concentration is higher than 20 atomic percent, but the maximum oxygen concentration is 40 atomic percent or less.

[0060] In Figures 14 and 17, the concentrations of scandium, aluminum, and nitrogen are lower in the surface layer of the ScAlN layer, which is due to errors in the EDX analysis. Also, the oxygen concentration is higher near the boundary between the AlGaN layer and the ScAlN layer than before and after that point, because the surface of the AlGaN layer formed by the MOVPE method before the ScAlN layer was formed by the sputtering method was slightly oxidized.

[0061] (Third Exam) In the third test, an aluminum scandium nitride layer was formed as the first barrier layer under different sputtering conditions than in the first test, and TEM observations were performed before and after annealing. The results are shown in Figures 18 and 19. Figure 18 shows the TEM observation image before annealing, and Figure 19 shows the TEM observation image after annealing.

[0062] As shown in Figure 18, before annealing, the first barrier layer contains an amorphous region 71 and a crystalline region 72. Region 72 also contains region 73 and region 74, which has more crystal grains than region 73. Region 73 is located below region 74. On the other hand, as shown in Figure 19, after annealing, the amorphous region 71 has changed into a crystalline region 72. Also, region 74, which has more crystal grains, has changed into region 73.

[0063] These changes in the structure of region 72 are thought to be due to the phenomenon described below. Figures 20 and 21 are schematic diagrams showing the changes in the structure of the crystalline region before and after annealing.

[0064] Before annealing, as shown in Figure 20, there are many crystal grains 28 in region 74. However, after annealing, as shown in Figure 21, the coarsening of the crystal grains 28 is promoted, and the number of crystal grains 28 decreases. Furthermore, this change in structure reduces the oxygen concentration in the first barrier layer. In other words, oxygen atoms can exist both inside the crystal grains 28 and at the grain boundaries, but after annealing, the number of grain boundaries decreases, causing the oxygen atoms that were present at the grain boundaries to be released to the outside. In addition, oxygen atoms inside the crystal grains 28 act as positive fixed charges, and oxygen atoms at the grain boundaries act as negative fixed charges. The release of oxygen atoms at the grain boundaries makes remote Coulomb scattering of the two-dimensional electron gas less likely to occur.

[0065] (Fourth Examination) In the fourth experiment, the annealing atmosphere was investigated. Specifically, annealing was performed in three different atmospheres: nitrogen (N2), hydrogen (H2), and ammonia (NH3), and the sheet carrier concentration and mobility were measured. For reference, the sheet carrier concentration and mobility before annealing were also measured. The results are shown in Figure 22. Figure 22 is a diagram showing the relationship between the annealing atmosphere and the sheet carrier concentration and mobility.

[0066] As shown in Figure 22, sheet carrier concentration and mobility improved in all atmospheres compared to before annealing. Furthermore, sheet carrier concentration and mobility were higher in a hydrogen atmosphere than in a nitrogen atmosphere. This is because hydrogen has a reducing effect, which easily lowers the oxygen concentration in the first barrier layer. Also, sheet carrier concentration and mobility were higher in an ammonia atmosphere than in a hydrogen atmosphere. This is because ammonia, like hydrogen, has a reducing effect, and nitrogen atoms in ammonia enter the nitrogen vacancies in the first barrier layer, reducing the amount of nitrogen vacancies.

[0067] In the nitride semiconductor transistor 1, the first barrier layer 26 formed by sputtering inevitably has a first region 261 having a first oxygen concentration of 20 atomic percent or less, and a second region 262 having a second oxygen concentration higher than 20 atomic percent. Here, if the maximum value of the second oxygen concentration is 50 atomic percent or less, the negative fixed charge contained in the first barrier layer 26 is small, and the sheet resistance can be reduced. If the maximum value of the second oxygen concentration is 40 atomic percent or less, the sheet resistance is particularly easy to reduce. The maximum value of the second oxygen concentration may also be 35 atomic percent or less. The first and second oxygen concentrations can be measured by energy-dispersive X-ray spectroscopy.

[0068] Furthermore, the nitride semiconductor transistor 1 having a second barrier layer 25 increases the concentration of the two-dimensional electron gas 50, making it easier to reduce the sheet resistance.

[0069] The rare earth group III element contained in the first barrier layer 26 is not limited to scandium. However, scandium has a relatively small ionic radius among the rare earth group III elements, and the nitride of scandium and aluminum can have a lower degree of lattice mismatch with gallium nitride than when other rare earth group III elements are included. For this reason, when the first barrier layer 26 contains scandium as a rare earth group III element, for example, the crystallinity of the nitride semiconductor layer 20 including the channel layer 23 and the first barrier layer 26 can be improved.

[0070] When the first barrier layer 26 is an aluminum scandium nitride layer, if the Sc composition ratio in the first barrier layer 26 is 5% or more, the concentration of the two-dimensional electron gas 50 is easily increased. Also, if the Sc composition ratio is 45% or less, the first barrier layer 26 is likely to have a wurtzite-type crystal structure. Generally, the higher the Sc composition ratio, the higher the dielectric constant of aluminum scandium nitride, and the more likely remote Coulomb scattering is to occur. However, in this embodiment, since the maximum value of the second oxygen concentration is 50 atomic percent or less, the sheet resistance can be reduced.

[0071] In the manufacturing method of nitride semiconductor transistor 1, if the semiconductor layer 26X is formed at a temperature of 700°C or lower, the semiconductor layer 26X is likely to have a wurtzite-type crystal structure. If the semiconductor layer 26X is formed at a temperature higher than 700°C, the semiconductor layer 26X may undergo phase separation into a phase having a Sc-rich rock salt-type crystal structure and a phase having an Al-rich wurtzite-type crystal structure.

[0072] If the annealing temperature is higher than the temperature at which the semiconductor layer 26X is formed, it is easier to increase the crystallinity of the semiconductor layer 26X and lower the oxygen concentration in the semiconductor layer 26X. However, if the annealing temperature is higher than 1000°C, there is a risk that the semiconductor layer 26X will undergo phase separation into a phase with a Sc-rich rock salt-type crystal structure and a phase with an Al-rich wurtzite-type crystal structure. If the annealing temperature is 1000°C or lower, it is possible to reduce the likelihood of phase separation of the semiconductor layer 26X due to annealing.

[0073] The annealing atmosphere is not limited and can be, for example, an atmosphere containing at least one gas selected from nitrogen, hydrogen, and ammonia. The ratio of the mixed gases is, for example, nitrogen:hydrogen:ammonia = 100:1:10. In this case, it is easier to reduce the oxygen concentration in the semiconductor layer 26X. When the atmospheric gas contains hydrogen or ammonia, the oxygen concentration is particularly easily reduced due to the reducing effect, and when the atmospheric gas contains ammonia, it is easier to reduce nitrogen vacancies in the semiconductor layer 26X.

[0074] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims. [Explanation of Symbols]

[0075] 1 Nitride semiconductor transistor 10 circuit boards 20 Nitride semiconductor layer 21 Nucleation layer 22 Buffer Layers 23 channel layers 24 Spacer layer 25. Second barrier layer 26. First barrier layer 26X semiconductor layer 27 Top 28 crystal grains 30 insulating film 30D, 30G, 30S aperture 40D, 40S recess 41D, 41S regrowth layer 42D drain electrode 42S Source Electrode 43 gate 50, 50X, 50Y Two-dimensional electron gas 71, 72, 73, 74 area 261 First area 262 Second area 263 Third area 264 4th area

Claims

1. It has a channel layer and a first barrier layer that overlap each other, The first barrier layer contains a rare earth group III element, aluminum, and nitrogen. The first barrier layer is, A first region having a first oxygen concentration of 20 atomic percent or less, A second region having a second oxygen concentration higher than 20 atomic percent, It has, The first region is located between the channel layer and the second region. The first region is thicker than the second region. A nitride semiconductor transistor in which the maximum value of the second oxygen concentration is 50 atomic percent or less.

2. The nitride semiconductor transistor according to claim 1, wherein the maximum value of the second oxygen concentration is 40 atomic percent or less.

3. The channel layer and the first barrier layer are located in a second barrier layer, The nitride semiconductor transistor according to claim 1 or claim 2, wherein the second barrier layer comprises gallium, aluminum, and nitrogen.

4. The nitride semiconductor transistor according to claim 1 or claim 2, wherein the first barrier layer contains scandium as a rare earth group III element.

5. A process for forming overlapping channel layers and semiconductor layers, The process involves annealing the semiconductor layer to lower the oxygen concentration in the semiconductor layer and form a first barrier layer, It has, The semiconductor layer is formed by sputtering, The semiconductor layer comprises a rare earth group III element, aluminum, and nitrogen, and is a method for manufacturing a nitride semiconductor transistor.

6. The method for manufacturing a nitride semiconductor transistor according to claim 5, wherein the semiconductor layer is formed at a temperature of 700°C or lower.

7. The method for manufacturing a nitride semiconductor transistor according to claim 5 or 6, wherein the annealing temperature is higher than the temperature at which the semiconductor layer is formed.

8. The method for manufacturing a nitride semiconductor transistor according to claim 7, wherein the annealing temperature is 1000°C or less.

9. The method for manufacturing a nitride semiconductor transistor according to claim 5 or 6, wherein the annealing is carried out in an atmosphere containing at least one gas selected from nitrogen gas, hydrogen gas, and ammonia gas.

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