Printed circuit board

Abstract

To provide a printed circuit board having conductive posts with improved uniformity. [Solution] The printed circuit board of the present invention comprises an insulating layer and conductive posts disposed on the insulating layer, wherein the conductive posts include a barrier layer, a seed layer disposed on the barrier layer, and a plating layer disposed on the seed layer.

Description

Technical Field

[0001] The present invention relates to a printed circuit board.

Background Art

[0002] Recently, in order to meet the trend of weight reduction and miniaturization of mobile devices, there is an increasing need to embody thin, light, short, and small characteristics in the printed circuit boards mounted on them. On the other hand, as mobile devices become thinner, lighter, shorter, and smaller, an undercut phenomenon occurs during the process of embodying fine circuits, which may cause defects in the fine circuits. In response to the technical requirements for this, research has continued to improve reliability while embodying circuits with fine line widths and intervals.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above conventional problems, and an object of the present invention is to provide a printed circuit board having conductive posts with improved uniformity.

Means for Solving the Problems

[0005] A printed circuit board according to an aspect of the present invention made to achieve the above object includes an insulating layer and conductive posts disposed on the insulating layer, and the conductive posts include a barrier layer, a seed layer disposed on the barrier layer, and a plating layer disposed on the seed layer.

[0006] The barrier layer may contain Ni. The side surface of the barrier layer and the side surface of the seed layer may be discontinuous. The minimum width of the barrier layer may be wider than the minimum width of the seed layer. The side surface of the barrier layer can be separated from the inner surface of the insulating layer facing the conductive post. The lower surface of the barrier layer may be located below the upper surface of the insulating layer. The upper surface of the barrier layer may be at the same level as the upper surface of the insulating layer. The sides of the seed layer and the sides of the plating layer may include curved surfaces. The side surface of the seed layer and the side surface of the plating layer can be continuous. The aforementioned plating layer may have a shape in which its width narrows from the top to the bottom. The seed layer may have a shape that widens from top to bottom. The printed circuit board may further include an additional barrier layer disposed on the plating layer. The additional barrier layer may include at least one of Au, Ni, and Pt. The width of the additional barrier layer may be wider than the width of the plating layer. The ends of the additional barrier layer may extend to cover a portion of the side surface of the plating layer. The plating layer may include a first plating layer and a second plating layer disposed on the first plating layer. The side surface of the first plating layer may have a greater inclination with respect to the thickness direction of the insulating layer than the side surface of the second plating layer. [Effects of the Invention]

[0007] According to the printed circuit board of the present invention, the loss characteristics of the conductor layer can be improved. Furthermore, by including conductive posts that can improve uniformity, it can contribute to improving the performance of the printed circuit board. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram illustrating a schematic example of an electronic equipment system. [Figure 2] It is a perspective view schematically showing an example of an electronic device. [Figure 3] It is a cross-sectional view schematically showing an example of a printed circuit board. [Figure 4] It is a diagram showing an example of a method for manufacturing a printed circuit board. [Figure 5] It is a diagram showing an example of a method for manufacturing a printed circuit board. [Figure 6] It is a diagram showing an example of a method for manufacturing a printed circuit board. [Figure 7] It is a diagram showing an example of a method for manufacturing a printed circuit board. [Figure 8] It is a cross-sectional view schematically showing another example of a printed circuit board. [Figure 9] It is a diagram showing another example of a method for manufacturing a printed circuit board. [Figure 10] It is a diagram showing another example of a method for manufacturing a printed circuit board. [Figure 11] It is a cross-sectional view schematically showing another example of a printed circuit board. [Figure 12] It is a cross-sectional view schematically showing another example of a printed circuit board.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail while referring to the drawings.

[0010] However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Also, the embodiments of the present invention are provided to more fully explain the present invention to ordinary technicians. Therefore, the shapes and sizes of elements in the drawings are exaggerated for clearer explanation, and elements denoted by the same reference numerals in the drawings are the same elements.

[0011] ≪Electronic Device≫

[0012] FIG. 1 is a block diagram schematically showing an example of an electronic device system.

[0013] Referring to the drawings, the electronic device 1000 houses a main board 1010. Physical and / or electrical connections are made on the main board 1010 to chip-related components 1020, network-related components 1030, other components 1040, etc. These are also coupled to other electronic components described later to form various signal lines 1090.

[0014] Chip-related components 1020 include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory; application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller; logic chips such as an analog-digital converter, an ASIC (application-specific IC), etc., but are not limited thereto, and it goes without saying that other different forms of chip-related electronic components may be included. Also, these chip-related components 1020 may be combined with each other. The chip-related components 1020 are in a package form including the chips and electronic components described above.

[0015] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM®, GPS, GPRS, CDMA®, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It also includes any other wireless or wired standards and protocols. Needless to say, network-related component 1030 can be combined with chip-related component 1020.

[0016] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, and MLCCs (multi-layer ceramic condensers). However, they are not limited to these, and may also include other passive elements in chip component form used for various other applications. It goes without saying that other components 1040 can be combined with chip-related components 1020 and / or network-related components 1030.

[0017] Depending on the type of electronic device 1000, the electronic device 1000 may or may not include other electronic components that are physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. Needless to say, other electronic components used for various purposes may also be included, depending on the type of electronic device 1000.

[0018] Electronic devices 1000 include smartphones, personal digital assistants, digital video cameras, digital still cameras, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smartwatches, and automobiles. However, it goes without saying that electronic devices 1000 are not limited to these, and could be any other electronic device that processes data.

[0019] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0020] Referring to the drawing, the electronic device is, for example, a smartphone 1100. Inside the smartphone 1100 is a motherboard 1110, to which various components 1120 are physically and / or electrically connected. In addition, other components, such as a camera module 1130 and / or a speaker 1140, are physically and / or electrically connected to or not connected to the motherboard 1110. Some of the components 1120 are the chip-related components mentioned above, such as a component package 1121, but are not limited to these. The component package 1121 is in the form of a printed circuit board on which electronic components, including active and / or passive components, are surface-mounted. Alternatively, the component package 1121 is in the form of a printed circuit board with active and / or passive components built-in. On the other hand, it goes without saying that the electronic device is not necessarily limited to a smartphone 1100, but could be any other electronic device as mentioned above.

[0021] Printed circuit boards

[0022] Figure 3 is a schematic cross-sectional view showing an example of a printed circuit board.

[0023] Referring to Figure 3, the printed circuit board 100 according to this embodiment includes an insulating layer 101 and a conductive post 120, where the conductive post 120 is embodied in a multilayer structure. Specifically, the conductive post 120 includes a barrier layer 121, a seed layer 122, and a plating layer 123. In addition to these, the conductive post 120 further includes an additional barrier layer 124 above the plating layer 123. By providing the barrier layer 121 below the seed layer 122 and the plating layer 123, the conductive layer 111 can be protected during the etching process of the seed layer 122 and other layers, the change in surface roughness of the conductive layer 111 can be reduced, and variations in the thickness of the conductive post 120 can be minimized. The main components of the printed circuit board 100 will be described in detail below.

[0024] The insulating layer 101 contains an insulating material and is implemented in a multilayer structure. Here, the insulating material of the insulating layer 101 includes a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or materials such as inorganic fillers, organic fillers, and glass fibers (glass fiber, glass cloth, and / or glass fabric) together with such a resin. The insulating material is a photosensitive material and / or a non-photosensitive material. For example, insulating materials such as SR (Solder Resist), ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PPG (Prepreg), RCC (Resin Coated Copper), and CCL (Copper Clad Laminate) can be used, but are not limited to these, and other polymer materials can also be used.

[0025] A conductor layer 111 is arranged in the insulating layer 101. The conductor layer 111 contains a highly electrically conductive metal, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and is implemented in a multilayer structure as needed. In addition to the conductor layer 111, the insulating layer 101 further includes conductor layers, pads, conductive vias, etc., arranged at the same or different levels.

[0026] The conductive post 120 is placed on the insulating layer 101, and in this case, on the conductor layer 111 and connected to the conductor layer 111. When the conductive post 120 is placed on the insulating layer 101, it does not necessarily have to be placed on the upper surface of the insulating layer 101, and at least a portion of the conductive post 120 may be placed below the upper surface of the insulating layer 101. The conductive post 120 includes a barrier layer 121, a seed layer 122 placed on the barrier layer 121, and a plating layer 123 placed on the seed layer 122. The barrier layer 121 functions as an etching-blocking layer that protects the conductor layer 111, etc., during the etching process of the seed layer 122, etc., when forming the conductive post 120. Therefore, if the upper seed layer 122, plating layer 123, etc., is a material with different etching characteristics, for example, if the seed layer 122 and plating layer 123 contain Cu, the barrier layer 121 may contain a material such as Ni or Au. In this case, considering the possibility of etching and removing the barrier layer 121 in a subsequent process, the barrier layer 121 is realized as a layer containing Ni. The barrier layer 121 protects the conductor layer 111 during the etching process of the seed layer 122, etc., thereby reducing changes in the surface roughness of the conductor layer 111 and reducing the risk of signal loss in the conductor layer 111.

[0027] As described above, when the barrier layer 121 performs the etching prevention function, the sides of the barrier layer 121 and the sides of the seed layer 122 are discontinuous. Also, the minimum width of the barrier layer 121 is wider than the minimum width of the seed layer 122, and in this case, the seed layer 122 has its minimum width at its top. Here, the widths of the barrier layer 121, the seed layer 122, and the plating layer 123, which will be described later, are defined as the width in the direction perpendicular to the thickness direction of the insulating layer 101 (the horizontal direction relative to the drawing), and are measured from one cross-section of the printed circuit board 100. In this case, in order to improve the accuracy of the width measurement, an average value obtained from the widths of multiple cross-sections is used.

[0028] More specifically, the shape of the barrier layer 121 is described as follows: the sides of the barrier layer 121 are separated from the insulating layer 101. That is, as shown in Figure 3, the sides of the barrier layer 121 are separated from the inner surface of the insulating layer 101 facing the conductive post 120, and this structure is obtained by selectively etching a portion of the barrier layer 121. Also, the lower surface of the barrier layer 121 is located below the upper surface of the insulating layer 101. In this case, the upper surface of the barrier layer 121 is at the same level as the upper surface of the insulating layer 101, which is obtained by forming the barrier layer 121 on the conductive layer 111 before forming the seed layer 122 on the insulating layer 101.

[0029] The seed layer 122 and the plating layer 123 form the main body of the conductive post 120, and the seed layer 122 functions as a seed for forming the plating layer 123. The plating layer 123 is formed in a plating process, such as an electroplating process, using the seed layer 122 as a seed. As a specific example of the process, the plating layer 123 is formed on multiple conductive posts 120 or multiple printed circuit boards 100 by panel plating, and then individualized in an etching process. When the plating layer 123 is obtained by plating a large area in the form of panel plating, the variation in the thickness of the plating layer 123 is reduced, thereby improving the uniformity of the conductive post 120. The metal material of the seed layer 122 and the metal material of the plating layer 123 are the same, but are not limited to this, and may include different metal materials. For example, the seed layer 122 and the plating layer 123 are metal layers containing copper (Cu), but are not necessarily limited to this. As another example, the seed layer 122 may contain materials such as aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, while the plating layer 123 may contain copper (Cu). In other words, the seed layer 122 and the plating layer 123 may contain different metallic materials.

[0030] As described above, the conductive post 120 is individualized by etching the barrier layer 121 as an etching-blocking layer, and this etching process results in the sides of the seed layer 122 and the plating layer 123 having curved surfaces. Instead of etching the seed layer 122 and the plating layer 123 separately, they are etched simultaneously, in which case the sides of the seed layer 122 and the plating layer 123 are continuous. Furthermore, the plating layer 123 has a shape that narrows in width from top to bottom. Conversely, the seed layer 122 has a shape that widens in width from top to bottom.

[0031] On the other hand, an additional barrier layer 124 is provided on the plating layer 123. The additional barrier layer 124 acts as an etching mask when etching the seed layer 122 and the plating layer 123, and remains as a component of the conductive post 120 after such etching process. Considering this function, the additional barrier layer 124 contains at least one of Au, Ni, and Pt. In the case of the additional barrier layer 124, it can be modified to allow for an efficient etching process. That is, as in the modification shown in Figure 11, the width of the additional barrier layer 124 is wider than the width of the plating layer 123. Also, as in the modification shown in Figure 12, the edges of the additional barrier layer 124 extend to cover a portion of the side surface of the plating layer 123. The modifications in Figures 11 and 12 also apply to the embodiment in Figure 8.

[0032] Figures 4 to 7 show an example of a method for manufacturing a printed circuit board.

[0033] Referring to Figures 4 to 7, an example of a method for manufacturing a printed circuit board will be described, focusing on the process of forming conductive posts. First, referring to Figure 4, a conductor layer 111 and a barrier layer 121 are formed on an insulating layer 101, and a seed layer 122 is formed on top of them. In this case, the conductor layer 111 and the barrier layer 121 are formed in a form in which at least a portion is embedded in the insulating layer 101, and the barrier layer 121 is formed to have the same width as the conductor layer 111. Conductor pattern formation processes known in the art, such as SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), and subtractive processes, can be used for the conductor layer 111 and the barrier layer 121. The seed layer 122 is formed by electroless plating of Cu and is attached to the insulating layer 101 in the form of copper foil.

[0034] Next, as shown in Figure 5, a plating layer 123 is formed on the seed layer 122. As described above, the plating layer 123 is formed by panel plating on multiple conductive posts 120 or multiple printed circuit boards 100. In this case, the plating layer 123 is formed relatively thickly, and the variation in thickness can be reduced depending on the conductive posts 120. Subsequently, as shown in Figure 6, an additional barrier layer 124 is formed, and the additional barrier layer 124 acts as a mask during the subsequent etching process. In this case, the additional barrier layer 124 is selectively formed in the region corresponding to the region where the conductive posts 120 are formed. Next, as shown in Figure 7, a portion of the seed layer 122 and the plating layer 123 is removed to form conductive posts. In the etching process of the seed layer 122 and the plating layer 123, wet processes, dry processes, etc., used in the art are used, and for example, an etching solution is applied that selectively reacts with the seed layer 122 and the plating layer 123 without reacting with the barrier layers (121, 124). Next, a selective etching process is applied to remove a portion of the barrier layer 121 to realize a conductive post 120 as shown in Figure 3.

[0035] Figure 8 is a schematic cross-sectional view showing another example of a printed circuit board.

[0036] Referring to Figure 8, another example of a conductive post will be described. In the embodiment of Figure 8, the conductive post 120 includes a first plating layer 131 and a second plating layer 132, and the other components are embodied in the same form as before. The first plating layer 131 and the second plating layer 132 are formed by different plating processes. Specifically, the first plating layer 131 is formed by the panel plating process described above, and the second plating layer 132 is formed by a pattern plating process. In this case, as shown in the illustrated form, the side surface of the first plating layer 131 has a greater inclination with respect to the thickness direction of the insulating layer 101 (up and down direction relative to the drawing) than the side surface of the second plating layer 132. This difference in the inclination of the side surfaces of the first and second plating layers (131, 132) is obtained during the process in which the first plating layer 131 is selectively etched. This corresponds to the case where the first plating layer 131, formed in the form of panel plating, is etched more than the second plating layer 132.

[0037] Figures 9 and 10 show other examples of methods for manufacturing printed circuit boards.

[0038] Referring to Figures 9 and 10, another example of a method for manufacturing a printed circuit board is described, illustrating the process of forming the conductive posts shown in Figure 8. The first plating layer 131 is formed on the seed layer 122 and is formed by panel plating over, for example, multiple conductive posts 120 or multiple printed circuit boards 100. In this case, the first plating layer 131 is formed to a relatively thinner thickness compared to the process of forming the plating layer 123 in Figure 5. Subsequently, a second plating layer 132 is formed on the first plating layer 131, and the second plating layer 132 is formed in a patterned form, separated from those belonging to other conductive posts. For this purpose, the second plating layer 132 is formed by pattern plating. Then, as shown in Figure 10, the seed layer 122, the first plating layer 131, and a portion of the second plating layer 132 are removed to form the conductive posts. In the etching process of the seed layer 122, the first plating layer 131, and the second plating layer 132, wet processes, dry processes, etc., used in the art can be used. For example, an etching solution that selectively reacts with the seed layer 122, the first plating layer 131, and the second plating layer 132 without reacting with the barrier layers (121, 124) can be applied. Subsequently, a selective etching process is applied to remove a portion of the barrier layer 121 to realize a conductive post 120 as shown in Figure 8.

[0039] In this invention, "on a cross-section" refers to the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. "On a plane" refers to the shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0040] In this invention, terms such as "upper side," "upper part," and "upper surface" are used for convenience to refer to the direction toward the surface on which the electronic components are mounted, based on the cross-section of the drawing, while terms such as "lower side," "lower part," and "lower surface" are used to refer to the opposite direction. However, this is merely a definition of direction for explanatory purposes, and it goes without saying that the scope of rights in the patent claims is not particularly limited by such descriptions of direction.

[0041] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where there is a physical connection and cases where there is no connection. Moreover, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, within the scope of the rights, the first component may be named the second component, and similarly the second component may be named the first component.

[0042] The expression "example" as used in this invention does not mean the same embodiment, but is provided to highlight and illustrate different unique features. However, the presented example does not preclude its embodiment in combination with features of other examples. For example, even if a matter described in one example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that contradicts or is contrary to that description.

[0043] The terms used in this invention are used merely to illustrate an example and are not intended to limit the invention. In this context, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0044] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0045] 100 Printed Circuit Boards 101 Insulating layer 111 Conductor layer 120 conductive posts 121 Barrier layer 122 Seed Layer 123 Plating layer 124 Additional barrier layer 131 First Plating Layer 132 Second Plating Layer 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related components 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 signal line 1100 Smartphone 1110 Motherboard 1120 parts 1121 Parts Package 1130 Camera Module 1140 speaker

Claims

1. Insulating layer and, The insulating layer comprises a conductive post disposed on the insulating layer, The conductive post is characterized by including a barrier layer, a seed layer disposed on the barrier layer, and a plating layer disposed on the seed layer.

2. The printed circuit board according to claim 1, characterized in that the barrier layer contains Ni.

3. The printed circuit board according to claim 1, characterized in that the side surface of the barrier layer and the side surface of the seed layer are discontinuous.

4. The printed circuit board according to claim 1, characterized in that the minimum width of the barrier layer is wider than the minimum width of the seed layer.

5. The printed circuit board according to claim 1, characterized in that the side surface of the barrier layer is separated from the inner surface of the insulating layer facing the conductive post.

6. The printed circuit board according to claim 1, characterized in that the lower surface of the barrier layer is located below the upper surface of the insulating layer.

7. The printed circuit board according to claim 6, characterized in that the upper surface of the barrier layer is located at the same level as the upper surface of the insulating layer.

8. The printed circuit board according to claim 1, characterized in that the side surface of the seed layer and the side surface of the plating layer include a curved surface.

9. The printed circuit board according to claim 8, characterized in that the side surface of the seed layer and the side surface of the plating layer are continuous.

10. The printed circuit board according to claim 1, characterized in that the plating layer has a shape that narrows in width from top to bottom.

11. The printed circuit board according to claim 1, characterized in that the seed layer has a shape that widens from top to bottom.

12. The printed circuit board according to claim 1, further comprising an additional barrier layer disposed on the plating layer.

13. The printed circuit board according to claim 12, characterized in that the additional barrier layer includes at least one of Au, Ni, and Pt.

14. The printed circuit board according to claim 12, characterized in that the width of the additional barrier layer is wider than the width of the plating layer.

15. The printed circuit board according to claim 12, characterized in that the end of the additional barrier layer extends to cover a portion of the side surface of the plating layer.

16. The printed circuit board according to claim 1, characterized in that the plating layer includes a first plating layer and a second plating layer disposed on the first plating layer.

17. The printed circuit board according to claim 16, characterized in that the side surface of the first plating layer has a greater inclination with respect to the thickness direction of the insulating layer than the side surface of the second plating layer.

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