Imaging device and imaging method

Abstract

This suppresses the decrease in measurement accuracy due to the degree of excessive light. [Solution] The imaging device includes a pixel capable of converting an amount of charge corresponding to the amount of incident light into a voltage and outputting it as a voltage signal on a signal line, and a detection circuit that detects that overexposure has occurred when the amount of change in the potential of the voltage signal over a predetermined time range is greater than the amount of change in the potential of a reference signal that has been continuously displaced for a predetermined time range. The potential of the reference signal increases or decreases monotonically over time. The detection circuit detects that overexposure has occurred when there is a predetermined magnitude relationship between the potential of the voltage signal and the voltage of the reference signal at the end of the time range.

Description

Technical Field

[0001] The present disclosure relates to an imaging device and an imaging method.

Background Art

[0002] In an image sensor, for example, in the case of an excessive amount of light such as sunlight with a very high luminance incident thereon, pixels that would originally be white may be misjudged as black, resulting in an abnormal output called a solar black spot in the captured image.

[0003] For this reason, there is an image sensor provided with a comparison circuit that compares the potential of a vertical signal line that reads out signal charges photoelectrically converted from each imaging pixel with a predetermined threshold value to detect reception of an excessive amount of light (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] [[ID=�8]] However, there is a risk that the measurement accuracy may decrease depending on the degree of the excessive amount of light.

[0006] Therefore, the present disclosure provides an imaging device and an imaging method capable of suppressing a decrease in measurement accuracy depending on the degree of the excessive amount of light.

Means for Solving the Problems

[0007] In order to solve the above problems, according to the present disclosure, pixels capable of converting the amount of charge corresponding to the amount of incident light into a voltage and outputting it as a voltage signal to a signal line, A detection circuit that detects that an overexposure has occurred when the change in the potential of the voltage signal during a predetermined time range is greater than the change in the potential of a reference signal that has been continuously subjected to a predetermined displacement during that time range, An imaging device is provided that includes the following.

[0008] The reference signal may, within the time range, have a potential that is monotonically increasing or decreasing from the reference potential as time progresses.

[0009] The detection circuit may detect that an overexposure has occurred if, at the end of the time range, there is a predetermined magnitude relationship between the potential of the voltage signal and the voltage of the reference signal.

[0010] The aforementioned pixel is A photoelectric conversion element that generates and stores charge in response to incident light, A charge-voltage conversion unit that stores the charge generated by the photoelectric conversion element as the charge quantity and converts it into the voltage, The system includes a transfer transistor that controls the potential barrier between the photoelectric conversion element and the charge-voltage conversion unit. The voltage signal may be a signal that exceeds the potential barrier of a predetermined magnitude.

[0011] An analog-to-digital conversion unit connected to the signal line, which converts the voltage signal into a digital value, Further preparations may be necessary.

[0012] The analog-to-digital conversion unit is connected to the signal line via a first switch. The detection circuit may change the first switch from a connected state to a disconnected state when it detects that excessive light has occurred.

[0013] The detection circuit may, when it detects that the amount of light overexposure has occurred, set the input potential to the analog-to-digital conversion unit to a predetermined potential.

[0014] The detection circuit is connected such that a terminal on the input side of the analog-to-digital conversion unit and the ground potential are connected via a second switch. When the detection circuit detects that the excessive light amount has occurred, after changing the first switch to the non-connected state, the second switch may be changed from the non-connected state to the connected state.

[0015] The detection circuit may be connected to the signal line via a buffer unit.

[0016] The buffer unit has a first amplification transistor that amplifies the voltage signal, and the detection circuit may be connected to the signal line via the first amplification transistor.

[0017] The buffer unit has a second amplification transistor that amplifies the reference signal, and the detection circuit may be connected to the reference signal via the second amplification transistor.

[0018] The first amplification transistor and the second amplification transistor may be connected to a common constant current source or different constant current sources.

[0019] The detection circuit has a differential amplification unit that amplifies the voltage signal and the reference signal, and a dynamic comparator that outputs a determination signal indicating that the excessive light amount has occurred when there is a predetermined magnitude relationship between the voltage signal amplified by the differential amplification unit and the reference signal at the end point of the time range. and a logic control unit that controls the first switch and the second switch based on the determination signal. may also be included.

[0020] The amplified signal of the first amplification transistor is input to a first terminal of the differential amplification unit via a first capacitor, and the amplified signal of the second amplification transistor may be input to a second terminal of the differential amplification unit via a second capacitor.

[0021] When the detection circuit detects that the excessive light amount has occurred, the analog-to-digital conversion unit may output a predetermined value.

[0022] A signal processing unit that processes the output value of the analog-to-digital conversion unit is further provided, When the detection circuit detects that the excessive light amount has occurred, the signal processing unit may output a predetermined value.

[0023] The analog-to-digital conversion unit includes a comparator that detects the timing when the voltage signal and the second reference signal match, and a counter that counts the elapsed time until the matching timing, When the detection circuit detects that the excessive light amount has occurred, the counter may output a predetermined value.

[0024] The analog-to-digital conversion unit includes a comparator that, when detecting the timing when the voltage signal and the second reference signal match, changes the first logical value to the second logical value and outputs it, a logic gate that outputs the output value of the comparator according to the output value of the detection circuit, and a counter that counts the elapsed time until the matching timing based on the second logical value, When the detection circuit detects that the excessive light amount has occurred, the logic gate may output the first logical value.

[0025] The analog-to-digital conversion unit includes a comparator that, when detecting the timing when the voltage signal and the second reference signal match, changes the first logical value to the second logical value and outputs it, and a counter that counts the elapsed time until the matching timing based on the second logical value, [[ID=!40]]When the detection circuit detects that the excessive light amount has occurred, the comparator may output the first logical value.

[0026] To solve the above problems, according to this disclosure, the pixel performs the process of converting an amount of charge corresponding to the amount of incident light into a voltage and outputting it as a voltage signal to a signal line, A detection step in which an overexposure occurs when the change in the potential of the voltage signal during a predetermined time range is greater than the change in the potential of a reference signal that has been continuously subjected to a predetermined displacement during that time range, An imaging method is provided that includes the following features. [Brief explanation of the drawing]

[0027] [Figure 1] A block diagram showing the schematic configuration of the imaging device according to this embodiment. [Figure 2] A diagram showing an example of the internal configuration of the sunspot correction circuit, AD conversion unit, and pixels. [Figure 3] A time chart showing an example of operation when excessive light levels are not detected. [Figure 4] This is a comparative example under excessive light conditions, and the time chart shows the case when the detection circuit is stopped. [Figure 5] Figure 4 shows an example of an acquired image. [Figure 6] A time chart showing the results when the detection circuit is operated under excessive light conditions. [Figure 7] A diagram showing an example of a comparator circuit configuration. [Figure 8] A diagram showing an example of the circuit configuration of a detection circuit. [Figure 9] A time chart showing an example of operation under normal conditions. [Figure 10] A time chart showing an example of operation under excessive light conditions. [Figure 11] A time chart showing an example of processing results related to the comparative example. [Figure 12] A time chart showing an example of the processing results according to this embodiment. [Figure 13] A time chart showing an example of processing results in a comparative example without a buffer section. [Figure 14] A diagram showing an example of the circuit configuration of a detection circuit according to a modified example 1 of the first embodiment. [Figure 15] This figure shows an example of the circuit configuration of a detection circuit according to a modified example 2 of the first embodiment. [Figure 16] This figure shows an example of the circuit configuration of a detection circuit according to a modified example 3 of the first embodiment. [Figure 17] This figure shows an example of the circuit configuration of a detection circuit according to a modified example 4 of the first embodiment. [Figure 18] A time chart showing an example of normal operation according to Modification 4 of the First Embodiment. [Figure 19] A time chart showing an example of operation in an over-light condition according to Modification 4 of the First Embodiment. [Figure 20] A diagram showing an example configuration of the imaging device 1 according to the second embodiment. [Figure 21] A diagram showing an example configuration of the imaging device 1 according to the third embodiment. [Figure 22] A diagram showing an example configuration of the imaging device 1 according to the fourth embodiment. [Figure 23] A diagram showing an example configuration of the imaging device 1 according to the fifth embodiment. [Modes for carrying out the invention]

[0028] The following description will focus on the main components of the imaging device and imaging method, but there may be components and functions of the imaging device and imaging method that are not shown or described. The following description does not exclude any components or functions that are not shown or described.

[0029] (First Embodiment) Figure 1 is a block diagram showing the schematic configuration of the imaging device 1 according to this embodiment. In this specification, the imaging device 1 may be referred to as an image sensor. As shown in Figure 1, the imaging device 1 includes a pixel array unit 2, a vertical scanning circuit 3, a first reference signal (RFEslope) generation circuit 4, a sunspot correction circuit 5, a second reference signal generation circuit (DAC) 6, an AD conversion unit (SS-ADC) 7, a horizontal transfer circuit 8, and a timing control circuit 9.

[0030] The pixel array section 2 has a plurality of pixels 10 arranged in the row and column directions. Each pixel 10 can convert an amount of charge corresponding to the amount of incident light into a voltage and output it as a voltage signal Vsl on the signal line VSL. Each pixel 10 has a photoelectric conversion element that generates a charge corresponding to the amount of incident light, and a charge-voltage conversion unit that converts the accumulated charge transferred from the photoelectric conversion element into a voltage. The voltage signal converted by the charge-voltage conversion unit is output as a voltage signal Vsl on the vertical signal line VSL. Details of the pixel 10 will be described later.

[0031] The vertical scanning circuit 3 sequentially drives a plurality of row selection lines arranged in the row direction. A plurality of pixels 10, also arranged in the row direction, are connected to a single row selection line. The voltage signals photoelectrically converted by the plurality of pixels 10 connected to the driven row selection lines are input to at least one of the sunspot correction circuit 5 and the AD conversion unit 7 via a plurality of corresponding vertical signal lines VSL.

[0032] The first reference signal (RFEslope) generation circuit 4 generates a first reference signal, which is the potential that the sunspot correction circuit 5 uses as a reference for the amount of potential change. For example, the first reference signal generation circuit 4 generates a slope potential signal RFEslope as a reference signal, in which the potential from the reference potential increases monotonically or decreases monotonically as time progresses within a predetermined time range.

[0033] The sunspot correction circuit 5 corrects the digital signal based on the photoelectric conversion signal of the pixel 10 according to the amount of change in the potential of the voltage signal Vsl over a predetermined time range. For example, the sunspot correction circuit 5 corrects the digital signal according to the amount of change in the potential of the voltage signal Vsl over a predetermined time range and the amount of change in the potential of the slope potential signal RFEslope generated by the first reference signal generation circuit 4.

[0034] More specifically, the sunspot correction circuit 5 detects that overexposure has occurred when the change in the potential of the pressure signal Vsl over a predetermined time range is greater than the change in the potential of the slope potential signal RFEslope, which has a predetermined displacement maintained over that time range. When the sunspot correction circuit 5 detects that overexposure has occurred, it corrects the value of the digital signal based on the pixel 10 to, for example, a digital signal value equivalent to white. Further details of the sunspot correction circuit 5 will be described later.

[0035] The second reference signal generator (DAC) 6 generates, for example, a ramp wave signal Vramp as the second reference signal. A ramp wave signal is a signal whose voltage level changes linearly over time.

[0036] The analog-to-digital conversion unit (AD conversion unit) 7 converts the voltage signal Vsl of the vertical signal line VSL into a digital signal. The AD conversion unit 7 generates a count value according to the time it takes for the ramp wave signal Vramp and the voltage signal Vsl to match. The AD conversion unit 7 is, for example, a single-slope AD conversion unit, and generates a count value according to the time it takes for the voltage signal Vsl of the vertical signal line VSL and the ramp wave signal Vramp to match.

[0037] More specifically, the AD conversion unit 7 generates a count value as the difference between, for example, the first count value of the P phase (described later) and the second count value of the D phase. The details of the AD conversion unit 7 will also be described later.

[0038] The horizontal transfer circuit 8 controls the sequential supply of count values ​​from multiple AD conversion units 7 to the data output line. The horizontal transfer circuit 8 can supply count values ​​to the data output line when the sunspot correction circuit 5 does not perform correction processing, and can supply correction values ​​to the data output line when the sunspot correction circuit 5 performs correction processing.

[0039] The timing control circuit 9 controls the timing of the entire imaging device 1. Specifically, this timing control circuit 9 controls the timing of the pixel array unit 2, the vertical scanning circuit 3, the first reference signal (RFEslope) generation circuit 4, the sunspot correction circuit 5, the second reference signal generation circuit (DAC) 6, the AD conversion unit (SS-ADC) 7, and the horizontal transfer circuit 8.

[0040] Figure 2 shows an example of the internal configuration of the sunspot correction circuit 5, the AD conversion unit 7, and the pixel 10. First, the configuration of the pixel 10 will be explained.

[0041] As shown in Figure 2, pixel 10 includes a photoelectric conversion element PD, a transfer transistor TG, a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and a floating diffusion (charge-voltage conversion) FD. The source of the transfer transistor TG is connected to the cathode of the photoelectric conversion element PD. The transfer transistor TG, reset transistor RST, amplification transistor AMP, and selection transistor SEL are N-channel MOS (Metal Oxide Semiconductor) transistors. Hereafter, they may be referred to as "NMOS transistors." On the other hand, P-channel MOS (Metal Oxide Semiconductor) transistors may be referred to as "PMOS transistors." Note that pixel 10 is just an example and is not limited to this configuration.

[0042] The drain of the transfer transistor TG, the source of the reset transistor RST, and the gate of the amplification transistor AMP are connected to the floating diffusion FD. The drains of the reset transistor RST and the amplifier transistor AMP are connected to the power supply voltage node. The source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line VSL.

[0043] The transfer signal input to the gate of the transfer transistor TG, the reset signal input to the gate of the reset transistor RST, and the selection signal input to the gate of the selection transistor SEL are supplied from the vertical scanning circuit 3. The row selection lines in Figure 1 are more specifically divided into wiring that supplies the transfer signal, wiring that supplies the reset signal, and wiring that supplies the selection signal.

[0044] The photoelectric conversion element PD is, for example, a photodiode, which accumulates charge in proportion to the amount of incident light through photoelectric conversion. When the reset transistor RST is turned on, the charge held in the floating diffusion element FD is reset. Subsequently, when the reset transistor RST is turned off, a certain amount of charge remains in the floating diffusion element FD due to the effects of charge injection and pumping charge by the reset transistor RST. This charge is amplified by the amplification transistor AMP and supplied to the vertical signal line VSL by turning on the selection transistor SEL. The process of detecting the voltage corresponding to the remaining charge in the floating diffusion element FD is called the P phase.

[0045] In this embodiment, as the accumulated charge in the floating diffusion FD increases, the voltage supplied to the vertical signal line VSL decreases. Furthermore, the state in which the charge overflows beyond the amount of accumulated charge in the floating diffusion FD is referred to as the so-called worn-out state.

[0046] The transfer transistor TG controls the magnitude of the potential barrier between the photoelectric conversion element PD and the floating diffusion element FD. When the transfer transistor TG is turned on, the potential barrier decreases, and the signal charge accumulated in the photoelectric conversion element PD is transferred to the floating diffusion element FD. This signal charge is amplified by the amplification transistor AMP and supplied to the vertical signal line VSL by turning on the selection transistor SEL. The process of detecting a voltage corresponding to the signal charge is called the D phase.

[0047] On the other hand, when the amount of incident light increases due to the incidence of sunlight or other light on the photoelectric conversion element PD, the charge accumulated in the photoelectric conversion element PD can exceed the potential barrier of the off-state transfer transistor TG, leak into the floating diffusion element FD, and accumulate, resulting in an over-light state.

[0048] Next, the configuration of the sunspot correction circuit 5 will be described. The sunspot correction circuit 5 includes a detection circuit 40, a first switch VSLSW, and a second switch VSLGND. The detection circuit 40 detects an over-exposure state in which a predetermined amount of light is incident on the photoelectric conversion element PD for a predetermined period of time. For example, an over-exposure state occurs when sunlight or other light is incident, and is a state that can affect the measurement accuracy of the AD conversion unit 7.

[0049] When the detection circuit 40 detects an overexposure condition, it stops the first measurement operation, which is the normal measurement operation of the AD converter 7. When the detection circuit 40 detects an overexposure condition, it performs a second measurement operation to correct the measured value of the AD converter 7 to a predetermined value. This predetermined value is a value that indicates white corresponding to a predetermined luminance value or higher. For example, this white corresponds to a worn-out white (blown-out white).

[0050] Furthermore, the detection circuit 40 controls the electrical conduction and non-conduction states between the first switch VSLSW and the second switch VSLGND according to the timing control circuit 9. The first switch VSLSW and the second switch VSLGND can be composed of switching elements such as transistors. In this embodiment, the conduction state of a switching element or switch may be referred to as "on," and the non-conduction state as "off."

[0051] In the first measurement operation, the detection circuit 40 turns on the first switch VSLSW and turns off the second switch VSLGND. This allows the normal photoelectric conversion process to be executed.

[0052] On the other hand, when the detection circuit 40 detects an overexposure condition, it turns off the first switch VSLSW and then turns on the second switch VSLGND. This makes it possible to obtain measurement values ​​that address overexposure without performing measurements in a state that affects the measurement accuracy of the AD conversion unit 7.

[0053] More specifically, when the detection circuit 40 performs detection processing, it conducts the first switch VSLSW and deconducts the second switch VSLGND during the period when the transfer transistor TG is off. Subsequently, with the transfer transistor TG off, the detection circuit 40 detects the overexposure state based on the change in potential of the voltage signal Vsl over a predetermined time range and the change in potential of the slope potential signal RFEslope generated by the first reference signal generation circuit 4.

[0054] For example, the detection circuit 40 detects an overexposure state when the potential of the voltage signal Vsl and the potential of the slope potential signal RFEslop have a predetermined magnitude relationship within a predetermined time range. As described above, when the detection circuit 40 detects an overexposure state, it deactivates the first switch VSLSW and then makes the second switch VSLGND conductive to the ground potential. As a result, the ground potential is applied to the AD conversion unit 7.

[0055] Next, the configuration of the AD conversion unit 7 will be described. As shown in Figure 2, a comparator 22, a counter 23, and capacitors C1 and C2 are provided for each vertical signal line VSL extending in the column direction. Capacitors C1 and C2 are used for potential offset correction. If an over-exposure condition is not detected, the first switch VSLSW maintains a conductive state, and the switching element VSLGN maintains a non-conductive state. As a result, in the first measurement operation where an over-exposure condition is not detected, the normal AZ (auto-zero) process and the processing of the P phase and D phase are performed.

[0056] After the AZ processing of comparator 22, the ramp wave signal generated by the second reference signal generation circuit 6 is supplied via capacitor C1. In addition, the voltage signal Vsl of the vertical signal line VSL is supplied via capacitor C2.

[0057] The counter 23 performs count-up or count-down operations in synchronization with the clock signal from the timing control circuit 9.

[0058] Comparator 22 compares the voltage level of the corresponding vertical signal line VSL (Vsl) with the voltage level of the ramp wave signal Vramp and outputs an output value VCO indicating the comparison result. When the potential of the ramp wave signal Vramp is higher than that of the voltage signal Vsl, the output value VCO of comparator 22 is high. Subsequently, when the ramp wave signal decreases and falls below the VSL potential, the output value VCO of comparator 22 transitions to a low level. Note that the logic inversion of high level and low level can also be reversed. That is, when the potential falls below the VSL potential, the output value VCO of comparator 22 may transition from a low level to a high level. Further details of comparator 22 will be described later.

[0059] Next, we will explain the operation examples. Figure 3 is a time chart showing an example of operation when no overexposure condition is detected. Figure 4 is a comparative example in the overexposure condition, and is a time chart when the detection circuit 40 is stopped. Figure 5 is a diagram showing an example of the captured image in Figure 4. Figure 6 is a time chart when the detection circuit 40 is operated in the overexposure condition. In Figures 3, 4, and 6, the horizontal axis represents time, and the vertical axis represents potential. The solid line represents the voltage signal Vsl of the vertical signal line VSL, and the dashed line represents the ramp wave signal Vramp.

[0060] First, let's explain an example of operation when no overexposure condition is detected. As shown in Figure 3, the reset transistor RST is turned on between times t0 and t1, and the charge accumulated in the floating diffusion FD is discharged. Also, by turning on the selection transistor SEL at time t0, a voltage signal Vsl is supplied to the vertical signal line VSL. Subsequently, the AZ processing of the comparator 22 is completed at time t2. As a result, the voltage signal Vsl at time t2 becomes the reference potential.

[0061] Subsequently, at time t3, the P-phase ramp wave signal Vramp is supplied, and at the start of the P-phase where the voltage drop begins, the ramp wave signal Vramp is pre-set so that its potential is higher than the waveform of the P-phase potential of the voltage signal Vsl (hereinafter sometimes referred to as the VSL potential). The ramp wave signal Vramp is a signal whose voltage level decreases linearly over time.

[0062] Therefore, for a certain period of time from the start of the P phase, the ramp wave signal Vramp has a higher potential than the voltage signal Vsl, and the output value VCO of the comparator 22 is at a high level. Subsequently, as the ramp wave signal decreases and falls below the VSL potential at time t4, the output value VCO of the comparator 22 transitions to a low level.

[0063] Next, the P phase ends at time t5. The counter 23 measures the time from the start of the P phase until the logical inversion described above occurs as the first count value. Through this operation, the AD converter 7 converts the voltage amplitude of the analog voltage signal Vsl into digital time information.

[0064] Next, at time t5, the transfer transistor TG is turned on, and the stored charge of the photoelectric converter PD is transferred to the floating diffusion transistor FD. As a result, the voltage signal Vsl decreases.

[0065] Next, at time t6, the D-phase ramp signal Vramp is supplied, and at the start of the D-phase where the voltage drop begins, the ramp signal is pre-set so that its potential is higher than the D-phase potential waveform of the voltage signal Vsl. The voltage level of the ramp signal Vramp decreases linearly over time.

[0066] Therefore, for a certain period of time from the start of the P phase, the ramp wave signal Vramp has a higher potential than the voltage signal Vsl, and the output value VCO of the comparator 22 is at a high level. Subsequently, when the ramp wave signal Vramp decreases and falls below the voltage signal Vs at time t7, the output value VCO of the comparator 22 transitions to a low level.

[0067] Next, the D phase ends at time t8. The counter 23 measures the time from the start of the D phase until the aforementioned logic inversion occurs as the second count value. Through this operation, the AD converter 7 converts the voltage amplitude of the analog voltage signal Vsl into digital time information. Using the comparator 22 and the counter 23, the AD converter 7 converts the voltage signal difference Vsig on the vertical signal line into a digital signal based on the difference between the second count value and the first count value.

[0068] Next, we will explain the case when the detection circuit 40 is stopped. As shown in Figure 4, the reset transistor RST turns on between times t0 and t1, and the charge accumulated in the floating diffusion FD is discharged.

[0069] Furthermore, by turning on the selection transistor SEL at time t0, a voltage signal Vsl is supplied to the vertical signal line VSL, and the AZ processing ends at time t2. As a result, the voltage signal Vsl at time t2 becomes the reference potential. Due to the strong incident light, charge leaks from the photoelectric conversion element PD, and the voltage signal Vsl begins to decrease from the start time t1 of the AZ processing, causing the reference potential at time t2 to drop below the reference potential in Figure 3.

[0070] Subsequently, at time t3, the P-phase ramp wave signal Vramp is supplied. As described above, the voltage level of the P-phase ramp wave signal Vramp decreases linearly with time. Meanwhile, in the P-phase as well, strong incident light causes charge to leak from the photoelectric conversion element PD, and the voltage signal Vsl also continues to decrease. In the example in Figure 4, the decrease in the ramp wave signal Vramp is greater than the decrease in the voltage signal Vsl, so at time t4, the ramp wave signal Vramp falls below the voltage signal Vsl, and the output value VCO of the comparator 22 transitions to a low level.

[0071] Next, the P phase ends at time t5. The counter 23 measures the time from the start of the P phase until the logical inversion described above occurs as the first count value. Through this operation, the AD converter 7 converts the voltage amplitude of the analog voltage signal Vsl into digital time information.

[0072] Next, at time t5, the transfer transistor TG turns on, and the accumulated charge of the photoelectric converter PD is transferred to the floating diffusion FD. In the D phase as well, the strong incident light continues to generate charge in the photoelectric converter PD, causing the voltage signal Vsl to drop to a wear-out level.

[0073] Next, at time t6, the D-phase ramp signal Vramp is supplied, and the ramp signal is pre-set so that at the start of the D-phase where the voltage drop begins, the potential of the ramp signal is higher than the waveform of the D-phase potential of the voltage signal Vsl. The voltage level of the ramp signal Vramp decreases linearly over time.

[0074] Next, the D phase ends at time t8. The counter 23 measures the time from the start of the D phase until the aforementioned logic inversion occurs as the second count value. Through this operation, the AD converter 7 converts the voltage amplitude of the analog voltage signal Vsl into digital time information.

[0075] The AD conversion unit 7 uses a comparator 22 and a counter 23 to convert the voltage signal difference Vsig2 on the vertical signal line into a digital signal. Ideally, the voltage signal difference Vsig2 should be larger than the voltage signal difference Vsig because it is high brightness. However, since the voltage signal Vsl began to decrease from the start of AZ processing t1, a reversal phenomenon occurs where the voltage signal difference Vsig2 becomes smaller than the voltage signal difference Vsig.

[0076] As shown in Figure 5, a gray area appears when a reversal phenomenon occurs where the voltage signal difference Vsig2 becomes smaller than the voltage signal difference Vsig. The gray area is actually at the level of wear and tear, and should therefore be a blown-out white area.

[0077] As can be seen from the above, when excessive light occurs, the reference value for AZ processing is changed according to the degree of excessive light. Furthermore, the amount of excessive light occurring in the P phase may or may not match the P phase ramp wave signal Vramp, depending on the degree of excessive light. As a result, the magnitude of the voltage signal difference Vsig2 also fluctuates depending on the degree of excessive light.

[0078] Next, we will explain the case in which the detection circuit 40 is operated. As shown in Figure 6, this differs from Figure 4 in that the detection operation of the detection circuit 40 is performed between the start time t1 of the AZ processing and the start time t3 of the P phase.

[0079] At time t0, the reset transistor RST is turned on, causing the first switch VSLSW to conduct and the second switch VSLGND to deconduct. Subsequently, between time t1 and time t3, the first reference signal generation circuit 4 begins supplying a time-series monotonically decreasing slope potential signal RFEslope to the detection circuit 40.

[0080] The detection circuit 40 starts measuring the slope potential signal RFEslope and the voltage signal Vsl. Subsequently, the reset transistor RST is turned off at time t1, and the selection transistor SEL is turned on at time t0, supplying the voltage signal Vsl to the vertical signal line VSL. Due to the strong incident light, charge leaks from the photoelectric conversion element PD, and the voltage signal Vsl starts to decrease from time t1, the start of the AZ processing.

[0081] The AZ processing ends at time t2. As a result, the voltage signal Vsl at time t2 becomes the reference potential. Due to the strong incident light, charge leaks out from the photoelectric conversion element PD, and the voltage signal Vsl continues to decrease from the start time t1 of the AZ processing.

[0082] Next, at time t3, the P-phase ramp wave signal Vramp is supplied. Subsequently, the detection circuit 40 determines whether or not an overexposure state exists where the change in the potential of the voltage signal Vsl is greater than the change in the potential of the slope potential signal RFEslope during a predetermined period between time t1 and time 3. More specifically, the detection circuit 40 determines whether or not an overexposure state exists where the potential of the slope potential signal RFEslope and the potential of the voltage signal Vsl have a predetermined magnitude relationship at the end of the predetermined period.

[0083] If the voltage signal Vsl continues to decrease from the start time t1 of the AZ processing, and for a predetermined period the change in the voltage signal Vsl is greater than the change in the slope potential signal RFEslope, the detection circuit 40 determines that an overexposure state is occurring. As a result, the detection circuit 40 deactivates the first switch VSLSW and opens the second switch VSLGND.

[0084] Subsequently, the P-phase ramp signal Vramp decreases, and the P-phase ends at time t5. Since the logic inversion described above does not occur from the start of the P-phase to time t5, the counter 23 outputs, for example, the first count value at time t5. The AD conversion unit 7 detects that the logic inversion of the P-phase did not occur and, regardless of the second count value of the D-phase, overwrites the digital output, which is the difference between the second count value and the first count value, with a digital signal corresponding to white, for example, and terminates processing. This makes it possible to change the digital signal to a value corresponding to white. In this way, since the detection circuit 40 can detect in advance that there is an over-light condition, it is possible to suppress erroneous conversions by the AD conversion unit 7 and obtain the desired conversion value, for example, equivalent to white.

[0085] Next, the circuit configuration and operation of comparator 22 will be described. Figure 7 shows an example of the circuit configuration of comparator 22.

[0086] As shown in Figure 7, the comparator 22 is a differential amplifier circuit composed of transistors MN1 and MN2 that constitute the differential input stage, transistors MP1 and MP2 that constitute the current mirror circuit, a constant current source 25, an auto-zero switch AZSW, and capacitors C1 and C2. Transistors MN1 and MN2 are NMOS transistors, and transistors MP1 and MP2 are PMOS transistors.

[0087] In order to improve the accuracy of the comparison between the ramp wave signal Vramp and the voltage signal Vsl, it is desirable that the output value VCO of the comparator 22 be at an intermediate potential when the potential of the ramp wave signal Vramp and the potential of the voltage signal Vsl are equal.

[0088] However, in reality, due to the relative variations of transistors MN1, MN2, MP1, and MP2, as well as the influence of their DC operating points, an offset voltage is generated in the comparator 22.

[0089] As shown in Figure 1, a comparator 22 is provided for each vertical signal line VSL, i.e., for each column. However, variations in the offset voltage for each vertical signal line VSL can cause abnormalities such as vertical lines in the captured image. Therefore, the offset voltage needs to be canceled.

[0090] Therefore, in comparator 22, a reference voltage is applied to the + terminal to which the ramp wave signal Vramp is input, and the P-phase potential is applied to the - terminal to which the voltage signal Vsl is input, and the auto-zero switch AZSW is turned on.

[0091] As a result, a voltage equal to the gate-source voltage Vgs of transistor MP1 is applied to the terminal of capacitor C1 on the side of transistor MN1, while a reference voltage is applied to the other terminal of capacitor C1. Capacitor C1 then maintains the potential difference between its two terminals. Furthermore, negative feedback is applied to the gate of transistor MN2 so that the drain current of transistor MP2 and the drain current of transistor MN2 are equal.

[0092] The gate voltage of transistor MN2, due to the negative feedback described above, becomes a potential where the offset voltage that remains and is not canceled by the negative feedback of the differential amplifier circuit is superimposed on the gate voltage of transistor MN1. This potential is applied to the terminal of capacitor C2 on the side of transistor MN2, and the P-phase potential is applied to the other terminal. Capacitor C2 maintains the potential difference between its two terminals.

[0093] When the auto-zero switch AZSW is turned off in this state, a voltage corresponding to the variation from the reference potential of the ramp wave signal is applied to the gate of transistor MN1 via capacitor C1. On the other hand, on the vertical signal line VSL side, a voltage obtained by subtracting the offset voltage from the P-phase potential is applied to the gate of transistor MN2, thereby canceling out the offset voltage of the differential amplifier circuit. This operation is called the auto-zero process (hereinafter referred to as AZ process) of comparator 22.

[0094] Furthermore, comparator 22 performs AZ processing at the P-phase potential and then compares it with the D-phase potential. In other words, comparator 22 applies the potential difference between the P-phase and D-phase to the gate of transistor MN2, thereby also performing CDS (Cardio-Slope Differential), which is the P-phase potential minus the D-phase potential. This series of operations—AZ processing, AD conversion, and CDS—is a function called single-slope ADC.

[0095] Next, the circuit configuration and operation of the detection circuit 40 will be described. Figure 8 shows an example of the circuit configuration of the detection circuit 40.

[0096] As shown in Figure 8, the detection circuit 40 includes a buffer section 42, a differential amplifier section 44, a dynamic comparator 46, and a logic control section 48. The buffer section 42 includes transistors MN3 and MN4, and a constant current source 50. Transistors MN3 and MN4 are NMOS transistors.

[0097] The source of transistor MN3 is connected to the VDD voltage line, and its drain node is connected to the source of transistor MN4 and one end of capacitor C1. The drain node of transistor MN4 is connected to the constant current source 50 and one end of capacitor C2.

[0098] The gate of transistor MN3 is connected to the vertical signal line VSL, which supplies the voltage signal Vsl. The gate of transistor MN4 is connected to the output signal line of the first reference signal generation circuit 4, which supplies the slope potential signal RFEslope. Transistors MN3 and MN4 are source followers.

[0099] The current flowing through transistors MN3 and MN4 is constant, and the source output voltage changes depending on the voltage applied to the gate. In other words, transistors MN3 and MN4 act as amplifier circuits for the voltage signal Vsl and the slope potential signal RFEslope, respectively.

[0100] As can be seen, when the potential of the voltage signal Vsl decreases, the potential of the source node of transistor MN3 decreases. Similarly, when the potential of the slope potential signal RFEslope decreases, the potential of the source node of transistor MN4 decreases. In this way, the detection circuit 40 is connected to the vertical signal line VSL and the output signal line of the first reference signal generation circuit 4 via the buffer unit 42. This suppresses the effect of parasitic RC. Therefore, compared to the case where the differential amplifier unit 44 is directly connected to the vertical signal line VSL and the output signal line, the occurrence of kickback due to the release of the switch in the differential amplifier unit 44 is suppressed.

[0101] The differential amplifier 44 has a circuit configuration equivalent to that of the comparator 22. In the differential amplifier 44, a reference voltage is applied to the terminal to which the slope potential signal RFEslope is input, and the switch CLK1 is turned on while the P-phase potential is applied to the terminal to which the voltage signal Vsl is input.

[0102] As a result, a voltage obtained by dropping the power supply voltage VDD by the gate-source voltage Vgs of transistor MP2 is applied to the terminal of capacitor C2 on the transistor MN2 side, and a reference voltage is applied to the other terminal of capacitor C2. Capacitor C2 then maintains the potential difference between its two terminals. Furthermore, negative feedback is applied to the gate of transistor MN1 so that the drain current of transistor MP1 and the drain current of transistor MN1 are equal.

[0103] The gate voltage of transistor MN1 becomes a potential where the offset voltage that remains and is not canceled by the negative feedback of the differential amplifier circuit is superimposed on the gate voltage of transistor MN1 due to the negative feedback described above. This potential is applied to the terminal of capacitor C1 on the side of transistor MN1, and the P-phase potential is applied to the other terminal. Capacitor C1 maintains the potential difference between its two terminals.

[0104] In this state, when the clock switch CLK1 is turned off, a voltage corresponding to the variation of the slope potential signal RFEslope from the reference potential is applied to the gate of transistor MN2 via capacitor C2. On the other hand, on the vertical signal line VSL side, a voltage obtained by subtracting the offset voltage from the P-phase potential is applied to the gate of transistor MN1, thereby canceling out the offset voltage of the differential amplifier circuit. This operation is called the auto-zero process of the differential amplifier section 44.

[0105] The INp terminal of the dynamic comparator 46 is connected to the connection node on the transistor MN1 side in the differential amplifier section 44, and the INn terminal is connected to the connection node on the transistor MN2 side in the differential amplifier section 44. The potential INP of the connection node on the transistor MN1 side is supplied to the INp terminal. The potential INP of the connection node on the transistor MN2 side is supplied to the INn terminal.

[0106] The dynamic comparator 46 is a circuit that determines the relative magnitudes of two input signals at the rising edge timing of the clock signal CLK2 without applying a steady-state bias current. For example, when the clock signal CLK2 changes from a low level to a high level, it compares the potential INP based on the voltage signal Vsl on the INp terminal side with the potential INN based on the slope potential signal RFEslope on the INN terminal side.

[0107] In other words, the dynamic comparator 46 transitions the output signal OUT from a low level to a high level when the potential INP based on the voltage signal Vsl and the potential INN based on the slope potential signal RFEslope have a predetermined magnitude relationship, indicating an overexposure state. More specifically, the dynamic comparator 46 outputs an output signal OUT indicating that overexposure has occurred when the change in the potential of the voltage signal is greater than the change in the potential of the reference signal after the elapsed time range. In this embodiment, when the dynamic comparator 46 detects that overexposure has occurred, the dynamic comparator 46 transitions the output signal OUT from a low level to a high level.

[0108] The logic control unit 48 includes a logic negation circuit (inverter) 54, a logic AND circuit (AND) 56, and a logic OR circuit (OR) 58. The output terminal of the dynamic comparator 46 is connected to the input terminal of the logic negation circuit 54 and to one of the input terminals of the logic AND circuit 56.

[0109] The other input terminal of the AND circuit 56 is supplied with the control signal VSLGNDtime from the timing control circuit 9 (see Figure 1). The output terminal of the AND circuit 56 is connected to the switching element VSLGND (see Figure 2) and outputs the control signal ToVSLGND.

[0110] The output terminal of the logic negation circuit 54 is connected to one input terminal of the logic OR circuit 58. The other input terminal of the logic OR circuit 58 is supplied with the control signal VSLSWtime from the timing control circuit 9. The output terminal of the logic OR circuit 58 is connected to the first switch VSLSW and outputs the control signal ToVSLSW.

[0111] As can be seen from the above, the logic control unit 48 conducts the first switch VSLSW (see Figure 2) when the output signal OUT is at a low level (not in an over-illumination state) or when the control signal VSLSWtime is at a high level. On the other hand, the logic control unit 48 deconducts the first switch VSLSW when the output signal OUT is at a high level (not in an over-illumination state) AND the control signal VSLSWtime is at a low level. In other words, when there is no over-illumination state, the conduction state of the first switch VSLSW is controlled by the control signal VSLSWtime.

[0112] Furthermore, the logic control unit 48 conducts the switch VSLSGND (see Figure 2) when the output signal OUT is at a high level (overexposure state) and the control signal VSLGNDtime is at a high level. On the other hand, the logic control unit 48 deconducts the switch VSLSGND when the output signal OUT is at a low level (not overexposure state) or when the control signal VSLGNDtime is at a low level. In other words, when overexposure is present, the conduction state of the switch VSLGND is controlled by the control signal VSLGNDtime.

[0113] Here, with reference to Figures 2, 7, and 8, and using Figures 9 and 10, detailed operation examples of the comparator 22 and the detection circuit 40 will be explained. Figure 9 is a time chart showing an example of operation under normal conditions. Figure 10 is a time chart showing an example of operation under excessive light conditions. The horizontal axis represents time. The vertical axis represents the voltage signal Vsl, the ramp signal Vramp, the control signal AZ of the comparator 22 switch AZSW, the slope potential signal REFslope of the first reference signal generation circuit 4, the control signal AZ2 of the switch CLK1, the clock signal CLK2 of the dynamic comparator 46, the output signal INP to the INp terminal of the dynamic comparator 46, the output signal INN to the INN terminal, the control signal VSLSWtime, the control signal VSLGNDtime, the control signal ToVSLSW, and the control signal ToVSLGND. In this embodiment, the upper side of the page represents the high-level signal, and the lower side represents the low-level signal. Alternatively, the high-level and low-level signals of each signal may be inverted.

[0114] First, let's explain an example of operation when no overexposure condition is detected. As shown in Figure 9, at time t0, the reset transistor RST turns on. The control signals AZ, AZ2, and ToVSLSW, which control the switching operation, are at a high level, and ToVSGND is at a low level. That is, at time t0, switches AZSW, CK1, and the first switch VSLSW are on, and switch VSGND is off.

[0115] Between time points t0 and t1, the reset transistor RST is turned on, and the charge accumulated in the floating diffusion FD is discharged. Also, at time point t0, the selection transistor SEL is turned on, supplying a voltage signal Vsl to the vertical signal line VSL.

[0116] Next, at time t11, the slope potential signal REFslope begins to decrease in potential. At time t12, switch CLK1 is turned off, the AZ processing of the differential amplifier 44 is completed, and the detection time range of the detection circuit 40 begins. As a result, the output voltage INN to terminal INn of the differential amplifier 44 begins to decrease in accordance with the decrease in potential of the slope potential signal REFslope. On the other hand, since there is no change in the voltage signal Vsl, the output voltage INP to terminal INp increases slightly.

[0117] Next, at time t2, switch AZSW is turned off, and the AZ processing of comparator 22 ends. As a result, the voltage signal Vsl at time t2 becomes the reference potential.

[0118] Next, at time t3, the P-phase ramp wave signal Vramp is supplied. Then, at time t31, the clock signal CLK2 becomes high, ending the time range of the detection circuit 40, and the dynamic comparator 46 performs the comparison process. At this time, since the potential of the slope potential signal REFslope is smaller, the output signal OUT of the dynamic comparator 46 remains at a low level.

[0119] At time t32, the control signal VSLSWtime becomes low, but the output signal OUT remains low, so the first switch VSLSW remains ON. At time t33, the control signal VSLGNDtime becomes high, but the output signal OUT remains low, so the second switch VSLGND remains OFF.

[0120] Subsequently, at time t34, the P-phase ramp wave signal Vramp begins to decline. After that, the ramp wave signal Vramp decreases further, and when it falls below the VSL potential at time t4, the output value VCO of comparator 22 transitions to a low level.

[0121] Subsequently, at time t5, the P phase ends, and the control signal VSLGNDtime becomes low, but the output signal OUT remains at a low level, so the second switch VSLGND remains in the off state. The counter 23 measures the time from the start of the P phase t3 to time t4, when the logic inversion described above occurs, as the first count value. Through this operation, the AD converter 7 converts the voltage amplitude of the analog voltage signal Vsl into digital time information.

[0122] Next, at time t51, the control signal VSLSWtime becomes high, but the output signal OUT remains low, so the switch VSLS remains ON. Also at time t51, the slope potential signal REFslope returns to the reference potential, the transfer transistor TG turns ON, and the stored charge of the photoelectric conversion element PD is transferred to the floating diffusion element FD. As a result, the voltage signal Vsl begins to decrease. Subsequently, at time t52, the clock signal CLK2 becomes low, and the dynamic comparator 46 terminates its comparison process.

[0123] Next, at time t6, the D-phase ramp wave signal Vramp is supplied, and the voltage drop begins. When it falls below the voltage signal Vsl at time t7, the output value VCO of comparator 22 transitions to a low level.

[0124] Next, the D phase ends at time t8. The counter 23 measures the time t7 from the start of the D phase t6 until the aforementioned logic inversion occurs as the second count value. The AD conversion unit 7 converts the voltage amplitude of the analog signal voltage signal difference Vsig into digital signal time information based on the difference between the second count value and the first count value. In this way, since the change in potential of the voltage signal Vsl is within a predetermined reference value during the period t2 to t32, which is a predetermined time range of the detection circuit 40, the normal first measurement operation is performed.

[0125] Next, we will describe an example of operation when an overexposure state is detected by the amount of overexposure. As shown in Figure 10, the control operation up to time t11 is the same as in Figure 9, but differs from Figure 9 in that the voltage signal Vsl starts to decrease from time t1 due to the amount of overexposure. The following describes the operation after time t11 that differs from Figure 9.

[0126] At time t11, the slope potential signal REFslope begins to decrease in potential. At time t12, switch CK1 is turned off, the AZ processing of the differential amplifier 44 is completed, and the detection time of the detection circuit 40 begins. The voltage signal Vsl continues to decrease in potential at a larger rate from time t1 to time t31 when the detection time ends.

[0127] Referring again to Figure 8, the decrease in the source potential of transistor MN3 due to the decrease in the voltage signal Vsl is greater than the decrease in the source potential of transistor MN4 due to the decrease in the rope potential signal REFslope. Therefore, the output voltage INP to terminal INp increases over time, and the output voltage INN to terminal INn decreases over time.

[0128] As a result, the output voltage INN to terminal INn of the differential amplifier 44 begins to decrease in accordance with the decrease in the potential of the slope potential signal REFslope. On the other hand, the output voltage INP to terminal INp begins to increase due to the amount of overexposure, in accordance with the decrease in the potential of the voltage signal Vsl, which is larger than the decrease in the potential of the slope potential signal REFslope.

[0129] Next, at time t2, switch AZSW is turned off, and the AZ processing of comparator 22 ends. As a result, the voltage signal Vsl at time t2 becomes the reference potential.

[0130] Next, at time t3, the P-phase ramp wave signal Vramp is supplied. Then, at time t31, the clock signal CLK2 becomes high, ending the time range of the detection circuit 40, and the dynamic comparator 46 performs the comparison process. At this time, a predetermined relationship is satisfied in which the output voltage INP to terminal INp is greater than the output voltage INN to terminal INn, so the output signal OUT of the dynamic comparator 46 transitions from a low level to a high level.

[0131] At time t32, the control signal VSLSWtime becomes low, and the output signal OUT remains high, so the first switch VSLSW changes from the ON state to the OFF state. At time t33, the control signal VSLGNDtime becomes high, but the output signal OUT remains high, so the second switch VSLGND changes from the OFF state to the ON state.

[0132] Subsequently, at time t34, the P-phase ramp wave signal Vramp begins to decrease. Although the ramp wave signal decreases, the ground potential is applied to the transistor MN3 of the detection circuit 40 as a voltage signal Vsl, so the output value OUT of the comparator 22 remains high without falling below the potential of the voltage signal Vsl.

[0133] Subsequently, at time t5, the P phase ends, the control signal VSLGNDtime becomes low, and the second switch VSLGND changes from the ON state to the OFF state. The counter 23 measures the time from time t31, when the P phase starts, to time t5, when the P phase ends, as the first count value. Through this operation, the AD converter 7 converts the voltage amplitude of the voltage signal Vsl into time information, using the time up to time t5 as the first count value. In this case, the first count value represents the maximum value.

[0134] Next, at time t51, the control signal VSLSWtime becomes high, and the first switch VSLSW changes from the off state to the on state. Also at time t51, the slope potential signal REFslope returns to the reference potential, the transfer transistor TG turns on, and the stored charge of the photoelectric conversion element PD is transferred to the floating diffusion element FD. As a result, the voltage signal Vsl begins to decrease and reaches the wear level due to the amount of light.

[0135] Next, at time t6, the D-phase ramp wave signal Vramp is supplied, and the voltage drop begins. When it falls below the wear-out level voltage signal Vsl at time t7a, the output value VCO of comparator 22 transitions to a low level.

[0136] Next, the D phase ends at time t8. The counter 23 measures the time t7a from the start of the D phase t6 until the logical inversion due to the wear-out level potential described above occurs as the second count value. Through this operation, the AD converter 7 converts the voltage amplitude of the analog signal Vsl into time information, which is the D phase digital signal.

[0137] Next, the D phase ends at time t8. The counter 23 measures the time t7a from the start time t6 of the D phase until the logical inversion described above occurs as the second count value. When the first count value reaches its maximum value, the AD conversion unit 7 overwrites the difference between the second count value and the first count value with a digital value equivalent to white.

[0138] Thus, the change in the voltage signal Vsl during the predetermined time range t12 to t31 of the detection circuit 40 becomes greater than the change in the slope potential signal REFslope, and the second measurement operation is performed. This makes it possible to obtain a digital value equivalent to white even in the case of excessive light. The change in the slope potential signal REFslope can be set according to the level of excessive light required for the purpose. For example, as the amount of excessive light to be detected decreases, the change in the slope potential signal REFslope can be made smaller.

[0139] Figure 11 is a time chart showing an example of processing results for a comparative example. This is an example in which the first reference signal (RFEslope) generation circuit 4 for the comparative example outputs a step-shaped reference potential signal REFstep.

[0140] In Figure 11, the horizontal axis represents time, and the vertical axis, from top to bottom, shows the control signal AZ of the comparator 22 switch AZSW, the voltage signal Vsl, the reference potential signal REFstep, and the potential INP based on the voltage signal Vsl.

[0141] At this time, the potential INP based on the voltage signal Vsl should transition to the high level side at time tc, but an inversion delay occurs due to the influence of parasitic capacitance in the differential amplifier 44. If this inversion delay coincides with the timing when the clock signal CLK2 changes from a low level to a high level, a judgment error may occur.

[0142] Figure 12 is a time chart showing an example of the processing result according to this embodiment. This is an example in which the first reference signal (RFEslope) generation circuit 4 outputs a slope-shaped slope potential signal REFslope. The horizontal axis represents time, and the vertical axis, from top to bottom, shows the control signal AZ of the comparator 22 switch AZSW, the voltage signal Vsl, the slope potential signal REFslope, and the potential INP based on the voltage signal Vsl.

[0143] As shown in Figure 12, the potential INP based on the voltage signal Vsl is always on the high level side. Similarly, the potential INN based on the reference potential signal REFstep (not shown) is always on the low level side. In this way, because a slope-shaped slope potential signal REFslope is used, no inversion delay occurs. Therefore, the timing at which the clock signal CLK2 changes from a low level to a high level cannot coincide with the inversion delay, thus suppressing a decrease in the detection accuracy of the overexposure state in the detection circuit 40.

[0144] Figure 13 is a time chart showing an example of processing results in a comparative example that does not have a buffer unit 42. In the differential amplifier unit 44 of the comparative example (see Figure 8), the electric summer signal Vsl is input to capacitor C1 and the electric summer signal Vsl is input to capacitor C2.

[0145] Figure 13 shows time on the horizontal axis and the control signal AZ2, voltage signal Vsl, and slope potential signal REFslope of switch CK1 on the vertical axis, from top to bottom. As shown in Figure 13, so-called kickback occurs at the timing when switch CK1 changes from on to off. Kickback occurs due to the presence of parasitic RC, and therefore takes time to settle. For this reason, insufficient settling can lead to judgment errors. In contrast, the detection circuit 40 according to this embodiment has a buffer section 42, so such kickback is suppressed and the decrease in detection accuracy of the overexposure state is suppressed.

[0146] As described above, according to this embodiment, the pixel 10 converts the amount of charge corresponding to the amount of incident light into a voltage and outputs it as a voltage signal Vsl to the signal line VSL, and the detection circuit 40 detects the amount of change in the voltage signal Vsl that has changed within a predetermined time range. Since the amount of overexposure corresponds to the amount of change in the voltage signal Vsl within a predetermined time range, it becomes possible to determine the amount of overexposure more accurately regardless of the intensity of the overexposure.

[0147] (Modification 1 of the first embodiment) The imaging device 1 according to Modification 1 of the First Embodiment differs from the imaging device 1 according to the First Embodiment in that the logic control unit 48 of the detection circuit 40 is further capable of test operation between the first switch VSLSW and the second switch VSLGND using a TEST signal. The differences from the imaging device 1 according to the First Embodiment will be described below.

[0148] Figure 14 shows an example of the circuit configuration of the detection circuit 40 according to Modification 1 of the first embodiment. As shown in Figure 11, the logic control unit 48 further has a logical OR circuit 60. This logical OR circuit 60 is used for testing the operation of the first switch VSLSW and the second switch VSLGND.

[0149] One input terminal of the OR circuit 60 is connected to the output terminal of the dynamic comparator 46, and the other input terminal is connected to the timing control circuit 9. The output terminal of the OR circuit 60 is connected to the input terminal of the negation circuit 54.

[0150] The timing control circuit 9 supplies a high-level or low-level TEST signal to the other input terminal of the OR circuit 60. As shown in Figures 9 and 10, by setting the TEST signal to a low level during the period from time t0 to time t31, to a high level during the period from time t31 to time t52, and to a low level during the period from time t52 to time t8, the operation of the first switch VSLSW and the second switch VSLGND in the case of excessive light intensity can be tested.

[0151] Similarly, as shown in Figures 9 and 10, by setting the TEST signal to a low level during the period from time t0 to time t8, the operation of the first switch VSLSW and the second switch VSLGND in the absence of excessive light can be tested.

[0152] (Modification 2 of the first embodiment) The imaging device 1 according to Modification 2 of the First Embodiment differs from the imaging device 1 according to the First Embodiment in that the transistors MN3 and MN4 of the buffer unit 42 each have a constant current source. The differences from the imaging device 1 according to the First Embodiment will be described below.

[0153] Figure 15 shows an example of the circuit configuration of the detection circuit 40 according to a modified example 2 of the first embodiment. As shown in Figure 12, transistors MN3 and MN4 of the buffer section 42 each have constant current sources 50 and 52. This makes it possible to independently balance the voltages of transistors MN3 and MN4.

[0154] (Modification 3 of the first embodiment) The imaging device 1 according to Modification 3 of the First Embodiment differs from the imaging device 1 according to the First Embodiment in that the differential amplifier 44 has a differential voltage difference between the voltage signal Vsl and the slope potential signal RFEslope input to one end and a ground potential input to the other end. The differences from the imaging device 1 according to the First Embodiment will be described below.

[0155] Figure 16 shows an example of the circuit configuration of the detection circuit 40 according to Modification 3 of the First Embodiment. As shown in Figure 13, it differs from the differential amplifier 44 according to the First Embodiment in that the drain node of transistor MN4 is connected to the gate node of transistor MN1 of the differential amplifier 44 via capacitor C3. It also differs from the differential amplifier 44 according to the First Embodiment in that the other end of capacitor C2 is at ground potential.

[0156] The potential signal RFEslope is inverted and then added to the voltage signal Vsl to form an added signal. This added signal fluctuates over time, and the potential difference with the low-potential ground potential increases over time. In this way, it is also possible to compare the potentials by setting the reference potential to a low potential.

[0157] (Modification 4 of the first embodiment) The imaging device 1 according to Modification 4 of the First Embodiment differs from the imaging device 1 according to the First Embodiment in that the constant current source 50 and the constant current source 25 in the detection circuit 40 are connected via a switch. The differences from the imaging device 1 according to the First Embodiment will be described below.

[0158] Figure 17 shows an example of the circuit configuration of the detection circuit 40 according to modification 4 of the first embodiment. As shown in Figure 17, the constant current source 50 and transistor MN4 in the buffer section 42 are connected via switch 50a. Also, the constant current source 25 and transistors MN1 and MN2 in the differential amplifier section 44 are connected via switch 52a.

[0159] Figure 18 is a time chart showing an example of normal operation according to Modification 4 of the First Embodiment. A control signal Sp that turns on switches 50a and 52a is added to the same time chart as in Figure 9. Figure 19 is a time chart showing an example of operation in an over-light state according to Modification 4 of the First Embodiment. A control signal Sp that turns on switches 50a and 52a is added to the same time chart as in Figure 10.

[0160] The horizontal axis represents time. The vertical axis represents the voltage signal Vsl, the ramp signal Vramp, the control signal AZ of the switch AZSW of comparator 22, the slope potential signal REFslope of the first reference signal generation circuit 4, the control signal AZ2 of the switch CK1, the clock signal CLK2 of the dynamic comparator 46, the output signal INP to the INp terminal of the dynamic comparator 46, the output signal INN to the INN terminal, the control signals VSLSWtime, VSLGNDtime, ToVSLSW, ToVSGND, and Sp.

[0161] As shown in Figures 18 and 19, the control signals AZ and AZ2 reach a high level before they reach a low level, and the clock signal CLK2 reaches a low level before it reaches a low level. In this way, it is possible to limit the current from the constant current sources 25 and 50 to the time range required to drive the buffer section 42 and the differential amplifier section 44. This makes it possible to suppress the power consumption of the detection circuit 40.

[0162] (Second Embodiment) The imaging device 1 according to the second embodiment differs from the imaging device 1 according to the first embodiment in that the detection circuit 40 controls the output value of the signal processing unit. The differences from the imaging device 1 according to the first embodiment will be described below.

[0163] Figure 20 shows an example of the configuration of the imaging device 1 according to the second embodiment. The imaging device 1 according to the second embodiment further includes a signal processing logic block 70 that processes the output value of the AD conversion unit 7a. The signal processing logic block 70 performs image processing such as noise suppression on the output value of the AD conversion unit 7a. In this embodiment, the signal processing logic block 70 corresponds to the signal processing unit.

[0164] As shown in Figure 20, when the detection circuit 40 detects excessive light, it executes a process in the signal processing logic block 70 to rewrite the output value of the pixel where the excessive light occurred to a value equivalent to white. Since the detection circuit 40 has a buffer unit 42, it is possible to detect excessive light while suppressing the impact on the AD conversion unit 7. In this way, by controlling the output value of the AD conversion unit 7a to a value equivalent to white, it is possible to obtain a pixel value equivalent to white even when excessive light occurs.

[0165] (Third embodiment) The imaging device 1 according to the third embodiment differs from the imaging device 1 according to the first embodiment in that the detection circuit 40 controls the output value of the counter 23 when it detects that excessive light is occurring. The differences from the imaging device 1 according to the first embodiment will be described below.

[0166] Figure 21 shows an example of the configuration of the imaging device 1 according to the third embodiment. Since the detection circuit 40 has a buffer unit 42, it is possible to detect the amount of overexposure while suppressing the influence on the AD conversion unit 7. Furthermore, when the detection circuit 40 detects an amount of overexposure, it controls the counter value of the counter 23 to a value equivalent to the target white. In this way, by controlling the counter value to a value equivalent to the target white, the detection circuit 40 can control the output value of the AD conversion unit 7 to a value equivalent to the target white even when an amount of overexposure occurs.

[0167] (Fourth Embodiment) The imaging device 1 according to the fourth embodiment differs from the imaging device 1 according to the first embodiment in that the AD conversion unit 7 further has a logic gate 24, and when it detects that excessive light is occurring, the detection circuit 40 controls the output value of the logic gate 24. The differences from the imaging device 1 according to the first embodiment will be described below.

[0168] Figure 22 shows an example of the configuration of the imaging device 1 according to the fourth embodiment. The AD conversion unit 7 includes a logic gate 24 that takes the output signal of the comparator 22 as input and outputs a logic signal to the counter 23.

[0169] As described above, the output value VCO of comparator 22 is high when the potential of the ramp wave signal Vramp is higher than that of the voltage signal Vsl. Subsequently, when the ramp wave signal decreases and falls below the VSL potential, the output value VCO of comparator 22 transitions to a low level.

[0170] If the detection circuit 40 does not detect excessive light, the logic gate 24 outputs a logic signal to the counter 23 that holds the value of the output value VCO. On the other hand, if the detection circuit 40 detects excessive light, the logic gate 24 maintains the logic signal at a high level. This makes it possible to achieve a state equivalent to when the ramp wave signal Vramp and the voltage signal Vsl do not cross in the P phase. In this way, by controlling the logic gate 24, the detection circuit 40 controls the value of the output value VCO to the desired value, thereby enabling the output value of the AD converter 7 to be controlled to a value equivalent to the desired white light, even when excessive light occurs.

[0171] (Fifth embodiment) The imaging device 1 according to the fifth embodiment differs from the imaging device 1 according to the first embodiment in that the detection circuit 40 performs control to fix the signal line inside the comparator 22 to a specific voltage when it detects that excessive light is occurring. The differences from the imaging device 1 according to the first embodiment will be described below.

[0172] Figure 23 shows an example of the configuration of the imaging device 1 according to the fifth embodiment. When the detection circuit 40 detects that light is present, it performs control to fix the signal line inside the comparator 22 to a specific voltage. This makes it possible to control the P-phase so that the ramp wave signal Vramp and the voltage signal Vsl do not cross. This makes it possible to control the output value of the AD conversion unit 7 to a value equivalent to the desired white, even when excessive light occurs. Alternatively, instead of controlling the P-phase so that the ramp wave signal Vramp and the voltage signal Vsl do not cross, it is also possible to control the CDS result to be white by forcibly setting the P-phase count to 0 and forcibly setting the D-phase count to a full count.

[0173] Furthermore, this technology can take the following configuration.

[0174] (1) A pixel capable of converting an amount of charge corresponding to the amount of incident light into a voltage and outputting it as a voltage signal on a signal line, A detection circuit that detects that an overexposure has occurred when the change in the potential of the voltage signal during a predetermined time range is greater than the change in the potential of a reference signal that has been continuously subjected to a predetermined displacement during that time range, An imaging device equipped with the following features.

[0175] (2) The imaging apparatus according to (1), wherein the reference signal has a potential that increases monotonically or decreases monotonically from a reference potential over time within the time range.

[0176] (3) The imaging apparatus according to (2), wherein the detection circuit detects that an overexposure has occurred when there is a predetermined magnitude relationship between the potential of the voltage signal and the voltage of the reference signal at the end of the time range.

[0177] (4) The aforementioned pixel is A photoelectric conversion element that generates and stores charge in response to incident light, A charge-voltage conversion unit that stores the charge generated by the photoelectric conversion element as the charge quantity and converts it into the voltage, The system includes a transfer transistor that controls the potential barrier between the photoelectric conversion element and the charge-voltage conversion unit, The imaging apparatus according to (3), wherein the voltage signal is a signal when the voltage exceeds a potential barrier of a predetermined magnitude.

[0178] (5) An analog-to-digital conversion unit connected to the signal line, which converts the voltage signal into a digital value, The imaging device described in (3) is further provided.

[0179] (6) The analog-to-digital conversion unit is connected to the signal line via a first switch. The imaging apparatus according to (5), wherein the detection circuit changes the first switch from a connected state to a disconnected state when it detects that an overexposure has occurred.

[0180] (7) The imaging apparatus according to (6), wherein the detection circuit, when it detects that the amount of light overexposure has occurred, sets the input potential to the analog-to-digital conversion unit to a predetermined potential.

[0181] (8) The detection circuit is configured such that the input terminal of the analog-to-digital conversion unit is connected to the ground potential via a second switch. The imaging apparatus according to (7), wherein the detection circuit, upon detecting that the amount of light overexposure has occurred, changes the first switch to the disconnected state, and then changes the second switch from the disconnected state to the connected state.

[0182] (9) The imaging apparatus according to (8), wherein the detection circuit is connected to the signal line via a buffer unit.

[0183] (10) The imaging apparatus according to (9), wherein the buffer unit has a first amplification transistor for amplifying the voltage signal, and the detection circuit is connected to the signal line via the first amplification transistor.

[0184] (11) The imaging apparatus according to (10), wherein the buffer unit has a second amplification transistor for amplifying the reference signal, and the detection circuit is connected to the reference signal via the second amplification transistor.

[0185] (12) The imaging apparatus according to (11), wherein the first amplification transistor and the second amplification transistor are connected to a common constant current source or to different constant current sources.

[0186] (13) The detection circuit is A differential amplifier unit that amplifies the voltage signal and the reference signal, A dynamic comparator that outputs a determination signal indicating that the amount of overexposure has occurred when the voltage signal amplified by the differential amplifier and the reference signal have a predetermined magnitude relationship at the end of the time range, A logic control unit controls the first switch and the second switch based on the determination signal, The imaging apparatus according to (12), having the following:

[0187] (14) The amplified signal from the first amplification transistor is input to the first terminal of the differential amplifier section via the first capacitor. The imaging apparatus according to (13), wherein the amplified signal of the second amplification transistor is input to the second terminal of the differential amplifier via the second capacitor.

[0188] (15) The imaging apparatus according to (5), wherein the analog-to-digital conversion unit outputs a predetermined value when the detection circuit detects that the amount of light overexposure has occurred.

[0189] (16) The signal processing unit that processes the output value of the analog-to-digital conversion unit is provided as follows: Furthermore, The imaging apparatus according to (5), wherein the signal processing unit outputs a predetermined value when the detection circuit detects that the amount of light overexposure has occurred.

[0190] (17) The aforementioned analog-to-digital conversion unit is A comparator that detects the timing at which the voltage signal and the second reference signal coincide, The system includes a counter that counts the elapsed time until the aforementioned matching timing. The imaging apparatus according to (5), wherein the counter outputs a predetermined value when the detection circuit detects that the amount of light overexposure has occurred.

[0191] (18) The aforementioned analog-to-digital conversion unit is A comparator that, upon detecting the timing when the voltage signal and the second reference signal coincide, changes the first logical value to the second logical value and outputs it, A logic gate that outputs the output value of the comparator according to the output value of the detection circuit, A counter that counts the elapsed time until the matching timing based on the second logical value, The imaging apparatus according to (5), wherein the logic gate outputs the first logic value when the detection circuit detects that the amount of light overflow has occurred.

[0192] (19) The aforementioned analog-to-digital conversion unit is A comparator that, upon detecting the timing when the voltage signal and the second reference signal coincide, changes the first logical value to the second logical value and outputs it, A counter that counts the elapsed time until the matching timing based on the second logical value, The imaging apparatus according to (5), wherein the comparator outputs the first logical value when the detection circuit detects that the amount of light overexposure has occurred.

[0193] (20) The process involves a pixel converting an amount of charge corresponding to the amount of incident light into a voltage, and outputting it as a voltage signal to a signal line. A detection step in which an overexposure occurs when the change in the potential of the voltage signal during a predetermined time range is greater than the change in the potential of a reference signal that has been continuously subjected to a predetermined displacement during that time range, An imaging method comprising:

[0194] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents. [Explanation of Symbols]

[0195] 1: Imaging device, 7, 7a: AD conversion unit, 10: Pixel, 22: Comparator, 23: Counter, 25: Constant current source, 40: Detection circuit, 42: Buffer unit, 44: Differential amplifier unit, 46: Dynamic comparator, 48: Logic control unit, 50, 50a, 50b: Constant current source, FD: Floating diffusion (charge-voltage conversion unit), MN3: Transistor (first transistor), MN4: Transistor (second transistor), PD: Photoelectric conversion element, RFEslope: Slope potential signal (reference signal), TG: Transfer transistor, VSLSW: First switch, VSLGND: Second switch, Vramp: Ramp wave signal, VSL: Vertical signal line, Vsl: Voltage signal

Claims

1. A pixel capable of converting an amount of charge corresponding to the amount of incident light into a voltage and outputting it as a voltage signal on a signal line, A detection circuit that detects that an overexposure has occurred when the change in the potential of the voltage signal during a predetermined time range is greater than the change in the potential of a reference signal that has been continuously subjected to a predetermined displacement during that time range, An imaging device equipped with the following features.

2. The imaging apparatus according to claim 1, wherein the reference signal has a potential that monotonically increases or decreases over time from a reference potential within the time range.

3. The imaging apparatus according to claim 2, wherein the detection circuit detects that an overexposure has occurred when there is a predetermined magnitude relationship between the potential of the voltage signal and the voltage of the reference signal at the end of the time range.

4. The aforementioned pixel is A photoelectric conversion element that generates and stores charge in response to incident light, A charge-voltage conversion unit that stores the charge generated by the photoelectric conversion element as the charge quantity and converts it into the voltage, The system includes a transfer transistor that controls the potential barrier between the photoelectric conversion element and the charge-voltage conversion unit, The imaging apparatus according to claim 3, wherein the voltage signal is a signal when the voltage exceeds a potential barrier of a predetermined magnitude.

5. An analog-to-digital conversion unit connected to the signal line, which converts the voltage signal into a digital value, The imaging device according to claim 3, further comprising:

6. The analog-to-digital conversion unit is connected to the signal line via a first switch. The imaging apparatus according to claim 5, wherein the detection circuit changes the first switch from a connected state to a disconnected state when it detects that an overexposure has occurred.

7. The imaging apparatus according to claim 6, wherein the detection circuit, when it detects that the amount of light overexposure has occurred, sets the input potential to the analog-to-digital conversion unit to a predetermined potential.

8. The detection circuit is configured such that the input terminal of the analog-to-digital conversion unit is connected to the ground potential via a second switch. The imaging apparatus according to claim 7, wherein the detection circuit, upon detecting that the amount of light overexposure has occurred, changes the first switch to the disconnected state, and then changes the second switch from the disconnected state to the connected state.

9. The imaging apparatus according to claim 8, wherein the detection circuit is connected to the signal line via a buffer unit.

10. The imaging apparatus according to claim 9, wherein the buffer unit has a first amplification transistor for amplifying the voltage signal, and the detection circuit is connected to the signal line via the first amplification transistor.

11. The imaging apparatus according to claim 10, wherein the buffer unit has a second amplification transistor for amplifying the reference signal, and the detection circuit is connected to the reference signal via the second amplification transistor.

12. The imaging apparatus according to claim 11, wherein the first amplification transistor and the second amplification transistor are connected to a common constant current source or to different constant current sources.

13. The detection circuit is A differential amplifier unit that amplifies the voltage signal and the reference signal, A dynamic comparator that outputs a determination signal indicating that the amount of overexposure has occurred when the voltage signal amplified by the differential amplifier and the reference signal have a predetermined magnitude relationship at the end of the time range, A logic control unit controls the first switch and the second switch based on the determination signal, The imaging device according to claim 12, having the following features.

14. The amplified signal from the first amplification transistor is input to the first terminal of the differential amplifier via the first capacitor. The imaging apparatus according to claim 13, wherein the amplified signal of the second amplification transistor is input to the second terminal of the differential amplifier via the second capacitor.

15. The imaging apparatus according to claim 5, wherein the analog-to-digital conversion unit outputs a predetermined value when the detection circuit detects that the amount of light overexposure has occurred.

16. The signal processing unit that processes the output value of the analog-to-digital conversion unit is provided as follows: Furthermore, The imaging apparatus according to claim 5, wherein the signal processing unit outputs a predetermined value when the detection circuit detects that the amount of light overexposure has occurred.

17. The aforementioned analog-to-digital conversion unit is A comparator that detects the timing at which the voltage signal and the second reference signal coincide, The system includes a counter that counts the elapsed time until the aforementioned matching timing, The imaging apparatus according to claim 5, wherein the counter outputs a predetermined value when the detection circuit detects that the amount of light overexposure has occurred.

18. The aforementioned analog-to-digital conversion unit is A comparator that, upon detecting the timing when the voltage signal and the second reference signal coincide, changes the first logical value to the second logical value and outputs it, A logic gate that outputs the output value of the comparator according to the output value of the detection circuit, A counter that counts the elapsed time until the matching timing based on the second logical value, The imaging apparatus according to claim 5, wherein the logic gate outputs the first logic value when the detection circuit detects that the amount of light overexposure has occurred.

19. The aforementioned analog-to-digital conversion unit is A comparator that, upon detecting the timing when the voltage signal and the second reference signal coincide, changes the first logical value to the second logical value and outputs it, A counter that counts the elapsed time until the matching timing based on the second logical value, The imaging apparatus according to claim 5, wherein the comparator outputs the first logical value when the detection circuit detects that the amount of light overexposure has occurred.

20. The process involves a pixel converting an amount of charge corresponding to the amount of incident light into a voltage, and outputting it as a voltage signal to a signal line. A detection step in which an overexposure occurs when the change in the potential of the voltage signal during a predetermined time range is greater than the change in the potential of a reference signal that has been continuously subjected to a predetermined displacement during that time range, An imaging method comprising:

Images