Gallium nitride semiconductor equipment

Abstract

The present invention provides a gallium nitride semiconductor device that can reduce hole trapping without introducing high concentrations of magnesium. [Solution] The gallium nitride semiconductor device comprises a gallium nitride substrate, an insulating film provided on the first surface of the gallium nitride substrate, and a boron-doped region provided in the area of ​​the gallium nitride substrate on the first surface side, including the interface in contact with the insulating film.

Description

Technical Field

[0001] The present disclosure relates to a gallium nitride semiconductor device.

Background Art

[0002] In a MOSFET formed on a gallium nitride (GaN) substrate (see, for example, Patent Document 1), a large amount of hole traps exist at the interface between the GaN substrate and the gate insulating film. It has been pointed out that these hole traps cause characteristic variations due to gate bias stress. These hole traps can be deactivated by introducing Mg at a high concentration into the above interface (see, for example, Non-Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When Mg, which is an acceptor, is introduced at a high concentration into the interface between the GaN substrate and the gate insulating film, the threshold value of the MOSFET becomes too high, which is not practical. An object of the present disclosure is to provide a gallium nitride semiconductor device capable of reducing hole traps without introducing Mg at a high concentration.

Means for Solving the Problems

[0006] To solve the above problems, a gallium nitride semiconductor device according to one aspect of the present disclosure comprises a gallium nitride substrate, an insulating film provided on a first surface of the gallium nitride substrate, and a boron-doped region provided in a region of the gallium nitride substrate on the first surface side that includes an interface in contact with the insulating film. [Effects of the Invention]

[0007] According to one aspect of this disclosure, a gallium nitride semiconductor device can be provided that can reduce hole trapping without introducing high concentrations of Mg. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a cross-sectional view showing an example of the configuration of a horizontal MOSFET according to the present disclosure. [Figure 2] Figure 2 is a magnified cross-sectional view showing the region that overlaps with line AA' in the cross-sectional view shown in Figure 1. [Figure 3] Figure 3 is a schematic graph showing the B concentration and Mg concentration in the region overlapping with line AA' in the cross-sectional view shown in Figure 1. [Figure 4] Figure 4 is a cross-sectional view showing an example configuration of a normally-off vertical MOSFET according to Embodiment 2 of this disclosure. [Figure 5] Figure 5 is a cross-sectional view showing a modified example of a vertical MOSFET according to Embodiment 2 of this disclosure. [Figure 6A] Figure 6A is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure, in order of steps. [Figure 6B] Figure 6B is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure, in order of steps. [Figure 6C] Figure 6C is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure, in order of steps. [Figure 6D] Figure 6D is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure, in order of steps. [Figure 6E]Figure 6E is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure, in order of steps. [Figure 6F] Figure 6F is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure, in order of steps. [Figure 7] Figure 7 is a cross-sectional view showing a B-doping method (Example 1) for a GaN substrate. [Figure 8] Figure 8 is a graph illustrating the B concentration distribution obtained by B ion implantation. [Figure 9] Figure 9 is a schematic diagram showing a B-doping method (Example 2) for a GaN substrate. [Figure 10] Figure 10 is a cross-sectional view showing an example configuration of a normally-off vertical MOSFET according to Embodiment 4 of this disclosure. [Figure 11] Figure 11 is a plan view showing an example of the configuration of a gallium nitride semiconductor device according to Embodiment 5 of this disclosure. [Figure 12] Figure 12 shows a portion of the cross-section obtained by cutting the plan view shown in Figure 11 along the line BB'. [Modes for carrying out the invention]

[0009] Embodiments of the present disclosure are described below. In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each device and component, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following explanation. Furthermore, it goes without saying that there are parts where the relationships and ratios of dimensions differ between drawings.

[0010] Furthermore, in the following explanation, the terms X-axis, Y-axis, and Z-axis may be used to describe directions. For example, the X-axis and Y-axis directions are parallel to the surface 10a of the GaN substrate 10, which will be described later. The Z-axis direction is perpendicular to the surface 10a of the GaN substrate 10. The X-axis, Y-axis, and Z-axis directions are mutually orthogonal.

[0011] Furthermore, in the following explanation, the direction of the Z-axis arrow may be referred to as "up," and the opposite direction of the Z-axis arrow may be referred to as "down." "Up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions to specify the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical concept of this disclosure. For example, it goes without saying that if the paper is rotated 180 degrees, "up" becomes "down" and "down" becomes "up."

[0012] Furthermore, in the following explanation, the + and - signs attached to P and N indicating conductivity types mean that the semiconductor region has a relatively higher or lower impurity concentration compared to semiconductor regions without + and - signs, respectively. However, even if the same P and P (or N and N) signs are attached to semiconductor regions, this does not mean that the impurity concentrations of each semiconductor region are exactly the same.

[0013] <Embodiment 1> (Example configuration) Figure 1 is a cross-sectional view showing an example configuration of a normally-off lateral MOSFET 1 (an example of a "transistor" in this disclosure) according to an embodiment of this disclosure. Normally-off characteristics mean that when no voltage is applied to the gate electrode, there is no channel and no drain current flows.

[0014] As shown in Figure 1, the lateral MOSFET 1 is provided on a gallium nitride substrate (an example of the "gallium nitride substrate" in this disclosure; hereinafter referred to as a GaN substrate) 10. The lateral MOSFET 1 includes a gate insulating film 42 (an example of the "insulating film" in this disclosure) provided on the surface 10a (an example of the "first surface" in this disclosure) side of the GaN substrate 10, a gate electrode 44 provided on the gate insulating film 42, a P-type well region 23 provided on the GaN substrate 10, an N+-type source region 26 and drain region 27 provided on the surface of the well region 23 and in its vicinity, below both sides of the gate electrode 44, a P+-type contact region 25 provided on the surface 10a of the GaN substrate 10 and in contact with the well region 23, a source electrode 54 provided on the surface 10a side of the GaN substrate 10 and in contact with the source region 26 and contact region 25, and a drain electrode 56 provided on the surface 10a side of the GaN substrate 10 and in contact with the drain region 27. The surfaces of the well region 23, contact region 25, source region 26, and drain region 27 are also the surface 10a of the GaN substrate 10.

[0015] The GaN substrate 10 is, for example, a GaN single crystal substrate. The GaN substrate 10 has a surface 10a and a back surface located on the opposite side of surface 10a. For example, the GaN substrate 10 has a threading dislocation density of 1 × 10⁻⁶. 7 cm -2 This is a low-dislocation self-supporting GaN substrate with a dislocation count of less than [value missing].

[0016] The donor (N-type impurity) contained in the GaN substrate 10 may be one or more elements such as Si (silicon), Ge (germanium), and O (oxygen). The acceptor element (P-type impurity) contained in the GaN substrate 10 may be one or more elements such as Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc).

[0017] Because the GaN substrate 10 is a low-dislocation self-supporting GaN substrate, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This makes it possible to manufacture power devices with a high yield rate. In addition, during the heat treatment included in the manufacturing process of the lateral MOSFET 1, it is possible to prevent ion-implanted impurities from deeply diffusing along the dislocations.

[0018] The GaN substrate 10 may include a GaN single crystal substrate and a single crystal GaN layer epitaxially grown on the GaN single crystal substrate. Furthermore, the surface 10a of the GaN substrate 10 may be a polar surface, such as a c-plane (Ga polar surface or N polar surface), or it may be a non-polar surface, such as an m-plane or a-plane.

[0019] In the lateral MOSFET 1, the semiconductor material is GaN, but the semiconductor material may also contain one or more elements such as aluminum (Al) and indium (In). The semiconductor material may also be a mixed crystal semiconductor containing trace amounts of Al and In, i.e., AlxInyGa1-x-yN (0≦x<1, 0≦y<1). Note that GaN is the case where x=y=0 in AlxInyGa1-x-yN.

[0020] The P-type well region 23 is provided in the depth direction (for example, in the opposite direction to the Z-axis arrow) from the surface 10a of the GaN substrate 10. For example, the well region 23 is formed by ion implantation of acceptor elements (P-type impurities) to a predetermined depth from the surface 10a of the N-type GaN substrate 10, and activation of the acceptor elements by heat treatment. Alternatively, the P-type well region 23 may be formed by epitaxial growth on the N-type GaN single crystal substrate or N-type GaN layer of the GaN substrate 10.

[0021] The P+-type contact region 25 is a region where acceptor elements are ion-implanted to a predetermined depth from the surface of the well region 23 and the acceptor elements are activated by heat treatment. The contact region 25 has a higher concentration of acceptor elements than the well region 23. Alternatively, the contact region 25 and the well region 23 may have the same concentration of acceptor elements. In that case, the contact region 25 is a part of the well region 23 and may be formed simultaneously with the well region 23 in the same process. The well region 23 and the contact region 25 contain at least one of Mg and Be as acceptor elements.

[0022] For example, the well region 23 and the contact region 25 contain Mg as an acceptor element. The Mg concentration in the well region 23 is, for example, 5×10 18 cm -3 or less, and preferably 1×10 17 cm -3 or more and 5×10 18 cm -3 or less, and more preferably 5×10 17 cm -3 or more and 5×10 18 cm -3 or less. Also, the Mg concentration in the contact region 25 is 1×10 18 cm -3 or more and 2×10 20 cm -3 or less.

[0023] The source region 26 and the drain region 27 are regions where donor elements (N-type impurities) are ion-implanted to a predetermined depth from the surface 10a of the well region 23 and the donor elements are activated by heat treatment. The source region 26 and the drain region 27 are N+-type regions. The source region 26 and the drain region 27 have the same concentration of donor elements. The source region 26 and the drain region 27 are formed simultaneously in the same process. The source region 26 and the drain region 27 contain at least one of Si, Ge, and O as donor elements. For example, the source region 26 and the drain region 27 contain Si as the donor element. The Si concentrations in the source region 26 and the drain region 27 are 1 × 10⁻⁶ each. 19 cm -3 The above 5 x 10 20 cm -3 The following applies:

[0024] The gate insulating film 42 is, for example, a silicon oxide film (SiO2 film). The gate insulating film 42 may also be an oxide such as Al2O3 or HfO, or a composite film thereof. The thickness of the gate insulating film 42 is, for example, 50 nm to 100 nm. The gate insulating film 42 is provided, for example, on a flat surface 10a. The gate electrode 44 is provided on the gate insulating film 42. For example, the gate electrode 44 is a planar type provided on a flat gate insulating film 42. The gate electrode 44 is made of, for example, polysilicon doped with impurities. A metal gate electrode such as Ti silicide, W silicide, or TiN may be used for the gate electrode 44.

[0025] The source electrode 54 and the drain electrode 56 are provided on the surface 10a of the GaN substrate 10, respectively. The source electrode 54 is in contact with the source region 26 and the contact region 25. The drain electrode 56 is in contact with the drain region 27. The source electrode 54 and the drain electrode 56 are made of, for example, an Al or Al-Si alloy. The source electrode 54 and the drain electrode 56 may have a barrier metal layer between the surface 10a of the GaN substrate 10 and the Al (or Al-Si). Titanium (Ti) may be used as the material for the barrier metal layer.

[0026] Figure 2 is an enlarged cross-sectional view showing the region overlapping with line AA' in the cross-sectional view shown in Figure 1. The region overlapping with line AA' includes the interface IF between the GaN substrate 10 and the gate insulating film 42 and its vicinity. As shown in Figure 2, the lateral MOSFET 1 includes a boron-doped region Bd provided in the region on the surface 10a side of the GaN substrate 10, which includes the interface IF in contact with the gate insulating film 42. The boron-doped region Bd is a region in which boron (B) is doped, i.e., introduced. The boron-doped region Bd may also be called a boron-introduced region or a boron-containing region. Furthermore, the region in the GaN substrate 10 that includes the interface IF is also the region in which the channel of the lateral MOSFET 1 is formed. Therefore, the region in the GaN substrate 10 that includes the interface IF is also called the channel region ch.

[0027] As shown in Figure 2, the boron-doped region Bd may be provided not only in the channel region ch of the GaN substrate 10, but also in the gate insulating film 42 in contact with the interface IF. For example, the boron-doped region Bd may be provided continuously from the channel region ch including the interface IF to the gate insulating film 42. That is, boron (B) may be continuously doped from the channel region ch including the interface IF to the gate insulating film 42.

[0028] The presence of a boron-doped region Bd reduces (i.e., inactivates) hole traps in the channel region ch without affecting device characteristics such as thresholds. To explain this in more detail, in the initial stage of forming a gate insulating film 42 such as SiO2 or Al2O3 on the surface 10a of the GaN substrate 10, the surface 10a of the GaN substrate 10 is exposed to a source gas containing oxygen and is slightly oxidized. As a result, a GaOx layer (not shown) is formed at the interface IF between the surface 10a of the GaN substrate 10 and the gate insulating film 42 with a thickness of only a small amount, for example, less than 1 nm. Vo (defects caused by oxygen deficiency) exists in the GaOx layer, and this causes hole traps.

[0029] However, in the embodiments of this disclosure, a boron-doped region Bd exists in the region including the surface 10a (interface IF) of the GaN substrate 10. The boron in the boron-doped region Bd is incorporated into the GaOx layer when the surface 10a of the GaN substrate 10 is oxidized. Since the Vo in the GaOx layer is energetically stabilized by bonding with B (boron), Vo readily bonds with B. When Vo bonds with B, the Vo level moves towards the conduction band and changes into an electron trap, so it ceases to function as a hole trap (i.e., becomes inactive).

[0030] This is the same mechanism as when Vo combines with Mg and Vo ceases to function as a hole trap, but unlike Mg, B does not form a level in the GaN gap (i.e., it does not act as a donor or acceptor), and therefore does not affect device characteristics such as thresholds. By using B doping instead of Mg doping to reduce hole traps, it is possible to reduce hole traps without affecting device characteristics such as thresholds.

[0031] In the horizontal MOSFET 1 shown in Figures 1 and 2, it is preferable that the boron concentration in the boron-doped region Bd is higher than the hole trap concentration in the channel region ch, which includes the interface IF. For example, the boron concentration in the boron-doped region Bd is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following is true: 5 × 10 18 cm -3 The above 1 x 10 21 cm -3 The following is preferable: 1 × 10 19 cm -3 The above 1 x 10 21 cm -3 The following is more preferable:

[0032] Figure 3 is a schematic graph showing the boron (B) and magnesium (Mg) concentrations in the region overlapping with the AA' line in the cross-sectional view shown in Figure 1. As shown in Figure 3, it is preferable that the B concentration is maximum at the interface IF of the GaN substrate 10 or at a location near the interface IF on the GaN substrate 10. This makes it possible to reduce hole traps in the channel region ch without affecting device characteristics such as thresholds.

[0033] Figure 3 illustrates a case where the Mg concentration in the P-type well region 23 is constant, and the maximum B concentration (Bmax) at and near the interface IF is higher than this Mg concentration. For example, the Mg concentration is 5 × 10⁻⁶. 18 cm -3 It is less than 5 × 10⁻¹⁰, and the maximum B concentration (Bmax) is 5 × 10⁻¹⁰. 18 cm -3 That's fine too.

[0034] As shown in Figure 3, if the depth of the boron-doped region Bd in the GaN substrate 10 is d, then the depth d is in the range of 1 nm to 10 nm from the interface IF. Also, if the thickness of the boron-doped region Bd in the gate insulating film 42 is t, then t is in the range of 1 nm to 10 nm. While d = t is also possible, Figure 3 illustrates the case where d > t.

[0035] (Effects of Embodiment 1) As described above, the gallium nitride (GaN) semiconductor device according to Embodiment 1 of the present disclosure comprises a GaN substrate 10, an insulating film provided on the surface 10a of the GaN substrate 10, and a boron-doped region Bd provided in a region on the surface 10a side of the GaN substrate 10 that includes the interface in contact with the insulating film. With this, even if Vo (defects caused by oxygen deficiency) is present at the interface IF in contact with the insulating film and in its vicinity on the GaN substrate 10, Vo can be combined with B so that Vo does not act as a hole trap (i.e., is inactivated). This makes it possible to add Mg to a high concentration (for example, 1 × 10⁻⁶). 19 cm -3It is possible to reduce hole trapping without doping to higher concentrations.

[0036] For example, a GaN semiconductor device includes a lateral MOSFET 1 provided on a GaN substrate 10. The lateral MOSFET 1 has a boron-doped region Bd in the region where the channel is formed on the GaN substrate 10 (i.e., the channel region ch including the interface IF). This allows Vo to be coupled with B even when Vo is present in the channel region ch, preventing Vo from acting as a hole trap. Compared to reducing hole traps by doping with a high concentration of Mg, this method allows for reducing hole traps while keeping the threshold low.

[0037] <Embodiment 2> In Embodiment 1 described above, a horizontal MOSFET was shown as an example of the "transistor" of this disclosure. However, the "transistor" of this disclosure is not limited to a horizontal type, and may be vertical. Figure 4 is a cross-sectional view showing an example configuration of a normally-off vertical MOSFET 1A according to Embodiment 2 of this disclosure. As shown in Figure 4, the vertical MOSFET 1A is provided on a GaN substrate 10.

[0038] The GaN substrate 10 includes, for example, an N+-type GaN single crystal substrate 11 and an N--type GaN layer 22 provided on the GaN single crystal substrate 11. As shown in Figure 4, the GaN substrate 10 has a back surface 10b opposite to the front surface 10a. This back surface 10b is also the back surface of the GaN single crystal substrate 11. The n-type dopant contained in the GaN single crystal substrate 11 is one or more elements from Si (silicon), O (oxygen), and Ge (germanium), one example being O. The impurity concentration of O in the GaN single crystal substrate 11 is 2 × 10⁻⁶. 18 / cm 3 That's all.

[0039] The GaN single crystal substrate 11 has, for example, a threading dislocation density of 1 × 10⁻⁶ 7 cm -2The GaN single crystal substrate may be a low-dislocation self-supporting GaN substrate. Because the GaN single crystal substrate 11 is a low-dislocation self-supporting substrate, the dislocation density of the GaN layer 22 formed on the GaN single crystal substrate 11 is also reduced. Furthermore, by using a low-dislocation self-supporting substrate for the GaN single crystal substrate 11, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN single crystal substrate 11. This allows the manufacturing equipment to produce power devices with a high yield rate. Additionally, during heat treatment, it is possible to prevent ion-implanted impurities from deeply diffusing along the dislocations.

[0040] The GaN layer 22 is provided on the GaN single crystal substrate 11. The GaN layer 22 is an N-type GaN single crystal layer, formed on the GaN single crystal substrate 11 by epitaxial growth. The n-type dopant (n-type impurity) contained in the GaN layer 22 is one or more elements from Si (silicon), O (oxygen), and Ge (germanium), for example, O. Furthermore, the surface 10a of the GaN substrate 10 (i.e., the surface of the GaN layer 22) may be a polar surface, such as a c-plane (Ga polar surface or N polar surface), or it may be a non-polar surface, such as an m-plane or a-plane.

[0041] As shown in Figure 4, the vertical MOSFET 1A has a gate insulating film 42 provided on the surface 10a side of the GaN substrate 10, a gate electrode 44 provided on the gate insulating film 42, a P+ type well region 23 provided in the GaN layer 22, an N+ type source region 26 provided on the surface 23 and its vicinity and below both sides of the gate electrode 44, and a P+ type contact region 25 provided on the surface 10a of the GaN substrate 10 and its vicinity and in contact with the well region 23. The Mg concentration in the well region 23 is the same as in the case of the horizontal MOSFET 1. The vertical MOSFET 1A also has a source electrode 54 provided on the surface 10a side of the GaN substrate 10 and in contact with the source region 26 and the contact region 25, an interlayer insulating film 48 that insulates between the source electrode 54 and the gate electrode, and a drain electrode 56 provided on the back surface 10b side of the GaN substrate 10.

[0042] The vertical MOSFET 1A further has an n-type JFET region 24 provided in the GaN layer 22. The JFET region 24 is provided in a position facing the gate electrode 44, for example, via a gate insulating film 42. The JFET region 24 faces the surface 10a of the GaN substrate 10 and is in contact with the N+-type layer 31 in the thickness direction of the vertical MOSFET 1A (for example, the Z-axis direction). The JFET region 24 is also in contact with the well region 23 in a direction intersecting the thickness direction of the vertical MOSFET 1A (for example, the X-axis direction). Figure 4 illustrates the case where the depth of the JFET region 24 from the surface 10a and the depth of the well region 23 from the surface 10a are the same, but the depth of the JFET region 24 from the surface 10a may be greater than the depth of the well region 23 from the surface 10a.

[0043] In the GaN layer 22, the region where the well region 23, source region 26, and contact region 25 are not provided may be called the drift region. The JFET region 24 is also part of the drift region. The drift region functions as a current path between the GaN single crystal substrate 11 and the well region 23.

[0044] As shown in Figure 4, the vertical MOSFET 1A has a boron-doped region Bd in the area on the surface 10a side of the GaN substrate 10, including the interface IF that contacts the gate insulating film 42. Similar to the horizontal MOSFET 1 shown in Figure 1, the boron-doped region Bd in the vertical MOSFET 1A shown in Figure 4 is provided in the channel region ch including the interface IF of the GaN substrate 10. Furthermore, the boron-doped region Bd is provided not only in the channel region ch but also in the gate insulating film 42 that contacts the interface IF. For example, as shown in Figure 2, the boron-doped region Bd is provided continuously from the channel region ch to the gate insulating film 42. In Figure 4, in the portion exposed to the contact hole of the interlayer insulating film 48 (hereinafter also referred to as the exposed portion), at least a part of the boron-doped region Bd provided on the surface of the contact region 25 and source region 26 is removed, and a recess is created on the surface 10a of the GaN substrate 10. Therefore, in the exposed areas, the impurity concentration of boron (B) is lower on the surface of the contact region 25 and the surface of the source region 26 compared to the underside of the gate insulating film 42. Alternatively, boron may not be doped at all.

[0045] Furthermore, the vertical MOSFET 1A is provided on the GaN substrate 10 and has an N-type JFET region 24 located between one adjacent well region 23 and the other well region 23 in a direction parallel to the surface 10a (for example, in the X-axis direction). The boron-doped region Bd is also located in the region of the JFET region 24 that is in contact with the gate insulating film 42 (i.e., the surface and its vicinity). The boron-doped region Bd is provided continuously from the surface and its vicinity of the JFET region 24 to the gate insulating film 42.

[0046] The boron concentration in the boron-doped region Bd is the same as in the case of the lateral MOSFET 1. For example, the B concentration in the boron-doped region Bd is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following is true: 5 × 10 18 cm -3 The above 1 x 10 21 cm -3The following is preferable: 1 × 10 19 cm -3 The above 1 x 10 21 cm -3 The following is more preferable:

[0047] The depth d of the boron-doped region Bd in the GaN substrate 10 and the thickness t of the boron-doped region Bd in the gate insulating film 42 are the same as in the case of the lateral MOSFET 1. For example, as shown in Figure 3, the depth d of the boron-doped region Bd from the interface IF is between 1 nm and 10 nm. The thickness t of the boron-doped region Bd from the interface IF is in the range of 1 nm and 10 nm. d = t, but as shown in Figure 3, d > t is also possible.

[0048] (Effects of Embodiment 2) As described above, the vertical MOSFET 1A according to Embodiment 2 of this disclosure has a boron-doped region Bd in the region where the channel is formed in the GaN substrate 10 (i.e., the channel region ch including the interface IF). This makes it possible to couple Vo with B even when Vo is present in the channel region ch, so that Vo does not act as a hole trap. Compared to the case where hole traps are reduced by doping with a high concentration of Mg, it is possible to reduce hole traps while keeping the threshold low.

[0049] (Modified version of Embodiment 2) Figure 5 is a cross-sectional view showing a modified vertical MOSFET 1A according to Embodiment 2 of this disclosure. In the modified example shown in Figure 5, the difference from the vertical MOSFET 1A shown in Figure 4 lies in the surface of the P+ type contact region 25 exposed within the contact hole of the interlayer insulating film 48 and the surface of the N+ type source region 26. In this modified example, the difference is that the boron-doped region Bd remains on the surface of the exposed contact region 25 and the surface of the exposed source region 26. Even in this configuration, the same effects as those of Embodiment 2 are achieved.

[0050] <Embodiment 3> As Embodiment 3 of this disclosure, a method for manufacturing a planar vertical MOSFET (vertical DMOS) will be described. Figures 6A to 6F are cross-sectional views showing the manufacturing method of a vertical MOSFET according to Embodiment 3 of this disclosure in order of steps. Vertical MOSFETs are manufactured using various devices such as a film deposition apparatus, an exposure apparatus, an ion implantation apparatus, an etching apparatus, a heat treatment apparatus, and a plasma irradiation apparatus. Hereinafter, these devices will be collectively referred to as manufacturing apparatus.

[0051] As shown in Figure 6A, the manufacturing apparatus epitaxially grows an N-type GaN layer 22 on an N+-type GaN single crystal substrate 11. Next, as shown in Figure 6B, the manufacturing apparatus sequentially ion-implants acceptor elements (e.g., Mg) and donor elements (e.g., O, Si) into the GaN layer 22 using photolithography and ion implantation techniques, and then heat-treats the layer to form a P+-type well region 23, an n-type JFET region 24, a P+-type contact region 25, and an N+-type source region 26. In this example, the formation of the P+-type contact region 25 is shown, but the formation of the contact region 25 may be omitted. In this case, the P+-type well region 23 is extended to the position of the contact region 25.

[0052] Next, as shown in Figure 6C, the manufacturing apparatus dops the surface 10a side of the GaN substrate 10 with boron (B) to form a boron-doped region Bd. Here, the B concentration in the boron-doped region Bd is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following is preferably 5 × 10 18 cm -3 The above 1 x 10 21 cm -3 More preferably 1 × 10 19 cm -3 The above 1 x 10 21 cm -3 The amount of B doping is adjusted as follows. In addition, the GaN substrate is doped with B so that the B concentration is at its maximum on the surface 10a of the GaN substrate 10.

[0053] Figure 7 is a cross-sectional view showing a B doping method (Example 1) for a GaN substrate 10. Figure 8 is a graph illustrating the B concentration distribution by B ion implantation. B doping may also be performed by ion implantation. As shown in Figure 7, the manufacturing apparatus forms an insulating film 59 on the surface 10a of the GaN substrate 10, and implants B into the surface 10a of the GaN substrate 10 and its vicinity through this insulating film 59. The insulating film 59 is a through-film for ion implantation, and is, for example, a silicon oxide film (SiO2). In this ion implantation, as shown in Figure 8, the thickness of the insulating film 59 and the B implantation energy (acceleration voltage) are adjusted so that the B concentration reaches its maximum value (Bmax) on the surface 10a of the GaN substrate 10. After ion implantation, the insulating film 59 is removed.

[0054] Figure 9 is a schematic diagram showing a B-doping method (Example 2) for a GaN substrate 10. B-doping may also be performed by plasma irradiation. As shown in Figure 9, a gas containing B (e.g., B2H6 gas) is introduced into a chamber in which the GaN substrate 10 is placed, and a high frequency is applied between electrodes in the chamber to generate plasma. The surface 10a of the GaN substrate 10 is exposed to this plasma (i.e., B plasma discharge). This dops the surface 10a of the GaN substrate 10 and its vicinity with B. In this method, the B concentration is maximum at the surface 10a of the GaN substrate 10. In addition, a B concentration distribution is formed in which the B concentration gradually decreases in the depth direction from the surface 10a of the GaN substrate 10.

[0055] For example, after doping the surface and vicinity of the GaN substrate 10 with B using the method shown in Figure 7 or Figure 9, the process proceeds to Figure 6D. As shown in Figure 6D, the manufacturing apparatus sequentially forms the gate insulating film 42 and the gate electrode 44 on the surface 10a of the B-doped GaN substrate 10. Next, as shown in Figure 6E, the manufacturing apparatus forms the interlayer insulating film 48 on the surface 10a side of the GaN substrate 10.

[0056] Next, as shown in Figure 6F, the manufacturing apparatus uses photolithography and etching techniques to partially remove the interlayer insulating film 48, the gate insulating film 42, the P+ type layer 32, and the N+ type layer 31 in that order, thereby forming a contact hole H1 on the contact region 25 and the source region 26. Here, the surface 10a side of the GaN substrate 10 is over-etched to the extent that at least a portion of the boron-doped region Bd is removed from the contact region 25 and the source region 26 located at the bottom of the contact hole H1.

[0057] Subsequently, the manufacturing apparatus forms a source electrode 54 (see Figure 4) on the surface 10a side of the GaN substrate 10 and brings the source electrode 54 into contact with the N+ type source region 26 and the P+ type well region 23. Furthermore, a drain electrode 56 (see Figure 4) is formed on the back surface 10b side of the GaN substrate 10 and brings the drain electrode 56 into contact with the N+ type GaN single crystal substrate 11. Through these steps, the planar vertical MOSFET 1A shown in Figure 4 is completed.

[0058] Furthermore, by reducing the amount of over-etching during the contact hole H1 formation process, as explained with reference to Figure 6F, a modified version of the vertical MOSFET 1A shown in Figure 5 is completed.

[0059] <Embodiment 4> In Embodiment 2 described above, a planar vertical MOSFET was shown as an example of the "transistor" of this disclosure. However, in embodiments of this disclosure, the vertical MOSFET is not limited to the planar type, but may also be a trench gate type. Figure 10 is a cross-sectional view showing an example configuration of a normally-off vertical MOSFET 1B according to Embodiment 4 of this disclosure. As shown in Figure 10, the vertical MOSFET 1B is provided on a GaN substrate 10.

[0060] As shown in Figure 10, the trench gate-side vertical MOSFET 1B includes a trench H2 provided on the surface 10a side of the GaN substrate 10. The gate electrode 44 of the vertical MOSFET 1B is located in the trench H2 via a gate insulating film 42.

[0061] Furthermore, in the GaN substrate 10, a P+ type region 28 is provided at the bottom of the trench H2. The depletion layer extending from the P+ type region 28 to the N- type GaN layer 22 suppresses the application of a high electric field to the gate insulating film 42, thereby improving the breakdown voltage of the gate insulating film 42.

[0062] Boron-doped regions Bd are provided on the sides and bottom of the trench H2. For example, on the sides of the trench H2, the boron-doped regions Bd are provided continuously from the channel region ch to the gate insulating film 42. On the bottom of the trench H2, the boron-doped regions Bd are provided continuously from the P+ type region 28 to the gate insulating film 42.

[0063] The Mg concentration in the P-type well region 23 and the B concentration in the boron-doped region Bd are the same as in the case of the lateral MOSFET 1 and the planar vertical MOSFET 1A. The depth d of the boron-doped region Bd in the GaN substrate 10 and the thickness t of the boron-doped region Bd in the gate insulating film 42 are also the same as in the case of the lateral MOSFET 1 and the planar vertical MOSFET 1A. However, in the trench gate type vertical MOSFET 1B, the interface IF that contacts the gate insulating film 42 is not the surface 10a of the GaN substrate 10, but the side of the trench H2. Therefore, the distance from the side of the trench H2 in the horizontal direction (for example, in the X-axis direction) corresponds to the depth d of the boron-doped region Bd.

[0064] In this example, in the N-type GaN layer 22, a boron-doped region Bd is formed by doping B into the portion sandwiched between the P-type well region 23 and the P+-type region 28, and facing the trench H2. Furthermore, in the N+-type source region 26, a boron-doped region Bd is formed by doping B into the portion facing the trench H2. The boron-doped region Bd is continuously provided from the bottom surface of the trench H2 along the side surface of the trench H2 to the surface 10a of the GaN substrate 10.

[0065] A boron-doped region Bd in this manner can be formed, for example, by obliquely ion-implanting boron into the GaN substrate 10 after the formation of the trench H2 and before the formation of the gate insulating film 42, or by exposing the GaN substrate 10 to a B plasma discharge.

[0066] (Effects of Embodiment 4) The trench gate type vertical MOSFET 1B according to Embodiment 4 has a boron-doped region Bd in the region where the channel is formed on the GaN substrate 10 (i.e., the channel region ch on the side of the trench H2, including the interface IF). This allows Vo to be coupled with B even when Vo is present in the channel region ch on the side of the trench H2, so that Vo does not act as a hole trap. Compared to the case where hole traps are reduced by doping with a high concentration of Mg, it is possible to reduce hole traps while keeping the threshold low.

[0067] <Embodiment 5> The technology of this disclosure may be applied to peripheral breakdown structures rather than transistors, or to both transistors and peripheral breakdown structures. It may also be applied to the peripheral breakdown structure of a diode. Figure 11 is a plan view showing an example configuration of a GaN semiconductor device 100 according to Embodiment 5 of this disclosure. Figure 12 is a view showing a part of the cross-section obtained by cutting the plan view shown in Figure 11 along the BB' line.

[0068] As shown in Figure 11, the GaN semiconductor device 100 has an active region 110 and a peripheral breakdown structure 130 (an example of the "breakdown structure" in this disclosure). A vertical MOSFET (for example, the vertical MOSFETs 1A, 1B, etc. mentioned above) is arranged in the active region 110. The active region 110 has a gate pad 112 and a source pad 114. The gate pad 112 and the source pad 114 are electrode pads electrically connected to the gate electrode 44 and source electrode 54 mentioned above, respectively.

[0069] In a plan view from the Z-axis direction, the peripheral breakdown structure 130 surrounds the active region 110. The peripheral breakdown structure 130 has, for example, a JTE (Junction Termination Extension) structure. For example, as shown in Figure 12, the peripheral breakdown structure 130 has a P-type region 63 with a lower P-type impurity concentration than the P-type well region 23. This makes it easier for the depletion layer in the gate-off state to spread to the outer edge of the GaN layer 22, thereby maintaining the breakdown voltage of the vertical MOSFET. Other breakdown structures, such as a guard ring, may be used for the peripheral breakdown structure 130.

[0070] Furthermore, the peripheral pressure-resistant structure 130 has a boron-doped region Bd provided in a region on the surface 10a side of the GaN substrate 10, including the interface in contact with the field insulating film 65. The boron-doped region Bd is provided in a region including the interface in contact with the field insulating film 65 in both the P-type region 63 (an example of the "P-type region" in this disclosure) that constitutes the peripheral pressure-resistant structure 130 and the N-type region (an example of the "N-type region" in this disclosure) which is part of the N-type GaN layer 22 and located on the outer periphery of the P-type region 63. The boron-doped region Bd is provided continuously from the region including the interface in contact with the field insulating film 65 in the GaN substrate 10 to the field insulating film 65. In addition, the boron-doped region Bd is provided over the entire area directly beneath the field insulating film 65.

[0071] The boron concentration in the boron-doped region Bd is the same as in the case of the vertical MOSFETs 1A and 1B described above, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies. Furthermore, the depth of the boron-doped region Bd in the GaN substrate 10 is the same as in the case of the vertical MOSFETs 1A and 1B described above, and is, for example, in the range of 1 nm to 10 nm from the surface 10a of the GaN substrate 10 (i.e., the interface between the P-type region 63 and the field insulating film 65).

[0072] (Effects of Embodiment 5) The GaN semiconductor device 100 according to Embodiment 5 includes a peripheral breakdown structure 130 provided around the active region 110 on the GaN substrate 10. The peripheral breakdown structure 130 has a boron-doped region Bd in the region including the interface with the field insulating film 65 in the P-type region and N-type region that constitute the peripheral breakdown structure 130. This makes it possible to combine Vo with B even when Vo is present in the region including the interface with the field insulating film 65, so that Vo does not act as a hole trap. This makes it easy to extend the depletion layer from the P-type region 63 to the outer periphery of the GaN substrate 10, enabling further improvement of breakdown voltage.

[0073] As shown in Figure 12, the peripheral breakdown structure 130 may include an N+ type region 67 provided on the outer edge of the GaN substrate 10 and a channel stopper electrode 69 connected to the N+ type region 67. The outer edge of the GaN substrate 10 has its crystal structure destroyed by dicing and is conductive. Therefore, the N+ type region 67 and the channel stopper electrode 69 are fixed at the same potential as the drain electrode 56. The N+ type region 67 can stop the depletion layer from growing from the P- type region 63.

[0074] <Other Embodiments> As described above, this disclosure is described by embodiments and their modifications, but the descriptions and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure. For example, the gate insulating film 42 is not limited to an SiO2 film, but may be other insulating films. Silicon oxynitride (SiON) films, silicon nitride (Si3N4) films, and aluminum oxide (Al2O3) films can also be used for the gate insulating film 42. Furthermore, composite films made by stacking several single-layer insulating films can also be used for the gate insulating film 42. In addition, one or more of Embodiments 1, 2, and 4 described for the MOSFET may be combined with Embodiment 5 described for the peripheral breakdown voltage structure.

[0075] Furthermore, although the above embodiment described introducing B into the GaOx layer from the GaN side, B may also be introduced into the GaOx layer from the insulating film side (for example, gate insulating film 42, field insulating film 65).

[0076] Thus, this technology naturally includes various embodiments and modifications not described herein. Within the scope of the embodiments and modifications described above, at least one of various omissions, substitutions, and modifications of the components can be made. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist.

[0077] Furthermore, this disclosure may also adopt the following structure. (1) Gallium nitride substrate and An insulating film provided on the first surface of the gallium nitride substrate, A gallium nitride semiconductor device comprising: a boron-doped region provided in the first surface side of the gallium nitride substrate, in a region including the interface in contact with the insulating film; and (2) The boron concentration in the boron-doped region is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The gallium nitride semiconductor device described in (1) above is as follows: (3) The gallium nitride semiconductor device according to (1) or (2), wherein the depth of the boron-doped region in the gallium nitride substrate is in the range of 1 nm to 10 nm from the interface. (4) The gallium nitride semiconductor device according to any one of (1) to (3), wherein the boron-doped region is continuously provided on the gallium nitride substrate from the region including the interface to the insulating film. (5) The gallium nitride substrate is provided with a transistor, The insulating film is the gate insulating film of the transistor, The aforementioned transistor is A gate electrode provided on the gate insulating film, The gallium nitride substrate has a P-type well region provided at a position facing the gate electrode via the gate insulating film, The gallium nitride semiconductor device according to any one of (1) to (4), wherein the boron-doped region is located in the channel region in the well region where the transistor channel is formed. (6) The aforementioned channel region contains 5 × 10⁶ Mg as a P-type impurity. 18 cm -3 A gallium nitride semiconductor device according to (5) above, comprising the following concentrations. (7) The aforementioned transistor is An N-type source region provided on the first surface side of the gallium nitride substrate, A source electrode provided on the first surface side and in contact with the source region, A gallium nitride semiconductor device according to (5) or (6), comprising a drain electrode provided on the second surface side of the gallium nitride substrate, which is opposite to the first surface, and in contact with the gallium nitride substrate. (8) The aforementioned transistor is The gallium nitride substrate has an N-type JFET region located between one adjacent well region and the other adjacent well region in a direction parallel to the first surface, The gallium nitride semiconductor device according to any one of (5) to (7), wherein the boron-doped region is located in the region in contact with the gate insulating film in the JFET region. (9) The gallium nitride substrate is provided with a trench on the first surface side, The gate electrode is provided in the trench via the gate insulating film, The gallium nitride semiconductor device according to any one of (5) to (7), wherein the boron-doped region is located on the side of the trench. (10) The gallium nitride substrate is provided with a pressure-resistant structure around the active region, The insulating film is the field insulating film of the pressure-resistant structure, The gallium nitride semiconductor device according to any one of (1) to (4), wherein the boron-doped region is provided in the P-type region and N-type region constituting the breakdown structure, in a region including the interface in contact with the field insulating film. [Explanation of symbols]

[0078] 10 GaN substrates 10a surface 10b back side 11 GaN single crystal substrate 22 GaN layer 23 well area 24 JFET area 25 Contact area 26 Source Area 27 Drain region 28 P+ type region 31 N+ type layer 32 P+ type layer 42 Gate insulating film 44 gate 48 Interlayer insulating film 54 Source electrodes 56 Drain electrode 59 Insulating film 63 P-type region 65 Field Insulating Film 67 N+ type region 69 Channel stopper electrode 100 GaN semiconductor device 110 Active area 112 Gate Pad 114 Sourcepad 130 Peripheral pressure-resistant structure Bd Boron-doped area ch channel region H1 Contact Hole H2 Trench IF interface

Claims

1. Gallium nitride substrate and An insulating film provided on the first surface of the gallium nitride substrate, A gallium nitride semiconductor device comprising: a boron-doped region provided in the first surface side of the gallium nitride substrate, in a region including the interface in contact with the insulating film; and

2. The boron concentration in the boron-doped region is 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The gallium nitride semiconductor device according to claim 1, which is as follows:

3. The gallium nitride semiconductor device according to claim 1 or 2, wherein the depth of the boron-doped region in the gallium nitride substrate is in the range of 1 nm to 10 nm from the interface.

4. The gallium nitride semiconductor device according to claim 1 or 2, wherein the boron-doped region is continuously provided in the gallium nitride substrate from the region including the interface to the insulating film.

5. The gallium nitride substrate is provided with a transistor, The insulating film is the gate insulating film of the transistor, The aforementioned transistor is A gate electrode provided on the gate insulating film, The gallium nitride substrate has a P-type well region provided at a position facing the gate electrode via the gate insulating film, The gallium nitride semiconductor device according to claim 1 or 2, wherein the boron-doped region is located in the channel region in the well region where the transistor channel is formed.

6. The aforementioned channel region contains 5 × 10⁶ Mg as a P-type impurity. １８ cm －３ The gallium nitride semiconductor device according to claim 5, comprising the following concentrations.

7. The aforementioned transistor is An N-type source region provided on the first surface side of the gallium nitride substrate, A source electrode provided on the first surface side and in contact with the source region, The gallium nitride semiconductor device according to claim 5, further comprising a drain electrode provided on the second surface side of the gallium nitride substrate, which is opposite to the first surface, and in contact with the gallium nitride substrate.

8. The aforementioned transistor is The gallium nitride substrate has an N-type JFET region located between one adjacent well region and the other adjacent well region in a direction parallel to the first surface, The gallium nitride semiconductor device according to claim 5, wherein the boron-doped region is located in the region of the JFET region that is in contact with the gate insulating film.

9. The gallium nitride substrate is provided with a trench on the first surface side, The gate electrode is provided in the trench via the gate insulating film, The gallium nitride semiconductor device according to claim 5, wherein the boron-doped region is located on the side of the trench.

10. The gallium nitride substrate is provided with a pressure-resistant structure around the active region, The insulating film is the field insulating film of the pressure-resistant structure, The gallium nitride semiconductor device according to claim 1 or 2, wherein the boron-doped region is provided in the P-type region and N-type region constituting the breakdown structure, in a region including the interface in contact with the field insulating film.

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