Substrate structure, multilayer substrate structure, electronic device

Abstract

Reduce thermal stress risks and manufacturing costs. [Solution] The present invention provides a substrate structure comprising a bridge substrate, a functional chip unit, a gap, and a filler. The bridge substrate has a thermal expansion coefficient (CTE) of 10 ppm / °C or less along the horizontal plane, and the bridge substrate has a channel. At least a portion of the functional chip unit is housed within the channel. A gap is formed between the functional chip unit and the bridge substrate. The filler is filled into the gap. By controlling the thermal expansion coefficient of the bridge substrate and integrating the functional chip unit within the channel, the substrate structure of the present invention can effectively address thermal stress problems and improve structural integrity.

Description

Technical Field

[0001] The present invention relates to a substrate structure, which is applicable to the fields of semiconductor packaging or other electronic components.

[0002] As electronic products tend to be lighter, thinner, and smaller, semiconductor packaging technologies are constantly being innovated. These packaging technologies have their own characteristics, but still face many technical bottlenecks and problems. First and foremost, the problem lies in the difference in the coefficient of thermal expansion (CTE) between different materials in the package structure. When an electronic device undergoes temperature changes during operation, internal stress accumulates due to the mismatch in thermal expansion between materials, gradually causing reliability problems such as warping of the structure and interfacial delamination. Secondly, with the improvement of chip functions, conventional electrical connection methods are difficult to meet the requirements of high-speed transmission. Long-distance wiring paths not only cause signal loss but also lead to serious crosstalk interference, potentially limiting the overall transmission bandwidth.

[0003] Furthermore, a purely electrically connected structure limits the potential for future development towards optoelectronic integration. In terms of packaging density, existing technologies often struggle to achieve high-level functional integration within a limited space. In the manufacturing process, existing packaging technologies generally require extremely high alignment accuracy, and the processes are complex. This not only affects the yield but also increases the production cost, and the complex manufacturing processes also enhance the potential risk of failure, affecting the stability and consistency of the products.

[0004] In view of such a situation, in the industry, there is an urgent need for a new type of package structure that can simultaneously solve the above technical problems, manage thermal stress effectively, improve signal transmission efficiency, and enhance integration density, thereby improving the feasibility and reliability of the manufacturing process.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The object of the present invention is to provide a substrate structure and one or more exemplary embodiments thereof, and to explain that the manufacturing method of the substrate structure of the present invention can achieve both a reduction in thermal stress risk and a reduction in manufacturing cost.

[0006] To achieve the above objective, the present invention provides a substrate structure. The substrate structure comprises a bridge substrate having a channel and defining a coefficient of thermal expansion (CTE) of 10 ppm / °C or less along the horizontal plane; a functional chip unit having at least a portion housed within the channel; a gap formed between the functional chip unit and the bridge substrate; and a filler material filling the gap.

[0007] In some embodiments, the bridge substrate is a single-layer substrate.

[0008] In some embodiments, the bridge substrate is a multi-layered board material.

[0009] In some embodiments, the bridge substrate includes glass, silicon dioxide (SiO2), ceramic, glass ceramic, compound semiconductor material, or polyimide (PI), or a combination of one or more of these materials.

[0010] In some embodiments, the channel connects both sides of the bridge substrate.

[0011] In some embodiments, the functional chip unit is housed in a channel, and the bridge substrate and the functional chip unit each define a thickness, with the thickness of the functional chip unit being close to the thickness of the bridge substrate.

[0012] In some embodiments, the thermal expansion coefficient (CTE) of the bridge substrate along the horizontal plane is 8 ppm / °C or less.

[0013] In some embodiments, the thermal expansion coefficient (CTE) of the bridge substrate along the horizontal plane is 4 ppm / °C or less.

[0014] In some embodiments, the functional chip unit approaches the filler material along a horizontal plane.

[0015] In some embodiments, the functional chip unit defines a coefficient of thermal expansion (CTE) along the horizontal plane, and the ratio of the thermal expansion coefficient of the bridge substrate to the thermal expansion coefficient of the functional chip unit is 0.5 or greater.

[0016] In some embodiments, the functional chip unit defines a coefficient of thermal expansion (CTE) along the horizontal plane, and the ratio of the thermal expansion coefficient of the bridge substrate to the thermal expansion coefficient of the functional chip unit is 2.5 or less.

[0017] In some embodiments, the filler defines a coefficient of thermal expansion (CTE) along the horizontal plane, and the coefficient of thermal expansion of the filler is greater than that of the bridge substrate and the functional chip unit.

[0018] In some embodiments, the functional chip unit includes one or more functional chips.

[0019] In some embodiments, the functional chip unit includes one or more bridge dies (BDs), deep trench capacitors (DTCs), voltage regulators (VRs), integrated passive devices (IPDs), electrical integrated circuits (EICs), photonic integrated circuits (PICs), or photoelectric elements, or a combination of one or more of these materials.

[0020] In some embodiments, the photoelectric element includes an optical transmitter and / or an optical sensor.

[0021] In some embodiments, the optical transmitter is a light-emitting diode (LED), an organic light-emitting diode (OLED), or a laser diode (LD).

[0022] In some embodiments, the substrate structure further includes a material property layer. The material property layer is located on one side of the bridge substrate, at least partially covers the gap, and is connected to the filling material.

[0023] In some embodiments, at least two of the material property layer, the filling material, and the bridge substrate include the same material.

[0024] In some embodiments, the material property layer includes polyimide (PI).

[0025] In some embodiments, the material property layer defines a coefficient of thermal expansion (CTE) along the horizontal plane, and the difference between the coefficient of thermal expansion of the material property layer and that of the bridge substrate is 1.3 ppm / °C or less.

[0026] In some embodiments, the material property layer defines a coefficient of thermal expansion (CTE) along the horizontal plane, and the difference between the coefficient of thermal expansion of the material property layer and that of the bridge substrate is 0.7 ppm / °C or more.

[0027] In some embodiments, the material property layer is connected to the bridge substrate and is arranged intermittently (in a consecutive and discontinuous manner) along the horizontal plane of the bridge substrate.

[0028] In some embodiments, the material property layer is connected to the bridge substrate and is arranged in a planar manner along the horizontal plane of the bridge substrate.

[0029] In some embodiments, the substrate structure further includes a conductive member that penetrates the bridge substrate independently of the channel.

[0030] In some embodiments, the substrate structure further includes a layer structure, and at least a part of the layer structure covers one side of the bridge substrate, the gap, and the functional chip unit. Communication is performed between the layer structure and the functional chip unit by at least one of an electrical signal and an optical signal.

[0031] In some embodiments, the substrate structure further includes a conductive member that is electrically connected to the layer structure through the bridge substrate independently of the channel.

[0032] In some embodiments, the layer structure is defined to have a dielectric loss (DF) of 0.006 or less at a frequency of 10 GHz.

[0033] In some embodiments, the layer structure straddles the gap and covers at least a part thereof.

[0034] In some embodiments, the layer structure includes a layer material and a single-layer or multi-layer communication layer that binds to the layer material. The communication layer or at least a part of these communication layers straddles the gap and covers at least a part thereof.

[0035] In some embodiments, the substrate structure further includes another layer structure, and at least a part of the other layer structure covers the other side of the bridge substrate, the gap, and the functional chip unit. Communication is performed between the other layer structure and the functional chip unit by at least one of an electrical signal and an optical signal.

[0036] In some embodiments, the other layer structure is defined to have a dielectric loss (DF) of 0.006 or less at a frequency of 10 GHz.

[0037] In some embodiments, the other layer structure straddles the gap and covers at least a part thereof.

[0038] In some embodiments, the other layer structure includes a layer material and a single-layer or multi-layer communication layer that binds to the layer material. The communication layer or at least a part of these communication layers straddles the gap and covers at least a part thereof.

[0039] In some embodiments, the layer structure includes a waveguide structure, and the waveguide structure is coupled to a functional chip unit.

[0040] In some embodiments, another layer structure includes a waveguide structure, which is coupled to a functional chip unit.

[0041] In some embodiments, one layer structure and another layer structure are asymmetrical.

[0042] In some embodiments, the ratio of the absolute difference in the total volume expansion within the planar area of ​​the bridge substrate between one layer structure and another layer structure is 30% or more.

[0043] In some embodiments, the functional chip unit includes one or more optical transmitters and / or one or more optical sensors.

[0044] In some embodiments, the optical transmitter and / or photodetector are positioned toward the waveguide structure.

[0045] In some embodiments, the functional chip unit has a line width of 1 μm or less on the side facing the layer structure.

[0046] In some embodiments, the functional chip unit has a line spacing of 1 μm or less on the side facing the layer structure.

[0047] In some embodiments, the functional chip unit has a line width of 1 μm or less on the side facing another layer structure.

[0048] In some embodiments, the functional chip unit has a line spacing of 1 μm or less on the side facing another layer structure.

[0049] In some embodiments, the substrate structure further includes conductive members that, independently of the channels, penetrate the bridge substrate and electrically connect one layer structure to another.

[0050] In some embodiments, the substrate structure further includes another material properties layer, which is located between another layer structure and the bridge substrate and connected to the filler.

[0051] In some embodiments, the other material properties layer and the filler are made of the same material.

[0052] In some embodiments, the other material properties layer includes polyimide.

[0053] In some embodiments, another material property layer is connected to the bridge substrate and arranged intermittently along the horizontal plane of the bridge substrate (in a continuous and discontinuous manner).

[0054] In some embodiments, another material properties layer is connected to the bridge substrate and positioned in a planar manner along the horizontal plane of the bridge substrate.

[0055] In some embodiments, the bridge substrate is a multilayer substrate and includes a multilayer board material and a single or multilayer adhesive layer that joins multiple board materials.

[0056] In some embodiments, the conductive member includes a plurality of sub-conductive members that penetrate a plurality of plate materials along a vertical direction perpendicular to the planar direction, and a conductive material that joins two adjacent sub-conductive members.

[0057] In some embodiments, the bridge substrate includes a conductive layer and is arranged on one or at least a portion of a plurality of plate materials, and the conductive member electrically connects one or more corresponding sub-conductive members via the conductive layer.

[0058] In some embodiments, the filler includes silicon dioxide (SiO2), ceramic, glass ceramic, glass frit, glass powder, glass paste, epoxy resin, silicone, or polyimide (PI), or a combination of one or more of these materials.

[0059] In some embodiments, the material properties layer includes silicon dioxide (SiO2), ceramic, glass ceramic, glass frit, glass powder, glass paste, epoxy resin, silicone, or polyimide (PI), or a combination of one or more of these materials.

[0060] In some embodiments, the adhesive layer includes glass frit, glass powder, glass paste, or a combination of one or more of these materials.

[0061] In some embodiments, the substrate structure further includes a temporary carrier substrate, which is connected to a bridge substrate.

[0062] In some embodiments, the substrate structure further includes a temporary carrier substrate, which is connected to the bridge substrate via a layered structure.

[0063] In some embodiments, the temporary carrier substrate is a glass substrate or includes a glass substrate.

[0064] In some embodiments, the bridge substrate defines one or more corners or side edges, the material properties layer is arranged in a planar manner along the horizontal plane of the bridge substrate, and the material properties layer covers at least one side edge.

[0065] In some embodiments, the bridge substrate defines one or more corners or side edges, and a chamfer provided on one of these corners or side edges. The material properties layer is arranged in a planar manner along the horizontal plane of the bridge substrate, and the material properties layer covers the chamfer.

[0066] In some embodiments, the substrate structure further includes conductive members that, independently of the channels, penetrate the bridge substrate and filler material and are electrically connected to the layer structure.

[0067] To achieve the above objectives, the present invention provides a laminated substrate structure. The laminated substrate structure includes a packaging substrate and a substrate structure laminated on the packaging substrate, wherein a functional chip unit of the substrate structure communicates with the packaging substrate with at least one of electrical signals and optical signals.

[0068] In some embodiments, the packaging substrate includes glass, silicon dioxide (SiO2), ceramic, glass ceramic, compound semiconductor material, polyimide (PI), bismaleimide triazine resin (BT), or FR4 substrate, or a combination of one or more of these materials.

[0069] In some embodiments, the packaging substrate includes at least one of a waveguide structure and an electrical layer.

[0070] To achieve the above objective, the present invention provides an electronic device. The electronic device comprises a substrate, a substrate structure laminated on the substrate, a plurality of electronic elements provided on one side of the substrate structure and communicating with a functional chip unit via the layer structure with at least one of electrical signals and optical signals, and a plurality of external conductive structures provided on the other side of the substrate structure and located between the substrate structure and the substrate, electrically connecting the substrate structure and the substrate.

[0071] In some embodiments, the electronic elements may be high-band memory (HBM), switch chips, neural processing units (NPU), tensor processing units (TPU), central processing units (CPU), or graphics processing units (GPU), or a combination of one or more of these elements.

[0072] In some embodiments, one of the electronic elements includes a photodetector or a photoelectric converter, or a combination of one or more of these elements.

[0073] In some embodiments, one of the electronic elements has a line width of 1 μm or less on the surface facing the layer structure.

[0074] In some embodiments, one of the electronic elements has a line spacing of 1 μm or less on the surface facing the layer structure.

[0075] In some embodiments, the electronic device further includes a protective layer that covers these electronic elements and is connected to the substrate structure.

[0076] The above description is illustrative and does not limit the present invention. In addition to the above exemplary embodiments, examples, and features, other embodiments, examples, and features of the present invention can be clearly understood by referring to the drawings and the following detailed description. [Brief explanation of the drawing]

[0077] [Figure 1A] This figure shows a cross-section of the substrate structure 100A according to the first embodiment of the present invention. [Figure 1B] This figure shows a cross-section of substrate structure 100B according to another embodiment of the present invention. [Figure 1C] This figure shows a cross-section of substrate structure 100C according to another embodiment of the present invention. [Figure 1D] This figure shows a cross-section of substrate structure 100D according to another embodiment of the present invention. [Figure 1E] This figure shows a cross-section of a substrate structure 100E according to another embodiment of the present invention. [Figure 2A] This figure shows a cross-section of substrate structure 100F according to an embodiment of the present invention. [Figure 2B] This figure shows a cross-section of substrate structure 100G according to an embodiment of the present invention. [Figure 2C] This figure shows a cross-section of the substrate structure 100H according to an embodiment of the present invention. [Figure 2D] This figure shows a cross-section of the substrate structure 100I according to an embodiment of the present invention. [Figure 2E] This figure shows a cross-section of substrate structure 100J according to an embodiment of the present invention. [Figure 3A] This figure shows a cross-section of substrate structure 200A according to an embodiment of the present invention. [Figure 3B] This figure shows a cross-section of substrate structure 200B according to an embodiment of the present invention. [Figure 3C] This figure shows a cross-section of substrate structure 200C according to an embodiment of the present invention. [Figure 3D] This figure shows a cross-section of substrate structure 200D according to an embodiment of the present invention. [Figure 3E] This figure shows a cross-section of the substrate structure 200E according to an embodiment of the present invention. [Figure 4]This figure shows a cross-section of a laminated substrate structure according to an embodiment of the present invention. [Figure 5A] This figure shows a cross-section of an electronic device I according to an embodiment of the present invention. [Figure 5B] This figure shows a cross-section of electronic device II according to an embodiment of the present invention. [Figure 5C] This figure shows a cross-section of electronic device III according to an embodiment of the present invention. [Figure 5D] This figure shows a cross-section of the electronic device IV according to an embodiment of the present invention. [Figure 6] This figure shows a cross-section of an electronic device V according to an embodiment of the present invention. [Figure 7A] This figure shows a flowchart of a method for manufacturing a substrate structure 100K according to one embodiment of the present invention. [Figure 7B] This figure shows a flowchart of a method for manufacturing a substrate structure 100K according to one embodiment of the present invention. [Figure 7C] This figure shows a flowchart of a method for manufacturing a substrate structure 100K according to one embodiment of the present invention. [Figure 7D] This figure shows a flowchart of a method for manufacturing a substrate structure 100K according to one embodiment of the present invention. [Figure 7E] This figure shows a flowchart of a method for manufacturing a substrate structure 100K according to one embodiment of the present invention. [Figure 7F] This figure shows a flowchart of a method for manufacturing a substrate structure 100K according to one embodiment of the present invention. [Figure 7G] This figure shows a flowchart of a method for manufacturing a substrate structure 100K according to one embodiment of the present invention. [Figure 8A] This figure shows a cross-section of substrate structure 100L according to an embodiment of the present invention. [Figure 8B] This figure shows a cross-section of substrate structure 100M according to an embodiment of the present invention. [Figure 8C] This figure shows a cross-section of substrate structure 100N according to an embodiment of the present invention. [Modes for carrying out the invention]

[0078] The following describes a better embodiment of the substrate structure of the present invention with reference to the drawings, and the same elements are denoted by the same reference numerals.

[0079] The advantages and features of the present invention and methods for realizing the present invention will be clearly described in the following embodiments with reference to the drawings. However, the present invention can be embodied in several different forms and should not be construed as being limited to the following embodiments. On the contrary, the embodiments disclosed below are provided to clarify and complete this specification and to fully convey the scope of the claims of the present invention to those skilled in the art, and the present invention is limited only to the claims. For this reason, prior components, operations and techniques are not described in detail in the embodiments to avoid obscuring the technical features of the present invention. Throughout the specification, identical or approximate elements are denoted by the same or approximate reference numerals. Throughout the specification, when it is mentioned that one element is “connected” to another element, that element is “directly or indirectly mechanically connected” to the other element, or “electrically connected” to the other element, and further permits the insertion of one or more intermediate elements between them. Furthermore, it should be understood that in this specification, the terms “includes” or “composes” specify the described features, integers, steps, operations, elements and / or assemblies, and do not preclude the presence or addition of one or more other features, integers, steps, operations, elements and / or assemblies, or combinations thereof. The terms "and / or" indicate the possibility of an intersection or union. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those commonly understood by those skilled in the art. It should be understood further that terms or terms (e.g., terms or terms defined in the claims or in common dictionaries) should be interpreted as having the same meaning in the description of the relevant technology, and not as an ideal or overly formal meaning unless explicitly defined herein.

[0080] Please refer to Figure 1A. Figure 1A shows a substrate structure 100A of a first embodiment of the present invention. The substrate structure 100A comprises a bridge substrate 10, a functional chip unit 20, a gap 30, and a filler material 40. The bridge substrate 10 defines a coefficient of thermal expansion (CTE) of 8 ppm / °C or less along the horizontal plane (XY plane); the bridge substrate 10 has a channel 35. At least a portion of the functional chip unit 20 is housed in the channel 35. The gap 30 is formed between the functional chip unit 20 and the bridge substrate 10. The filler material 40 fills the gap 30.

[0081] The bridge substrate 10 is a single-layer substrate or a multilayer substrate (e.g., a multilayer substrate). In some embodiments, the bridge substrate 10 includes an organic material, or at least one layer of the bridge substrate 10 includes an organic material. In some embodiments, the bridge substrate 10 includes glass, silicon dioxide (SiO2), ceramic, glass ceramic, compound semiconductor material, or polyimide (PI), or a combination of one or more of these materials. As shown in the figure, the number of channels 35 is not limited to one, and the number of corresponding elements increases accordingly. The channels 35 may connect both sides of the bridge substrate 10, or at least one side of the bridge substrate 10, or they may not connect both sides of the bridge substrate 10, and are not limited to these.

[0082] The functional chip unit 20 includes one or more chips, which are housed in the channel 35 in a modular or non-modular form, with the bridge substrate 10 and the functional chip unit 20 each defining a thickness, and the thickness of the functional chip unit 20 being close to the thickness of the bridge substrate 10. Typically, the thickness of the functional chip unit 20 does not exceed the thickness of the bridge substrate 10, as this is advantageous for subsequent processes when the functional chip unit 20 is fully housed in the channel 35. The functional chip unit 20 is in contact with the filler material 40 along the horizontal plane. The functional chip unit 20 includes, but is not limited to, one or more bridge dies (BDs), deep trench capacitors (DTCs), voltage regulators (VRs), integrated passive devices (IPDs), electrical integrated circuits (EICs), photonic integrated circuits (PICs), or photoelectric elements, or a combination of one or more of these materials. A photoelectric element includes an optical transmitter and / or an optical sensor. The optical transmitter is a light-emitting diode (LED), an organic light-emitting diode (OLED), or a laser diode (LD).

[0083] The filler 40 includes silicon dioxide (SiO2), ceramic, glass ceramic, glass frit, glass powder, glass paste, epoxy resin, silicone, or polyimide (PI), or a combination of one or more of these materials.

[0084] In the substrate structure 100B of Figure 1B, the substrate structure 100B further includes a material properties layer 60, which is located on at least one side of the bridge substrate 10 and connected to the filler 40; the material properties layer 60 may cover at least a portion of the gap 30. The material properties layer 60 includes glass, silicon dioxide (SiO2), ceramic, glass ceramic, glass frit, glass powder, glass paste, compound semiconductor material, epoxy resin, silicone, or polyimide (PI), or a combination of one or more of these materials. In one embodiment, at least two of the material properties layer 60, filler 40, and bridge substrate 10 may include the same or different materials, such as, but are not limited to, polyimide, epoxy resin, or silicone. The material properties layer 60 is connected to the bridge substrate 10 and is arranged intermittently (in a consecutive and discontinuous manner) along the horizontal plane of the bridge substrate 10, or in a planar manner along the horizontal plane of the bridge substrate 10. As shown in Figure 1B, the material properties layer 60 is arranged intermittently along the horizontal plane of the bridge substrate 10. Furthermore, the substrate structure 100B further includes a conductive member 70 that penetrates the bridge substrate 10 independently of the channel 35. The conductive member 70 may be a single structure or a composite structure combining multiple sub-elements.

[0085] In the substrate structure 100C shown in Figure 1C, the two material property layers 60 and 60A are provided on opposite sides of the bridge substrate 10. The conductive member 70A is independent of the channel 35 and penetrates the bridge substrate 10. The two material property layers 60 and 60A are arranged intermittently along the horizontal plane of the bridge substrate 10, and at least a portion of them covers the channel 35.

[0086] In the substrate structure 100D shown in Figure 1D, the material properties layer 60B is arranged in a plane along the horizontal plane of the bridge substrate 10, and the material properties layer 60B may be attached to the bridge substrate 10 in the form of a thin plate or thin film.

[0087] In the substrate structure 100E shown in Figure 1E, the two material property layers 60B and 60C are provided on opposite sides of the bridge substrate 10, respectively, and are arranged in a planar manner along the horizontal plane of the bridge substrate 10.

[0088] All of the above embodiments are combinable.

[0089] The difference between the series in Figure 2 and the series in Figure 1 lies in the presence or absence of a layered structure. This will be explained in detail below.

[0090] Please refer to Figure 2A. Figure 2A shows a substrate structure 100F of the first embodiment of the present invention. The substrate structure 100F comprises a bridge substrate 10, a functional chip unit 20, a gap 30, a filler material 40, and a layer structure 50. The bridge substrate 10 defines a coefficient of thermal expansion (CTE) of 8 ppm / °C or less along the horizontal plane (XY plane); it has a channel 35 connecting both sides of the bridge substrate 10. At least a portion of the functional chip unit 20 is housed in the channel 35. The gap 30 is formed between the functional chip unit 20 and the bridge substrate 10. The filler material 40 fills the gap 30. At least a portion of the layer structure 50 covers one side of the bridge substrate 10, the gap 30, and the functional chip unit 20. Communication between the layer structure 50 and the functional chip unit 20 is conducted using at least one of electrical signals and optical signals. In this embodiment, the layer structure 50 is located on the same side (bottom) as the bridge substrate 10, the gap 30, and the functional chip unit 20.

[0091] The layer structure 50 spans the gap 30 and covers at least a portion of it. The layer structure 50 includes single-layer or multi-layer layer material, and at least one layer material and the material of the bridge substrate 10 are the same material. The layer structure 50 includes the layer material and a single-layer or multi-layer communication layer coupled to the layer material. In some embodiments, the functional chip unit 20 has a line width of 1 μm or less on the side facing the layer structure 50. The functional chip unit 20 has a line spacing of 1 μm or less on the side facing the layer structure 50. The layer structure 50 is defined to have a dielectric loss (DF) of 0.006 or less at a frequency of 10 GHz. In Figure 2A, the layer structure 50 includes the layer material and a communication layer 51 coupled to the layer material, the communication layer 51 being an electrical layer and electrically connected to the functional chip unit 20.

[0092] The thermal expansion coefficient (CTE) of the bridge substrate 10 along the horizontal plane may be 4 ppm / °C or less. Furthermore, the thermal expansion coefficient (CTE) of the functional chip unit 20 can be defined along the same horizontal plane. In one embodiment, the ratio of the thermal expansion coefficient of the bridge substrate 10 to the thermal expansion coefficient of the functional chip unit 20 is 0.5 or more. In another embodiment, the ratio of the thermal expansion coefficient of the bridge substrate 10 to the thermal expansion coefficient of the functional chip unit 20 can be further defined as 2.5 or less. The thermal expansion coefficient (CTE) of the filler material 40 can be defined along the horizontal plane. The thermal expansion coefficient of the filler material 40 is greater than the thermal expansion coefficient of the bridge substrate 10 and the thermal expansion coefficient of the functional chip unit 20.

[0093] In the substrate structure 100G of Figure 2B, the layer structure 50A includes a communication layer which is a redistribution layer (RDL). The substrate structure 100G further includes a material properties layer 60, which is located on at least one side of the bridge substrate 10 and connected to the filler 40. The material properties layer 60 may be located between the layer structure 50A and the bridge substrate 10, and at least a portion of the material properties layer 60 may cover the gap 30. The material properties layer 60 and the filler 40 may be made of the same material (for example, materials of the same material placed in separate processes, or a portion of the material properties layer 60 extending from the filler 40); the material properties layer 60 may be made of the same material as the bridge substrate 10 (for example, materials of the same material placed in separate processes). Refer to the above for the material or combination of material properties layer 60. The material properties layer 60 can be located on the same side or opposite side of the layer structure 50A and the bridge substrate 10. The material properties layer 60 is connected to the bridge substrate 10 and is arranged intermittently along the horizontal plane of the bridge substrate 10, or in a planar manner along the horizontal plane of the bridge substrate 10. As shown in Figure 2B, the material properties layer 60 is arranged intermittently along the horizontal plane of the bridge substrate 10. The substrate structure 100G further includes a conductive member 70, which, independently of the channel 35, penetrates the bridge substrate 10 and is electrically connected to the redistribution layer (RDL) of the layer structure 50A.

[0094] In the substrate structure 100H of Figure 2C, the two material property layers 60 and 60A are provided on opposite sides of the bridge substrate 10, respectively, and in this embodiment, material property layer 60A is located between the bridge substrate 10 and the layer structure 50B. Furthermore, the layer structure 50B includes a communication layer, which includes at least a redistribution layer (RDL) and a plurality of conductive members 70C that penetrate the layer structure 50B and are electrically connected to the functional chip unit 20. As described above, the layer structure 50B includes a layer material laminated in single or multi-layer layers and a single or multi-layer communication layer bonded to the layer material. The communication layer includes a redistribution layer (RDL) and conductive members 70C that are electrically connected along the Z direction. Conductive member 70A is electrically connected to the redistribution layer (RDL) of the layer structure 50B. In this embodiment, the conductive members 70C are arranged corresponding to the functional chip unit 20, and the redistribution layer (RDL) is arranged between the functional chip unit 20 and at least a portion of the bridge substrate 10.

[0095] In the substrate structure 100I of Figure 2D, the material properties layer 60B is arranged in a planar manner along the horizontal plane of the bridge substrate 10. Furthermore, the layer structure 50C includes a layer material stacked in single or multi-layers and a single or multi-layer communication layer coupled to the layer material. The communication layer includes at least an electrical layer and an optical layer. The electrical layer is a redistribution layer (RDL) electrically connected to a conductive member 70A provided on the bridge substrate 10; the optical layer is a waveguide structure 55 coupled to the functional chip unit 20 via an optical channel 80.

[0096] In the substrate structure 100J of Figure 2E, the two material property layers 60A and 60C are provided on opposite sides of the bridge substrate 10, respectively, and are arranged planarly along the horizontal plane of the bridge substrate 10. Furthermore, the layer structure 50D includes a layer material laminated in single or multi-layer layers, and a single or multi-layer communication layer coupled to the layer material. The communication layer includes at least an electrical layer and an optical layer. The electrical layer is a redistribution layer (RDL) electrically connected to a conductive member 70A provided on the bridge substrate 10 and a conductive member 70B of the functional chip unit 20; the optical layer is a waveguide structure 55 coupled to the functional chip unit 20 via an optical channel 80. In some embodiments, the material property layer 60 is connected to the layer structure 50D, and the layer materials of the material property layer 60 and the layer structure 50D may be made of different materials and formed by different processes, or they may be made of the same material and formed by the same process. In another embodiment, the material properties layer 60 can define a coefficient of thermal expansion (CTE) along the horizontal plane, and the difference between the coefficient of thermal expansion of the material properties layer 60 and the coefficient of thermal expansion of the bridge substrate 10 is 1.3 ppm / °C or less. In yet another embodiment, the difference between the coefficient of thermal expansion of the material properties layer 60 and the coefficient of thermal expansion of the bridge substrate is 0.7 ppm / °C or more. In some embodiments in which the layer structure 50 is integrated into the material properties layer 60, the coefficient of thermal expansion of the material properties layer 60 can be broadly interpreted as the equivalent coefficient of thermal expansion of the material properties layer 60 and the layer structure 50, and at the same time, the bridge substrate 10 at this point refers to the equivalent coefficient of thermal expansion generated as a multilayer substrate, and the difference between the equivalent coefficient of thermal expansion of the material properties layer 60 and the equivalent coefficient of thermal expansion of the bridge substrate 10 is 1.3 ppm / °C or less. In another embodiment, the difference between the equivalent coefficient of thermal expansion of the material properties layer 60 and the equivalent coefficient of thermal expansion of the bridge substrate is 0.7 ppm / °C or more. It should be noted that this explanation does not describe the necessary examples, but merely illustrates the equivalent thermal expansion coefficients derived from uniformly multilayered structures and their integration.

[0097] All of the above embodiments are combinable.

[0098] The series in Figure 3 illustrates the diversity of the bridge substrate body. In the substrate structure 200A of Figure 3A, the bridge substrate 10A is a multilayer substrate and includes a multilayer board material 220 and a single or multilayer adhesive layer 240 that joins multiple board materials. The bridge substrate 10A further has an electrical layer 260 placed on the outermost part of the board material 220, and this electrical layer 260 may be placed as an independent element coupled to the bridge substrate 10A, or it may be a layer structure combined with the bridge substrate 10A. To make it easier to understand, if we take the arrangement in which the electrical layer 260 is coupled to the bridge substrate 10A as an example, the electrical layer 260 can be coupled to the bridge substrate 10A via the adhesive layer 240. The functional chip unit 20 is placed in the channel of the bridge substrate 10A as in the embodiment described above. The plate material 220 is, for example, polyimide (PI), and the adhesive layer 240 includes glass frit, glass powder, glass paste, or a combination of one or more of these materials.

[0099] In the substrate structure 200B of Figure 3B, the conductive member 70 penetrates the bridge substrate 10B and connects the upper and lower sides of the bridge substrate 10B. The conductive member 70 here is a single structure and electrically connects the electrical layers 260 on both the upper and lower sides.

[0100] In the substrate structure 200C of Figure 3C, the conductive member 70C penetrates the bridge substrate 10C and connects the upper and lower sides of the bridge substrate 10C. The conductive member 70C here is a composite structure and electrically connects the electrical layers 260 on both the upper and lower sides. The conductive member 70C includes a plurality of sub-conductive members 72 that penetrate a plurality of plate materials 220 along the vertical direction Z perpendicular to the planar direction, and a conductive member 74 that joins two adjacent sub-conductive members 72.

[0101] In the substrate structure 200D of Figure 3D, the electrical layer 260 is bonded to the bridge substrate 10D (where there is no adhesive layer 240 adjacent to the electrical layer 260) without an adhesive layer 240, and the conductive member 70D penetrates the bridge substrate 10D and connects the upper and lower sides of the bridge substrate 10D. The conductive member 70D here is a composite structure and electrically connects the electrical layers 260 on both the upper and lower sides. The bridge substrate 10D includes one or more conductive layers 280, and the plurality of conductive layers 280 are arranged on the inner surface of one plate material 220, or at least some of the plate materials 220. The conductive member 70D includes a plurality of sub-conductive members 72A that penetrate the plurality of plate materials 220 along a vertical direction Z perpendicular to the planar direction, and a conductive member 74A that electrically connects the corresponding one or more sub-conductive members 72A via the conductive layer 280.

[0102] The difference between the substrate structure 200E in Figure 3E and the substrate structure 200D in Figure 3D is that the electrical layer 260 is located on only one side of the bridge substrate 10E.

[0103] All of the above embodiments are combinable.

[0104] Figure 4 shows a laminated substrate structure, with substrate structure 100H as an example, but is not limited to this, and is further coupled to a packaging substrate 900. Substrate structure 100H is laminated on the packaging substrate 900, and the functional chip unit 20 of the substrate structure communicates with the packaging substrate 900 with at least one of electrical signals and optical signals. The packaging substrate 900 includes glass, silicon dioxide (SiO2), ceramic, glass ceramic, compound semiconductor material, polyimide (PI), bismaleimide triazine resin (BT), or FR4 substrate, or a combination of one or more of these materials. The packaging substrate 900 includes at least one of an optical layer and an electrical layer. All drawings in this embodiment show electrical signals as an example.

[0105] All of the above embodiments are combinable.

[0106] Figures 5A and 5B show electronic devices I and II, which comprise a substrate structure, a plurality of electronic elements provided on one side of the substrate structure, and a plurality of external conductive structures provided on the other side of the substrate structure.

[0107] As shown in Figure 5A, the electronic device I comprises a substrate structure 300A, a plurality of electronic elements 200 provided on one side of the substrate structure 300A, a plurality of external conductive structures 310 provided on the other side of the substrate structure 300A, and a protective layer 500 (not an essential element) that covers the plurality of electronic elements 200 and is connected to the substrate structure 300A. The substrate structure 300A comprises a bridge substrate 10F, one or more functional chip units 20B, one or more gaps 30A corresponding to these functional chip units 20B, one or more fillers 40A corresponding to these functional chip units 20B, and two-layer structures 50A arranged on both sides of the bridge substrate 10F. In some embodiments, the two-layer structure 50A is symmetrical. In this embodiment, the two-layer structure 50A is asymmetrical, and the meaning of the asymmetrical structure is that it exhibits asymmetry in the electrical structure or non-electrical structure with the bridge substrate as the central axis. This includes a redistribution layer (RDL) or build-up layer, and ABF (Ajinomoto Buildup Film) can be used as an example, but is not limited to this embodiment. Also, for example, the ratio of the absolute difference in the total volume expansion within the planar range of the bridge substrate between layer structure 50X and layer structure 50Y' is 30% or more. Each layer structure is not limited to a single layer, and each layer material undergoes volume expansion during temperature change intervals, and in the case of multilayer materials, it is the sum of these volume expansions during similar temperature change intervals. When comparing two layer structures, there is an absolute difference ratio, and for example, if the difference is taken as the numerator and the smaller volume expansion change as the denominator, this absolute difference ratio is 30% or more. In this embodiment, the layer structure 50A is an electrical layer (all are redistribution layers as examples), the functional chip unit 20B is a single bridge chip as an example, the external conductive structure 310 is an underbump metal layer (UBM) and a copper bump as examples, and the conductive member 70G and the functional chip unit 20B, which are placed on the bridge substrate 10F, are electrically connected to the layer structure 50A provided on opposite sides of the bridge substrate 10F.The layer structures 50A on both sides of the bridge substrate 10F have progressively changing line widths or line spacings, and one of the electronic elements 200 has a line width of 1 μm or less on the side facing the layer structure 50A; the other electronic element 200 has a line spacing of 1 μm or less on the side facing the layer structure 50A. The electronic element 200 is a functional chip and may be a high-band memory (HBM), a switch chip, a neural processing unit (NPU), a tensor processing unit (TPU), a central processing unit (CPU), or a graphics processing unit (GPU), or a combination of one or more of these elements. Alternatively, the electronic element 200 may include a photodetector, a photoelectric converter, or a combination of one or more of these elements. These embodiments are combinable.

[0108] As shown in Figure 5B, the electronic device II comprises a substrate structure 300B, a plurality of electronic elements 200 provided on one side of the substrate structure 300B, a plurality of external conductive structures 310 provided on the other side of the substrate structure 300B, and a protective layer 500 (not an essential element) that covers the plurality of electronic elements 200 and is connected to the substrate structure 300B. The substrate structure 300B comprises a bridge substrate 10F, one or more functional chip units 20B, one or more gaps 30A corresponding to these functional chip units 20B, one or more fillers 40A corresponding to these functional chip units 20B, and a layer structure 50A disposed on one side of the bridge substrate 10F and a layer structure 50B disposed on the other side. The layer structure 50A is an electrical layer (partially a rewiring layer, partly including a plurality of conductive members 70F), and the layer structure 50B is an insulating layer. The layer structure 50A and / or the layer structure 50B are defined as having a dielectric loss (DF) of 0.006 or less at a frequency of 10 GHz. These conductive members 70F of the layer structure 50A are arranged in correspondence with these functional chip units 20B. The functional chip unit 20B is exemplified by a single bridge chip, and the external conductive structure 310 is exemplified by an underbump metal layer (UBM) and copper bumps. The conductive members 70G and functional chip units 20B arranged on the bridge substrate 10F are electrically connected to the layer structure 50A on one side of the bridge substrate 10F and to the external conductive structure 310 on the other side. The layer structure 50A on one side of the bridge substrate 10F has a stepped line width or line spacing, and one of the electronic elements 200 has a line width of 1 μm or less on the surface facing the layer structure 50A; the other electronic element 200 has a line spacing of 1 μm or less on the surface facing the layer structure 50A.The electronic element 200 is a functional chip and may be a high-band memory (HBM), a switch chip, a neural processing unit (NPU), a tensor processing unit (TPU), a central processing unit (CPU), or a graphics processing unit (GPU), or a combination of one or more of these elements. Alternatively, the electronic element 200 may include a photodetector, a photoelectric converter, or a combination of one or more of these elements. These embodiments are combinable.

[0109] Figures 5C and 5D show electronic devices III and IV, which comprise substrate structures 300C and 300D, a plurality of electronic elements provided on one side of substrate structures 300A and 300B, a plurality of external conductive structures 310 provided on the other side of substrate structures 300C and 300D, and a packaging substrate 900 electrically connected to these external conductive structures 310. Compared to electronic devices I and II in Figures 5A and 5B, electronic devices III and IV differ in that the packaging substrate 900 is added. In other words, substrate structures 300C and 300D each include substrate structures 300A and 300B and the packaging substrate 900. Similarly, the packaging substrate 900 includes glass, silicon dioxide (SiO2), ceramic, glass ceramic, compound semiconductor material, polyimide (PI), bismaleimide triazine resin (BT), or FR4 substrate, or a combination of one or more of these materials.

[0110] The electronic device V in Figure 6 comprises a substrate structure 300E, a plurality of electronic elements 600 provided on one side of the substrate structure 300E, a plurality of external conductive structures 310A provided on the other side of the substrate structure 300E, and a substrate 400A that electrically connects these external conductive structures 310A. The substrate structure 300E comprises a bridge substrate 10G, one or more functional chip units 20C, one or more gaps (not shown) corresponding to these functional chip units 20C, one or more fillers 40B corresponding to these functional chip units 20C, and two-layer structures 50G and 50H arranged on both sides of the bridge substrate 10G, respectively. The layer structures 50G and 50H are exemplified by single-layer electrical layers, the functional chip unit 20C is exemplified by two functional chip units 20D and 20E, the external conductive structure 310A is exemplified by a copper bump, the conductive member 70H electrically connects the layer structures 50G and 50H on both sides of the bridge substrate 10G, the substrate 400A is a multilayer structure of at least two layers 410 and 420, and includes an electrical layer 250A corresponding to the external conductive structure 310A and a waveguide structure 55A corresponding to these functional chip units 20C. The functional chip unit 20E is a photoelectric conversion element array and includes at least a light-emitting element array 20EA and a light-receiving element array 20EB. The functional chip unit 20D is a photoelectric conversion driving circuit. The electronic element 600 is a semiconductor main chip. The functional chip unit 20D electrically connects the functional chip unit 20E and the electronic element 600. The waveguide structure 55A can be directly or indirectly connected to the substrate structure 300E and defines an optical coupling region 55B that is coupled in correspondence with the light-emitting element array 20EA and the photodetector array 20EB. The photoelectric conversion element array transmits and receives optical signals to and from the waveguide structure 55A and is electrically driven by the functional chip unit 20D to perform conversion between optical signals and electrical signals. The optical coupling region 55B is further provided with a fine uneven structure 444 to improve coupling efficiency. In this embodiment, the electronic element 600 defines a vertical direction, and at least a portion of the electronic element 600, at least a portion of the functional chip unit 20D, at least a portion of the functional chip unit 20E and at least a portion of the waveguide structure 55A are arranged along the vertical direction of the electronic element 600 and are further arranged sequentially along the vertical direction.The embodiment shown in Figure 3 can be combined with the previous embodiment, for example, to arrange different functional chip units horizontally or stacked vertically.

[0111] Figures 7A to 7G show, but are not limited to, one method for manufacturing the substrate structure 100K of the present invention. In Figures 7A to 7C, one side of the bridge substrate 10H is pre-placed on a carrier layer 930 having a thin metal film 920 via a bonding sheet 910, and a sacrificial film 940 is placed on the other side of the bridge substrate 10H. Laser drilling is performed from the other side of the bridge substrate 10H, reaching and stopping at the thin metal film 920 to form a seed layer 950 in the hole, and then electroplating is performed. After forming a conductive member 960 to a certain extent by electroplating, the carrier layer 930 can be removed and an electrical layer 970 can be further placed on the thin metal film 920. Furthermore, a patterning process is performed on the thin metal film 920 (and its electrical layer 970). As shown in Figures 7D to 7G, at this point, the semi-finished product with the carrier layer 930 removed is moved to a temporary carrier board 980, which may be a rigid substrate such as a glass substrate. Channels 35 are provided in the bridge substrate 10H, and the functional chip unit 20 is placed in the channels 35 to simultaneously complete the filler and material property layers (in this embodiment, this is collectively referred to as epoxy molding compound molding (EMC molding) 990). In the pre-process, intermediate process, and post-process of the epoxy molding compound molding process, optical / telecommunication-related manufacturing processes can be carried out on the functional chip unit 20. Furthermore, by grinding the surface of the epoxy molding compound molding 990, at least the electrical communication parts (for example, the conductive member 960 and the terminal 960A of the functional chip unit 20) are exposed. Finally, the substrate structure 100K is obtained by removing the temporary carrier board 980. It should be noted that commercially available intermediate product structures include at least Figure 7G, and the bridge substrate 10H and the primary carrier substrate 980 can be considered intermediate structures of the bridge substrate.

[0112] In the substrate structures 100L, 100M, and 100N shown in Figures 8A to 8C, the bridge substrate defines one or more corners or side edges and a chamfer positioned on one of these corners or side edges, and the material properties layer is positioned plane along the horizontal plane of the bridge substrate and covers one or more of the corners or side edges of one or more bridge substrates (the bridge substrates are joined to each other). In substrate structure 100L, the bridge substrate 10J defines one or more outer corners 81, inner corners 82 or outer upper and lower side edges 84, outer peripheral side edge 85, and inner peripheral side edge 86. It should be understood that the inner corners 82 and inner peripheral side edge 86 are located in channel 35. In this embodiment, the chamfer is located on an outer corner (reference numeral 81A, to distinguish it from an outer corner 81 without a chamfer), the material properties layer 60D covers the chamfer 83, and the material properties layer 60D further includes at least one of the outer upper and lower side edges 84 and the outer peripheral side edge 85, and in particular includes the outer peripheral side edge 85. The chamfer 83 of the bridge substrate 10J is positioned on only one of the outer corners 81A. Specifically, the layer structure 50G includes an electrical layer 260B and an optical layer (waveguide structure 55C), and the functional chip unit 20 has photoelectric properties; in this embodiment, the chamfer 83 of the bridge substrate 10J is positioned on the outer corner 81A facing the layer structure 50G. In this embodiment, the bridge substrate 10J is provided with an additional layer structure 50J in addition to the layer structure 50G, and these two layer structures 50G and 50J are positioned on opposite sides of the bridge substrate 10J, respectively, with an asymmetrical arrangement being used as an example. For example, the layer structure 50G is a redistribution layer (RDL), and the layer structure 50J is a build-up layer, but the embodiment is not limited to this.

[0113] In substrate structure 100M, the difference between bridge substrate 10K and bridge substrate 10J is that the chamfer 83 of bridge substrate 10K is located on the opposing outer corners 81A of both sides of bridge substrate 10K; the material properties layer 60E covers the chamfer 83, and the material properties layer 60E further includes at least one of the outer upper and lower side edges 84 and the outer peripheral side edge 85, in particular including the outer peripheral side edge 85. Furthermore, in substrate structure 100L, the conductive member 70I penetrates directly through bridge substrate 10J independently of the channel. In substrate structure 100M, the conductive member 70J further penetrates the filler material 40C of bridge substrate 10K. In other words, in the through-hole of bridge substrate 10K in substrate structure 100M, the filler material 40C for passing the conductive member 70J can be placed first and electrically connected to the layer structure 50H. The layer structure 50H similarly includes an electrical layer 260C and an optical layer (waveguide structure 55D), and the functional chip unit 20 similarly has photoelectric properties. Furthermore, in the substrate structure 100M, the conductive member 70I is provided penetrating the material properties layer 60N connected to the bridge substrate 10K.

[0114] In the substrate structure 100N, the difference between the bridge substrate 10L and the bridge substrate 10K is that the chamfer 83 of the bridge substrate 10L is further positioned at the inner corner 82A of the bridge substrate 10L; the material properties layer 60E covers the chamfer 83, and the material properties layer 60E further includes at least one of the outer upper and lower side edges 84 and the outer peripheral side edge 85, particularly including the outer peripheral side edge 85. Furthermore, the chamfer 83 is provided in through holes where the filler 40D and conductive member 70K are positioned. Here, the conductive member 70K is electrically connected to the layer structure 50I by penetrating the bridge substrate 10L, the filler 40D and the material properties layer 60F independently of the channel. It should be noted that the material properties layer and the filler can be formed simultaneously on the bridge substrate, and subsequent processes are carried out after the through holes and channels are positioned on the bridge substrate, material properties layer and filler. The material properties layer and the filler may be made of the same material or different materials. Furthermore, as shown in Figure 5, the material properties layer, filler, and protective layer may be made of the same material or different materials. In addition, the difference between the bridge substrate 10L and the bridge substrate 10K is that the functional chip unit 20F includes the first chip 20G and the second chip 20J, the first chip 20G is electrically connected to the electrical layer 260D of the layer structure 50I, and the second chip 20J is electrically connected to the electrical layer 260D of the layer structure 50I and the waveguide structure 55E.

[0115] As described above, various embodiments of the present invention are described in the specification for illustrative purposes and various modifications are possible without departing from the scope and spirit of the invention. Therefore, it should be understood that these various embodiments do not limit the true scope and spirit of the invention.

[0116] The above are illustrative and not limiting. All equivalent modifications or changes made without departing from the spirit and scope of the present invention should be included in the claims. [Explanation of Symbols]

[0117] 100A~100N, 200A~200E, 300A~300E Circuit board structure 10, 10A~10L Bridge board 20, 20B~20F Functional Chip Unit 20EA light-emitting element array 20EB photodetector array 20G 1st chip 20J 2nd chip 30, 30A gap 35 channels 40, 40A~40D Filling material 50, 50A~50D, 50G~50J, 50X, 50Y' layer structure 51 Communication Layer 55, 55A, 55C~55E waveguide structure 55B Optical coupling area 60, 60A~60F, 60N material characteristic layer 70, 70A~70K, 72, 72A, 960 Conductive material 74, 74A conductive material 80 optical channels 81, 81A outside corner 82, 82A Interior angle 83 Chamfering 84 Upper and lower outer edges 85 Outer edge 86 Inner circumferential edge 200, 600 electronic elements 220 Board material 240 Adhesive layer 250A, 260, 260B~260D, 970 Electrical layers 280 Conductive layer 310, 310A external conductive structure 400A circuit board 410, 420 layers 444 Fine uneven structure 500 protective layer 900 Packaging substrates 910 Bonding Sheet 920 Thin metal layer 930 Career Level 940 layers of victims 950 seed layer 960A terminal 980 Temporary carrier substrate 990 Epoxy Molding Compound I, II, III, IV, V Electronic equipment X, Y, Z directions

Claims

1. A bridge substrate having a channel and defining a coefficient of thermal expansion (CTE) of 10 ppm / °C or less along the horizontal plane, A functional chip unit, at least a portion of which is housed within the channel, The gap formed between the functional chip unit and the bridge substrate, A substrate structure characterized by comprising a filler material that fills the gaps.

2. The substrate structure according to claim 1, characterized in that the bridge substrate has a coefficient of thermal expansion (CTE) of 8 ppm / °C or less along the horizontal plane.

3. The substrate structure according to claim 1, characterized in that the functional chip unit defines a coefficient of thermal expansion (CTE) along the horizontal plane, and the ratio of the coefficient of thermal expansion of the bridge substrate to the coefficient of thermal expansion of the functional chip unit is 0.5 or more and / or 2.5 or less.

4. The substrate structure according to claim 1, further comprising a material properties layer, wherein the material properties layer is located on one side of the bridge substrate, at least a portion of which covers the gap and is connected to the filler.

5. The substrate structure according to claim 4, characterized in that the material properties layer defines a coefficient of thermal expansion (CTE) along the horizontal plane, and the difference between the coefficient of thermal expansion of the material properties layer and the coefficient of thermal expansion of the bridge substrate is 1.3 ppm / °C or less and / or 0.7 ppm / °C or more.

6. The substrate structure according to claim 1, further comprising a layer structure, wherein at least a portion of the layer structure covers the bridge substrate, the gap, and one side of the functional chip unit, and communication between the layer structure and the functional chip unit is performed between at least one of electrical signals and optical signals.

7. The substrate structure according to claim 6, further comprising another layer structure, wherein at least a portion of the other layer structure covers the bridge substrate, the gap and the other side of the functional chip unit, and communication between the other layer structure and the functional chip unit is performed between at least one of electrical signals and optical signals.

8. The substrate structure according to claim 7, characterized in that the ratio of the absolute difference in the total volume expansion of the aforementioned layer structure and the other layer structure within the planar range of the bridge substrate is 30% or more.

9. The substrate structure according to claim 6, characterized in that the functional chip unit has a line width of 1 μm or less on the side facing the layer structure.

10. The substrate structure according to claim 4, wherein the bridge substrate defines one or more corners or side edges, the material properties layer is arranged in a plane along the horizontal plane of the bridge substrate, and the material properties layer covers at least one side edge.

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