Capacitor and method for manufacturing the same

Abstract

To provide a capacitor with low process costs and a method for manufacturing the same. [Solution] The capacitor comprises a substrate 1 having a first main surface 10, a second main surface 11 facing in the opposite direction to the first main surface 10, and a groove 2 penetrating the first main surface 10 and the second main surface 11; at least one first conductive layer 3 formed along the first main surface 10 and the side surface 20 of the groove 2; at least one second conductive layer 4 formed along the second main surface 11 and the side surface 20 of the groove 2; at least one dielectric layer 5 formed along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2; a first electrode 7 electrically connected to the first conductive layer 3 on the first main surface 10; and a second electrode 8 electrically connected to the second conductive layer 4 on the second main surface 11. The first conductive layer 3 and the second conductive layer 4 are alternately stacked with the dielectric layer 5 in between, and the first conductive layer 3 and the second conductive layer 4 are electrically insulated.

Description

Technical Field

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[0001] The present invention relates to a capacitor and a method for manufacturing the same.

Background Art

[0002] Conventionally, a capacitor in which a conductive layer and a dielectric layer are laminated inside a groove formed in a semiconductor substrate is known. Patent Document 1 discloses a substrate having a first surface, a second surface separated from the first surface, and a through-opening extending between the first surface and the second surface, a first metal element that can be exposed on the first surface and extend into the through-opening, a second metal element that can be exposed on the second surface and extend into the through-opening, and a capacitor dielectric layer that at least insulates the first metal element and the second metal element from each other within the through-opening.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, when forming the first electrode connected to the first metal element on the first surface and the second electrode connected to the second metal element on the second surface, there is a step of removing a part of the unnecessary first metal element and second metal element adjacent to the first surface and the second surface, and the process cost is high.

[0005] The present invention has been proposed in view of the above circumstances, and an object thereof is to provide a capacitor and a method for manufacturing the same with a low process cost.

Means for Solving the Problems

[0006] A capacitor according to one aspect of the present invention comprises a substrate having a first main surface, a second main surface facing in the opposite direction to the first main surface, and a groove penetrating the first main surface and the second main surface; at least one first conductive layer formed along the first main surface and the side surface of the groove; at least one second conductive layer formed along the second main surface and the side surface of the groove; at least one dielectric layer formed along the first main surface, the second main surface, and the side surface of the groove; a first electrode electrically connected to the first conductive layer on the first main surface; and a second electrode electrically connected to the second conductive layer on the second main surface, wherein the first conductive layer and the second conductive layer are alternately stacked with the dielectric layer in between, and the first conductive layer and the second conductive layer are electrically insulated.

[0007] A method for manufacturing a capacitor according to one aspect of the present invention includes the steps of: forming at least one first conductive layer along the first main surface and the side surface of the groove of a substrate having a first main surface, a second main surface facing in the opposite direction to the first main surface, and a groove penetrating the first main surface and the second main surface; forming at least one second conductive layer along the second main surface and the side surface of the groove; forming at least one dielectric layer along the first main surface, the second main surface, and the side surface of the groove; forming a first electrode electrically connected to the first conductive layer on the first main surface; and forming a second electrode electrically connected to the second conductive layer on the second main surface, wherein the first conductive layer and the second conductive layer are alternately stacked with the dielectric layer in between, and the first conductive layer and the second conductive layer are electrically insulated. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a capacitor with low process costs and a method for manufacturing the same. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a cross-sectional view of a capacitor according to the first embodiment. [Figure 2] Figure 2 is a plan view showing the steps of the manufacturing method for a capacitor according to the first embodiment. [Figure 3]Figure 3 is a cross-sectional view along line II-II in Figure 2, and shows the steps of the capacitor manufacturing method according to the first and second embodiments (Part 1). [Figure 4] Figure 4 is a cross-sectional view showing the steps of the manufacturing method for a capacitor according to the first embodiment (part 2). [Figure 5] Figure 5 is a cross-sectional view showing the steps of the manufacturing method for a capacitor according to the first embodiment (part 3). [Figure 6] Figure 6 is a cross-sectional view showing the steps of the manufacturing method for a capacitor according to the first embodiment (part 4). [Figure 7] Figure 7 is a cross-sectional view showing the steps of the manufacturing method for a capacitor according to the first embodiment (part 5). [Figure 8] Figure 8 is a cross-sectional view showing the steps of the manufacturing method for a capacitor according to the first embodiment (part 6). [Figure 9] Figure 9 is a cross-sectional view showing the steps of the manufacturing method for a capacitor according to the first embodiment (part 7). [Figure 10] Figure 10 is a cross-sectional view showing the steps of the manufacturing method of a capacitor according to the first embodiment (part 8). [Figure 11] Figure 11 is a cross-sectional view of a capacitor according to the second embodiment. [Figure 12] Figure 12 is a cross-sectional view showing the steps of the manufacturing method for a capacitor according to the second embodiment (part 2). [Figure 13] Figure 13 is a cross-sectional view showing the steps of the manufacturing method for a capacitor according to the second embodiment (part 3). [Figure 14] Figure 14 is a cross-sectional view showing the steps of the manufacturing method for a capacitor according to the second embodiment (part 4). [Figure 15] Figure 15 is a cross-sectional view showing the steps of the manufacturing method for a capacitor according to the second embodiment (part 5). [Figure 16] Figure 16 is a cross-sectional view showing the steps of the manufacturing method for a capacitor according to the second embodiment (part 6). [Modes for carrying out the invention]

[0010] Embodiments will be described with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same parts and the description thereof will be omitted. Further, the dimensional ratios in the drawings are exaggerated for convenience of explanation and may be different from the actual ratios. Also, there are portions where the dimensional relationships and ratios between the drawings are different from each other.

[0011] (First Embodiment) Referring to FIG. 1, a capacitor 100 according to the first embodiment includes a substrate 1, at least one layer of a first conductive layer 3, at least one layer of a second conductive layer 4, at least one layer of a dielectric layer 5, a first electrode 7, and a second electrode 8. The substrate 1 has a first main surface 10, a second main surface 11 facing in the opposite direction to the first main surface 10, and a groove 2 penetrating the first main surface 10 and the second main surface 11. At least one layer of the first conductive layer 3 is formed along the first main surface 10 and the side surface 20 of the groove 2. At least one layer of the second conductive layer 4 is formed along the second main surface 11 and the side surface 20 of the groove 2. At least one layer of the dielectric layer 5 is formed along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2. The first electrode 7 is electrically connected to the first conductive layer 3 on the first main surface 10. The second electrode 8 is electrically connected to the second conductive layer 4 on the second main surface 11. The first conductive layer 3 and the second conductive layer 4 are alternately laminated with the dielectric layer 5 interposed therebetween. The first conductive layer 3 and the second conductive layer 4 are electrically insulated from each other.

[0012] [[ID=~11]] Hereinafter, in the embodiments, an XYZ coordinate system, which is an example of a rectangular coordinate system, will be used. In the present embodiment, a plane parallel to the first main surface 10 and the second main surface 11 of the substrate 1 is defined as an XY plane, and a direction perpendicular to the XY plane is defined as a Z direction. The X direction is a direction parallel to the plane of the paper of FIG. 1 and perpendicular to the Z direction. The Y direction is a direction perpendicular to the X direction and the Z direction.

[0013] In the example shown in FIG. 1, the first conductive layer 3 includes three layers of the first conductive layer (3a to 3c), the second conductive layer 4 includes three layers of the second conductive layer (4a to 4c), and the dielectric layer 5 includes five layers of the dielectric layer (5a to 5e). The first conductive layer 3a is formed along the first main surface 10 of the substrate 1 and the side surface 20 of the groove 2, and the dielectric layer 5a is formed along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2 so as to cover the first conductive layer 3a. On the dielectric layer 5a, the second conductive layer 4a is formed along the second main surface and the side surface 20 of the groove 2, and the dielectric layer 5b is formed along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2 so as to cover the second conductive layer 4a. Similarly, three layers of the first conductive layer (3a to 3c) and three layers of the second conductive layer (4a to 4c) are alternately stacked with five layers of the dielectric layer (5a to 5e) interposed therebetween. Note that the number of each layer of the first conductive layer 3, the second conductive layer 4, and the dielectric layer 5 is not limited to this. At least one layer of the first conductive layer 3 and the second conductive layer 4 is formed, at least one layer of the dielectric layer 5 is formed between the first conductive layer 3 and the second conductive layer 4, and it is only necessary that the first conductive layer 3 and the second conductive layer 4 are electrically insulated. Also, the layer exposed on the outermost surface of the stacked structure including the first conductive layer 3, the second conductive layer 4, and the dielectric layer 5 may be any of the first conductive layer 3, the second conductive layer 4, and the dielectric layer 5.

[0014] An insulating layer 6a is disposed above (on the positive side in the Z direction) the above-described stacked structure along the first main surface 10. The insulating layer 6a electrically insulates between the first electrode 7 and the above-described stacked structure. An insulating layer 6b is disposed below (on the negative side in the Z direction) the above-described stacked structure along the second main surface 11. The insulating layer 6b electrically insulates between the second electrode 8 and the above-described stacked structure. The first electrode 7 and the second electrode 8 are electrically insulated. The insulating layers (6a, 6b) may be disposed inside the groove 2 as long as the groove 2 is not filled.

[0015] On the first main surface 10, a first opening 12 is formed that penetrates the first conductive layer (3b, 3c), the dielectric layer (5a~5e), and the insulating layer 6a. The first conductive layer 3a is exposed at the bottom of the first opening 12. The first electrode 7 is embedded in the first opening 12 and positioned on top of the insulating layer 6a. The first electrode 7 is electrically connected to the first conductive layer 3a at the bottom of the first opening 12 and to the first conductive layer (3b, 3c) at the side surface of the first opening 12. Since the second conductive layer (4a~4c) is not exposed at the bottom or side surface of the first opening 12, the first electrode 7 is electrically insulated from the second conductive layer (4a~4c). On the other hand, on the second main surface 11, a second opening 13 is formed that penetrates the second conductive layer (4b, 4c), the dielectric layer (5a~5e), and the insulating layer 6b. The second conductive layer 4a is exposed on the bottom surface of the second opening 13. The second electrode 8 is embedded in the second opening 13 and positioned on the insulating layer 6b. The second electrode 8 is electrically connected to the second conductive layer 4a on the bottom surface of the second opening 13 and to the second conductive layers (4b, 4c) on the sides of the second opening 13. Since the first conductive layers (3a-3c) are not exposed on the bottom or sides of the second opening 13, the second electrode 8 is electrically insulated from the first conductive layers (3a-3c). Furthermore, since the first electrode 7 and the second electrode 8 are electrically insulated, the first conductive layers (3a-3c) electrically connected to the first electrode 7 are electrically insulated from the second conductive layers (4a-4c) electrically connected to the second electrode 8.

[0016] A void 21 is formed inside the groove 2. None of the substrate 1, the first conductive layer 3, the second conductive layer 4, the dielectric layer 5, the insulating layers (6a, 6b), the first electrode 7, or the second electrode 8 are located in the void 21. The void 21 allows for the distribution of stress generated inside the capacitor 100, thereby improving the mechanical strength of the capacitor 100.

[0017] The basic operation of the capacitor 100 shown in Figure 1 will be explained below. When a positive voltage is applied to the first electrode 7 to create a high potential, the first conductive layer (3a~3c) electrically connected to the first electrode 7 becomes high potential and is charged with positive charge. When a negative voltage is applied to the second electrode 8 to create a low potential, the second conductive layer (4a~4c) electrically connected to the second electrode 8 becomes low potential and is charged with negative charge. At this time, polarization occurs inside the dielectric layer (5a~5e) and capacitance is generated. Capacitance is generated similarly when a negative voltage is applied to the first electrode 7 and a positive voltage is applied to the second electrode 8.

[0018] The capacitor 100 shown in Figure 1 has a capacitor cell in which one first conductive layer 3 and one second conductive layer 4 are stacked with one dielectric layer 5 in between. In the capacitor 100, three layers of the first conductive layer 3 and the second conductive layer 4, and five layers of dielectric layer 5, stacked along the side surface 20 of the groove 2, form five capacitor cells connected in series. The first electrode 7 electrically connects the three layers of the first conductive layer 3, and the second electrode 8 electrically connects the three layers of the second conductive layer 4, thereby forming a structure in which the five capacitor cells are connected in parallel. As a result, the capacitance density of the capacitor 100 can be improved. Capacitance density in this disclosure refers to the capacitance per unit area of ​​the first main surface 10 of the substrate 1.

[0019] Referring to Figure 1, the distance between the first conductive layer 3 and the second conductive layer 4 closest to the first conductive layer 3 is defined as the vertical distance L. The point where the first main surface 10 or the second main surface 11 intersects with the side surface 20 of the groove 2 is defined as the corner 30. The dimension of the dielectric layer 5 when viewed from the corner 30 in the stacking direction of the aforementioned laminated structure is defined as the thickness D1 of the dielectric layer 5. The thickness D1 of the dielectric layer 5 is greater than the vertical distance L. In the example shown in Figure 1, the thickness D1 is more than twice the vertical distance L. By having a large thickness D1 of the dielectric layer 5 when viewed from the corner 30 in the stacking direction, where stress is easily applied when the capacitor 100 undergoes thermal expansion, the stress generated inside the capacitor 100 can be alleviated.

[0020] Substrate 1 is an insulator, for example, a substrate containing a silicon oxide film (SiO2). Substrate 1 may also be an insulator containing a silicon nitride film (Si3N4) and aluminum oxide (Al2O3), etc. Because substrate 1 is an insulator, substrate insulation is unnecessary, making element isolation easy.

[0021] The substrate 1 may be a semiconductor or a metal. By making the substrate 1 a semiconductor or metal with a high concentration of impurities added, the substrate 1 can be used as the first conductive layer 3 or the second conductive layer 4.

[0022] Referring to Figure 1, the Z-direction dimension of substrate 1 is defined as the height H of substrate 1, and the X-direction dimension of groove 2 is defined as the width W of groove 2. The height H may be greater than the width W. When the height H is greater than the width W, the area of ​​the side surface 20 of groove 2 per unit area of ​​the first main surface 10 of substrate 1 increases, and the capacity density can be improved.

[0023] The first conductive layer 3 and the second conductive layer 4 are N-type polycrystalline silicon (Si) doped with N-type impurities such as phosphorus (P) or arsenic (As). The first conductive layer 3 and the second conductive layer 4 may also be P-type polycrystalline silicon doped with P-type impurities such as boron (B) or aluminum (Al), N-type or P-type silicon carbide (SiC), titanium (Ti), aluminum (Al), and germanium (Ge), as well as semiconductors, metals, or metal silicides.

[0024] The dielectric layer 5 includes, for example, at least one of a silicon nitride film, a silicon oxide film, and aluminum oxide.

[0025] The insulating layers (6a, 6b) are, for example, silicon oxide films.

[0026] The first electrode 7 and the second electrode 8 are metals, such as titanium, nickel (Ni), molybdenum (Mo), and silver (Ag). The first electrode 7 and the second electrode 8 may also be stacked layers of two or more metals, for example, including a multilayer film of titanium / nickel / silver.

[0027] A method for manufacturing the capacitor 100 according to the first embodiment will be described with reference to Figures 2 to 10. Note that the method for manufacturing the capacitor 100 according to the first embodiment described below is just one example, and it can be realized by various other manufacturing methods. Figure 3 is a cross-sectional view along line II-II in Figure 2, and Figures 1, 4 to 10 are cross-sectional views covering the same area as Figure 3.

[0028] As shown in Figures 2 and 3, a groove 2 is formed by etching a portion of the substrate 1 so as to penetrate from the first main surface 10 to the second main surface 11 of the substrate 1, which has a first main surface 10 and a second main surface 11 facing in the opposite direction to the first main surface 10. Specifically, first, a mask material (not shown) is formed on the first main surface 10 of the substrate 1. The mask material is, for example, a silicon oxide film and can be formed by thermal CVD (Chemical Vapor Deposition) or plasma CVD. Next, a resist is patterned on the mask material (not shown). The resist can be patterned by a general photolithography method. Next, the mask material is etched using the patterned resist as a mask. For example, the mask material can be etched by dry etching such as reactive ion etching. After etching the mask material, the resist is removed with oxygen plasma or sulfuric acid. The mask material patterned in this way has openings in the area where the groove 2 is formed. The substrate 1 exposed through the openings in the mask material is etched by dry etching to form the groove 2.

[0029] Next, as shown in Figure 4, a first conductive layer 3a is formed along the first main surface 10 and the side surface 20 of the groove 2 of the substrate 1. The first conductive layer 3a is, for example, N-type polycrystalline silicon. Polycrystalline silicon can be formed with good coverage on the first main surface 10 and the side surface 20 of the groove 2 with a high aspect ratio by vacuum CVD. In vacuum CVD, polycrystalline silicon can be formed by supplying silane (SiH4) as a reaction gas and thermally decomposing the silane into silicon. By supplying silane from the first main surface 10 side toward the substrate 1 and controlling the pressure of the silane so that it does not reach the plane including the second main surface 11, polycrystalline silicon can be formed only along the first main surface 10 and the side surface 20 of the groove 2, without forming it on the plane including the second main surface 11. After that, for example, by performing an annealing treatment in phosphorus oxychloride (POCl3) at 950°C, N-type polycrystalline silicon Si is formed, and a conductive first conductive layer 3a is obtained.

[0030] Next, as shown in Figure 5, a dielectric layer 5a is formed along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2 so as to cover the first conductive layer 3a. The dielectric layer 5a is, for example, a silicon nitride film. By vacuum CVD or ALD (Atomic Layer Deposition), a silicon nitride film can be formed with good coverage along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2 with a high aspect ratio. In vacuum CVD, for example, silane and ammonia (NH3) are supplied as reaction gases, and a silicon nitride film can be formed by the reaction of the two. In ALD, for example, ammonia and dimethylsilane ((CH3)2SiH2) are supplied alternately as reaction gases, and a silicon nitride film can be formed by the reaction of the two.

[0031] Next, as shown in Figure 6, a second conductive layer 4a is formed on the dielectric layer 5a along the second main surface 11 and the side surface 20 of the groove 2. The second conductive layer 4a is, for example, N-type polycrystalline silicon. Polycrystalline silicon can be formed with good coverage along the second main surface 11 and the side surface 20 of the groove 2 with a high aspect ratio by a reduced-pressure CVD method similar to that used for the first conductive layer 3a. In the reduced-pressure CVD method, silane is supplied from the second main surface 11 side toward the substrate 1, and the pressure of the silane is controlled so that it does not reach the plane including the first main surface 10. This allows polycrystalline silicon to be formed only along the second main surface 11 and the side surface 20 of the groove 2, without forming it on the plane including the first main surface 10. Subsequently, for example, by annealing in phosphorus oxychloride at 950°C, N-type polycrystalline silicon is formed, and a conductive second conductive layer 4a is obtained.

[0032] By repeating a similar procedure, as shown in Figure 7, three first conductive layers (3a-3c) and three second conductive layers (4a-4c) are alternately stacked with five dielectric layers (5a-5e) in between.

[0033] Next, as shown in Figure 8, an insulating layer 6a is formed along the first main surface 10, and an insulating layer 6b is formed along the second main surface 11. The insulating layers (6a, 6b) are, for example, silicon oxide films and can be formed by a CVD method using TEOS (Tetra Ethyl Ortho Silicate). The insulating layers (6a, 6b) electrically insulate the first electrode 7 and the second electrode 8. By not filling the inside of the groove 2 with insulating layers (6a, 6b), a void 21 is formed inside the groove 2. None of the substrate 1, first conductive layer 3, second conductive layer 4, dielectric layer 5, insulating layers (6a, 6b), first electrode 7, or second electrode 8 are formed in the void 21. The void 21 allows for the dispersion of stress generated inside the capacitor 100, thereby improving the mechanical strength of the capacitor 100. The void 21 also provides a process margin when forming the aforementioned laminated structure.

[0034] Next, as shown in Figure 9, a resist 9 is applied to the insulating layer 6a of the first main surface 10 and the insulating layer 6b of the second main surface 11, and the resist 9 is patterned by photolithography to have an opening in the region where the first opening 12 will later be formed. Using the patterned resist 9 as a mask, the first conductive layer (3b, 3c), dielectric layer (5a~5e), and insulating layer 6a are etched by dry etching, such as reactive ion etching, to form the first opening 12.

[0035] Next, as shown in Figure 10, the resist 9 is applied again onto the insulating layer 6a of the first main surface 10 so as to cover the first opening 12 formed on the first main surface 10. The resist 9 is patterned using photolithography to have an opening in the region where the second opening 13 will later be formed. Using the patterned resist 9 as a mask, the second conductive layer (4b, 4c), dielectric layer (5b~5e), and insulating layer 6b are etched by dry etching, such as reactive ion etching, to form the second opening 13.

[0036] By forming the first opening 12 and the second opening 13 by dry etching, the first opening 12 and the second opening 13 with a high aspect ratio can be formed.

[0037] The first opening 12 and the second opening 13 may be formed by wet etching. This allows for the formation of the first opening 12 and the second opening 13 at a low cost. For wet etching, for example, hydrofluoric acid (HF) or hot phosphoric acid (H3PO4) can be used.

[0038] In the process of forming the first opening 12, by forming the first opening 12 on the first main surface 10, the first conductive layer 3 and dielectric layer 5 formed along the first main surface 10 can be etched together to form the first opening 12. Similarly, in the process of forming the second opening 13, by forming the second opening 13 on the second main surface 11, the second conductive layer 4 and dielectric layer 5 formed along the second main surface 11 can be etched together to form the second opening 13. This reduces the process cost of the capacitor 100. Furthermore, by etching in a single step, the opening width of the mask used during etching can be reduced, thereby reducing the area occupied by the first opening 12 and the second opening 13, and improving the capacitance density of the capacitor 100.

[0039] Next, the resist 9 is removed using oxygen plasma or sulfuric acid (not shown).

[0040] Next, as shown in Figure 1, a first electrode 7 is formed along the first main surface 10 so as to fill the first opening 12. A second electrode 8 is formed along the second main surface 11 so as to fill the second opening 13. The first electrode 7 and the second electrode 8 are made of, for example, titanium and can be formed by sputtering or electron beam (EB) deposition.

[0041] By the above manufacturing method, the capacitor 100 according to the first embodiment shown in Figure 1 is completed.

[0042] (Effects and Benefits) As described above, the capacitor 100 according to the first embodiment provides the following effects.

[0043] The capacitor 100 comprises at least one first conductive layer 3 formed along the first main surface 10 and the side surface 20 of the groove 2, at least one second conductive layer 4 formed along the second main surface 11 and the side surface 20 of the groove 2, and at least one dielectric layer 5 formed along the first main surface 10, the second main surface 11 and the side surface 20 of the groove 2. The first conductive layer 3 and the second conductive layer 4 are alternately stacked with the dielectric layer 5 in between, and the first conductive layer 3 and the second conductive layer 4 are electrically insulated. The first conductive layer 3 and the second conductive layer 4 are alternately stacked with the dielectric layer 5 in between, and the second conductive layer 4 is not formed on a plane including the first main surface. As a result, in the process of forming the first electrode 7 which is electrically connected to the first conductive layer 3 on the first main surface 10, it is not necessary to remove the unnecessary second conductive layer 4. As a result, in the process of forming the second electrode 8 which is electrically connected to the second conductive layer 4 on the second main surface 11, it is not necessary to remove the unnecessary first conductive layer 3. Therefore, the number of steps for forming the first electrode 7 and the second electrode 8 is reduced, making it possible to provide a capacitor 100 with a lower process cost.

[0044] The capacitor 100 has multiple capacitor cells formed by connecting multiple first conductive layers 3, multiple second conductive layers 4, and multiple dielectric layers 5 in series, which are stacked along the side surface 20 of the groove 2. The first electrode 7 electrically connects the multiple first conductive layers 3, and the second electrode 8 electrically connects the multiple second conductive layers 4, thereby forming a structure in which the multiple capacitor cells are connected in parallel. As a result, the capacitance density of the capacitor 100 can be improved.

[0045] The thickness D1 of the dielectric layer 5, when viewed in the stacking direction from the corner 30 where the first main surface 10 or the second main surface 11 intersects with the side surface 20 of the groove 2, is greater than the vertical distance L between the first conductive layer 3 and the second conductive layer 4 closest to the first conductive layer 3. The larger thickness D1 of the dielectric layer 5 when viewed in the stacking direction from the corner 30, where stress tends to concentrate when the capacitor 100 undergoes thermal expansion, allows for the reduction of stress generated inside the capacitor 100.

[0046] In the first opening 12 formed on the first main surface 10 of the capacitor 100, the first electrode 7 is electrically connected to a plurality of first conductive layers 3, and in the second opening 13 formed on the second main surface 11, the second electrode 8 is electrically connected to a plurality of second conductive layers 4. In other words, the first electrode 7 and the first conductive layer 3, and the second electrode 8 and the second conductive layer 4 are each electrically connected at one opening. Therefore, compared to a case where multiple openings are required to electrically connect the first electrode 7 and the first conductive layer 3, and the second electrode 8 and the second conductive layer 4, the area occupied by the first opening 12 and the second opening 13 can be reduced, and the capacitance density of the capacitor 100 can be improved.

[0047] The first opening 12 is formed on the first main surface 10 by simultaneously etching the first conductive layer 3 and the dielectric layer 5 that are formed along the first main surface 10. The second opening 13 is formed on the second main surface 11 by simultaneously etching the second conductive layer 4 and the dielectric layer 5 that are formed along the second main surface 11. As a result, the number of steps required to form the first electrode 7 and the second electrode 8 is reduced, making it possible to provide a capacitor 100 with a lower process cost.

[0048] The height H of the substrate 1 from the first main surface 10 to the second main surface 11 is greater than the width W of the groove 2 parallel to the first main surface 10. As a result, the area of ​​the side surface 20 of the groove 2 per unit area of ​​the first main surface 10 of the substrate 1 is increased, and the area of ​​the capacitor cell formed by the first conductive layer 3, the second conductive layer 4, and the dielectric layer 5 laminated along the side surface 20 of the groove 2 can be increased, thereby improving the capacitance density of the capacitor 100.

[0049] The substrate 1 of the capacitor 100 is an insulator. Therefore, it is easy to isolate the capacitor 100 formed on the substrate 1 from other elements.

[0050] A method for manufacturing a capacitor 100 includes the steps of: forming at least one first conductive layer 3 along the first main surface 10 and the side surface 20 of the groove 2 of a substrate having a first main surface 10, a second main surface 11 facing in the opposite direction to the first main surface 10, and a groove 2 penetrating the first main surface 10 and the second main surface 11; forming at least one second conductive layer 4 along the second main surface 11 and the side surface 20 of the groove 2; and forming at least one dielectric layer 5 along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2. The first conductive layer 3 and the second conductive layer 4 are stacked alternately with the dielectric layer 5 in between to electrically insulate the first conductive layer 3 and the second conductive layer 4. The first conductive layer 3 and the second conductive layer 4 are stacked alternately with the dielectric layer 5 in between, and the second conductive layer 4 is not formed on a plane including the first main surface 10. Therefore, in the step of forming the first electrode 7 which is electrically connected to the first conductive layer 3 on the first main surface 10, there is no need to remove the unnecessary second conductive layer 4. Furthermore, the first conductive layer 3 and the second conductive layer 4 are stacked alternately with the dielectric layer 5 in between, and the first conductive layer 3 is not formed on a plane including the second main surface 11. Therefore, in the step of forming the second electrode 8 which is electrically connected to the second conductive layer 4 on the second main surface 11, there is no need to remove the unnecessary first conductive layer 3. As a result, the number of steps for forming the first electrode 7 and the second electrode 8 is reduced, and a capacitor manufacturing method with a lower process cost can be provided.

[0051] The manufacturing method for the capacitor 100 involves forming the first conductive layer 3 and the second conductive layer 4 using a reduced-pressure CVD method or an ALD method. In the reduced-pressure CVD method or ALD method, the region in which the first conductive layer 3 and the second conductive layer 4 are formed is controlled by adjusting the pressure of the reaction gas. This allows for precise control of the shape, coverage, and depth formed on the side surface 20 of the groove 2 of the first conductive layer 3 and the second conductive layer 4.

[0052] The manufacturing method for capacitor 100 includes the step of forming the first electrode 7, which involves forming a first opening 12 on the first main surface 10 that penetrates the first conductive layer 3 and the dielectric layer 5, and the step of embedding the first electrode 7 in the first opening. The manufacturing method for capacitor 100 includes the step of forming a second opening 13 on the second main surface 11 that penetrates the second conductive layer 4 and the dielectric layer 5, and the step of embedding the second electrode 8 in the second opening. In the step of forming the first opening 12, by forming the first opening 12 on the first main surface 10, the first conductive layer 3 and the dielectric layer 5 formed along the first main surface 10 can be etched together to form the first opening 12. Also, in the step of forming the second opening 13, by forming the second opening 13 on the second main surface 11, the second conductive layer 4 and the dielectric layer 5 formed along the second main surface 11 can be etched together to form the second opening 13. Therefore, a capacitor manufacturing method with low process costs can be provided.

[0053] (Second Embodiment) Referring to Figure 11, the configuration of the capacitor 100 according to the second embodiment will be described. In addition to the configuration of the capacitor 100 according to the first embodiment, the capacitor 100 according to the second embodiment has a laminated structure consisting of a first conductive layer 3, a second conductive layer 4, and a dielectric layer 5, and at least one of the thickness D2 of the first conductive layer 3 and the thickness D3 of the second conductive layer 4 when viewed in the stacking direction is small enough to be close to at least one of the plane including the first main surface 10 and the plane including the second main surface 11.

[0054] The other configurations and operations of the capacitor 100 according to the second embodiment are the same as those of the capacitor 100 according to the first embodiment, and therefore will not be described.

[0055] In the example shown in Figure 11, the thickness D2 of the first conductive layer 3 is smaller the closer it is to the plane containing the second main surface 11. The thickness D3 of the second conductive layer 4 is smaller the closer it is to the plane containing the first main surface 10. In other words, the edges of the first conductive layer 3 are chamfered near the plane containing the second main surface 11, and the edges of the second conductive layer 4 are chamfered near the plane containing the first main surface 10. As a result, electric field concentration occurring at the corners of the first conductive layer 3 and the second conductive layer 4 can be suppressed, and the voltage withstand capability of the capacitor 100 can be improved.

[0056] Note that the thickness D2 of the first conductive layer 3 and the thickness D3 of the second conductive layer 4 may be the same. Also, if the first conductive layer 3 and the second conductive layer 4 include multiple layers, each layer may have a different thickness.

[0057] The manufacturing method for the capacitor 100 according to the second embodiment will be described with reference to Figures 3 and 12 to 16. Figures 11 to 16 are cross-sectional views of the same area as in Figure 3. Note that the manufacturing method for the capacitor 100 according to the second embodiment described below is just one example, and it can be realized by various other manufacturing methods. The same parts as the manufacturing method for the capacitor 100 according to the first embodiment will be omitted from the explanation.

[0058] First, as shown in Figure 3, similar to the first embodiment, a groove 2 is formed by etching a part of the substrate 1 so as to penetrate from the first main surface 10 to the second main surface 11 of the substrate 1, which has a first main surface 10 and a second main surface 11 facing in the opposite direction to the first main surface 10.

[0059] Next, as shown in Figure 12, a first conductive layer 3a is formed along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2 of the substrate 1. The difference from the first embodiment is that the first conductive layer 3a is formed along the second main surface 11. Similar to the first embodiment, the first conductive layer 3a is, for example, N-type polycrystalline silicon. Polycrystalline silicon can be formed with good coverage along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2 with a high aspect ratio by the reduced-pressure CVD method. Subsequently, for example, by annealing in phosphorus oxychloride at 950°C, N-type polycrystalline silicon is formed, and a conductive first conductive layer 3a is obtained.

[0060] Next, as shown in Figure 13, the first conductive layer 3a formed on the plane including the second main surface 11 is selectively etched and removed by dry etching, such as reactive ion etching, from the second main surface 11 toward the substrate 1. Furthermore, the first conductive layer 3a is selectively etched so that the thickness D2 of the first conductive layer 3a formed along the side surface 20 of the groove 2 becomes smaller as it approaches the plane including the second main surface 11.

[0061] The first conductive layer 3a shown in Figure 13 may also be obtained by adjusting the pressure of the reaction gas in the reduced-pressure CVD method when forming the first conductive layer 3a in Figure 12. Specifically, in the reduced-pressure CVD method, silane, which is the reaction gas, is supplied from the first main surface 10 side toward the substrate 1, and by adjusting the pressure of the silane, polycrystalline silicon can be formed on the side surface 20 of the groove 2 such that the thickness decreases as it approaches the plane containing the second main surface 11. Furthermore, by adjusting the pressure of the silane so as not to reach the plane containing the second main surface 11, polycrystalline silicon can be formed only along the first main surface 10 and the side surface 20 of the groove 2, without forming it on the plane containing the second main surface 11. Subsequently, for example, by performing an annealing treatment in phosphorus oxychloride at 950°C, N-type polycrystalline silicon is formed, and the first conductive layer 3a shown in Figure 13 is obtained. In addition, in the reduced-pressure CVD method, polycrystalline silicon may be formed along the side surface 20 of the groove 2 such that its thickness decreases as it approaches the plane including the second main surface 11, and polycrystalline silicon may also be formed along the second main surface 11. In this case, in a later step, the polycrystalline silicon formed along the second main surface 11 can be selectively etched by dry etching to obtain the first conductive layer 3a having the shape shown in Figure 13.

[0062] Next, as shown in Figure 14, a dielectric layer 5a is formed along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2 so as to cover the first conductive layer 3a. Similar to the first embodiment, the dielectric layer 5a is, for example, a silicon nitride film and can be formed by vacuum CVD and ALD methods.

[0063] Next, as shown in Figure 15, a second conductive layer 4a is formed on the dielectric layer 5a along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2 of the substrate 1. The difference from the first embodiment is that the second conductive layer 4a is formed along the first main surface 10. Similar to the first embodiment, the second conductive layer 4a is, for example, N-type polycrystalline silicon. Polycrystalline silicon can be formed with good coverage along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2 with a high aspect ratio by the reduced-pressure CVD method. After that, for example, by annealing in phosphorus oxychloride at 950°C, N-type polycrystalline silicon is formed and a conductive second conductive layer 4a is obtained.

[0064] Next, as shown in Figure 16, the second conductive layer 4a formed on the plane including the first main surface 10 is selectively etched and removed by dry etching, such as reactive ion etching, from the first main surface 10 toward the substrate 1. Furthermore, the second conductive layer 4a is selectively etched so that the thickness D3 of the second conductive layer 4a formed on the side surface 20 of the groove 2 becomes smaller as it approaches the plane including the first main surface 10.

[0065] The second conductive layer 4a shown in Figure 16 may also be obtained by adjusting the pressure of the reaction gas in the reduced-pressure CVD method when forming the second conductive layer 4a in Figure 15. Specifically, in the reduced-pressure CVD method, silane, which is the reaction gas, is supplied from the second main surface 11 side toward the substrate 1, and by adjusting the pressure of the silane, polycrystalline silicon can be formed on the side surface 20 of the groove 2 such that the thickness decreases as it approaches the plane containing the first main surface 10. Furthermore, by adjusting the pressure of the silane so as not to reach the plane containing the first main surface 10, polycrystalline silicon can be formed only along the second main surface 11 and the side surface 20 of the groove 2, without forming it on the plane containing the first main surface 10. Subsequently, for example, by performing an annealing treatment in phosphorus oxychloride at 950°C, N-type polycrystalline silicon is formed, and the second conductive layer 4a shown in Figure 16 is obtained. In the reduced-pressure CVD method, polycrystalline silicon may be formed on the side surface 20 of the groove 2 such that its thickness decreases as it approaches the plane containing the first main surface 10, and polycrystalline silicon may also be formed along the first main surface 10. In this case, in a later step, the polycrystalline silicon formed on the plane containing the first main surface 10 can be selectively etched by dry etching to obtain the second conductive layer 4a having the shape shown in Figure 16.

[0066] By uniformly forming the first conductive layer 3a and the second conductive layer 4a along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2, the first conductive layer 3a and the second conductive layer 4a can be formed with good coverage. Subsequently, by selectively removing the first conductive layer 3a and the second conductive layer 4a formed in unnecessary areas, the shape, coverage, and depth formed on the side surface 20 of the groove 2 of the first conductive layer 3a and the second conductive layer 4a can be precisely controlled.

[0067] Next, a dielectric layer 5b is formed along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2 so as to cover the second conductive layer 4a (not shown). The same procedure is repeated to alternately stack three first conductive layers (3a to 3c) and three second conductive layers (4a to 4c) with five dielectric layers (5a to 5e) in between. The subsequent manufacturing method is the same as in the first embodiment.

[0068] By the above manufacturing method, the capacitor 100 according to the second embodiment shown in Figure 11 is completed.

[0069] (Effects and Benefits) As described above, the capacitor 100 according to the second embodiment provides the following effects in addition to the effects of the capacitor 100 according to the first embodiment.

[0070] In the laminated structure consisting of a first conductive layer 3, a second conductive layer 4, and a dielectric layer 5, at least one of the thicknesses D2 of the first conductive layer 3 and D3 of the second conductive layer 4, when viewed in the stacking direction, is smaller the closer it is to at least one of the planes including the first main surface 10 and the second main surface 11. In other words, at least one of the first conductive layer 3 and the second conductive layer 4 is chamfered in the vicinity of at least one of the planes including the first main surface 10 and the second main surface 11. As a result, electric field concentration occurring at at least one corner of the first conductive layer 3 and the second conductive layer 4 can be suppressed, and the voltage withstand capability of the capacitor 100 can be improved.

[0071] The step of forming the first conductive layer 3 in the manufacturing method of the capacitor 100 includes the steps of forming the first conductive layer 3 along the first main surface 10, the second main surface, and the side surface 20 of the groove 2, and selectively removing the first conductive layer 3 formed on a plane including the second main surface 11. The step of forming the second conductive layer 4 includes the steps of forming the second conductive layer 4 along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2, and selectively removing the second conductive layer formed on a plane including the first main surface 10. By uniformly forming the first conductive layer 3 and the second conductive layer 4 along the first main surface 10, the second main surface 11, and the side surface 20 of the groove 2, the first conductive layer 3 and the second conductive layer 4 can be formed with good coverage. Subsequently, by selectively removing the first conductive layer 3 and the second conductive layer 4 formed in unnecessary areas, the shape, coverage, and depth formed on the side surface 20 of the groove 2 can be precisely controlled.

[0072] The embodiments described above are merely examples of how the present invention can be implemented. Therefore, the present invention is not limited to the embodiments described above, and various modifications can be made to other forms as long as they do not depart from the technical spirit of the present invention, depending on the design and other factors. [Explanation of Symbols]

[0073] 100 Capacitors 1 circuit board 2 grooves 3, 3a~3c first conductive layer 4, 4a~4c second conductive layer 5, 5a~5e Dielectric layer 6a, 6b Insulating layer 7 1st electrode 8 Second electrode 10 First Main Surface 11. Second main surface 12 First opening 13. Second opening 20 Side view 30 corners

Claims

1. A substrate having a first main surface, a second main surface facing in the opposite direction to the first main surface, and a groove penetrating the first main surface and the second main surface, A first conductive layer formed along the first main surface and the side surface of the groove, A second conductive layer, formed along the second main surface and the side surface of the groove, At least one dielectric layer formed along the first main surface, the second main surface and the side surface of the groove, A first electrode electrically connected to the first conductive layer on the first main surface, A second electrode electrically connected to the second conductive layer on the second main surface, Equipped with, The first conductive layer and the second conductive layer are alternately stacked with the dielectric layer in between. The first conductive layer and the second conductive layer are electrically insulated. Capacitor.

2. When viewed from a corner, which is the point where the first main surface or the second main surface intersects with the side surface of the groove, in the stacking direction of the stacked structure consisting of the first conductive layer, the second conductive layer, and the dielectric layer, the thickness of the dielectric layer is greater than the vertical distance between the first conductive layer and the second conductive layer closest to the first conductive layer. The capacitor according to claim 1.

3. In the first opening formed on the first main surface, the first electrode is electrically connected to a plurality of the first conductive layers. In the second opening formed on the second main surface, the second electrode is electrically connected to a plurality of the second conductive layers. The capacitor according to claim 1.

4. The thickness of the first conductive layer and the thickness of the second conductive layer, when viewed in the stacking direction of the laminated structure comprising the first conductive layer, the second conductive layer, and the dielectric layer, is smaller the closer it is to at least one of the planes including the first main surface and the plane including the second main surface. The capacitor according to claim 1.

5. The height of the substrate from the first main surface to the second main surface is greater than the width of the groove parallel to the first main surface. The capacitor according to claim 1.

6. The aforementioned substrate is an insulator. The capacitor according to claim 1.

7. A step of forming at least one first conductive layer along the side surface of the first main surface and the groove of a substrate having a first main surface, a second main surface facing in the opposite direction to the first main surface, and a groove penetrating the first main surface and the second main surface, A step of forming at least one second conductive layer along the second main surface and the side surface of the groove, A step of forming at least one dielectric layer along the first main surface, the second main surface and the side surface of the groove, A step of forming a first electrode electrically connected to the first conductive layer on the first main surface, A step of forming a second electrode electrically connected to the second conductive layer on the second main surface, Includes, The first conductive layer and the second conductive layer are alternately stacked with the dielectric layer in between. The first conductive layer and the second conductive layer are electrically insulated. Capacitor manufacturing method.

8. The step of forming the first conductive layer is: A step of forming the first conductive layer along the first main surface, the second main surface and the side surface of the groove, A step of selectively removing the first conductive layer formed on a plane including the second main surface. Includes, The step of forming the aforementioned second conductive layer is: A step of forming the second conductive layer along the first main surface, the second main surface and the side surface of the groove, A step of selectively removing the second conductive layer formed on a plane including the first main surface. including, A method for manufacturing a capacitor according to claim 7.

9. In the steps of forming the first conductive layer and the second conductive layer, the first conductive layer and the second conductive layer are formed by a reduced-pressure CVD method or an ALD method. In the reduced-pressure CVD method or the ALD method, the surface on which the first conductive layer and the second conductive layer are formed is controlled by adjusting the pressure of the reaction gas. A method for manufacturing a capacitor according to claim 7.

10. The step of forming the aforementioned first electrode is: A step of forming a first opening on the first main surface that penetrates the first conductive layer and the dielectric layer, The steps include embedding the first electrode in the first opening, Includes, The process of forming the two adjacent electrodes is as follows: A step of forming a second opening on the second main surface that penetrates the second conductive layer and the dielectric layer, The steps include embedding the second electrode in the second opening, Includes, In the step of forming the first opening, the first conductive layer and the dielectric layer are etched together to form the first opening. In the step of forming the second opening, the second conductive layer and the dielectric layer are etched together to form the second opening. A method for manufacturing a capacitor according to claim 7.

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