Element placement identification device and element placement identification method

Abstract

The present invention provides an element placement identification device and an element placement identification method that can identify the desired element placement state without misidentifying elements, even when there is a misalignment in the placement positions of multiple elements on a substrate. [Solution] This element arrangement identification device 100 comprises an imaging unit 20 that images a substrate 200 on which a plurality of semiconductor elements 210 are arranged, and a processing unit 40 that performs an identification process to identify the arrangement state of each of the plurality of semiconductor elements 210 on the substrate 200. The processing unit 40 is configured to set a search area 310 for each of the plurality of semiconductor elements 210 in the image captured by the imaging unit 20, based on the positions of adjacent semiconductor elements 210, to search for the arrangement state of the semiconductor element 210 to be used for identification processing.

Description

Technical Field

[0004]

[0001] The present invention relates to an element arrangement specifying device and an element arrangement specifying method, and particularly to an element arrangement specifying device and an element arrangement specifying method for specifying the arrangement state of elements based on a captured image.

Background Art

[0002] Conventionally, an inspection device (element arrangement specifying device) for mounting components that specifies the arrangement state of elements based on a captured image has been known (see, for example, Patent Document 1).

[0003] The inspection device for mounting components in Patent Document 1 described above includes a storage means for storing a chip (element) component pattern, an imaging unit for imaging the chip components mounted on a jig substrate, and an inspection means for inspecting the position or angle of the chip components based on the image of the imaged chip components and the chip component pattern generated by stretching the chip component pattern stored in the storage unit. In the chip mounting area on the jig substrate, a pair of marks are printed for each mounting position of each chip component so as to sandwich each chip for measuring the mounting position and mounting angle.

[0004] In the inspection apparatus described in Patent Document 1, the inspection means selects two chip component patterns with a high degree of matching by selecting, rotating, and overlapping multiple chip component patterns generated by stretching and contracting the chip component patterns stored in the memory unit for each chip component sandwiched between a pair of marks captured by the imaging unit. Furthermore, the inspection apparatus described in Patent Document 1 generates multiple other chip component patterns having a degree of stretching and contraction between the two extracted chip component patterns, and performs a process to determine the degree of matching again for each captured chip component. In other words, the inspection apparatus described in Patent Document 1 repeats a series of processes of selecting two chip component patterns with a high degree of matching, generating multiple other chip component patterns based on the selected chip component patterns, and obtaining the degree of matching of the chip component patterns for each captured chip component an arbitrary number of times. As a result, the inspection apparatus described in Patent Document 1 obtains the mounting position and mounting angle (arrangement state) of the chip component based on a pair of marks for measuring the mounting position and mounting angle, and the chip component pattern with the highest degree of matching. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2007-103660 [Overview of the project] [Problems that the invention aims to solve]

[0006] As described above, Patent Document 1 discloses an inspection device that acquires the state (placement state) of the mounting position and mounting angle of a chip component based on marks for measuring mounting position and mounting angle, and the chip component pattern with the highest degree of matching. However, although not explicitly stated in Patent Document 1, due to issues such as processing accuracy, the position of the chip to be placed may be slightly off from a predetermined mark on the substrate. In this case, especially when a large number of chips are placed on the substrate, the displacement of the chip placement position can accumulate, resulting in a very large displacement between two chips placed at a relatively large distance apart. As a result, a chip different from the desired chip intended to be placed in the design may be placed at a predetermined mark. In this case, the inspection device may mistakenly identify a different chip from the desired chip intended to be placed in the design and determine the placement state incorrectly, resulting in the inconvenience of not being able to accurately determine the placement state of the element. For this reason, there is a need for an element placement identification device and an element placement identification method that can identify the desired element placement state without misidentifying elements, even when there is a displacement in the placement position of multiple chips (elements) on the substrate.

[0007] This invention was made to solve the above-mentioned problems, and one objective of this invention is to provide an element placement identification device and an element placement identification method that can identify the desired element placement state without causing misidentification of elements, even when there is a shift in the placement positions of multiple elements on a substrate. [Means for solving the problem]

[0008] To achieve the above objective, the element arrangement identification device in the first aspect of this invention comprises an imaging unit that images a substrate on which a plurality of elements are arranged, and a processing unit that performs an identification process to identify the arrangement state of each of the plurality of elements on the substrate. The processing unit is configured to set an element arrangement search area for each of the plurality of elements in the image captured by the imaging unit, based on the positions of adjacent elements, in order to search for the arrangement state of the element to be used for the identification process.

[0009] In the element placement identification device in the first aspect of this invention, as described above, the processing unit is configured to set an element placement search area for each of the multiple elements in the captured image captured by the imaging unit, based on the positions of adjacent elements, in order to search for the placement state of the elements to be used for identification processing. Here, when a large number of elements are placed on a substrate, the displacement of the elements accumulates, and the displacement of the positions of two elements placed at a relatively large distance apart can become very large, but the displacement of adjacent elements is relatively small. Therefore, by setting an element placement search area based on the positions of adjacent elements as described above, the placement state of the elements can be searched based on adjacent elements that are less affected by the displacement, making it less likely to mistakenly identify elements (misrecognition) in which elements different from the desired elements intended to be placed in the design are placed. As a result, even if there is a displacement in the placement positions of multiple elements on the substrate, the desired placement state of the elements can be identified without misrecognizing elements.

[0010] In the element placement identification device described in the first phase above, preferably, the processing unit is configured to set element placement search areas for multiple elements by starting with one reference element among a plurality of elements captured in the image and sequentially setting element placement search areas for adjacent elements. With this configuration, the position of each element identified in the element placement search area set based on one reference element can be obtained relative to the placement position of the reference element. As a result, the relative positional relationship of multiple elements on the substrate can be obtained.

[0011] In the element placement identification device in the first phase described above, preferably, the processing unit is configured to set element placement search areas for multiple elements before the identification process, and then perform the identification process in parallel in the set element placement search areas. With this configuration, since the identification process is performed in parallel in multiple element placement search areas, the processing related to element placement identification can be performed in a shorter time compared to finding an element placement search area one by one and then performing the identification process.

[0012] In an element placement identification device in which the above-described processing unit sets the element placement search area for adjacent elements sequentially, starting from one reference element, preferably the substrate includes a feature pattern that is distinguishable from multiple elements, and the processing unit is configured to select a reference element based on the position of the feature pattern. With this configuration, since the feature pattern is distinguishable from elements, the reference element can be easily selected using the feature pattern.

[0013] In this case, preferably, the processing unit is configured to select as a reference element one element closest to the location of the feature pattern, or one element located at a predetermined distance from the location of the feature pattern. With this configuration, the reference element can be selected based on easily identifiable criteria, such as one element closest to the location of the feature pattern, or one element located at a predetermined distance from the location of the feature pattern.

[0014] In the element placement identification device described in the first phase above, preferably, the processing unit is configured to set a target range for identifying the placement state of elements based on the captured image, and to perform identification processing for each of the multiple elements present within the target range. With this configuration, even when a large number of elements are placed on the substrate, identification processing can be performed for each target range, thus reducing the control load (processing load) of the processing unit compared to performing identification processing for all elements on the substrate at once.

[0015] In this case, preferably, the substrate includes a feature pattern that is distinguishable from multiple elements, and multiple feature patterns are provided on the substrate. The processing unit is configured to set the area enclosed by the multiple feature patterns as a specific target area. With this configuration, the specific target area can be easily set based on multiple feature patterns that are distinguishable from elements.

[0016] In an element placement identification device in which the above-described processing unit sets a range surrounded by multiple feature patterns as a specific target range, preferably, if some of the multiple feature patterns necessary for setting the specific target range are not captured in the captured image for identification processing, the processing unit reduces the imaging magnification of the imaging unit to acquire a low-magnification image captured so that all of the multiple feature patterns are captured, sets a low-magnification search area for each of the multiple elements in the low-magnification image to identify the placement state of the element based on the positions of adjacent elements, and sets the element placement search area in the captured image based on the positions of the feature patterns and elements captured in the captured image taken at a higher imaging magnification than the low-magnification image, and the positions of the feature patterns and elements captured in the low-magnification image. With this configuration, even if some of the multiple feature patterns necessary for setting the specific target range are not captured in the captured image, the element placement search area can be set based on a low-magnification image captured so that all of the multiple feature patterns are captured. As a result, the element placement search area can be appropriately set for elements arranged within multiple feature patterns.

[0017] To achieve the above objective, this second-phase method for identifying element placement comprises: an imaging step of imaging a substrate on which multiple elements are arranged; a setting step of setting an element placement search region for each of the multiple elements in the imaged image, based on the positions of adjacent elements, to identify the placement state of the element; and a identification step of performing a process to identify the placement state of each of the multiple elements on the substrate within the set element placement search region.

[0018] The element placement identification method according to the second phase described above includes a setting step of setting an element placement search area for each of the multiple elements in the captured image, based on the positions of adjacent elements, to identify the placement state of the elements. Here, when a large number of elements are placed, the positional displacement of the elements accumulates, and the positional displacement of two elements placed at a relatively large distance apart can become very large, but the positional displacement between adjacent elements is relatively small. Therefore, by setting an element placement search area based on the positions of adjacent elements as described above, the placement state of the elements can be searched based on adjacent elements that are less affected by the displacement, making it less likely to mistakenly identify elements that are not the desired elements intended to be placed in the design. As a result, even when there is a displacement in the placement positions of multiple elements on the substrate, an element placement identification method can be provided that can identify the desired element placement state without misidentifying elements. [Effects of the Invention]

[0019] According to the present invention, as described above, even when there is a misalignment in the placement positions of multiple elements on a substrate, it is possible to provide an element placement identification device and an element placement identification method that can identify the desired element placement state without causing misidentification of elements. [Brief explanation of the drawing]

[0020] [Figure 1] This figure shows the overall configuration of an element arrangement identification device according to the first embodiment of the present invention. [Figure 2] This is a plan view illustrating a substrate according to a first embodiment of the present invention. [Figure 3] This is a partial plan view illustrating the arrangement of elements on a substrate according to the first embodiment of the present invention. [Figure 4] This is a diagram illustrating a reference image according to a first embodiment of the present invention. [Figure 5] This is a diagram illustrating an image of a rotating element according to the first embodiment of the present invention. [Figure 6] This is a diagram for explaining the pattern matching performed by the processing unit according to the first embodiment of the present invention. [Figure 7] This is a flowchart for explaining the operation of the processing unit according to the first embodiment of the present invention. [Figure 8] This is a sub - flowchart for explaining the search area setting process performed by the processing unit according to the first embodiment of the present invention. [Figure 9] This is a diagram for explaining the search area setting process performed by the processing unit according to the first embodiment of the present invention. [Figure 10] This is a partial plan view for explaining the arrangement state of elements on a substrate according to a comparative example. [Figure 11] This is a partial plan view for explaining the arrangement state of elements on a substrate and the imaging field of view according to the second embodiment of the present invention. [Figure 12] This is a flowchart for explaining the operation of the processing unit according to the second embodiment of the present invention. [Figure 13] This is a sub - flowchart for explaining the search area setting process performed by the processing unit according to the second embodiment of the present invention. [Figure 14] This is a diagram for explaining the search area correction process performed by the processing unit according to the second embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0021] Hereinafter, an embodiment of the present invention will be described based on the drawings.

[0022] [First Embodiment] Referring to FIGS. 1 and 2, the configuration of the element arrangement specifying apparatus 100 according to the first embodiment of the present invention will be described.

[0023] (Overall Configuration of the Element Arrangement Specifying Apparatus) As shown in Figure 1, the element placement identification device 100 comprises a substrate holding unit 10, an imaging unit 20, a moving mechanism 30, and a processing unit 40. The element placement identification device 100 is a device for identifying the positions of multiple semiconductor elements 210 arranged on a substrate 200.

[0024] As shown in Figure 2, multiple semiconductor elements 210 are arranged on the substrate 200 at intervals from each other in a predetermined region A. Multiple feature patterns 201, which are distinguishable from the semiconductor elements 210, are arranged on the substrate 200 at predetermined intervals. The multiple semiconductor elements 210 are arranged in the X direction and the Y direction, which is orthogonal to the X direction. Furthermore, one side of the X direction is designated as the X1 direction and the other as the X2 direction. Similarly, one side of the Y direction is designated as the Y1 direction and the other as the Y2 direction. The direction in which the multiple semiconductor elements 210 are placed on the substrate 200 is defined as the Z direction. Note that the XY plane corresponds to the horizontal plane.

[0025] As the semiconductor element 210, for example, a thin rectangular element with sides of about several hundred micrometers to several tens of millimeters, such as a memory chip, is used. Note that the semiconductor element 210 is an example of the "element" in the claims.

[0026] The substrate holding unit 10 is configured to hold the substrate 200. Specifically, the substrate holding unit 10 includes a substrate mounting table 11 on which the substrate 200 is placed in a horizontal position. The substrate mounting table 11 has grooves or holes formed therein that are connected to a negative pressure generating means such as a vacuum pump (not shown). The substrate holding unit 10 holds the substrate 200 by creating a negative pressure state in the grooves or holes formed in the substrate mounting table 11, and releases the substrate 200 by opening the grooves or holes formed in the substrate mounting table 11 to the atmosphere.

[0027] As shown in Figure 1, the imaging unit 20 is configured to image the substrate 200. Specifically, the imaging unit 20 is positioned above the substrate mounting table 11 on which the substrate 200 is placed, in the Z direction, so as to image the substrate 200 from above (Z1 direction). The imaging unit 20 includes an imaging camera 21 for imaging the substrate 200. Image data of the substrate 200 captured by the imaging camera 21 is output to the processing unit 40.

[0028] The moving mechanism 30 is configured to move the substrate holder 10 relative to the imaging unit 20 in the XY plane. Specifically, the moving mechanism 30 includes an X-direction moving mechanism 31 that moves the substrate holder 10 along the X direction, and a Y-direction moving mechanism 32 that moves the substrate holder 10 along the Y direction. The X-direction moving mechanism 31 and the Y-direction moving mechanism 32 are, for example, linear motion mechanisms combining a servo motor or pulse motor with a ball screw, or linear motion mechanisms using a linear motor. The moving mechanism 30 is positioned below the substrate holder 10 (in the Z2 direction).

[0029] The processing unit 40 is configured to control each part of the element placement identification device 100. Specifically, the processing unit 40 controls a negative pressure generating means (not shown) to create a negative pressure state in a groove or hole formed in the substrate mounting table 11 in order to hold the substrate 200, and to open the groove or hole formed in the substrate mounting table 11 to the atmosphere in order to release the substrate 200. The processing unit 40 also controls the imaging unit 20 to image the substrate 200. The processing unit 40 also controls the moving mechanism 30 to move the substrate holding unit 10 relative to the imaging unit 20. The processing unit 40 is a computer that enables image processing, including a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), GPU (Graphics Processing Unit), etc. as a processor. The processing unit 40 is also configured to perform a process to identify the arrangement state of multiple semiconductor elements 210 on the substrate 200 by performing pattern matching based on the image captured by the imaging unit 20.

[0030] (Regarding the arrangement of elements on the circuit board) Here, the substrate 200 imaged by the imaging unit 20 will be described in detail using Figure 3. Note that the imaging field of view V of the imaging unit 20, the line L parallel to the X-axis, the specific target area 300, and the search area 310 of the imaging unit 20, which will be described later, are drawn in Figure 3 for illustrative purposes and are not present in the actual captured image. Note that the search area 310 is an example of the "element arrangement search area" in the claims.

[0031] As shown in semiconductor element 210a, each edge of semiconductor element 210a along the X-axis direction is arranged parallel to the edge of substrate 200 along the X-axis direction, and each edge of semiconductor element 210a along the Y-axis direction is arranged parallel to the edge of substrate 200 along the Y-axis direction. This state is assumed to have a rotation angle of 0°. On the other hand, as shown in semiconductor element 210b, for example, there are cases where the semiconductor elements are arranged in an inclined state, such that the edge of semiconductor element 210b along the X-axis direction and the edge of substrate 200 along the X-axis direction are not arranged parallel to each other (the edge of semiconductor element 210b along the Y-axis direction and the edge of substrate 200 along the Y-axis direction are not arranged parallel to each other).

[0032] As described above, when the semiconductor element 210 is positioned at an angle, the direction in which the semiconductor element 210 is rotated counterclockwise from a rotation angle of 0° is defined as the positive rotation angle, and the direction in which the element is rotated clockwise from a rotation angle of 0° is defined as the negative rotation angle. For example, in Figure 3, the semiconductor element 210b is rotated 40° clockwise, so it is positioned at a rotation angle of 40.0° (-40.0°) in the negative direction.

[0033] In this first embodiment, the plurality of semiconductor elements 210 arranged on the substrate 200 are arranged so that they are shifted from the Y2 direction to the Y1 direction as you move from the X1 direction to the X2 direction. For example, if we compare the plurality of semiconductor elements 210 arranged in the row at the edge in the Y1 direction among the plurality of semiconductor elements 210 that enter the imaging field of view V with a line L parallel to the X axis, we can see that the semiconductor elements 210 at the edge in the X1 direction and the semiconductor elements 210 at the edge in the X2 direction are shifted in the Y direction by an amount greater than the size of one semiconductor element 210.

[0034] Furthermore, there are multiple feature patterns 201 (201a to 201d) arranged on the substrate 200 so as to surround multiple semiconductor elements 210 in the XY plane. Here, the feature patterns 201 are arranged at predetermined pattern intervals. Also, the multiple semiconductor elements 210 on the substrate are arranged so as to be surrounded by any four of the feature patterns 201. For example, the multiple semiconductor elements 210 that appear in the imaging field of view V are surrounded by feature patterns 201a, 201b, 201c, and 201d. The processing unit 40 (see Figure 1) is configured to identify the arrangement state of the multiple semiconductor elements 210 within a specific target range 300 surrounded by these feature patterns 201a, 201b, 201c, and 201d.

[0035] Note that this specific target range 300 is different from the range enclosed by the line connecting feature patterns 201a, 201b, 201c, and 201d by the shortest distance. Specifically, this specific target range 300 is the range enclosed by a straight line extending from feature patterns 201a and 201d along the Y direction, and a straight line extending from feature patterns 201b and 201c along the X direction. Although not shown in the figures, multiple specific target ranges 300 are set on the substrate 200, and a reference element 211 is set for each specific target range 300. In the first embodiment, for example, the semiconductor element 210 closest to feature pattern 201a within the specific target range 300 is selected as the reference element 211.

[0036] Furthermore, a search area 310 is set for each of the multiple semiconductor elements 210 by the processing unit 40. The search area 310 is set as a rectangular area larger than the semiconductor element 210 in the X and Y directions, enclosing each of the multiple semiconductor elements 210. In addition, each of the multiple search areas 310 is set so as not to overlap with other search areas 310. Note that the search area 310 is set for all semiconductor elements 210 within the specified target range 300, but for convenience, in the drawing the search area 310 is drawn only for the semiconductor elements 210 in the uppermost row in the Y1 direction. The search area 310 is set in order to determine the arrangement state, including the position (coordinates) and rotation angle of the semiconductor elements 210 within the area, by performing pattern matching within that area. Details on how to set the search area 310 will be described later.

[0037] (Regarding pattern matching) Here, using Figures 4 to 6, we will explain the pattern matching process used by the processing unit 40 to determine the arrangement state of the semiconductor elements 210. The reference image 1 and the rotating element images 1a to 1d are used for pattern matching.

[0038] The reference image 1 shown in Figure 4 is an image generated by the processing unit 40 based on one semiconductor element 210 selected by an operator or the like from the images of multiple semiconductor elements 210 arranged on a substrate 200 captured by the imaging unit 20. The reference image 1 is an image consisting of an element portion 2 and a background portion 3, and is also one of the rotating element images described later.

[0039] The rotating element images 1a to 1d shown in Figure 5 are images generated by the processing unit 40 rotating only the element portion 2 in the reference image 1 in the positive and negative directions within an angle range set by the operator or the like. Similar to the reference image 1 described above, the rotating element images 1a to 1d consist of element portions 2a to 2d and background portions 3a to 3d. In this first embodiment, for example, eight patterns of rotating element images 1a to 1d are generated in 2.5° increments within the range of -10° to 10° (0° is generated as the reference image 1). Note that in Figure 5, four patterns are shown for the sake of simplicity in the drawing. For example, the rotating element image 1a in Figure 4 is an image in which the element portion 2 in the reference image 1 has been rotated by -10.0°.

[0040] Next, the processing unit 40 (see Figure 1) performs pattern matching on the semiconductor elements 210 within one search area 310, as shown in Figure 6. In the pattern matching performed by the processing unit 40, each time the element portion 2 of the reference image 1 is moved within the search area 310, a correlation value (matching degree) is obtained that indicates the degree of correlation between the element portion 2 and the portion of the search area 310 at the location of the element portion 2. In this first embodiment, for example, the matching degree is determined by sequentially moving the element portion 2 one pixel at a time, starting from the upper left corner of the search area 310 (the end in the X1 direction and the end in the Y1 direction). After determining the correlation value for all pixels, the correlation value is similarly determined using the element portions 2a to 2d of the rotating element images 1a to 1d. Through this process, the processing unit 40 identifies the position and rotation angle with the highest correlation value as the position and angle in which the semiconductor element 210 is located.

[0041] (Process flow for determining element placement) Here, using Figures 2 and 7 to 9, we will explain the method for identifying the arrangement of all semiconductor elements 210 placed on the substrate 200 by the processing unit 40 in the element arrangement identification device 100 shown in Figure 1.

[0042] First, in the imaging process of step S1, the processing unit 40 controls the imaging unit 20 to image the substrate 200 in order to detect the arrangement state of each of the multiple semiconductor elements 210 as shown in Figure 2. Specifically, with the substrate 200 held by the substrate holding unit 10 (see Figure 1), the processing unit 40 divides the substrate 200 into several sections for each imaging field V and images them. Therefore, the processing unit 40 alternately controls the movement mechanism 30 (see Figure 1) that moves the substrate holding unit 10 holding the substrate 200 by a predetermined amount, and controls the imaging unit 20 that takes the images. After that, the process proceeds to step S2 in Figure 7.

[0043] In step S2, the process of setting the target area, the processing unit 40 sets the target area 300 to surround the multiple semiconductor elements 210 within the imaging field of view V, as shown in Figure 2. Specifically, the processing unit 40 first detects the positions (coordinates) of feature patterns 201a, 201b, 201c, and 201d from the captured image using an existing image processing method such as the grayscale search method. Then, the processing unit 40 sets the area surrounded by feature patterns 201a, 201b, 201c, and 201d as the target area 300. After that, the process proceeds to step S3 in Figure 7.

[0044] In the search area setting step S3, the processing unit 40 sets a search area 310 for each of the semiconductor elements 210 included within the specified target range 300, as shown in Figure 2. Here, the search area setting step is performed based on the flow shown in Figure 8.

[0045] First, as part of the element position detection step S3a, the processing unit 40 detects the placement position on the substrate 200 of each of the semiconductor elements 210 included within the specified target range 300, as shown in Figure 2. In this first embodiment, the coordinates of the semiconductor elements 210 are, for example, the coordinates of the edges of the semiconductor elements 210 in the X1 and Y1 directions. This detection process is performed using an existing image processing method, such as the grayscale search method, and the relative position (coordinates) of each semiconductor element 210 with respect to the feature pattern 201a is detected, with the center coordinates of the feature pattern 201a being set as the reference coordinate (0,0). After that, the process proceeds to step S3b.

[0046] Next, as part of the reference element selection step S3b, the processing unit 40 selects a reference element 211 from among the multiple semiconductor elements 210 included within the specified target range 300, as shown in Figure 3, to serve as the reference element 211 for setting the search area 310. Specifically, the processing unit 40 selects the semiconductor element 210 that is closest to the feature pattern 201a from among the multiple semiconductor elements 210 included within the specified target range 300 as the reference element 211. After that, the process proceeds to step S3c.

[0047] Next, as part of the reference search area setting step S3c, the processing unit 40 sets the search area 310 relative to the reference element 211, as shown in Figure 2. Specifically, the processing unit 40 sets the search area 310 as a rectangular area connecting four points that are separated by a predetermined distance set arbitrarily by the user from the coordinates of the X1 and Y1 ends (upper left corner of the paper) of the reference element 211. After that, the process proceeds to step S3d.

[0048] Next, as part of the adjacent element search region setting step S3d, the processing unit 40 sets a search region 310 for semiconductor elements 210 adjacent to the reference element 211, as shown in Figure 9. Specifically, the processing unit 40 sets a search region 310 for semiconductor elements 210c adjacent to the reference element 211 based on a position P2 that is a predetermined distance in the X2 direction from the position P1 of the X1 and Y1 edges (upper left corner of the paper) of the reference element 211. Here, although the semiconductor element 210c is positioned slightly shifted in the Y1 direction from its design position in the Y direction, it is contained within the search region 310 because the search region 310 is set based on the position of the adjacent reference element 211, which has a relatively small amount of shift. After that, the process proceeds to step S3e. Similarly, the processing unit 40 sets a search area 310 for semiconductor elements 210d adjacent to semiconductor element 210c based on a position P4 located at a predetermined distance in the X2 direction from the position P3 at the X1 and Y1 edges (upper left corner of the paper) of semiconductor element 210c. The same process is performed for semiconductor elements 210 adjacent in the Y direction.

[0049] Next, in step S3e, the processing unit 40 determines whether the setting of the search area 310 has been completed for all semiconductor elements 210 within the specified target range 300. If the setting of the search area 310 has not been completed for all semiconductor elements 210 within the specified target range 300, the adjacent element search area setting process in step S3d is performed again for the semiconductor elements 210 for which the search area 310 has not been set. If the setting of the search area 310 has been completed for all semiconductor elements 210 within the specified target range 300, the search area setting process is completed. After that, the process proceeds to step S4 in Figure 7.

[0050] In step S4, the arrangement state identification process, the processing unit 40 identifies the arrangement state of the semiconductor elements 210 within the specified target range 300. Pattern matching is performed in all of the search areas 310 set for the semiconductor elements 210 within the specified target range 300 to identify the arrangement state of all semiconductor elements 210, including their placement position and placement angle. Here, as a result of the search area setting process in step S3 performed earlier, search areas 310 have been set for all semiconductor elements 210 within the specified target range 300, and the processing unit 40 performs pattern matching in parallel and simultaneously for all of these search areas 310. After that, the process proceeds to step S5.

[0051] Next, in step S5, the processing unit 40 determines whether the identification of the arrangement state of the semiconductor elements 210 has been completed in all specified target areas 300. If the identification of the arrangement state of the semiconductor elements 210 has not been completed in all specified target areas 300, the processing in steps S2 to S4 is repeated at a different location (imaging field of view) on the substrate 200. The element arrangement identification process for one substrate 200 is completed when the arrangement state of the semiconductor elements 210 has been identified in all specified target areas 300 on the substrate 200.

[0052] [Comparative Example] In the comparative example shown in Figure 10, multiple semiconductor elements 210 are arranged on the substrate 200 such that they are shifted from the Y2 direction to the Y1 direction as they move from the X1 direction to the X2 direction. Here, we will describe a comparative example in which the processing unit 40 identifies the arrangement of the semiconductor elements 210 using search areas 310a to 310c that have been pre-set by the user. In this case, since the user cannot predict how much the semiconductor elements 210 will be shifted on the substrate 200, the search areas 310a to 310c are set based on the planned position (design position) where each of the multiple semiconductor elements 210 is to be placed.

[0053] In this case, for example, the search area 310a is appropriately set for the semiconductor element 220a located in the X1 direction. On the other hand, in the search area 310b set at a position further along the X2 direction, due to a misalignment of the semiconductor elements 210, none of the semiconductor elements 210 are included in the search area 310b. In this case, when pattern matching is performed by the processing unit 40, the correlation value becomes small at every position within the search area 310b, and the semiconductor element 210 cannot be properly identified. Furthermore, in the search area 310c set at a position further along the X2 direction, due to a misalignment of the semiconductor elements 210, semiconductor element 220c is located instead of semiconductor element 220b, which was intended to be located according to the design. In this case, the processing unit 40 can detect the arrangement state by pattern matching, but it mistakenly identifies semiconductor element 220b as semiconductor element 220c. Thus, depending on the setting of the area for pattern matching of the semiconductor elements 210, there may be cases where the arrangement state of the semiconductor elements 210 on the substrate 200 cannot be correctly identified.

[0054] [Effects of the First Embodiment] In the first embodiment described above, the following effects can be obtained.

[0055] In the first embodiment described above, the element placement identification device 100 includes an imaging unit 20 that images a substrate 200 on which a plurality of semiconductor elements 210 are arranged, and a processing unit 40 that performs identification processing to identify the arrangement state of each of the plurality of semiconductor elements 210 on the substrate 200. The processing unit 40 is configured to set a search area 310 for each of the plurality of semiconductor elements 210 in the image captured by the imaging unit 20, based on the positions of adjacent semiconductor elements 210, to search for the arrangement state of the semiconductor element 210 to be used for identification processing. The element placement identification method includes an imaging step of imaging a substrate 200 on which a plurality of semiconductor elements 210 are arranged, a setting step of setting a search area 310 for each of the plurality of semiconductor elements 210 in the image captured, based on the positions of adjacent semiconductor elements 210, and an identification step of performing processing to identify the arrangement state of each of the plurality of semiconductor elements 210 on the substrate 200 in the set search area 310. In cases where a large number of semiconductor elements 210 are placed on the substrate 200, the positional displacement of the semiconductor elements 210 accumulates, and the positional displacement of two semiconductor elements 210 placed at a relatively large distance apart can become very large, but the positional displacement of adjacent semiconductor elements 210 is relatively small. Therefore, by setting the search area 310 based on the positions of adjacent semiconductor elements 210 as described above, the arrangement state of the semiconductor elements 210 can be searched based on adjacent semiconductor elements 210 that are relatively less affected by displacement. This makes it less likely to mistakenly place a semiconductor element 210 that is different from the desired semiconductor element 210 that is intended to be placed in the design. As a result, even if there is a displacement in the placement positions of multiple semiconductor elements 210 on the substrate 200, the arrangement state of the desired semiconductor element 210 can be identified without misidentifying the semiconductor element 210.

[0056] Furthermore, in the first embodiment described above, the processing unit 40 is configured to set search regions 310 for multiple semiconductor elements 210 by starting with one reference element 211 that serves as a reference among the multiple semiconductor elements 210 captured in the image, and sequentially setting search regions 310 for adjacent semiconductor elements 210. This makes it possible to obtain the relative position of each semiconductor element 210 identified in the search region 310 set based on one reference element 211, based on the placement position of the reference element 211. As a result, the relative positional relationship of multiple semiconductor elements 210 on the substrate 200 can be obtained.

[0057] Furthermore, in the first embodiment described above, the processing unit 40 is configured to set search areas 310 for a plurality of semiconductor elements 210 before the identification process, and then to perform the identification process in parallel in the set search areas 310. As a result, since the identification process is performed in parallel in the plurality of search areas 310, the process related to identifying the element arrangement can be performed in a shorter time compared to determining each search area 310 one by one and then performing the identification process.

[0058] Furthermore, in the first embodiment described above, the substrate 200 includes a feature pattern 201 (201a) that is distinguishable from the multiple semiconductor elements 210, and the processing unit 40 is configured to select a reference element 211 based on the position of the feature pattern 201a. As a result, since the feature pattern 201a is distinguishable from the semiconductor elements 210, the reference element 211 can be easily selected using the feature pattern 201a.

[0059] Furthermore, in the first embodiment described above, the processing unit 40 is configured to select the semiconductor element 210 closest to the location of the feature pattern 201a as the reference element 211. This allows the reference element 211 to be selected based on an easily identifiable indicator: the semiconductor element 210 closest to the location of the feature pattern 201a.

[0060] Furthermore, in the first embodiment described above, the processing unit 40 is configured to set a target range 300 for identifying the arrangement state of semiconductor elements 210 based on the captured image, and to perform identification processing for each of the multiple semiconductor elements 210 present within the target range 300. As a result, even when a large number of semiconductor elements 210 are arranged on the substrate 200, identification processing can be performed for each target range 300, thereby reducing the control load (processing load) of the processing unit 40 compared to performing identification processing on all semiconductor elements 210 on the substrate 200 at once.

[0061] Furthermore, in the first embodiment described above, the substrate 200 includes a feature pattern 201 that is distinguishable from the plurality of semiconductor elements 210, and a plurality of feature patterns 201 are provided on the substrate 200. The processing unit 40 is configured to set the area enclosed by the plurality of feature patterns 201a to 201d as the specific target area 300. This makes it possible to easily set the specific target area 300 based on the plurality of feature patterns 201a to 201d that are distinguishable from the semiconductor elements 210.

[0062] [Second Embodiment] Next, the device arrangement identification device 100a and the method for identifying the device arrangement of semiconductor elements 210 according to the second embodiment will be described. The device configuration of the device arrangement identification device 100a is the same as that of the device arrangement identification device 100 shown in Figure 1, except for the processing unit 40a. In this second embodiment, a configuration for identifying the arrangement state of each semiconductor element 210 when at least one of the four feature patterns 201a to 201d is not within the imaging field of view will be described. Note that in the second embodiment, the explanation of points common to the first embodiment will be omitted.

[0063] As shown in Figure 11, the substrate 200 is provided with feature patterns 201a to 201d, similar to the first embodiment. In this second embodiment, the imaging field V1, which is imaged at a magnification sufficient to accurately identify the arrangement of the semiconductor elements 210, does not show feature patterns 201b to 201d other than feature pattern 201a. In this case, the target area 300 cannot be defined, and the range of semiconductor elements 210 for setting the search area 310 cannot be determined. On the other hand, if a low-magnification image is used in which all feature patterns 201a to 201d are contained within a single imaging field so that the target area 300 can be defined, the accuracy of identifying the arrangement of the semiconductor elements 210 decreases.

[0064] (Process flow for determining element placement) In the above-described case, the processing performed by the processing unit 40a to accurately determine the arrangement of semiconductor elements 210 on the substrate 200 will be explained using Figures 12 to 14.

[0065] First, in the low-magnification image acquisition process of step S11, the processing unit 40a controls the imaging unit 20 to image the substrate 200. Specifically, the processing unit 40a images the substrate 200 in several sections while the substrate 200 is held in the substrate holding unit 10 (see Figure 1). Therefore, the processing unit 40 alternately controls the movement mechanism 30 (see Figure 1) which moves the substrate holding unit 10 holding the substrate 200 by a predetermined amount, and controls the imaging unit 20 which takes the images. At this time, the imaging magnification of the imaging unit 20 is relatively low, such that all of the feature patterns 201a to 201d fit within a single imaging field of view. After that, the process proceeds to step S12.

[0066] In the step S12, the process of setting the specific target range, the area enclosed by the detected feature patterns 201a, 201b, 201c, and 201d in the low-magnification image captured at low magnification is set as the specific target range 300, following the same procedure as in the first embodiment. Then, the process proceeds to step S13.

[0067] In the search area setting step S13, the processing unit 40a uses a low-magnification image to set a provisional low-magnification search area 311 (see Figure 11) for each of the semiconductor elements 210 included within the specified target range 300. Here, the search area setting step is performed based on the flow shown in Figure 13. Note that each of steps S13a to S13e shown in Figure 13 is processed in the same way as each of steps S3a to S3e in the first embodiment, so the explanation is omitted. After that, the process proceeds to step S14.

[0068] In the high-magnification image acquisition process of step S14, the processing unit 40a alternately controls the movement mechanism 30 (see Figure 1) that moves the substrate holding unit 10, which holds the substrate 200, by a predetermined amount, and controls the imaging unit 20 that takes images, thereby acquiring high-magnification images for each imaging field V1 to V4. At this time, the imaging magnification of the imaging unit 20 is a relatively high magnification necessary to accurately identify the arrangement state of the semiconductor elements 210. As shown in Figure 11, imaging fields V1 to V4 are imaged so that at least one of the feature patterns 201 is included. In addition, each imaging field V1 to V4 is imaged so that semiconductor elements 210 common to adjacent fields are captured. After that, the process proceeds to step S15.

[0069] In the correction step S15, the processing unit 40a corrects the low-magnification search region 311, which was set based on the low-magnification image, to become the search region 312 in the high-magnification image. Specifically, the processing unit 40a first obtains the error at a specific position that occurs when the magnification is changed, based on the position (coordinates) of the feature pattern 201a acquired based on the low-magnification image and the position (coordinates) of the feature pattern 201a acquired based on the high-magnification image.

[0070] Here, Figure 14 is a magnified view of a portion of the imaging field V1 (see Figure 11). In this second embodiment, for example, the coordinates of the feature pattern 201a acquired based on the high-magnification image are (x1-Δx, y1-Δy), and are acquired with a Δx and Δy shift relative to the coordinates (x1, y1) of the feature pattern 201a acquired based on the low-magnification image. Therefore, the processing unit 40a sets a search area 312 by correcting the low-magnification search area 311 to a position shifted by Δx in the X1 direction and Δy in the Y1 direction. This correction is performed simultaneously for all semiconductor elements 210 within the imaging field V1 (see Figure 11). After that, the process proceeds to step S16.

[0071] In step S16, the arrangement state identification step, the processing unit 40a identifies the arrangement state of the semiconductor elements 210 within the imaging field of view V1. In this arrangement state identification step S16, the same processing as in step S4 of the first embodiment (see Figure 7) is performed. After that, the process proceeds to step S17.

[0072] In step S17, the processing unit 40a determines whether there is another field of view that captures the specific target area 300. If there is another field of view that captures the specific target area 300 (for example, imaging fields V2 to V4), the processing in steps S15 and S16 is performed in the other imaging fields V2 to V4. For example, in imaging field V2, the semiconductor element 210f common to imaging field V1 is captured, so based on the placement position of the semiconductor element 210f identified in imaging field V1 after correction due to the change in magnification, a search area 312 (see Figure 14) surrounding the semiconductor element 210g can be set to determine the placement state of the semiconductor element 210g. The same processing is performed for imaging fields V3 and V4. If there are no more other fields of view that capture the specific target area 300, the process proceeds to step S18.

[0073] Next, in step S18, the processing unit 40a determines whether the identification of the arrangement state of the semiconductor elements 210 has been completed in all specified target areas 300. If the identification of the arrangement state of the semiconductor elements 210 has not been completed in all specified target areas 300, the processing in steps S12 to S17 is repeated at a different location (imaging field of view) on the substrate 200. Once the identification of the arrangement state of the semiconductor elements 210 has been completed in all specified target areas 300 on the substrate 200, the element arrangement identification process for one substrate 200 is completed.

[0074] (Effects of the second embodiment) Next, the effects of the second embodiment will be described.

[0075] Furthermore, in the second embodiment described above, the processing unit 40a is configured to set a search area 312 in the captured image based on the positions of the semiconductor elements 210 and the semiconductor elements 210, respectively, based on the positions of the semiconductor elements 210 and the positions of the semiconductor elements 210 and the positions of the semiconductor elements 210 and the positions of the semiconductor elements 210 and the positions of the semiconductor elements 210 and the positions of the semiconductor elements 210 and the semiconductor elements 210, respectively, if some of the multiple feature patterns 201 necessary for setting the specific target range 300 are not captured in the captured image for specific processing. As a result, even if some of the multiple (four) feature patterns 201a to 201d necessary for setting the specific target range 300 are not captured in the captured image, the search area 312 can be set based on the low-magnification image captured so that all of the multiple feature patterns 201a to 201d are captured. As a result, the search region 312 can be appropriately set for semiconductor elements 210 that are arranged within multiple feature patterns 201.

[0076] Furthermore, the other effects of the second embodiment are the same as those of the first embodiment described above.

[0077] [Differentiation] It should be noted that the embodiments disclosed herein are illustrative and not restrictive in all respects. The scope of the present invention is indicated by the claims rather than by the description of the embodiments above, and further includes all modifications (exceptions) within the meaning and scope equivalent to the claims.

[0078] For example, in the first and second embodiments described above, the processing unit 40 is configured to set a search area 310 for multiple semiconductor elements 210 by starting with one reference element 211 among the multiple semiconductor elements 210 captured in the image and sequentially setting the search area 310 for adjacent semiconductor elements 210. However, the present invention is not limited to this. In the present invention, for example, multiple reference elements 211 may be set, and the search area 310 for adjacent semiconductor elements 210 may be set sequentially starting from the reference element 211 that is as close as possible to the semiconductor element 210 for which the search area 310 is to be set.

[0079] Furthermore, in the first and second embodiments described above, the processing unit 40 is configured to set search areas 310 for all semiconductor elements 210 before the identification process in the arrangement state identification step, and then to perform a process to identify the arrangement state in all the set search areas 310 in parallel. However, the present invention is not limited to this. In the present invention, the processing unit 40 may perform the identification process in each search area 310 each time one search area 310 is set, or it may perform a process to identify the arrangement state in each of the multiple search areas 310 each time multiple search areas 310 are set.

[0080] Furthermore, in the first and second embodiments described above, the substrate 200 includes a feature pattern 201 that is distinguishable from the plurality of semiconductor elements 210, and the processing unit 40 is configured to select a reference element 211 based on the position of the feature pattern 201, but the present invention is not limited thereto. In the present invention, for example, if an element with a distinctive appearance is placed on the substrate 200, the processing unit 40 may select the reference element 211 based on the element with a distinctive appearance without using the feature pattern 201.

[0081] Furthermore, while the first and second embodiments described above show an example in which the processing unit 40 is configured to select one semiconductor element 210 closest to the location of the feature pattern 201a as the reference element 211, the present invention is not limited thereto. In the present invention, the processing unit 40 may, for example, select one semiconductor element 210 located at a predetermined distance from the location of the feature pattern 201 as the reference element 211.

[0082] Furthermore, in the first and second embodiments described above, the processing unit 40 is configured to set a specific target range 300 for identifying the arrangement state of semiconductor elements 210 based on the captured image, and to perform specific processing for each of the multiple semiconductor elements 210 present within the specific target range 300. However, the present invention is not limited to this. In the present invention, for example, processing to identify multiple semiconductor elements 210 included in the imaging field of view may be performed without setting a specific target range 300.

[0083] Furthermore, in the first and second embodiments described above, the substrate 200 includes a feature pattern 201 that is distinguishable from the plurality of semiconductor elements 210, and a plurality of feature patterns 201 are provided on the substrate 200, and the processing unit 40 is configured to set the area enclosed by four feature patterns 201a to 201d as the specific target area 300, but the present invention is not limited thereto. In the present invention, the area enclosed by three or five or more feature patterns 201 may be set as the specific target area 300. Also, if the feature pattern itself has a frame shape that surrounds the semiconductor element 210, the specific target area 300 may be set based on one feature pattern 201.

[0084] Furthermore, in the first and second embodiments described above, the specific target area 300 is shown as the area enclosed by a straight line extending from feature pattern 201a and feature pattern 201d along the Y direction, and a straight line extending from feature pattern 201b and feature pattern 201c along the X direction, but the present invention is not limited thereto. In the present invention, the specific target area 300 may be enclosed by any line that passes through feature patterns 201a to 201d, for example, it may be the area enclosed by a straight line connecting feature patterns 201a to 201d with the shortest distance.

[0085] Furthermore, in the second embodiment described above, the processing unit 40a is configured to, when some of the multiple feature patterns 201 necessary for setting the target area 300 are not captured in the captured image for specific processing, reduce the imaging magnification of the imaging unit 20 to acquire a low-magnification image in which all of the multiple feature patterns 201 are captured, and then set the search area 312 in the captured image based on the positions of the feature patterns 201 and semiconductor elements 210 captured in the captured image taken at a higher imaging magnification than the low-magnification image, and the positions of the feature patterns 201 and semiconductor elements 210 captured in the low-magnification image. However, the present invention is not limited to this. In the present invention, for example, if the accuracy of the specification regarding the arrangement state does not need to be that high, the processing unit 40a may perform specific processing on the low-magnification search area 311.

[0086] Furthermore, while the first and second embodiments described above show examples in which the processing unit 40 identifies a plurality of semiconductor elements 210 that are arranged so as they are offset in the Y2 direction relative to the substrate 200 in the X2 direction, the present invention is not limited thereto. In the present invention, the processing unit 40 can identify the arrangement state of the semiconductor elements 210 regardless of how the plurality of semiconductor elements 210 are offset in the XY plane.

[0087] Furthermore, while the first and second embodiments described above show examples in which the processing unit 40 acquires a reference image 1 based on an image captured by the imaging unit 20, the present invention is not limited thereto. In the present invention, for example, when detecting the angle of a semiconductor element 210 of the same shape mounted on another substrate 200, the processing unit 40 may acquire a reference image 1 stored in a storage unit (not shown).

[0088] Furthermore, while the first and second embodiments described above show examples in which a thin semiconductor element 210, such as a memory, is used as the element of the present invention, the present invention is not limited thereto. Various elements other than the semiconductor element 210 may be used as the element of the present invention. [Explanation of Symbols]

[0089] 10 Board holding part 20 Imaging Department 30 Moving mechanism 40, 40a Processing Unit 100, 100a Element arrangement identification device 200 circuit boards Feature patterns 201, 201a, 201b, 201c, 201d 210, 210a~210e, 220a~220c Semiconductor devices (devices) 211 Reference element 300 Specific Target Scope 310, 312 Search area (element placement search area) 311 Low magnification search area

Claims

1. An imaging unit that images a substrate on which multiple elements are arranged, The system includes a processing unit that performs a specific processing to determine the arrangement state of each of the plurality of elements on the substrate, The aforementioned processing unit, An element arrangement identification device configured to set an element arrangement search area for each of the plurality of elements in the captured image captured by the imaging unit, based on the positions of adjacent elements, in order to search for the arrangement state of the elements to be used in the identification process.

2. The element placement identification device according to claim 1, wherein the processing unit is configured to set the element placement search area for the plurality of elements by starting with a reference element among the plurality of elements captured in the image and sequentially setting the element placement search area for the adjacent elements.

3. The element placement identification device according to claim 1, wherein the processing unit is configured to set element placement search areas for the plurality of elements before the identification process, and then perform the identification process in parallel in the set plurality of element placement search areas.

4. The substrate includes a characteristic pattern that is distinguishable from the plurality of elements, The element arrangement identification device according to claim 2, wherein the processing unit is configured to select the reference element based on the position of the feature pattern.

5. The element arrangement identification device according to claim 4, wherein the processing unit is configured to select as the reference element one of the elements closest to the position of the feature pattern, or one of the elements located at a predetermined distance from the position of the feature pattern.

6. The aforementioned processing unit, Based on the captured image, a specific target range is set to be used to identify the arrangement state of the elements, The element arrangement identification device according to claim 1, which is configured to perform the identification process for each of the plurality of elements located within the specified target range.

7. The substrate includes a characteristic pattern that is distinguishable from the plurality of elements, Multiple characteristic patterns are provided on the substrate. The element arrangement identification device according to claim 6, wherein the processing unit is configured to set the range enclosed by a plurality of feature patterns as the specified target range.

8. The aforementioned processing unit, In the captured image for performing the specified processing, if some of the multiple feature patterns necessary for setting the specified target range are not captured, the imaging magnification of the imaging unit is reduced to acquire a low-magnification image in which all of the multiple feature patterns are captured. For each of the plurality of elements in the low-magnification image, a low-magnification search area is set to identify the arrangement state of the element based on the positions of adjacent elements. The element arrangement identification device according to claim 7, configured to set the element arrangement search region in the captured image based on the position of the feature pattern and the position of the element in the captured image captured at a higher imaging magnification than the low-magnification image, and the position of the feature pattern and the position of the element in the low-magnification image.

9. An imaging process for imaging a substrate on which multiple elements are arranged, A setting step for each of the plurality of elements in the captured image, setting an element arrangement search area for determining the arrangement state of the element based on the positions of adjacent elements, A method for identifying element placement, comprising: a process of identifying the placement state of each of the plurality of elements on the substrate in the defined element placement search region.

Images