Semiconductor equipment

Abstract

This method suppresses surface recombination in the base layer while keeping the manufacturing process from becoming overly complex. [Solution] The invention comprises a collector layer 11, a base layer 12 disposed on the collector layer 11, an emitter layer 14 disposed on the base layer 12 and having a mesa structure formed by narrowing the width in the direction intersecting the stacking direction of the collector layer 11 and the base layer 12 compared to the base layer 12, a collector electrode 22 electrically connected to the collector layer 11, an emitter electrode 21 electrically connected to the emitter layer 14, and a base electrode 23 electrically connected to the base layer 12, and a surface recombination prevention layer 13 disposed between the emitter layer 14 and the base layer 12 and having a different configuration from the base layer 12 and the emitter layer 14, wherein the surface recombination prevention layer 13 is disposed between the base layer 14 and the emitter layer 14 on one surface 12a of the base layer 12, between the portion facing the emitter layer 14 in the stacking direction and the portion facing the base electrode 23.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, for example, Patent Document 1 has proposed a semiconductor device having a bipolar transistor in which a collector layer, base layer, and emitter layer are stacked in order. Specifically, in this semiconductor device, in order to reduce parasitic capacitance and the like, the emitter layer has a mesa structure in which the width of the base layer is narrower than the width of the base layer. In other words, the base layer of this semiconductor device has a shape in which a portion protrudes from the emitter layer in the stacking direction between the base layer and the emitter layer. Furthermore, in this semiconductor device, a ledge is formed in the emitter layer on one surface of the base layer on the emitter layer side in order to suppress surface recombination at the portion protruding from the emitter layer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 5491233 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, forming a ledge structure in the emitter layer would result in the formation of both a ledge structure and a mesa structure in the emitter layer, potentially complicating the manufacturing process.

[0005] This disclosure aims to provide a semiconductor device that can suppress surface recombination in the base layer while keeping the manufacturing process from becoming overly complex. [Means for solving the problem]

[0006] According to one aspect of this disclosure, the semiconductor device comprises a collector layer (11) of a first conductivity type, a base layer (12) of a second conductivity type disposed on the collector layer, an emitter layer (14) of a first conductivity type disposed on the base layer and having a mesa structure formed by narrowing the width in the direction intersecting the stacking direction of the collector layer and the base layer compared to the base layer, a collector electrode (22) electrically connected to the collector layer, an emitter electrode (21) electrically connected to the emitter layer, and a base electrode (23) electrically connected to the base layer, and has a surface recombination prevention layer (13) disposed between the emitter layer and the base layer and having a different configuration from the base layer and the emitter layer, wherein the surface recombination prevention layer is disposed to cover the space between the portion of one surface (12a) of the base layer on the emitter layer side that faces the emitter layer in the stacking direction and the portion that faces the base electrode.

[0007] According to this design, one side of the base layer facing the emitter layer is covered with a surface recombination prevention layer between the portion facing the base electrode and the portion facing the emitter layer. Therefore, surface recombination on the emitter layer side of the base layer can be suppressed, thus preventing a decrease in current gain. Furthermore, the surface recombination prevention layer has a different configuration from the emitter layer. Consequently, the emitter layer and the surface recombination prevention layer can be designed separately, preventing complexity in the manufacturing process.

[0008] Furthermore, according to another aspect of this disclosure, the semiconductor device comprises a collector layer (11) of a first conductivity type, a base layer (12) of a second conductivity type disposed on the collector layer, an emitter layer (14) of a first conductivity type disposed on the base layer and having a mesa structure formed by narrowing the width in the direction intersecting the stacking direction of the collector layer and the base layer compared to the base layer, a collector electrode (22) electrically connected to the collector layer, and an emitter electrode (21) electrically connected to the emitter layer, and has a surface recombination prevention layer (13) disposed between the emitter layer and the base layer and having a different configuration from the base layer and the emitter layer, wherein the surface recombination prevention layer is arranged to cover a portion of one side (12a) of the base layer on the emitter layer side that can become a current path.

[0009] According to this, one surface on the emitter layer side in the base layer is covered with a surface recombination prevention layer in a portion that can be a current path. Therefore, it is possible to suppress the occurrence of surface recombination on one surface on the emitter layer side in the base layer, and it is possible to suppress the decrease in current gain. Further, the surface recombination prevention layer has a configuration different from that of the emitter layer. Therefore, the designs of the emitter layer and the surface recombination prevention layer can be separated, and it is possible to suppress the complication of the manufacturing process.

[0010] Note that the reference signs with parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of Drawings

[0011] [Figure 1] It is a cross-sectional view of a semiconductor device in the first embodiment. [Figure 2] It is a diagram for explaining the operating state of the semiconductor device in the first embodiment. [Figure 3] It is a cross-sectional view of a semiconductor device in the second embodiment. [Figure 4] It is a cross-sectional view of a semiconductor device in the third embodiment.

Modes for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present disclosure will be described based on the drawings. In the following respective embodiments, parts that are the same or equivalent to each other will be described with the same reference signs.

[0013] (First Embodiment) The first embodiment will be described while referring to the drawings. As shown in FIG. 1, the semiconductor device includes a support substrate 10. In the present embodiment, the support substrate 10 is made of GaN (that is, gallium nitride), and is an n-type with a higher n-type carrier concentration than a collector layer 11 described later.

[0014] On the support substrate 10, a collector layer 11 made of GaN is disposed. The collector layer 11 is doped with impurities such as silicon, for example, and has an n-type carrier concentration of 1×10 16 cm -3 and is of n - type, with a thickness of 6 μm. Further, in the collector layer 11 of the present embodiment, a recessed portion is formed in the outer edge portion on the base layer 12 side described later.

[0015] On the collector layer 11, a base layer 12 made of GaN is disposed. The base layer 12 is doped with impurities such as Mg (i.e., magnesium), for example, and is of p - type, with a thickness of 100 nm. If the p-type carrier concentration of the base layer 12 is too high, when the semiconductor device is turned on as described later, the lifetime of electrons supplied from the emitter layer 14 tends to be shortened. For this reason, it is preferable that the peak concentration of the portion where the p-type carrier concentration is highest in the base layer 12 is 2×10 19 cm -3 or less. Further, if the p-type carrier concentration of the base layer 12 is too low, there is a possibility that the breakdown voltage required at present cannot be satisfied. For this reason, it is preferable that the peak concentration of the portion where the p-type carrier concentration is highest in the base layer 12 is 1×10 17 cm -3 or more. That is, it is preferable that the peak concentration of the portion where the p-type carrier concentration is highest in the base layer 12 is 1×10 17 cm -3 or more and 2×10 19 cm -3 or less.

[0016] Furthermore, in this embodiment, a first base contact layer 121 is formed in the base layer 12 at a position different from the position facing the emitter layer 14, which will be described later. The first base contact layer 121 in this embodiment is formed to penetrate the base layer 12 in the thickness direction and reach the collector layer 11. However, the first base contact layer 121 may be formed to terminate within the base layer 12 and not reach the collector layer 11. The first base contact layer 121 in this embodiment has a higher p-type carrier concentration than the base layer 12, for example, by doping with impurities such as Mg to bring the p-type carrier concentration to 4 × 10⁻⁶. 19 cm -3 It is said that...

[0017] A surface recombination prevention layer 13, which has a different configuration from the base layer 12 and the emitter layer 14 described later, is arranged on the base layer 12. In this embodiment, the surface recombination prevention layer 13 is composed of AlGaN (i.e., aluminum gallium nitride) with an Al composition of about 15%, but the proportions of each component can be changed as appropriate. Furthermore, in this embodiment, the surface recombination prevention layer 13 is doped with impurities such as silicon. - It is a type with a thickness of 100 nm. In this embodiment, the surface recombination prevention layer 13 is configured such that the portion that becomes the second surface recombination prevention layer 13b is completely depleted, as will be described in detail later. For this reason, if the carrier concentration is too high, the film thickness must be made extremely thin in order to achieve complete depletion. Therefore, the surface recombination prevention layer 13 has an n-type carrier concentration of 1 × 10⁻⁶. 17 cm -3 Preferably, the following applies, and in this embodiment, the n-type carrier concentration is 1 × 10 16 cm -3 It is said that the specific configuration and arrangement shape of the surface recombination prevention layer 13 will be described later, but the surface recombination prevention layer 13 is arranged on a portion of one surface 12a of the base layer 12 that can become a current path.

[0018] Furthermore, the surface recombination prevention layer 13 has a second base contact layer 131 connected to the first base contact layer 121 at a position different from the position facing the emitter layer 14, which will be described later. Specifically, the second base contact layer 131 is arranged to penetrate the surface recombination prevention layer 13 in the thickness direction. Also, in this embodiment, the second base contact layer 131 is doped with impurities such as Mg, for example, so that the p-type carrier concentration is 4 × 10⁻¹⁶, similar to the first base contact layer 121. 19 cm -3 It is said that...

[0019] In this embodiment, the first base contact layer 121 and the second base contact layer 131 are constructed by ion implanting Mg or the like as p-type impurities. However, the method of forming the first base contact layer 121 and the second base contact layer 131 can be changed as appropriate. For example, the first base contact layer 121 and the second base contact layer 131 may be constructed by forming trenches in the portions where the first base contact layer 121 and the second base contact layer 131 are formed, and arranging the embedded epitaxial layer in the trenches.

[0020] An emitter layer 14 made of AlGaN, a material with a larger band gap than the base layer 12, is placed on the surface recombination prevention layer 13. The emitter layer 14 is doped with impurities such as silicon, for example, to have an n-type carrier concentration of 7 × 10⁻⁶. 18 cm -3 n + It is considered a mold, and its thickness is said to be 50 nm.

[0021] An emitter contact layer 15 is arranged on the emitter layer 14 to enable ohmic connection with the emitter electrode 21, which will be described later. In this embodiment, the emitter contact layer 15 is made of GaN, for example, and is doped with impurities such as silicon to have an n-type carrier concentration of 7 × 10⁻⁶. 18 cm -3 n + It is considered a mold, and its thickness is said to be 50 nm.

[0022] Furthermore, the emitter layer 14 and the emitter contact layer 15 have a mesa structure that is narrower than the base layer 12, etc. Therefore, the base layer 12 has a portion that faces the emitter layer 14 and a portion that is different from the portion that faces the emitter layer 14 (i.e., a portion that does not face the emitter layer 14). The width refers to the length in the direction perpendicular to the stacking direction of the collector layer 11, base layer 12, and emitter layer 14, and in Figure 1 it is the length in the left-right direction of the paper. The stacking direction of the collector layer 11, base layer 12, and emitter layer 14 is the up-down direction of the paper in Figure 1, and will be simply referred to as the stacking direction below.

[0023] The emitter layer 14 and emitter contact layer 15 are formed as follows. First, starting from the support substrate 10 side, the constituent films constituting the collector layer 11, the base layer 12, the surface recombination prevention layer 13, the emitter layer 14, and the emitter contact layer 15 are sequentially stacked by epitaxial growth or the like. Then, by placing a mask as appropriate and dry etching the constituent films constituting the emitter layer 14 and the emitter contact layer 15, the mesa structure of the emitter layer 14 and emitter contact layer 15 is formed. In this embodiment, the portion of the surface recombination prevention layer 13 that is different from the portion facing the emitter layer 14 is slightly removed by dry etching, so that portion is thinner than the portion facing the emitter layer 14.

[0024] An emitter electrode 21, electrically connected to the emitter contact layer 15, is positioned on the emitter contact layer 15. A collector electrode 22, electrically connected to the collector layer 11, is positioned on the support substrate 10 opposite the collector layer 11. The emitter electrode 21 and the collector electrode 22 are constructed, for example, by laminating titanium and aluminum.

[0025] A base electrode 23 is provided on the second base contact layer 131, which is electrically connected to the base layer 12. The base electrode 23 is electrically connected to the base layer 12 through the second base contact layer 131 and the first base contact layer 121. The base electrode 23 is made of, for example, palladium (Pd).

[0026] Furthermore, in the semiconductor device of this embodiment, in order to suppress leakage current, a protective film 30 made of an oxide film or the like, with a thickness of about 50 nm, is arranged to cover the outer surfaces of the emitter contact layer 15, emitter layer 14, surface recombination prevention layer 13, base layer 12, collector layer 11, etc.

[0027] Here, the placement and configuration of the surface recombination prevention layer 13 will be described in detail. The surface recombination prevention layer 13 is arranged to cover a portion of the base layer 12 on the emitter layer 14 side (hereinafter simply referred to as the base layer 12a) that could become a current path. In this embodiment, the surface recombination prevention layer 13 is arranged to cover at least the portion of the base layer 12a between the portion facing the emitter layer 14 in the stacking direction and the portion where the first base contact layer 121 is formed. In other words, the surface recombination prevention layer 13 is arranged to cover at least the portion of the base layer 12a between the portion facing the emitter layer 14 in the stacking direction and the portion facing the base electrode 23.

[0028] In the following, the region between the emitter layer 14 and the base layer 12 in the surface recombination prevention layer 13 is referred to as the first surface recombination prevention layer 13a. Furthermore, in the following, the region of the surface recombination prevention layer 13 that is different from the first surface recombination prevention layer 13a and includes the portion of the surface recombination prevention layer 13 located between the second base contact layer 131 and the first surface recombination prevention layer 13a is referred to as the second surface recombination prevention layer 13b. In this embodiment, the first surface recombination prevention layer 13a and the second surface recombination prevention layer 13b are both made of AlGaN and have the same configuration, but they may have different configurations.

[0029] In this embodiment, the base layer 12 and the surface recombination prevention layer 13 are configured as described above, so that the band gap of the second surface recombination prevention layer 13b is larger than the band gap of the base layer 12. Furthermore, the carrier concentration and thickness of the second surface recombination prevention layer 13b are adjusted so that it becomes completely depleted when the semiconductor device is turned on as described later.

[0030] The above describes the configuration of the semiconductor device in this embodiment. In this embodiment, n-type corresponds to the first conductivity type, and p-type corresponds to the second conductivity type.

[0031] In such a semiconductor device, when a predetermined voltage is applied between the emitter electrode 21 and the base electrode 23 while a higher voltage is applied to the collector electrode 22 than to the emitter electrode 21, electrons flow from the emitter layer 14 through the base layer 12 to the collector layer 11, as shown by arrow A in Figure 2, and the device turns on. In Figure 2, electrons are represented by "-". In this embodiment, on one surface 12a of the base layer 12, the portion that could become a current path is covered with a surface recombination prevention layer 13. Specifically, on one surface 12a of the base layer 12, the portion from the part facing the emitter layer 14 in the stacking direction to the first base contact layer 121 is covered with the surface recombination prevention layer 13. Therefore, it becomes difficult for electrons to recombine on the surface 12a side of the base layer 12, and the decrease in current gain due to electron annihilation can be suppressed.

[0032] Furthermore, in this embodiment, the second surface recombination prevention layer 13b has a larger band gap than the base layer 12. Therefore, as shown by arrow B, it is possible to suppress the reverse flow of electrons that have flowed from the emitter layer 14 to the base layer 12 into the second surface recombination prevention layer 13b. Consequently, it is possible to further suppress the decrease in current gain.

[0033] Furthermore, in this embodiment, the second surface recombination prevention layer 13b is configured to be completely depleted when it is in the ON state. Therefore, electrons flowing from the emitter layer 14 to the surface recombination prevention layer 13 are suppressed from flowing from the first surface recombination prevention layer 13a to the second surface recombination prevention layer 13b, as shown by arrow C, and are suppressed from being discharged through the second base contact layer 131. Consequently, a further decrease in current gain can be suppressed.

[0034] In this embodiment, the first base contact layer 121 and the second base contact layer 131 have a higher p-type carrier concentration than the base layer 12. Therefore, compared to the case where, for example, the p-type carrier concentration of the second base contact layer 131 is the same as that of the base layer 12, the contact resistance between the base electrode 23 and the second base contact layer 131 can be reduced. Also, when electrons move within a p-type layer, they tend to move from the side with a higher carrier concentration to the side with a lower carrier concentration. Therefore, electrons that have flowed from the emitter layer 14 into the base layer 12 have difficulty entering the first base contact layer 121 from the base layer 12, as shown by arrow D, and their discharge through the first base contact layer 121 is suppressed. Furthermore, since the base layer 12 is connected to the base electrode 23 by making the p-type carrier concentration of the first base contact layer 121 higher than that of the base layer 12, it is not necessary to make the p-type carrier concentration of the base layer 12 high. Therefore, compared to a case where, for example, the p-type carrier concentration in the base layer 12 is the same as the p-type carrier concentration in the first base contact layer 121, the shortening of the electron lifetime can be suppressed. As a result, the decrease in current gain can be further suppressed.

[0035] According to the embodiment described above, one surface 12a of the base layer 12 facing the emitter layer 14 is covered with a surface recombination prevention layer 13 between the portion facing the emitter layer 14 and the portion facing the base electrode 23 and the portion facing the emitter layer 14. In other words, one surface 12a of the base layer 12 is covered in a portion that could become a current path. Therefore, surface recombination can be suppressed on the one surface 12a of the base layer 12 facing the emitter layer 14, and a decrease in current gain can be suppressed. Furthermore, the surface recombination prevention layer 13 has a different structure from the emitter layer 14. Therefore, the design of the emitter layer 14 and the surface recombination prevention layer 13 can be made separately, and the complexity of the manufacturing process can be suppressed.

[0036] (1) In this embodiment, a first base contact layer 121 is formed on the base layer 12, and a second base contact layer 131 is formed on the surface recombination prevention layer 13. The base layer 12 is electrically connected to the base layer 12 through the first base contact layer 121 and the second base contact layer 131. Therefore, it is possible to suppress the base layer 12 from becoming floating.

[0037] (2) In this embodiment, the band gap of the second surface recombination prevention layer 13b is larger than that of the base layer 12. Therefore, when the device is in the ON state, it is possible to suppress the reverse flow of electrons that have flowed from the emitter layer 14 to the base layer 12 into the second surface recombination prevention layer 13b. Consequently, it is possible to further suppress the decrease in current gain.

[0038] (3) In this embodiment, the second surface recombination prevention layer 13b is configured to be completely depleted when it is in the ON state. Therefore, electrons that flow from the emitter layer 14 to the surface recombination prevention layer 13 are prevented from flowing from the first surface recombination prevention layer 13a to the second surface recombination prevention layer 13b, and are prevented from being discharged through the second base contact layer 131. Thus, a further decrease in current gain can be suppressed.

[0039] (4) In this embodiment, the first base contact layer 121 and the second base contact layer 131 have a higher p-type carrier concentration than the base layer 12. Therefore, compared to the case where, for example, the p-type carrier concentration of the second base contact layer 131 is the same as that of the base layer 12, the contact resistance between the base electrode 23 and the second base contact layer 131 can be reduced. In addition, electrons that have flowed from the emitter layer 14 into the base layer 12 will have difficulty entering the first base contact layer 121 from the base layer 12, and will not be discharged through the first base contact layer 121. Furthermore, since the p-type carrier concentration of the first base contact layer 121 is higher than that of the base layer 12 to connect the base layer 12 to the base electrode 23, it is not necessary to make the p-type carrier concentration of the base layer 12 high. Therefore, compared to the case where, for example, the p-type carrier concentration of the base layer 12 is the same as that of the first base contact layer 121, the shortening of the electron lifetime can be suppressed. Therefore, further reduction in current gain can be suppressed.

[0040] (5) In this embodiment, the base layer 12 has a peak concentration of p-type carriers of 2 × 10 19 cm -3 The following is stated. Therefore, it is possible to suppress the shortening of the lifetime of electrons supplied from the emitter layer 14 when it is in the ON state. Consequently, it is possible to further suppress the decrease in current gain.

[0041] (Modification of the first embodiment) A modification of the first embodiment described above will now be explained. In the first embodiment, the first base contact layer 121 and the second base contact layer 131 may be configured such that the p-type carrier concentration of the second base contact layer 131 is higher than that of the first base contact layer 121. This makes it more difficult for electrons to flow from the first base contact layer 121 to the second base contact layer 131, thereby further suppressing the discharge of electrons from the base electrode 23.

[0042] (Second Embodiment) A second embodiment will now be described. This embodiment adds an etching stopper layer to the first embodiment. Other aspects are the same as the first embodiment, so a detailed explanation will be omitted here.

[0043] As shown in Figure 3, the semiconductor device of this embodiment has an etching stopper layer 40 positioned between the base layer 12 and the emitter layer 14, which is made of a different material from the surface recombination prevention layer 13 and the emitter layer 14, and which has a lower etching rate than the surface recombination prevention layer 13 and the emitter layer 14. In this embodiment, the etching stopper layer 40 is positioned between the first surface recombination prevention layer 13a and the emitter layer 14, and is made of, for example, Al.

[0044] Figure 3 shows a configuration in which the etching stopper layer 40, which is placed on the second surface recombination prevention layer 13b, is removed when the constituent films constituting the emitter layer 14 and the constituent films constituting the emitter contact layer 15 are dry-etched to form a mesa structure. However, the etching stopper layer 40 may also be placed on the second surface recombination prevention layer 13b, although this is not specifically shown. However, if the etching stopper layer 40 is also placed on the second surface recombination prevention layer 13b, the height of the etching stopper layer 40 will be the same for the portion placed on the first surface recombination prevention layer 13a and the portion placed on the second surface recombination prevention layer 13b. In addition, the etching stopper layer 40 may be placed, for example, inside the first surface recombination prevention layer 13a.

[0045] According to the embodiment described above, one surface 12a of the base layer 12 on the emitter layer 14 side is covered with a surface recombination prevention layer 13 between the portion facing the emitter layer 14 and the portion facing the base electrode 23 and the portion facing the emitter layer 14. Therefore, the same effects as in the first embodiment can be obtained.

[0046] (1) In this embodiment, an etching stopper layer 40 is placed between the base layer 12 and the emitter layer 14. The etching stopper layer 40 is used when dry etching the constituent films constituting the emitter layer 14 and the constituent films constituting the emitter contact layer 15 to form a mesa structure, and is also placed on the second surface recombination prevention layer 13b before the emitter layer 14 etc. are formed into a mesa structure. Therefore, when forming the emitter layer 14 and the emitter contact layer 15 into a mesa structure, the etching stopper layer 40 makes it easier to grasp the etching endpoint. Therefore, when forming the emitter layer 14 and the emitter contact layer 15 into a mesa structure, it is possible to suppress the complete removal of the second surface recombination prevention layer 13b, and it is possible to suppress the absence of the surface recombination prevention layer 13 in a portion of one surface 12a of the base layer 12 that can become a current path.

[0047] (Third embodiment) A third embodiment will now be described. This embodiment applies the semiconductor device of the first embodiment to a phototransistor (i.e., a photoresponsive device) that conducts current using the photoelectric effect. Other aspects are the same as in the first embodiment, so further explanation will be omitted here.

[0048] In the semiconductor device of this embodiment, as shown in Figure 4, the base electrode 23 is not disposed on the base layer 12, and the first base contact layer 121 and the second base contact layer 131 are not formed. However, in a cross-section different from that shown in Figure 4, a potential-maintaining electrode is disposed to maintain the potential of the base layer 12.

[0049] The surface recombination prevention layer 13 is arranged to cover at least the paths through which current can flow on one surface 12a of the base layer 12. That is, the surface recombination prevention layer 13 is arranged to cover the portion of one surface 12a of the base layer 12 facing the emitter layer 14, and the surrounding portion, in a range where current can spread. The range over which current can spread depends on the carrier concentration and thickness of the base layer 12, and is determined by simulation or experiment. In this embodiment, the surface recombination prevention layer 13 is arranged to cover the entire surface 12a of the base layer 12.

[0050] Furthermore, in this embodiment, the emitter electrode 21 is a transparent electrode made of, for example, ITO. The base layer 12 and the surface recombination prevention layer 13 have the same configuration as in the first embodiment.

[0051] The above describes the configuration of the semiconductor device in this embodiment. In such a semiconductor device, when light is incident, the light is absorbed by the base layer 12, generating a base current. This creates a forward bias between the emitter layer 14 and the base layer 12, causing electrons to flow from the emitter layer 14 through the base layer 12 to the collector layer 11, resulting in an ON state.

[0052] In this embodiment, the surface recombination prevention layer 13 is arranged to cover a path through which current can flow on one surface 12a of the base layer 12. Therefore, electrons are less likely to recombine on one surface of the base layer 12, and the decrease in current gain due to electron annihilation can be suppressed.

[0053] As described above, in this embodiment, one surface 12a of the base layer 12 on the emitter layer 14 side is covered with a surface recombination prevention layer 13 in the portion that could become a current path. Therefore, surface recombination can be suppressed on the one surface 12a of the base layer 12 on the emitter layer 14 side, and a decrease in current gain can be suppressed. Furthermore, the surface recombination prevention layer 13 has a different configuration from the emitter layer 14. Therefore, the design of the emitter layer 14 and the surface recombination prevention layer 13 can be made separately, and the complexity of the manufacturing process can be suppressed.

[0054] (1) In this embodiment, the band gap of the second surface recombination prevention layer 13b is larger than that of the base layer 12. Therefore, similar to the first embodiment, when the device is in the ON state, it is possible to suppress the reverse flow of electrons that have flowed from the emitter layer 14 to the base layer 12 into the second surface recombination prevention layer 13b. Thus, it is possible to further suppress the decrease in current gain.

[0055] (2) In this embodiment, the second surface recombination prevention layer 13b is configured to be completely depleted when it is in the ON state. Therefore, similar to the first embodiment, electrons that flow from the emitter layer 14 to the surface recombination prevention layer 13 are prevented from flowing from the first surface recombination prevention layer 13a to the second surface recombination prevention layer 13b, and are prevented from being discharged through the second base contact layer 131. Thus, a further decrease in current gain can be suppressed.

[0056] (3) In this embodiment, the base layer 12 has a peak concentration of p-type carriers of 2 × 10 19 cm -3 The following is stated. Therefore, similar to the first embodiment described above, it is possible to suppress the shortening of the lifetime of electrons supplied from the emitter layer 14 when it is in the ON state. Consequently, it is possible to further suppress the decrease in current gain.

[0057] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of ​​this disclosure.

[0058] For example, in each of the embodiments described above, a semiconductor device in which an npn type transistor is formed was used as an example, but the semiconductor device may also be composed of a pnp type transistor. In the case of a pnp type transistor, the p type corresponds to the first conductivity type and the n type corresponds to the second conductivity type.

[0059] Furthermore, in each of the above embodiments, the surface recombination prevention layer 13 is n - Although an example of a p-type layer has been described, the surface recombination prevention layer 13 may also be p-type.

[0060] Furthermore, in each of the above embodiments, an example was described in which the base layer 12 is composed of GaN and the emitter layer 14 is composed of AlGaN. However, the materials constituting the base layer 12 and the emitter layer 14 can be changed as appropriate. For example, at least one of the base layer 12 and the emitter layer 14 may be composed of a nitride, oxide, or carbide. In this case, the nitride is composed of at least one of Al (aluminum), In (indium), Ga (gallium), and B (boron). For example, Al x Ga y N 1-x-y It is composed of (0≦x≦1, 0≦x≦1, x+y=1). The oxide is composed of at least one of Al, In, Ga, B, Ni (nickel), Zn (zinc), Mg, Ge (germanium), Si (silicon), Ti (titanium), Sn (tin), for example, (Al x Ga y It is composed of 2O3 (0≦x≦1, 0≦x≦1, x+y=1). The carbide is composed of SiC (silicon carbide) or diamond.

[0061] Furthermore, in each of the above embodiments, the base layer 12 may be composed of multiple layers stacked together. In this case, it is preferable that the base layer 12 has a higher p-type carrier concentration in the portion located on the emitter layer 14 side than in the portion located on the collector layer 11 side.

[0062] Furthermore, in each of the above embodiments, the emitter contact layer 15 may be omitted, and the emitter layer 14 may be connected to the emitter electrode 21.

[0063] Furthermore, in each of the above embodiments, the support substrate 10 may be an insulating substrate. In this case, for example, the collector layer 11 has a portion exposed from the base layer 12 on the side opposite to the support substrate 10, and the collector electrode 22 is electrically connected to the portion of the collector layer 11 exposed from the base layer 12.

[0064] Furthermore, in each of the above embodiments, the protective film 30 may not be provided.

[0065] Furthermore, the above embodiments can be combined. For example, the second embodiment may be combined with the third embodiment to arrange the etching stopper layer 40.

[0066] [Disclosure of the Invention] The above disclosure can be understood from the following perspectives, for example. [First point of view] A semiconductor device, A first conductive collector layer (11), A second conductive base layer (12) is disposed on the collector layer, A first-conductivity type emitter layer (14) is disposed on the base layer and has a mesa structure in which the width in the direction intersecting the stacking direction of the collector layer and the base layer is narrower than that of the base layer, A collector electrode (22) electrically connected to the collector layer, The emitter electrode (21) is electrically connected to the emitter layer, The system comprises a base electrode (23) electrically connected to the base layer, The emitter layer and the base layer are disposed between them and have a surface recombination prevention layer (13) having a different configuration from the base layer and the emitter layer. The surface recombination prevention layer is arranged to cover the space between the portion of one surface (12a) of the base layer facing the emitter layer and the portion facing the base electrode in the stacking direction. [Second perspective] A second conductive first base contact layer (121) is formed on the base layer. The surface recombination prevention layer has a second base contact layer (131) of second conductivity type that is electrically connected to the first base contact layer. The base electrode is electrically connected to the base layer through the first base contact layer and the second base contact layer. The semiconductor device according to the first aspect, wherein the surface recombination prevention layer is arranged on one surface (12a) of the base layer on the emitter layer side, so as to cover the space between the portion facing the emitter layer in the stacking direction and the first base contact layer. [Third perspective] If the portion of the surface recombination prevention layer located between the emitter layer and the base layer is designated as the first surface recombination prevention layer (13a), and the portion located between the first surface recombination prevention layer and the second base contact layer is designated as the second surface recombination prevention layer (13b), The semiconductor device according to the second aspect, wherein the second surface recombination prevention layer is larger than the band gap of the base layer. [Fourth perspective] If the portion of the surface recombination prevention layer located between the emitter layer and the base layer is designated as the first surface recombination prevention layer (13a), and the portion located between the first surface recombination prevention layer and the second base contact layer is designated as the second surface recombination prevention layer (13b), The semiconductor device according to the second or third aspect, wherein the second surface recombination prevention layer has a carrier concentration and thickness that completely depletes the device when an ON state is reached in which current flows between the emitter layer and the collector layer. [Fifth perspective] The semiconductor device according to any one of the second to fourth aspects, wherein the first base contact layer and the second base contact layer have a higher carrier concentration than the base layer. [Sixth perspective] The semiconductor device according to any one of the second to fifth aspects, wherein the second base contact layer has a higher carrier concentration than the first base contact layer. [Seventh perspective] The base layer has a peak concentration of 2 × 10⁻⁶ of the second conductivity type. 19 cm -3 A semiconductor device described in any one of the following perspectives, from the second to the sixth. [Perspective 8] The semiconductor device according to any one of the second to seventh views, wherein an etching stopper layer (40) is disposed between the emitter layer and the base layer, the etching stopper layer (40) being made of a material different from the surface recombination prevention layer and having a lower etching rate than the surface recombination prevention layer. [Perspective 9] A semiconductor device, A first conductive collector layer (11), A second conductive base layer (12) is disposed on the collector layer, A first-conductivity type emitter layer (14) is disposed on the base layer and has a mesa structure in which the width in the direction intersecting the stacking direction of the collector layer and the base layer is narrower than that of the base layer, A collector electrode (22) electrically connected to the collector layer, The emitter electrode (21) is electrically connected to the emitter layer, The emitter layer and the base layer are disposed between them and have a surface recombination prevention layer (13) having a different configuration from the base layer and the emitter layer. The surface recombination prevention layer is arranged to cover a portion of one side (12a) of the base layer on the emitter layer side that could become a current path in a semiconductor device. [Perspective 10] If the portion of the surface recombination prevention layer that is positioned between the emitter layer and the base layer is designated as the first surface recombination prevention layer (13a), and the portion that is different from the first surface recombination prevention layer and covers a portion of one surface of the base layer that can become a current path is designated as the second surface recombination prevention layer (13b), The semiconductor device according to the ninth aspect, wherein the second surface recombination prevention layer is larger than the band gap of the base layer. [Perspective 11] If the portion of the surface recombination prevention layer that is positioned between the emitter layer and the base layer is designated as the first surface recombination prevention layer (13a), and the portion that is different from the first surface recombination prevention layer and covers a portion of one surface of the base layer that can become a current path is designated as the second surface recombination prevention layer (13b), The semiconductor device according to the ninth or tenth aspect, wherein the second surface recombination prevention layer has a carrier concentration and thickness that completely depletes the emitter layer and the collector layer when the device is in an ON state with current flowing between them. [Perspective 12] The base layer has a peak concentration of 2 × 10⁻⁶ of the second conductivity type. 19 cm -3 A semiconductor device described in any one of the following viewpoints 9 to 11. [Perspective 13] A semiconductor device according to any one of the 9th to 12th views, wherein an etching stopper layer (40) is disposed between the emitter layer and the base layer, the etching stopper layer (40) being made of a material different from the surface recombination prevention layer and having a lower etching rate than the surface recombination prevention layer. [Perspective 14] A semiconductor device according to any one of the first to thirteenth views, wherein at least one of the emitter layer and the base layer comprises a nitride, oxide, or carbide. [Perspective 15] The emitter layer and the base layer are, If the nitride is included, the nitride is made of a material containing Al, In, Ga, or B. The semiconductor device according to the 14th aspect, wherein, if it is composed of the aforementioned oxide, the material is composed of any of Al, In, Ga, B, Ni, Zn, Mg, Ge, Si, Ti, or Sn as the aforementioned oxide. [Perspective 16] The emitter layer and the base layer are, When the above nitride is included in the composition, Al x Ga y N 1-x-y It is constructed including (0≦x≦1, 0≦x≦1, x+y=1), When the composition includes the aforementioned oxide, (Al x Ga y ) is composed of 2O3 (0≦x≦1, 0≦x≦1, x+y=1), The semiconductor device according to the 14th aspect, which is composed of SiC or diamond when it includes the carbide. [Explanation of Symbols]

[0067] 11 Collector layer 12 Base Layer 12a one side 13 Surface recombination prevention layer 14. Emitter layer 21 Emitter electrode 22 Collector electrode 23 Base electrode

Claims

1. A semiconductor device, A first conductive collector layer (11) and A second conductive base layer (12) is disposed on the collector layer, A first-conductivity type emitter layer (14) is disposed on the base layer and has a mesa structure in which the width in the direction intersecting the stacking direction of the collector layer and the base layer is narrower than that of the base layer, A collector electrode (22) electrically connected to the collector layer, The emitter electrode (21) is electrically connected to the emitter layer, The base layer comprises a base electrode (23) electrically connected to the base layer, The emitter layer and the base layer are disposed between them and have a surface recombination prevention layer (13) which has a different configuration from the base layer and the emitter layer. The surface recombination prevention layer is arranged to cover the space between the portion of one surface (12a) of the base layer on the emitter layer side and the portion facing the base electrode in the stacking direction.

2. A second conductive first base contact layer (121) is formed on the base layer. The surface recombination prevention layer has a second base contact layer (131) of a second conductivity type that is electrically connected to the first base contact layer. The base electrode is electrically connected to the base layer through the first base contact layer and the second base contact layer. The semiconductor device according to claim 1, wherein the surface recombination prevention layer is arranged on one surface (12a) of the base layer on the emitter layer side, so as to cover the space between the portion facing the emitter layer in the stacking direction and the first base contact layer.

3. If the portion of the surface recombination prevention layer located between the emitter layer and the base layer is designated as the first surface recombination prevention layer (13a), and the portion located between the first surface recombination prevention layer and the second base contact layer is designated as the second surface recombination prevention layer (13b), The semiconductor device according to claim 2, wherein the second surface recombination prevention layer is larger than the band gap of the base layer.

4. If the portion of the surface recombination prevention layer located between the emitter layer and the base layer is designated as the first surface recombination prevention layer (13a), and the portion located between the first surface recombination prevention layer and the second base contact layer is designated as the second surface recombination prevention layer (13b), The semiconductor device according to claim 2, wherein the second surface recombination prevention layer has a carrier concentration and thickness that causes complete depletion when an ON state is reached in which current flows between the emitter layer and the collector layer.

5. The semiconductor device according to claim 2, wherein the first base contact layer and the second base contact layer have a higher carrier concentration than the base layer.

6. The semiconductor device according to claim 5, wherein the second base contact layer has a higher carrier concentration than the first base contact layer.

7. The base layer has a peak concentration of 2 × 10⁻⁶ of the second conductivity type. １９ cm －３ The semiconductor device according to claim 2, as follows:

8. The semiconductor device according to claim 2, wherein an etching stopper layer (40) is disposed between the emitter layer and the base layer, the etching stopper layer (40) being made of a material different from the surface recombination prevention layer and having a lower etching rate than the surface recombination prevention layer.

9. A semiconductor device, A first conductive collector layer (11) and A second conductive base layer (12) is disposed on the collector layer, A first-conductivity type emitter layer (14) is disposed on the base layer and has a mesa structure in which the width in the direction intersecting the stacking direction of the collector layer and the base layer is narrower than that of the base layer, A collector electrode (22) electrically connected to the collector layer, The emitter electrode (21) is electrically connected to the emitter layer, The emitter layer and the base layer are disposed between them and have a surface recombination prevention layer (13) which has a different configuration from the base layer and the emitter layer. The surface recombination prevention layer is arranged to cover a portion of one side (12a) of the base layer on the emitter layer side that could become a current path in a semiconductor device.

10. If the portion of the surface recombination prevention layer that is positioned between the emitter layer and the base layer is designated as the first surface recombination prevention layer (13a), and the portion that is different from the first surface recombination prevention layer and covers a portion of one surface of the base layer that can become a current path is designated as the second surface recombination prevention layer (13b), The semiconductor device according to claim 9, wherein the second surface recombination prevention layer is larger than the band gap of the base layer.

11. If the portion of the surface recombination prevention layer that is positioned between the emitter layer and the base layer is designated as the first surface recombination prevention layer (13a), and the portion that is different from the first surface recombination prevention layer and covers a portion of one surface of the base layer that can become a current path is designated as the second surface recombination prevention layer (13b), The semiconductor device according to claim 9, wherein the second surface recombination prevention layer has a carrier concentration and thickness that causes complete depletion when an ON state is reached in which current flows between the emitter layer and the collector layer.

12. The base layer has a peak concentration of 2 × 10⁻⁶ of the second conductivity type. １９ cm －３ The semiconductor device according to claim 9, as follows:

13. The semiconductor device according to claim 9, wherein an etching stopper layer (40) is disposed between the emitter layer and the base layer, the etching stopper layer (40) being made of a material different from the surface recombination prevention layer and having a lower etching rate than the surface recombination prevention layer.

14. The semiconductor device according to any one of claims 1 to 13, wherein at least one of the emitter layer and the base layer comprises a nitride, oxide, or carbide.

15. The emitter layer and the base layer are, If the nitride is included, the nitride is made of a material containing Al, In, Ga, or B. The semiconductor device according to claim 14, which, when composed of the aforementioned oxide, is composed of a material containing any of Al, In, Ga, B, Ni, Zn, Mg, Ge, Si, Ti, or Sn as the aforementioned oxide.

16. The emitter layer and the base layer are, When the nitride is included, Al ｘ Ga ｙ N １－ｘ－ｙ It is constructed including (0 ≤ x ≤ 1, 0 ≤ x ≤ 1, x + y = 1), When composed of the oxide, (Al ｘ Ga ｙ ), ２ O ３ where (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, x + y = 1), is included in the composition, The semiconductor device according to claim 14, which, when comprising the carbide, comprises SiC or diamond.

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