Memory control unit

Abstract

Verify that reading from program memory is performed correctly while erasing or writing to data memory or program memory. [Solution] The memory control device 100 includes a non-volatile memory circuit 13 on which data and programs are written, a first boost circuit 11 that generates a first signal necessary for erasing or writing data or programs to the memory circuit 13 when an externally acquired control signal is enabled, a second boost circuit 12 that generates a second signal necessary for reading data or programs to the memory circuit 13 when the control signal is enabled, and a CRC calculator 20 that determines whether the data or program read out according to the second signal is normal or not.

Description

Technical Field

[0001] This disclosure relates to a memory control device.

Background Art

[0002] Some microcontrollers equipped with non-volatile memories such as flash memories have a function of detecting errors in data or programs written to the non-volatile memory using CRC (Cyclic Redundancy Check) calculation as a security function.

[0003] For example, Patent Document 1 describes a power control integrated circuit provided with an error correction circuit that performs error correction when reading data from a flash memory in units of a predetermined data width.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] By the way, in the error correction circuit, CRC (Cyclic Redundancy Check) calculation is performed on the data or program written to the non-volatile memory, and by determining whether the result is as expected, it is confirmed whether there is a failure in the value of the non-volatile memory or the circuit related to the non-volatile memory.

[0006] However, since the CPU (Central Processing Unit) cannot read data or programs from the non-volatile memory during the erasure or writing of data or programs in the non-volatile memory, it is confirmed that the reading of data or programs is executed normally after the erasure or writing of data or programs.

[0007] This disclosure aims to provide a memory control device that can confirm that data or programs are being read from non-volatile memory while data or programs are being erased or written to the non-volatile memory, in light of the circumstances described above.

[0008] To solve the above problems, the memory control device according to this disclosure comprises: a non-volatile memory circuit on which data and programs are written; a first boost circuit that generates a first signal necessary for erasing or writing data or programs to the memory circuit when an externally acquired control signal is enabled; a second boost circuit that generates a second signal necessary for reading data or programs to the memory circuit when the control signal is enabled; and a check circuit that determines whether the data or program read in accordance with the second signal is normal or not. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows an example of a memory control device configuration according to the first embodiment. [Figure 2] Figure 2 shows a memory control device configuration according to a comparative example. [Figure 3] Figure 3 shows an example of a time chart for the first signal and the second signal according to the first embodiment. [Figure 4] Figure 4 shows an example of the configuration of a memory control device according to the second embodiment. [Detailed explanation]

[0010] Hereinafter, an example of an embodiment for carrying out the technology of this disclosure will be described in detail with reference to the drawings. Components and processes that perform similar operations, functions, and roles will be given the same reference numerals throughout the drawings, and redundant explanations may be omitted as appropriate. Each drawing is only a schematic representation to the extent necessary to fully understand the technology of this disclosure. Therefore, the technology of this disclosure is not limited to the illustrated examples. Furthermore, in this embodiment, explanations of configurations not directly related to this disclosure or well-known configurations may be omitted.

[0011] [First Embodiment] Figure 1 shows an example of the configuration of a memory control device 100 according to the first embodiment. As shown in Figure 1, the memory control device 100 according to this embodiment is configured as a microcontroller, for example, and includes a flash memory 10, a CRC calculator 20, a CPU 30, and a selector 40. The flash memory 10 is an example of a non-volatile memory and includes a first boost circuit 11, a second boost circuit 12, a memory circuit 13, and a switch 17.

[0012] The memory circuit 13 is a non-volatile memory circuit on which data and programs are written. The memory circuit 13 includes a data memory area 14 on which data is written and a program memory area 15 on which programs are written. The memory circuit 13 also stores a CRC expectation value 16 corresponding to the data or program.

[0013] The first boost circuit 11 generates a first signal necessary for erasing or writing data or a program to the memory circuit 13 when it activates an externally obtained control signal. The control signal is a signal prepared in advance to perform a safety function on the flash memory 10, and is obtained, for example, from the CPU 30. The first signal is a high-voltage signal necessary for erasing or writing data or a program.

[0014] When the control signal is enabled, the second boost circuit 12 generates a second signal necessary for reading data or a program from the memory circuit 13. The second signal is a voltage signal necessary for reading data or a program. The voltage of the second signal is lower than the voltage of the first signal.

[0015] The CRC calculator 20 is an example of a check circuit and uses the CRC expected value 16 to determine whether the data or program read in response to the second signal is normal or not. The CRC calculator 20 is located between the flash memory 10 and the CPU 30.

[0016] The CPU 30 is an example of a processor and controls the erasure or writing of data or programs to the flash memory 10, and the reading of data or programs.

[0017] Switch 17 disconnects the connection between the first boost circuit 11, which generates the first signal, and the memory circuit 13 while the CRC calculator 20 is performing its determination. In other words, while checking to read data or a program from the flash memory 10, the first boost circuit 11 generates the first signal, but the voltage of the first signal is controlled so that it is not applied to the memory circuit 13. Switch 17 is controlled to connect the first boost circuit 11 and the memory circuit 13 when the CRC calculator 20 is not performing its determination.

[0018] When the safety function is enabled, that is, when the connection between the first boost circuit 11 and the memory circuit 13 is disconnected by switch 17, the CRC arithmetic unit 20 outputs the address of the flash memory 10. Selector 40 is an address selector.

[0019] In the example shown in Figure 1, the first boost circuit 11 generates a first signal necessary for erasing or writing data to the data memory area 14 in response to the control signal, and the second boost circuit 12 generates a second signal necessary for reading the program to the program memory area 15. In other words, while checking to read the program from the program memory area 15, the first boost circuit 11 generates the first signal, while the voltage of the first signal is controlled so as not to be applied to the memory circuit 13.

[0020] Furthermore, depending on the control signal, the first boost circuit 11 may generate a first signal necessary for erasing or writing a program to the program memory area 15, and the second boost circuit 12 may generate a second signal necessary for reading data to the data memory area 14. In other words, while checking to read data from the data memory area 14, the first boost circuit 11 generates the first signal, while the voltage of the first signal is controlled not to be applied to the memory circuit 13.

[0021] FIG. 2 is a diagram showing the configuration of the memory control device 200 according to the comparative example. As shown in FIG. 2, the memory control device 200 according to the comparative example includes a flash memory 40, a CRC calculator 20, and a CPU 30. The flash memory 40 includes a data memory area 14, a program memory area 15, and a CRC expected value 16.

[0022] In the memory control device 200 according to the comparative example, as a security function using the CRC calculator 20, a CRC expected value 16, which is the CRC calculation result of the program memory area 15 to be read in advance, is prepared in the flash memory 40. The CPU 30 is set to the HALT mode (a mode in which the clock supply to the CPU 30 is stopped and power consumption is reduced). The program memory area 15 is read, and the read program is input to the CRC calculator 20. This process is performed on the flash memory 40, and finally, when the CRC expected value 16 is input to the CRC calculator 20, the result shows 0. Or, when all the values of the flash memory 40 are input to the CRC calculator 20, the output of the CRC calculator 20 matches the CRC expected value 16. Thereby, it is confirmed that the program in the flash memory 40 is normal (secure).

[0023] However, in the above comparative example, even if it can be confirmed that the reading of the program in the program memory area 15 is correct, it is impossible to confirm whether the reading of the program in the program memory area 15 operates normally during the erasure or writing of the data in the data memory area 14. During the erasure or writing of data, circuits other than reading operate, so it is insufficient as a security function for the program memory area 15. Also, if the erasure or writing of the data in the data memory area 14 is actually performed as a security function, the data memory value in the data memory area 14 may be rewritten. Even if the original data memory value is written back to the data memory area 14, the life of the memory cell may be shortened.

[0024] On the other hand, in the memory control device 100 according to the present embodiment, as shown in FIG. 1, a control signal used for executing the security function of the flash memory 10 is input to the flash memory 10. When this control signal is enabled, inside the flash memory 10, a first booster circuit 11 that generates a high voltage necessary for data erasure or writing is operated, but for the program memory area 15, it becomes a signal that controls the voltage necessary for program reading.

[0025] FIG. 3 is a diagram showing an example of a time chart of the first signal and the second signal according to the first embodiment. In FIG. 3, A, A + 1, A + 2,... are read addresses of the flash memory 10, showing an example when reading while incrementing. "A" in FIG. 3 indicates the address of the flash memory 10 output by the selector 40. The second signal indicates that a read boost voltage necessary for reading is generated or supplied inside the flash memory 10. So far, this is the operation of the conventional security function, but in the present embodiment, at the same time, the first signal, which is a high voltage signal necessary for erasure or writing, is generated by the first booster circuit 11. Usually, the power source used for the first booster circuit 11 is the same as the power source of a circuit other than the flash memory 10, and a microcontroller that can perform erasure or writing of the flash memory 10 and reading simultaneously must operate normally even in such a state.

[0026] As described above, according to the present embodiment, during the read check of the data or program written in the flash memory, by boosting the voltage necessary for erasure or writing of the data or program, the security function of the flash memory including during erasure or writing of the data or program can be realized.

[0027] [Second Embodiment] In the above first embodiment, the form using a CRC calculator as the check circuit has been described. In the second embodiment, the form using a BIST (Built In Self Test) circuit as the check circuit will be described.

[0028] Figure 4 shows an example of the configuration of a memory control device 100A according to the second embodiment. As shown in Figure 4, the memory control device 100A according to this embodiment is configured as a microcontroller, similar to the first embodiment, and includes a flash memory 10A, a BIST circuit 25, a CPU 30, and a selector 40. The flash memory 10A is an example of a non-volatile memory and includes a first boost circuit 11, a second boost circuit 12, a memory circuit 13, and a switch 17. The memory circuit 13 includes a data memory area 14 on which data is written and a program memory area 15 on which a program is written.

[0029] When the self-test is enabled, that is, when the connection between the first boost circuit 11 and the memory circuit 13 is disconnected by switch 17, the BIST circuit 25 outputs the address of the flash memory 10A. Selector 40 is an address selector.

[0030] As shown in Figure 4, the flash memory 10A may be equipped with a BIST circuit 25 for testing. Generally, test data is written to the flash memory 10A, and then read. Various algorithms exist for the data pattern and the address order of read. By adding a first boost circuit 11 and a second boost circuit 12 similar to those in the first embodiment described above to this mechanism, it becomes possible to perform a test equivalent to simultaneous erasure or writing and reading.

[0031] It goes without saying that the configuration of the memory control device described in each of the above embodiments is merely an example, and its configuration may be modified without departing from the spirit of the embodiment.

[0032] The following additional information is disclosed regarding the embodiments described above.

[0033] (Note 1) A non-volatile memory circuit on which data and programs are written, A first boost circuit that generates a first signal necessary for erasing or writing data or a program to the memory circuit when an externally acquired control signal is enabled, When the aforementioned control signal is enabled, a second boost circuit generates a second signal necessary for reading data or a program from the memory circuit, A check circuit that determines whether the data or program read out in response to the second signal is normal, A memory control device equipped with a memory control device. (Note 2) The check circuit further includes a switch that disconnects the connection between the first boost circuit generating the first signal and the memory circuit while the check circuit is making its determination. The memory control device described in Appendix 1. (Note 3) The memory circuit includes a data memory area where data is written and a program memory area where a program is written. The first boost circuit generates the first signal necessary for erasing or writing data to the data memory area. The second boost circuit generates the second signal necessary for reading the program from the program memory area. The memory control device described in Appendix 1 or Appendix 2. (Note 4) The memory circuit includes a data memory area where data is written and a program memory area where a program is written. The first boost circuit generates the first signal necessary for erasing or writing a program to the program memory area. The second boost circuit generates the second signal necessary for reading data from the data memory area. The memory control device described in Appendix 1 or Appendix 2. (Note 5) The aforementioned check circuit is configured as a CRC calculator. A memory control device as described in any one of the appendices 1 to 4. (Note 6) The aforementioned check circuit is configured as a BIST circuit. A memory control device as described in any one of the appendices 1 to 4. [Explanation of Symbols]

[0034] 10,10A Flash Memory 11. First Boost Circuit 12. Second Boost Circuit 13 Memory Circuit 14. Data memory area 15 Program memory area 16 CRC Expected Value 17 Switches 20 CRC calculator 25 BIST Circuit 30 CPU 40 Selector 100,100A Memory Control Unit

Claims

1. A non-volatile memory circuit on which data and programs are written, A first boost circuit generates a first signal necessary for erasing or writing data or a program to the memory circuit when an externally acquired control signal is enabled, When the aforementioned control signal is enabled, a second boost circuit generates a second signal necessary for reading data or a program from the memory circuit, A check circuit that determines whether the data or program read out in response to the second signal is normal, A memory control device equipped with a memory control device.

2. The check circuit further includes a switch that disconnects the connection between the first boost circuit generating the first signal and the memory circuit while the check circuit is making a determination. The memory control device according to claim 1.

3. The memory circuit includes a data memory area where data is written and a program memory area where a program is written. The first boost circuit generates the first signal necessary for erasing or writing data to the data memory area. The second boost circuit generates the second signal necessary for reading the program from the program memory area. The memory control device according to claim 1 or claim 2.

4. The memory circuit includes a data memory area where data is written and a program memory area where a program is written. The first boost circuit generates the first signal necessary for erasing or writing a program to the program memory area. The second boost circuit generates the second signal necessary for reading data from the data memory area. The memory control device according to claim 1 or claim 2.

5. The aforementioned check circuit is configured as a CRC calculator. The memory control device according to claim 1 or claim 2.

6. The aforementioned check circuit is configured as a BIST circuit. The memory control device according to claim 1 or claim 2.

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