Reference current source circuit

Abstract

This enables the stabilization of the temperature characteristics of transconductance without being affected by the source-bulk voltage. [Solution] The system comprises first to fourth NMOS transistors 11-14 whose source is connected to ground, first and second current mirror circuits 101, 102, and a voltage-current converter 103. The second current mirror circuit 102 uses second and third NMOS transistors 12, 13, and the input stage I1 of the voltage-current converter 103 VI1 The drain of the second NMOS transistor 12 and the output stage O1 of the first current mirror circuit CM1 The first output stage O1 of the voltage-current converter 103 is connected to it. VI1 The drain of the third NMOS transistor 13 is connected via resistor 21 to the input stage I1 of the voltage-current converter 103. VI1 The configuration includes a negative feedback loop that extends from the first NMOS transistor 12 to the drain, enabling stabilization of the temperature characteristics of the transconductance.

Description

[Technical Field]

[0001] The present invention relates to a reference current source circuit used in analog circuits and the like provided within an integrated circuit, and more particularly to a circuit that improves the stability of output characteristics by suppressing the so-called bulk effect. [Background technology]

[0002] As is well known, reference current source circuits are used as functional circuits that generate and supply the reference current required in various analog circuits (see, for example, Non-Patent Document 1). Figure 4 shows an example of a conventional reference current source circuit configuration disclosed in Non-Patent Document 1. The conventional circuit will be described below with reference to this figure. This reference current source circuit consists of a first current mirror circuit 201 and a second current mirror circuit 202, which are cascaded between the power supply voltage VDD and ground, and the first output transistor M p3p Therefore, the so-called source current (blowing current) is generated by the second output transistor M n3p Each of these components is configured to generate what is known as a sink current (sink current).

[0003] In this example, the first current mirror circuit 201 consists of three transistors M, which are PMOS (P-type metal-oxide-semiconductor) transistors. p1p M p2p M p3p It is composed of the following. Furthermore, the second current mirror circuit 202 consists of three transistors M, which are NMOS (N-type metal-oxide-semiconductor) transistors. n1p M n2p M n3p It is composed of the following.

[0004] Next, we will explain the operating principle of this conventional circuit. First, as a characteristic of NMOS transistors, the drain-source current IDSN In the saturation region, it is expressed as shown in Equation 1 below.

[0005] I DSN = (μ n C oxn W n / 2L n )(V GSN - V thn ) 2 ··· Equation 1

[0006] Here, μ n is the mobility of the NMOS transistor, C oxn is the gate oxide capacitance per unit area of the NMOS transistor, W n is the gate width of the NMOS transistor, L n is the gate length of the NMOS transistor, V GSN is the gate-source voltage of the NMOS transistor, and V thn is assumed to be the threshold voltage of the NMOS transistor.

[0007] On the other hand, as the characteristics of the PMOS transistor, the drain-source current I DSP is expressed as shown in Equation below in the saturation region.

[0008] I DSP = (μ p C oxp W p / 2L p )(V GSP - V thp ) 2 ··· Equation 2

[0009] Here, μ p is the mobility of the PMOS transistor, C oxp is the gate oxide capacitance per unit area of the PMOS transistor, W p is the gate width of the PMOS transistor, L p is the gate length of the PMOS transistor, V GSP is the gate-source voltage of the PMOS transistor, and V thp is assumed to be the threshold voltage of the PMOS transistor.

[0010] Furthermore, in the configuration shown in Figure 4, three PMOS transistors M operate in the saturation region. p1p ~M p3p Design all gates to have the same width and all gates to have the same length. In the configuration shown in Figure 4, three PMOS transistors M p1p ~M p3p Each gate-source voltage V GSP _ Mp1p ,V GSP _ Mp2p ,V GSP _ Mp3p They are all equal. As a result, in the configuration shown in Figure 4, three PMOS transistors M p1p ~M p3p Each drain-source current I DSP _ Mp1p ,I DSP _ Mp2p ,I DSP _ Mp3p They are all equal.

[0011] On the other hand, for NMOS transistors, within the range where they operate in the saturation region, two NMOS transistors M n1p M n3p The gate widths are designed to be equal, and the gate lengths are also designed to be equal. And, in the range where it operates in the saturation region, the NMOS transistor M n2p The gate width of the NMOS transistor M n1p While designing it to be larger than the gate width of the NMOS transistor M n2p The gate length of the NMOS transistor M n1p Design it to be equal to the gate length.

[0012] In the configuration shown in Figure 4, the PMOS transistor M p1p Drain-source current I DSP _ Mp1p and PMOS transistor M p2p Drain-source current I DSP _ Mp2p Since they are equal, the NMOS transistor Mn1p Drain-source current I between DSN _ Mn1p and NMOS transistor M n2p is also equal to the drain-source current I DSN _ Mn2p between them.

[0013] Therefore, in Figure 4, the following equations 3A, 3B, and 3C hold.

[0014] I DSN _ Mn1p = (μ n C oxn W n _ Mn1p / 2L n _ Mn1p )(V GSN _ Mn1p - V thn ) 2 ··· Equation 3A

[0015] I DSN _ Mn2p = (μ n C oxn W n _ Mn2p / 2L n _ Mn2p )(V GSN _ Mn2p - V thn ) 2 ··· Equation 3B000038800003890000390I DSN _ Mn1p = I DSN _ Mn2p ··· Equation 3C

[0017] From the configuration of Figure 4, the voltage across resistor R bp is V GSN _ Mn1p - V GSN _ Mn2p and the drain-source current I n2p of NMOS transistor M DSN _ Mn2p flows directly into resistor R bp as it is, so the current I bp flowing through resistor Rbiasp This can be expressed as shown in equation 4A below.

[0018] I biasp =(V GSN _ Mn1p - V GSN _ Mn2p ) / R bp ...Formula 4A

[0019] Furthermore, the following equation 4B holds true between each current.

[0020] I DSN _ Mn1p =I DSN _ Mn2p =I biasp ...Formula 4B

[0021] Note, R bp This is a resistor R bp Let this be the resistance value. Then, by rearranging equations 3A and 3B above into gate-source voltage form, we can obtain equations 5A and 5B as shown below.

[0022] V GSN _ Mn1p ={I DSN _ Mn1p / (μ n C oxn W n _ Mn1p / 2L n _ Mn1p )} 1 / 2 +V thn ...Formula 5A

[0023] V GSN _ Mn2p ={I DSN _ Mn2p / (μ n C oxn W n _ Mn2p / 2L n _ Mn2p )} 1 / 2 +V thn ...Formula 5B

[0024] Applying equation 4B to equations 5A and 5B, they can be rewritten as equations 6A and 6B shown below.

[0025] V GSN _ Mn1p ={I biasp / (μ n C oxn W n _ Mn1p / 2L n _ Mn1p )} 1 / 2 +V thn ...Formula 6A

[0026] V GSN _ Mn2p ={I biasp / (μ n C oxn W n _ Mn2p / 2L n _ Mn1p )} 1 / 2 +V thn ...Formula 6B

[0027] Furthermore, substituting equations 6A and 6B into the previous equation 4A and rearranging, we get the resistor R bp Current I flowing through bisp This can be expressed as shown in Equation 7 below.

[0028] I biasp ={2 / (μ n C oxn R 2 bp )}{(L n _ Mn1p / W n _ Mn1p ) 1 / 2 (L n _ Mn2p / W n _ Mn2p ) 1 / 2} 2 ...Formula 7

[0029] Here, differentiating equation 1 with respect to the gate-source voltage, we get the transconductance g of the NMOS transistor. mn This can be expressed as shown in Equation 8 below.

[0030] g mn =∂I DSN / ∂V GSN =(μ n C oxn W n / L n )(V GSN -V thn )...Equation 8

[0031] Furthermore, taking the square root of both sides of equation 1 yields equation 9 below.

[0032] I 1 / 2 DSN =(μ n C oxn W n / 2L n ) 1 / 2 (V GSN -V thn )...Equation 9

[0033] Furthermore, by using equation 9 to transform equation 8, we obtain equation 10 shown below.

[0034] g mn ={2(μ n C oxn W n / L n )I DSN} 1 / 2 ...Formula 10

[0035] I in Equation 10 DSN However, I shown in Equation 7 biasp If we assume that it is biased by , then equation 10 can be rewritten as equation 11 below.

[0036] g mn =(2 / R bp )(W n / L n ) 1 / 2 {(L n _ Mn1p / W n _ Mn1p ) 1 / 2 -(L n _ Mn2p / W n _Mn2p ) 1 / 2}...Equation 11

[0037] According to equation 11, the transconductance g mn Factors that contribute to the temperature characteristics are R bp It can be confirmed that this is the only case. Generally, as described in Non-Patent Document 1 and other sources, it is known that in a CMOS process, the temperature characteristics of the mobility of a MOS transistor are exponential, while the temperature characteristics of a resistor are polynomial. In equation 11, mobility is removed, which means g mn In terms of temperature characteristics, this means that the fluctuations in temperature characteristics are reduced, resulting in a more flat response to temperature changes.

[0038] The transconductance g mentioned above mn The temperature characteristics are based on the assumption that the source-bulk voltage of all MOS transistors is zero, and this assumption holds true for double-well CMOS and triple-well CMOS processes. [Prior art documents] [Non-patent literature]

[0039] [Non-Patent Document 1] Phillip E. Allen and Douglas R. Holberg, "CMOS Analog Circuit Design", OXFORD UNIVERSITY PRESS [Overview of the project] [Problems that the invention aims to solve]

[0040] However, in the case of a p-substrate type single-well CMOS process, all NMOS bulk terminals are electrically connected on the p-substrate, and the p-substrate is electrically grounded. Therefore, in principle, it cannot be said that the source-bulk voltage can always be made zero. In the conventional circuit shown in Figure 4, the NMOS transistor M n2p This falls under that category.

[0041] Furthermore, if the source-bulk voltage is not zero, the threshold voltage V of the NMOS transistor is... thn According to Non-Patent Document 1, it has been shown that this can be expressed as shown in Equation 12 below.

[0042] V thn =V THN0 +γ{(2φ f +V SBN ) 1 / 2 -(2φ f ) 1 / 2}...Equation 12

[0043] Here, V SBN V is the source-bulk voltage of an NMOS transistor. THN0 is V SBN The threshold voltage of an NMOS transistor, γ and φ when = 0. f This is a constant that depends on the manufacturing process. The transconductance g above is assumed to be zero under the assumption that the source-bulk voltage is zero. mn In the explanation of the temperature characteristics of the NMOS transistor M, the derivation of Equation 7 from Equations 6A and 6B was based on the assumption that the threshold voltages were equal. However, n2p If the source-bulk voltage is not zero, the threshold voltage in equation 6B becomes what is expressed in equation 12, and equation 7 can no longer be derived. This means that the transconductance g shown in equation 11 above is the same as that g. mn This means that the desired effect is lost, and the reduction in temperature characteristics is lost.

[0044] The present invention has been made in view of the above circumstances, and provides a reference current source circuit that can stabilize the temperature characteristics of transconductance without being affected by the source-bulk voltage. [Means for solving the problem]

[0045] To achieve the above-mentioned objectives of the present invention, the reference current source circuit according to the present invention is: First and second current mirror circuits, voltage-current converter, It has first to fourth NMOS transistors whose source is connected to ground, The second current mirror circuit is made up of the second and third NMOS transistors, The drain of the first NMOS transistor is connected to the input stage of the first current mirror circuit. The drain of the second NMOS transistor and the input stage of the voltage-current converter are connected to the output stage of the first current mirror circuit. The gate of the second NMOS transistor is connected to the gate and drain of the third NMOS transistor. The first output stage of the voltage-current converter is connected to the gate of the first NMOS transistor and the gate of the fourth NMOS transistor. A resistor is connected between the first output stage of the voltage-current converter and the drain of the third NMOS transistor. The first output current, which serves as the reference current, is obtained from the second output stage of the aforementioned voltage-current converter. The second output current, which serves as the reference current, is obtained from the drain of the fourth NMOS transistor. Each is configured to be capable of outputting an output. [Effects of the Invention]

[0046] According to the present invention, since the source-bulk voltage is always maintained at zero, unlike conventional circuits, the temperature characteristics of the transconductance are stabilized without being affected by the source-bulk voltage, and this provides a more stable and reliable reference current source circuit. [Brief explanation of the drawing]

[0047] [Figure 1] This is a block diagram showing an example of the basic circuit configuration of a reference current source circuit in an embodiment of the present invention. [Figure 2] Figure 1 is a circuit diagram showing a specific example of the reference current source circuit. [Figure 3] This characteristic diagram shows an example of the temperature characteristics of the transconductance in a reference current source circuit according to an embodiment of the present invention. [Figure 4] This is a circuit diagram showing an example of a conventional reference current source circuit configuration. [Modes for carrying out the invention]

[0048] Hereinafter, embodiments of the present invention will be described with reference to Figures 1 to 3. The components, arrangements, etc., described below are not intended to limit the present invention and can be modified in various ways within the scope of the spirit of the present invention. First, a basic configuration example of a reference current source circuit in an embodiment of the present invention will be described with reference to Figure 1. The reference current source circuit in the embodiment of the present invention comprises a first current mirror circuit (indicated as "CM1" in Figure 1) 101, a voltage-current converter (indicated as "VI1" in Figure 1) 103, and first to fourth NMOS (N-type metal-oxide-semiconductor) transistors (indicated as "M" in Figure 1). n1 "M n2 "M n3 "M n4 It is composed primarily of elements 11-14 (as indicated by the notation ").

[0049] To give a general overview of the circuit configuration of such a reference current source circuit, first, the first to fourth NMOS transistors 11 to 14 are all provided with their sources connected to ground. Then, the input stage I1 of the first current mirror circuit 101 CM1 The drain of the first NMOS transistor 11 is connected to this, and this first NMOS transistor 11 is operated by the voltage-current converter 103, as will be described in detail later.

[0050] Also, the output stage O1 of the first current mirror circuit 101 CM1 This, along with the drain of the second NMOS transistor 12 which constitutes the output stage of the second current mirror circuit 102, is connected to the input stage I1 of the voltage-current converter 103. VI1 Connected. First output stage O1 of the voltage-current converter 103 VI1 This is connected via a resistor (labeled "Rb" in Figure 1) 21 to the drain of the third NMOS transistor 13, which serves as the input stage of the second current mirror circuit 102. Furthermore, the first output stage O1 of the voltage-current converter 103 VI1 This is connected to the gate of the fourth NMOS transistor 14, which acts as a second output transistor that outputs a sink current, which is the reference current (details will be described later). Furthermore, the second output stage O2 of the voltage-current converter 103 VI1 This is an output stage that outputs a source current as a reference current (details will be described later).

[0051] Figure 2 shows a more specific example of the circuit configuration of the reference current source circuit of the present invention, and the specific circuit will be described with reference to this figure. Note that components identical to those shown in Figure 1 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. Furthermore, the explanation of the operation of the specific circuit shown in Figure 2 will be used in place of the explanation of the operation of the basic circuit configuration example shown in Figure 1.

[0052] First, the first current mirror circuit 101 consists of first and second PMOS (P-type metal-oxide-semiconductor) transistors (in Figure 2, these are referred to as "M"). p1 "M p2 It consists of 1 and 2 (written as "). Furthermore, the voltage-current converter 103 includes third and fourth PMOS transistors (in Figure 2, these are referred to as "M"). p3 "M p4 It consists of 3 and 4 (indicated as ").

[0053] In the first current mirror circuit 101, the gates of the first and second PMOS transistors 1 and 2 are interconnected, and the drain of the first PMOS transistor 1 (input stage I1) CM1 ) is connected to the positive supply voltage V, while each source is connected to the positive supply voltage V. DD It is set to be applied. Also, the drain of the second PMOS transistor 2 (output stage O1 CM1 ) is the input stage I1 of the voltage-current converter 103, which will be described later. VI1 It is connected to the drain of the second NMOS transistor 12 which constitutes the output stage of the second current mirror circuit 102.

[0054] In the voltage-current converter 103, the third and fourth PMOS transistors 3 and 4 have their respective sources both connected to the positive power supply voltage V DD While a voltage is applied, the gates are interconnected and the input stage I1 VI1 That's how it is. Furthermore, the drain of the third PMOS transistor 3 is connected to the first output stage O1 VI1 One end of the resistor 21 is connected to the drain of the third NMOS transistor 13 of the second current mirror circuit 102. Furthermore, the drain of the fourth PMOS transistor 4 is connected to the second output stage O2 VI1 It is connected to the first output terminal 31, and as described later, the reference current I O1 It is stated that a source current can be output as such.

[0055] In the second current mirror circuit 102, the gates of the second and third NMOS transistors 12 and 13 are interconnected, and the drain of the third NMOS transistor 13 is connected to them. The drain from the third NMOS transistor 13, which is the input stage, is connected to the first output stage O1 of the voltage-current converter 103 via the resistor 21. VI1 It is connected to the drain of the third PMOS transistor 3.

[0056] Furthermore, the drain of the second NMOS transistor 12, which forms the output stage, is connected to the output stage O1 of the first current mirror circuit 101. CM1 It is connected to the drain of the second PMOS transistor 2. Furthermore, the first output stage O1 of the voltage-current converter 103 VI1 The drain of the third PMOS transistor 3 is connected to the gate of the first NMOS transistor 11. Then, the drain from the first NMOS transistor 11 is connected to the input stage I1 of the first current mirror circuit 101. CM1 It is connected to the drain of the first PMOS transistor 1.

[0057] Furthermore, the first output stage O1 of the voltage-current converter 103 VI1 The drain of the third PMOS transistor 3 is connected to the gate of the fourth NMOS transistor 14. The drain of this fourth NMOS transistor 14 is connected to the second output terminal 32, and as will be described later, a reference current I O2 This allows for the acquisition of sink current.

[0058] Next, the circuit operation in this configuration will be described. First, in the reference current source circuit shown in Figure 2, since the sources of all NMOS transistors are connected to ground, the source-bulk voltage is maintained at zero V even in the case of a single-well CMOS process where the p-substrate is potentialally grounded. This means that, in equation 12 above, the threshold voltages of all NMOS transistors become equal.

[0059] Furthermore, in Figure 2, the ratio of the input current to the output current of the first current mirror circuit 101 is designed to be 1:1, and the gate widths of the second NMOS transistor 12 and the third NMOS transistor 13 are designed to be equal. Furthermore, the gate width of the first NMOS transistor 11 is designed to be smaller than that of the second NMOS transistor 12, while being equal to that of the fourth NMOS transistor 14. Furthermore, the gate lengths of the first to fourth NMOS transistors 11 to 14 are designed to be equal.

[0060] With this configuration, the input stage I1 of the voltage-current converter 103 VI1 Due to the effect of the negative feedback loop from the first output stage O1 of the voltage-current converter 103 to the drain of the second NMOS transistor 12, VI1 The current flowing through it becomes equal to the drain-source current of the first to fourth NMOS transistors 11 to 14. In this case, the voltage across resistor 21 is the gate voltage V of the first NMOS transistor 11. GSN _ Mn1 And the gate voltage V of the second NMOS transistor 12 GSN _ Mn2 Since it is the difference between the two, the current flowing through resistor 21 is I bias Therefore, equations 13A and 13B below hold true.

[0061] I bias =(V GSN _ Mn1 -V GSN _ Mn2 ) / R b ...Formula 13A

[0062] I DSN _ Mn1 =I DSN _ Mn2 =I DSN _ Mn3 =I DSN _ Mn4 =I bias ...Formula 13B

[0063] Note that here, R b This is the resistance value of resistor 21.

[0064] Furthermore, the gate width of the first NMOS transistor 11 is set to W n _Mn1 The gate length of the first NMOS transistor 11 is set to L n _ Mn1 The gate width of the second NMOS transistor 12 is set to W n _ Mn2 The gate length of the second NMOS transistor 12 is set to L n _ Mn2 Therefore, by performing the same calculations in Equation 13 as in Equations 3 through 7, we obtain Equation 14 shown below.

[0065] I bias ={2 / (μ n C oxn R 2 b )}{(L n _ Mn1 / W n _ Mn1 ) 1 / 2 -(L n _ Mn2 / W n _ Mn2 ) 1 / 2} 2 ...Formula 14

[0066] Equation 14 corresponds to Equation 7, which is assumed to hold true in conventional circuits under the assumption that the source-bulk voltage can be maintained at zero V. In conventional circuits, however, the source-bulk voltage cannot always be maintained at zero V, and Equation 7 does not always hold true. In contrast, in the reference current source circuit of the embodiment of the present invention, as described above, the source-bulk voltage is always maintained at zero V, so Equation 14 always holds true, and the effect of reducing the temperature characteristics of the transistor's transconductance is reliably obtained.

[0067] In the reference current source circuit shown in Figure 2, the gate width and gate length of each transistor described above are set to the second output stage O2 of the voltage-current converter 103. VI1 The first output terminal 31 connected to it receives the first output current I, which is the reference current. O1 This allows us to obtain a source current that is the same current value as the current flowing through resistor 21. Furthermore, according to equation 13B, the second output current I at the second output terminal 32 is the reference current, which is the drain current of the fourth NMOS transistor 14, having the same current value as the current flowing through the resistor 21. O2 It is output as follows. Note that the reference current at this second output terminal 32 is the sink current.

[0068] Figure 3 shows a characteristic diagram illustrating the simulation results of the change in transconductance in response to ambient temperature changes in a reference current source circuit according to an embodiment of the present invention. The figure will be described below. First, in Figure 3, the horizontal axis represents ambient temperature, and the vertical axis represents transconductance. In Figure 3, the simulation results of the transconductance change characteristics of the reference current source circuit in the embodiment of the present invention with respect to ambient temperature changes are shown by the solid characteristic curve. Furthermore, in Figure 3, the same simulation results for a conventional circuit (see Figure 4) are shown by the dashed characteristic curve.

[0069] Comparing the two, it can be confirmed that the reference current source circuit in the embodiment of the present invention exhibits an extremely small change in transconductance in response to changes in ambient temperature compared to the conventional circuit, and shows a flatter temperature characteristic compared to the conventional circuit. In Figure 3, comparing the slopes of the characteristic curves at around 40°C where the two characteristic curves intersect, the slope of the characteristic curve of the conventional circuit is approximately -0.19 [nS / K], while the slope of the characteristic curve of the present invention is extremely small at -0.0058 [nS / K], indicating an improvement effect of more than three times compared to the conventional circuit. [Industrial applicability]

[0070] This can be applied to reference current source circuits where stabilization of the temperature characteristics of transconductance is desired, without being affected by the source-bulk voltage. [Explanation of Symbols]

[0071] 1…First PMOS transistor 2…Second PMOS transistor 3…Third PMOS transistor 4…Fourth PMOS transistor 11…First NMOS transistor 12…Second NMOS transistor 13…Third NMOS transistor 14…The fourth NMOS transistor 101...First current mirror circuit 102...Second current mirror circuit 103...Voltage-current converter

Claims

1. First and second current mirror circuits, voltage-current converter, It comprises a first to fourth NMOS transistor whose source is connected to ground, The second current mirror circuit is made up of the second and third NMOS transistors, The drain of the first NMOS transistor is connected to the input stage of the first current mirror circuit. The drain of the second NMOS transistor and the input stage of the voltage-current converter are connected to the output stage of the first current mirror circuit. The gate of the second NMOS transistor is connected to the gate and drain of the third NMOS transistor. The first output stage of the voltage-current converter is connected to the gate of the first NMOS transistor and the gate of the fourth NMOS transistor. A resistor is connected between the first output stage of the voltage-current converter and the drain of the third NMOS transistor. The first output current, which serves as the reference current, is output from the second output stage of the voltage-current converter. The second output current, which serves as the reference current, is obtained from the drain of the fourth NMOS transistor. A reference current source circuit characterized by being configured to output each of the following:

2. The reference current source circuit according to claim 1, characterized in that the first current mirror circuit uses a PMOS transistor.

3. The reference current source circuit according to claim 1 or 2, characterized in that the voltage-current converter uses a PMOS transistor.

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