Semiconductor packages

Abstract

We provide a compact, highly efficient IVR (Integrated Voltage Regulator) package that enables miniaturization of electronic devices. [Solution] A semiconductor package 1 comprising an interposer 10 incorporating an IVR chip 20 and a first capacitor 30, wherein the interposer 10 includes a core layer 11 having a first surface and a second surface on the opposite side, a first wiring layer 14 formed on the first surface side of the core layer, a second wiring layer 15 formed on the second surface side of the core layer, and a through-hole conductor 16 electrically connected to the first wiring layer 14 and the second wiring layer 15 and formed to penetrate from the first surface to the second surface. In a plan view, the IVR chip 20 and the first capacitor 30 are surrounded by the through-hole conductor 16, and at least a portion of the IVR chip 20 and the first capacitor 30 overlap.

Description

Technical Field

[0001] The present invention relates to a semiconductor package.

Background Art

[0002] A voltage regulator (VR) is widely used to supply a constant voltage to electronic devices such as computers, servers, and smartphones. For the operation of a voltage regulator, an inductor and a capacitor are required. Conventionally, however, the voltage regulator, the inductor, and the capacitor have been mounted on a substrate. However, there has been a problem that the mounting area becomes large and the size of the electronic device becomes large.

[0003] To solve the above problems, an IVR (Integrated Voltage Regulator) package in which a voltage regulator, an inductor, and a capacitor are housed in one package has been disclosed. Patent Document 1 discloses a voltage conversion module. This voltage conversion module includes a multilayer wiring board having a plurality of layers of wiring patterns, a voltage conversion IC mounted on one of the inner layers of the plurality of layers of wiring patterns, a first capacitor electrically connected to the voltage conversion IC, a second capacitor electrically connected to the voltage conversion IC, and an inductor mounted adjacent to the second capacitor and electrically connected to the voltage conversion IC. Further, Patent Document 2 discloses an IVR package including an inductor and a capacitor. This IVR package has a laminated structure including a package substrate, a laminated structure having a passive element chip equipped with a capacitor and an IVR chip mounted on the package substrate, and an intermediate substrate disposed on the package substrate, having a structure surrounding the laminated structure, and having vias inside, and the inductor is included in the laminated structure or the intermediate substrate.

Prior Art Documents

Patent Documents

[0004] [Patent Document 1] Japanese Patent Publication No. 2012-079718 [Patent Document 2] Japanese Patent Publication No. 2023-116418 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, because the IVR chip is far from devices such as the CPU (Central Processing Unit) and GPU (Graphics Processing Unit), which consume large amounts of current, it suffers from poor voltage conversion efficiency. Furthermore, reducing the resistance of the inductor requires increasing its size, leading to the problem of larger IVR packages.

[0006] The present invention aims to solve the above problems and provide an IVR package that is compact, has high conversion efficiency, and enables miniaturization of electronic devices. [Means for solving the problem]

[0007] The invention described in claim 1 is a semiconductor device comprising an interposer incorporating an IVR (Integrated Voltage Regulator) chip and a first capacitor, wherein the interposer includes a core layer having a first surface and a second surface on the opposite side thereof, a first wiring layer formed on the first surface side of the core layer, a second wiring layer formed on the second surface side of the core layer, and through-hole conductors electrically connected to the first and second wiring layers and formed to penetrate from the first surface to the second surface, wherein in a plan view, the IVR chip and the first capacitor are surrounded by the through-hole conductors, and at least a portion of the IVR chip and the first capacitor overlap. The invention described in claim 2 is a semiconductor package according to claim 1, further comprising a logic chip mounted face down on a first wiring layer formed on the first surface side of the core layer of the interposer, and characterized in that, in a plan view, at least a portion of each of the logic chip, the IVR chip built into the interposer, and the first capacitor overlap each other. The invention described in claim 3 is a semiconductor package according to claim 1 or 2, characterized in that the interposer is mounted on a package substrate via electrodes formed on the surface of the second wiring layer formed on the second surface side of the core layer. The invention described in claim 4 is a semiconductor package according to claim 3, characterized in that the package substrate incorporates an inductor, and in a plan view, at least a portion of each of the inductor incorporated in the package substrate, the IVR chip incorporated in the interposer, the first capacitor, and the logic chip mounted face down on the interposer overlap each other. The invention described in claim 5 is a semiconductor package according to any one of claims 1 to 4, characterized in that the IVR chip embedded in the interposer is mounted face-down on the second wiring layer formed on the second surface side of the core layer and is electrically connected. The invention described in claim 6 is a semiconductor package according to any one of claims 1 to 5, characterized in that the first capacitor built into the interposer is mounted face-up on the first wiring layer formed on the first surface side of the core layer and is electrically connected. The invention described in claim 7 is a semiconductor package according to any one of claims 1 to 6, characterized in that the IVR chip and the first capacitor built into the interposer are in a stacked structure in contact with each other. The invention described in claim 8 is a semiconductor package according to claim 7, characterized in that the laminate of the IVR chip and the first capacitor is mounted face up on the IVR chip, which is mounted face down on the second wiring layer formed on the second surface side of the core layer, using an adhesive. The invention described in claim 9 is a semiconductor package according to claim 4, characterized in that the first capacitor built into the interposer is mounted face-down on the second wiring layer formed on the second surface side of the core layer and is electrically connected. The invention described in claim 10 is a semiconductor package according to claim 9, characterized in that the first capacitor, which is mounted face-down on the second wiring layer formed on the second surface side of the core layer, includes through electrodes. The invention described in claim 11 is a semiconductor package according to claim 10, characterized in that the IVR chip is mounted face-down on the first capacitor which is mounted face-down on the second wiring layer formed on the second surface side of the core layer, and the IVR chip is electrically connected to the second wiring layer by the through-electrode. The invention described in claim 12 is a semiconductor package according to any one of claims 8 to 11, characterized in that the interposer incorporates a second capacitor having a smaller capacitance than the first capacitor, adjacent to the laminate of the IVR chip and the first capacitor. The invention described in claim 13 is a semiconductor package according to claim 12, characterized in that the second capacitor is mounted face-down on the second wiring layer formed on the second surface side of the core layer and is electrically connected. The invention described in claim 14 is a semiconductor package according to claim 12, characterized in that the second capacitor is mounted face-up on the first surface side of the core layer and is electrically connected to the first wiring layer formed on the first surface side of the core layer. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide an IVR package that is small, has high conversion efficiency, and enables miniaturization of electronic devices. [Brief explanation of the drawing]

[0009] [Figure 1] This is a diagram showing a semiconductor package according to the first embodiment. [Figure 2] This is a plan view of the interposer. [Figure 3] This figure shows a semiconductor package of a modified example 1 of the first embodiment. [Figure 4] This is a diagram showing a semiconductor package according to the second embodiment. [Figure 5] This is a partially enlarged view of the semiconductor package according to the second embodiment. [Figure 6] This figure shows a semiconductor package according to a third embodiment. [Figure 7] This figure shows a semiconductor package of a modified example 1 of the third embodiment. [Modes for carrying out the invention]

[0010] <First Embodiment> The embodiments will be described in detail below with reference to the attached drawings. Figure 1 is a diagram showing a semiconductor package 1 of the first embodiment. The semiconductor package 1 of the first embodiment includes an interposer 10, an IVR chip 20, a first capacitor 30, an inductor 40, a logic chip 50, a memory chip 60, a package substrate 70, and a sealing resin 90.

[0011] The interposer 10 is a substrate for electrically connecting a plurality of chips. The interposer 10 includes a core layer 11 made of resin. A first wiring layer 14 is formed on the first surface 12 side of the core layer 11, and a second wiring layer 15 is formed on the second surface 13 side of the core layer 11. And it has through-hole conductors 16 penetrating from the first surface 12 to the second surface 13 of the core layer 11. The through-hole conductors 16 are electrically connected to the first wiring layer 14 and the second wiring layer 15. Further, the interposer 10 includes a first bump 17 as an example of an electrode outside the second wiring layer 15. The interposer 10 is mounted on a package substrate 70 described later by the first bump 17.

[0012] The IVR chip 20 is a voltage regulator and plays a role of supplying a constant voltage to an electronic device mounted on the interposer 10. The IVR chip 20 controls the voltage by repeatedly turning on and off a switch element. As the switch element, a MOSFET can be exemplified. The IVR chip 20 is mounted inside the interposer 10 in a face-down state and is electrically connected to the second wiring layer 15 by a second bump 21.

[0013] The first capacitor 30 is an element necessary for the operation of the IVR chip 20. The first capacitor 30 is connected to GND (earth), which is the reference potential, and / or VSS (negative power supply of the FET) for the purpose of storing electric charges. A capacitor with a large capacitance is used for the first capacitor 30 to prevent fluctuations in the power supply voltage and absorb ripple noise. As the first capacitor 30, a thin-film capacitor, a silicon capacitor, or the like is used.

[0014] The first capacitor 30 is laminated on the IVR chip 20, and the first capacitor 30 and the IVR chip 20 have a laminated structure. The first capacitor 30 may be directly laminated on the IVR chip 20, or may be laminated via an adhesive 80. The first capacitor 30 is mounted in the interposer 10 in a face-up state and is electrically connected to the first wiring layer 14 by the third bump 31. In FIG. 1, the IVR chip 20 and the first capacitor 30 are completely overlapped, but it is not limited thereto, and a state where a part thereof is overlapped may also be possible.

[0015] The inductor 40 is an element necessary for the operation of the IVR chip 20 together with the first capacitor 30. Due to its own resistance, when current flows through the inductor 40, power loss occurs, the voltage conversion efficiency decreases, and heat is generated due to the power loss. Therefore, it is preferable that the resistance of the inductor 40 is small. In order to reduce the resistance of the inductor 40, it is necessary to increase the cross-sectional area of the conductor constituting the inductor 40, and the size of the inductor 40 tends to increase. When a large-sized inductor 40 is mounted inside the interposer 10, the size of the entire package becomes large. Therefore, the inductor 40 is mounted inside the package substrate 70 with sufficient space. By incorporating the inductor 40 into the package substrate 70, miniaturization of the semiconductor package 1 becomes possible. The inductor 40 is arranged so as to overlap the IVR chip 20 and the first capacitor 30 in a plan view. Here, the plan view refers to a state where the semiconductor package 1 is viewed from the logic chip 50 side toward the package substrate 70 side in FIG. 1.

[0016] When the IVR chip 20, the first capacitor 30, and the inductor 40 are arranged horizontally in a planar manner, the distance between them increases. However, if at least one of the first capacitor 30 and the inductor 40 overlaps the IVR chip 20 vertically, the distance between them decreases, reducing parasitic capacitance and parasitic resistance. This improves the operating characteristics of the IVR chip 20 and enhances voltage conversion efficiency. In Figure 1, the inductor 40 is positioned so as to completely overlap the IVR chip 20 and the first capacitor 30 in a planar view. However, the arrangement is not limited to this; voltage conversion efficiency can also be improved even if only a portion of each component overlaps.

[0017] The logic chip 50 is, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or a DSP (Digital Signal Processor). The logic chip 50 is mounted face-down on the first wiring layer 14 of the interposer 10 and is electrically connected to the first wiring layer 14 by a fourth bump 51. The logic chip 50 is positioned so as to overlap the IVR chip 20 in a plan view. By overlapping the logic chip 50, which consumes a lot of current, with the IVR chip 20 in the vertical direction, the distance between them is shortened, improving power efficiency. In addition, stacking the logic chip 50 and the IVR chip 20 in the vertical direction makes it possible to miniaturize electronic devices.

[0018] In Figure 1, the logic chip 50 is positioned so as to completely overlap the IVR chip 20 and the first capacitor 30 in a plan view. However, it is not limited to this, and power efficiency can be improved even if at least a portion of each overlaps with the others. The state in which at least a portion of each overlaps with the others refers to a state in a plan view where a portion of the IVR chip 20 and a portion of the first capacitor 30 overlap, and another portion of the IVR chip 20 or another portion of the first capacitor 30 overlaps with a portion of the logic chip 50. Furthermore, it is more preferable that a portion of the IVR chip 20, a portion of the first capacitor 30, and a portion of the logic chip 50 all overlap in a plan view. Furthermore, in a plan view, it is preferable that at least a portion of each of the inductor 40, the IVR chip 20, the first capacitor 30, and the logic chip 50 overlaps with each other. This state is achieved if, in addition to the overlapping of the IVR chip 20, the first capacitor 30, and the logic chip 50, a portion of the inductor 40 overlaps with any of the IVR chip 20, the first capacitor 30, or the logic chip 50 in a plan view. It is even more preferable that a portion of the inductor 40, a portion of the IVR chip 20, a portion of the first capacitor 30, and a portion of the logic chip 50 all overlap in a plan view.

[0019] The memory chip 60 can be exemplified as being HBM (High Bandwidth Memory). The memory chip 60 is mounted face-down around the logic chip 50 and is electrically connected to the first wiring layer 14 by a fifth bump 61.

[0020] The package substrate 70 is a substrate that extends the electrodes (first bumps 17) of the interposer 10 to an external area and rewires them. The package substrate 70 includes a core layer 71 made of resin, a third wiring layer 72 formed on the upper surface of the core layer 71, and a fourth wiring layer 73 formed on the lower surface of the core layer 71. External connection terminals 74 for mounting the semiconductor package 1 to an external system board or main board are formed on the fourth wiring layer 73 of the package substrate 70. The interposer 10 is electrically connected to the third wiring layer 72 of the package substrate 70 by the first bumps 17 formed on the surface of the second wiring layer.

[0021] Figure 2 is a plan view of the interposer 10. Through-hole conductors 16 are formed on the left and right sides of the IVR chip 20 and the first capacitor 30. In the example shown in Figure 2, 3 × 12 through-hole conductors 16 are formed in two sets each on the left and right sides of the IVR chip 20 and the first capacitor 30, but the arrangement and number of through-hole conductors 16 are not limited to this. The IVR chip 20 and the first capacitor 30 being surrounded by through-hole conductors 16 means that through-hole conductors 16 are formed on at least two opposing sides of the IVR chip 20 and the first capacitor 30. In the example shown in Figure 2, through-hole conductors 16 are formed on the left and right sides of the IVR chip 20 and the first capacitor 30. In other words, the IVR chip 20 and the first capacitor 30 are surrounded by through-hole conductors 16 from the left and right. When the length of the sides of the IVR chip 20 and the first capacitor 30 facing the through-hole conductors 16 is L1, and the length of the region in which the through-hole conductors 16 are formed is L2, it is preferable that L1 ≤ L2. Here, the length of the region where the through-hole conductor 16 is formed refers to the distance between the furthest apart through-hole conductors 16 in the direction along the sides of the IVR chip 20 and the first capacitor 30.

[0022] The IVR chip 20 and the first capacitor 30 are surrounded by the through-hole conductor 16 from at least two opposing directions, thereby reducing ripple noise generated during the switching operation of the IVR chip 20. Furthermore, the IVR chip 20 and the first capacitor 30 are surrounded from above and below by the first wiring layer 14 and the second wiring layer 15 of the interposer 10 (see Figure 1). This further enhances the effect of reducing ripple noise.

[0023] (Modification 1 of the first embodiment) Figure 3 shows a semiconductor package 2 of Modification 1 of the first embodiment. In the first embodiment, the IVR chip 20 was mounted face down and the first capacitor 30 was mounted face up. In contrast, Modification 1 differs in that the first capacitor 30 is mounted face down and the IVR chip 20 is mounted face up. The differences from the first embodiment will be explained below. The same reference numerals are used for parts that are the same in the first embodiment and Modification 1, and their detailed explanations will be omitted.

[0024] The first capacitor 30 is mounted face-down inside the interposer 10 and is electrically connected to the second wiring layer 15 by a third bump 31. The IVR chip 20 is mounted face-up inside the interposer 10 and is electrically connected to the first wiring layer 14 by a second bump 21. In a plan view, at least a portion of each of the IVR chip 20, the first capacitor 30, the inductor 40, and the logic chip 50 overlaps with each other. The state in which at least a portion of each overlaps with each other means that, in a plan view, a portion of the IVR chip 20 and a portion of the first capacitor 30 overlap, another portion of the IVR chip 20 or another portion of the first capacitor 30 and a portion of the logic chip 50 overlap, and furthermore, a portion of the inductor 40 overlaps with either the IVR chip 20, the first capacitor 30, or the logic chip 50. Furthermore, it is more preferable that a portion of the inductor 40, a portion of the IVR chip 20, a portion of the first capacitor 30, and a portion of the logic chip 50 overlap in a plan view.

[0025] The semiconductor package 2 of the modified example 1, like the semiconductor package 1 of the first embodiment, provides the effects of improved voltage conversion efficiency, improved power efficiency, reduced ripple noise, and miniaturization of electronic devices.

[0026] <Second Embodiment> Figure 4 shows the semiconductor package 3 of the second embodiment. Figure 5 is an enlarged view of section V in Figure 4. The differences from the first embodiment will be described below. The same reference numerals are used for parts that are the same in the first and second embodiments, and their detailed descriptions will be omitted.

[0027] The first capacitor 130 in the second embodiment is used for the same purpose as the first capacitor 30 in the first embodiment. Therefore, the first capacitor 130 has the same capacitance as the first capacitor 30. The first capacitor 130 is mounted face down inside the interposer 10 and is electrically connected to the second wiring layer 15 by a third bump 131. A through electrode 132 is formed on the first capacitor 130 and is electrically connected to the second wiring layer 15 by the third bump 131. The IVR chip 20 is mounted face down on top of the first capacitor 130. The IVR chip 20 is electrically connected to the through electrode 132 of the first capacitor 130 by a second bump 21. As a result, the IVR chip 20 is electrically connected to the second wiring layer 15 of the interposer 10 via the second bump 21, the through electrode 132, and the third bump 131.

[0028] The semiconductor package 3 of the second embodiment, like the semiconductor package 1 of the first embodiment, provides the effects of improved voltage conversion efficiency, improved power efficiency, reduced ripple noise, and miniaturization of electronic devices.

[0029] <Third Embodiment> Figure 6 shows a semiconductor package 4 of the third embodiment. The semiconductor package 4 of the third embodiment differs from the semiconductor package 1 of the first embodiment in that it includes a second capacitor 230. The differences from the first embodiment will be described below. The same reference numerals are used for parts that are the same in the first and third embodiments, and their detailed descriptions will be omitted.

[0030] The second capacitor 230 is connected to a terminal with an unfixed potential for the purpose of transferring charge and is also called a flying capacitor. For example, it is connected to a transistor and used to reduce ripple noise. The capacitance of the second capacitor 230 is smaller than that of the first capacitor 30.

[0031] The second capacitor 230 is located inside the interposer 10, adjacent to the first capacitor 30. The second capacitor 230 is mounted face-down inside the interposer 10 and is electrically connected to the second wiring layer 15 by a sixth bump 231.

[0032] The semiconductor package 4 of the third embodiment provides the same effects as the semiconductor package 1 of the first embodiment, and furthermore, by including a second capacitor 230, noise can be reduced.

[0033] (Modification 1 of the third embodiment) Figure 7 shows a semiconductor package 5 of Modification 1 of the third embodiment. In the semiconductor package 4 of the third embodiment, the second capacitor 230 was mounted in a face-down state. In contrast, in the semiconductor package 5 of the third embodiment, the second capacitor 230 is mounted in a face-up state. The differences from the third embodiment will be explained below. The same reference numerals are used for parts that are the same in the third embodiment and Modification 1, and their detailed explanations will be omitted.

[0034] The second capacitor 230 is located inside the interposer 10, adjacent to the first capacitor 30. The second capacitor 230 is mounted face up inside the interposer 10 and is electrically connected to the first wiring layer 14 by a sixth bump 231.

[0035] The semiconductor package 5 of the third embodiment modification 1 provides the same effects as the semiconductor package 4 of the third embodiment.

[0036] Although embodiments have been described above, the technical scope of the present invention is not limited to the embodiments described above. It is clear from the claims that combinations of two or more of the above embodiments, as well as various modifications or improvements to the above embodiments, are also included in the technical scope of the present invention. [Explanation of Symbols]

[0037] 1,2,3,4,5…Semiconductor package, 10…Interposer, 11…Core layer, 14…First wiring layer, 15…Second wiring layer, 16…Through-hole conductor, 17…First bump, 20…IVR chip, 21…Second bump, 30,130…First capacitor, 31,131…Third bump, 40…Inductor, 50…Logic chip, 51…Fourth bump, 60…Memory lip, 61…Fifth bump, 70…Package substrate, 71…Core layer, 72…Third wiring layer, 73…Fourth wiring layer, 74…External connection terminal, 80…Adhesive, 90…Sealing resin, 132…Through-hole electrode, 230…Second capacitor, 231…Sixth bump

Claims

1. A semiconductor device comprising an interposer incorporating an IVR (Integrated Voltage Regulator) chip and a first capacitor, The interposer comprises a core layer having a first surface and a second surface on the opposite side, A first wiring layer formed on the first surface side of the core layer, A second wiring layer formed on the second surface side of the core layer, The device includes a through-hole conductor that is electrically connected to the first wiring layer and the second wiring layer and is formed to penetrate from the first surface to the second surface, In a plan view, the IVR chip and the first capacitor are surrounded by the through-hole conductor, A semiconductor package characterized in that at least a portion of the IVR chip and the first capacitor overlap.

2. The interposer further comprises a logic chip mounted face-down on the first wiring layer formed on the first surface side of the core layer of the interposer, The semiconductor package according to claim 1, characterized in that, in a plan view, at least a portion of each of the logic chip, the IVR chip embedded in the interposer, and the first capacitor overlap each other.

3. The semiconductor package according to claim 2, characterized in that the interposer is mounted on a package substrate via electrodes formed on the surface of the second wiring layer formed on the second surface side of the core layer.

4. The aforementioned package substrate incorporates an inductor, The semiconductor package according to claim 3, further characterized in that, in a plan view, at least a portion of each of the inductor built into the package substrate, the IVR chip built into the interposer, the first capacitor, and the logic chip mounted face down on the interposer overlap each other.

5. The IVR chip embedded in the interposer is mounted face-down on the second wiring layer formed on the second surface side of the core layer. Furthermore, the semiconductor package according to claim 4, characterized in that it is electrically connected.

6. The first capacitor, which is built into the interposer, is mounted face-up on the first wiring layer formed on the first surface side of the core layer. Furthermore, the semiconductor package according to claim 5, characterized in that it is electrically connected.

7. The semiconductor package according to claim 6, characterized in that the IVR chip and the first capacitor built into the interposer are in a stacked structure in contact with each other.

8. The semiconductor package according to claim 7, characterized in that the laminate of the IVR chip and the first capacitor is mounted face-up on the IVR chip, which is mounted face-down on the second wiring layer formed on the second surface side of the core layer, using an adhesive.

9. The first capacitor, which is built into the interposer, is mounted face-down on the second wiring layer formed on the second surface side of the core layer. Furthermore, the semiconductor package according to claim 4, characterized in that it is electrically connected.

10. The semiconductor package according to claim 9, characterized in that the first capacitor, which is mounted face-down on the second wiring layer formed on the second surface side of the core layer, includes through electrodes.

11. The IVR chip is mounted face-down on the first capacitor, which is mounted face-down on the second wiring layer formed on the second surface side of the core layer. The semiconductor package according to claim 10, further characterized in that the IVR chip is electrically connected to the second wiring layer by the through-electrode.

12. The semiconductor package according to any one of claims 8 to 11, characterized in that the interposer incorporates a second capacitor having a smaller capacitance than the first capacitor, adjacent to the stack of the IVR chip and the first capacitor.

13. The second capacitor is mounted face-down on the second wiring layer formed on the second surface side of the core layer. Furthermore, the semiconductor package according to claim 12, characterized in that it is electrically connected.

14. The second capacitor is mounted face-up on the first surface side of the core layer. The semiconductor package according to claim 12, further characterized in that it is electrically connected to the first wiring layer formed on the first surface side of the core layer.

Images