Photoelectric conversion device and photoelectric conversion system

Abstract

In a photoelectric converter composed of multiple circuit boards, the performance of peripheral circuits is improved, resulting in improved signal quality and cost reduction. [Solution] The photoelectric conversion device has a photoelectric conversion element and a pixel unit that outputs a signal corresponding to the light incident on the photoelectric conversion element, and a peripheral circuit that drives the pixel unit or processes the signal output from the pixel unit. The peripheral circuit has a circuit that includes a complementary connection between a first-conductivity type transistor provided on a first substrate and a second-conductivity type transistor provided on a second substrate.

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system.

Background Art

[0002] Techniques for improving the performance and functions of a photoelectric conversion device by laminating a plurality of substrates have been proposed. For example, in Patent Document 1, a photoelectric conversion element that outputs electrons as signal charges and an N-type transistor that transfers these electrons are arranged on a first substrate, and a P-type transistor that amplifies the signal charges is arranged on a second substrate, thereby achieving both suppression of 1 / f noise and high-speed driving. Further, in Patent Document 2, noise caused by leakage current is reduced by appropriately controlling the relationship between the voltage of the back gate of the amplification transistor and the voltage of the non-back gate of the sampling transistor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the techniques described in Patent Document 1 and Patent Document 2 are mainly aimed at reducing noise superimposed on pixel signals, and no particular consideration has been given to so-called peripheral circuits such as control circuits for controlling pixels and signal processing circuits for processing pixel signals.

[0005] An object of the present invention is to provide a technique for improving the performance of peripheral circuits, improving the signal quality output by a photoelectric conversion device, and reducing costs in a photoelectric conversion device composed of a plurality of substrates.

Means for Solving the Problems

[0006] According to one disclosure of this specification, a photoelectric conversion device is provided, comprising a pixel unit having a photoelectric conversion element and outputting a signal corresponding to incident light to the photoelectric conversion element, and a peripheral circuit for driving the pixel unit or processing the signal output from the pixel unit, wherein the peripheral circuit includes a circuit that includes a complementary connection between a first-conductivity type transistor provided on a first substrate and a second-conductivity type transistor provided on a second substrate. [Effects of the Invention]

[0007] According to the present invention, in a photoelectric conversion device composed of multiple substrates, the performance of peripheral circuits can be improved, resulting in improved signal quality and cost reduction. [Brief explanation of the drawing]

[0008] [Figure 1] This block diagram shows the schematic configuration of a photoelectric conversion device according to the first embodiment. [Figure 2] This is a schematic diagram showing an example of the configuration of a photoelectric conversion device according to the first embodiment. [Figure 3] This diagram illustrates the assignment of each functional block to each circuit board in the photoelectric conversion device according to the first embodiment. [Figure 4] This is a circuit diagram showing an example of the configuration of pixels and pixel memory in a photoelectric conversion device according to the first embodiment. [Figure 5] This is a circuit diagram showing an example of the configuration of a pixel vertical scanning circuit in a photoelectric conversion device according to the first embodiment. [Figure 6] This is a schematic diagram showing the scanning image in the row scanning direction in a photoelectric conversion device according to the first embodiment. [Figure 7] This figure illustrates the block-unit transfer operation of pixel signals from the pixel unit to the memory unit in a photoelectric conversion device according to the first embodiment. [Figure 8] This is a timing diagram (part 1) showing the driving method of the photoelectric converter according to the first embodiment. [Figure 9]Timing chart (Part 2) showing the drive method of the photoelectric conversion device according to the first embodiment. [Figure 10] Timing chart (Part 3) showing the drive method of the photoelectric conversion device according to the first embodiment. [Figure 11] It is a diagram for explaining the allocation of each functional block of the photoelectric conversion device according to the second embodiment to each substrate. [Figure 12] It is a circuit diagram showing a configuration example of a pixel and a pixel memory in the photoelectric conversion device according to the second embodiment. [Figure 13] It is a circuit diagram showing a configuration example of a signal processing circuit in the photoelectric conversion device according to the second embodiment. [Figure 14] It is a circuit diagram (Part 1) showing a configuration example of a logic circuit in the photoelectric conversion device according to the second embodiment. [Figure 15] It is a circuit diagram (Part 2) showing a configuration example of a logic circuit in the photoelectric conversion device according to the second embodiment. [Figure 16] It is a circuit diagram showing a configuration example of a signal processing circuit in the photoelectric conversion device according to the third embodiment. [Figure 17] It is a diagram for explaining the allocation of each functional block of the photoelectric conversion device according to the fourth embodiment to each substrate. [Figure 18] It is a block diagram showing a schematic configuration of a photoelectric conversion system according to the fifth embodiment. [Figure 19] It is a diagram showing a configuration example of a photoelectric conversion system and a moving body according to the sixth embodiment. [Figure 20] It is a block diagram showing a schematic configuration of a device according to the seventh embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the embodiments shown below are for embodying the technical idea of the present invention and do not limit the present invention. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential for the invention, and the plurality of features may be arbitrarily combined.

[0010] Also, in each of the embodiments described below, as an example of a photoelectric conversion device, a device for imaging applications will be mainly described. However, each embodiment is not limited to this device for imaging applications, and is also applicable to other examples included as a photoelectric conversion device. For example, there are a distance measuring device (a device for distance measurement using focus detection or TOF (Time Of Flight)), a photometric device (a device for measuring the amount of incident light), and the like.

[0011] Also, the conductivity type of the transistor described in the embodiments below is an example, and is not limited to only the conductivity types described in the embodiments. With respect to the conductivity types described in the embodiments, the conductivity type can be appropriately changed, and along with this change, the potentials of the gate, source, and drain of the transistor are appropriately changed. For example, for a transistor that operates as a switch, the low level and high level of the potential supplied to the gate may be reversed with respect to the description in the embodiments along with the change in the conductivity type.

[0012] Also, in the following embodiments, the connection between the elements of the circuit may be described. In this case, even when another element is interposed between the elements of interest, unless otherwise specified, the elements of interest are treated as being connected. For example, assume that element A is connected to one node of a capacitive element C having a plurality of nodes, and element B is connected to the other node. Even in such a case, unless otherwise specified, element A and element B are treated as being connected.

[0013] [First Embodiment] The schematic configuration of the photoelectric conversion device according to the first embodiment of the present invention will be described with reference to FIG. 1. FIG. 1 is a block diagram showing the schematic configuration of the photoelectric conversion device according to the present embodiment.

[0014] The photoelectric converter 100, as shown in Figure 1 for example, includes a pixel unit 10, a pixel vertical scanning circuit 20, a memory unit 30, a memory vertical scanning circuit 40, a signal processing unit 50, a bias generation circuit 60, a reference signal output circuit 70, a column control circuit 80, and a control circuit 90. The bias generation circuit 60 may include bias generation circuits 62, 64, and 66, which will be described later. The control circuit 90 may include a pixel control circuit 92, a memory control circuit 94, and a signal processing control circuit 96, which will be described later.

[0015] The pixel section 10 is provided with a plurality of pixels 12 arranged in a matrix across multiple rows and columns. Each of the plurality of pixels 12 includes a photoelectric conversion unit and outputs a pixel signal corresponding to the amount of incident light. Each pixel 12 may include one microlens and a color filter that transmits light in a predetermined wavelength range. In addition to the effective pixels that output a pixel signal corresponding to the amount of incident light, the pixel section 10 may also include optical black pixels in which the photoelectric conversion unit is shielded from light, and dummy pixels that do not output a signal. The specific circuit configuration of the pixels 12 will be described later.

[0016] Each row of the pixel section 10 has a control line 14 extending in a first direction (horizontal direction in Figure 1). Each control line 14 is connected to a pixel 12 arranged in the first direction, forming a common signal line for these pixels 12. The first direction in which the control lines 14 extend is sometimes called the row direction or horizontal direction. Each control line 14 may contain multiple signal lines. The control lines 14 are connected to the pixel vertical scanning circuit 20.

[0017] The memory unit 30 is provided with a plurality of pixel memories 32 arranged in a matrix across multiple rows and columns. Each of the plurality of pixel memories 32 contains one or more memories and holds the pixel signals output from the pixels 12. The plurality of pixel memories 32 arranged in the memory unit 30 may be arranged to correspond one-to-one with the plurality of pixels 12 arranged in the pixel unit 10. For example, the number of rows and columns of the pixel array constituting the pixel unit 10 may be the same as the number of rows and columns of the pixel memory array constituting the memory unit 30, and each of the plurality of pixel memories 32 may be configured to hold the pixel signals of pixels 12 with the same row number and column number. The specific circuit configuration of the pixel memories 32 will be described later.

[0018] Each row of the memory section 30 has a control line 34 extending in a first direction. Each control line 34 is connected to a pixel memory 32 arranged in the first direction, and these pixel memories 32 form a common signal line. Each control line 34 may contain multiple signal lines. The control lines 34 are connected to the memory vertical scanning circuit 40.

[0019] The pixel unit 10 and the memory unit 30 are connected via signal output lines 16 provided for each pixel 12, so as to connect pixels 12 and pixel memories 32 with the same row and column numbers. In Figure 1, for the sake of simplicity, each column is shown to have a common signal output line 16, but in reality, each pixel 12 is connected to a corresponding pixel memory 32 via a single signal output line 16. However, the signal output lines 16 may be arranged in each column of the pixel unit 10 and the memory unit 30, as shown in Figure 1, to form a common signal line for the pixels 12 and pixel memories 32 of the corresponding column. In this case, the signals of the pixels 12 are sequentially read to the signal output line 16 row by row, and the signals output to the signal output line 16 are sequentially written to the pixel memory 32 row by row, thereby enabling the transfer of signals from the pixel unit 10 to the memory unit 30.

[0020] Furthermore, each row of the memory section 30 has a signal output line 36 extending in the second direction. Each of the signal output lines 36 is connected to a pixel memory 32 arranged in the second direction, forming a common signal line for these pixel memories 32. The signal output lines 36 are connected to the signal processing unit 50.

[0021] The pixel vertical scanning circuit 20 is a pixel driving circuit that drives the pixels 12. The pixel vertical scanning circuit 20 has the function of generating control signals to drive the pixels 12 in response to control signals from the control circuit 90 and outputting the generated control signals to the pixel unit 10. The pixel vertical scanning circuit 20 may be configured using logic circuits such as a shift register and an address decoder. The pixel vertical scanning circuit 20 can sequentially output control signals to the control lines 14 of each row and perform the operation of sequentially driving the pixels 12 of the pixel unit 10 row by row, so-called vertical scanning. The pixel signals read from the pixels 12 row by row are input to the memory unit 30 via the signal output line 16. Alternatively, the transfer of pixel signals from the pixel unit 10 to the memory unit 30 may be performed in batches or in blocks. When transferring pixel signals in batches or in blocks, control signals should be output in batches or in blocks to the control lines 14 of each row.

[0022] The memory vertical scanning circuit 40 is a memory drive circuit that drives the pixel memory 32. The memory vertical scanning circuit 40 has the function of generating control signals to drive the pixel memory 32 in response to control signals from the control circuit 90 and outputting the generated control signals to the memory unit 30. The memory vertical scanning circuit 40 may be configured using logic circuits such as shift registers and address decoders. The memory vertical scanning circuit 40 sequentially outputs control signals to the control lines 34 of each row and performs an operation to sequentially drive the pixel memory 32 of the memory unit 30 row by row, so-called vertical scanning. The pixel signals read from the pixel memory 32 row by row are input to the signal processing unit 50 via the signal output line 16.

[0023] The signal processing unit 50 has a plurality of signal processing circuits 52 corresponding to each column of the memory unit 30. Each signal processing circuit 52 for each column is connected to the signal output line 36 of the corresponding column. Each of the plurality of signal processing circuits 52 performs predetermined signal processing on the pixel signal read from the pixel memory 32 of the corresponding column. Examples of processing performed by the signal processing circuit 52 include amplification processing and analog-to-digital conversion (AD conversion). To realize these functions, the signal processing circuit 52 may include a comparator circuit that compares the pixel signal read from the pixel memory 32 with a reference signal whose voltage changes over time, a drive circuit such as a current source, and an arithmetic processing circuit that performs data calculation processing. Note that it is not necessary to provide an arithmetic processing circuit for each column; the signals from each column may be sequentially input to a single arithmetic processing circuit.

[0024] The signal processing unit 50 may further include an output circuit (not shown) for outputting the pixel signal after arithmetic processing to the outside of the photoelectric converter 100. The external interface circuit provided by the output circuit is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit can be applied as an external interface circuit. Examples of SerDes transmission circuits include an LVDS (Low Voltage Differential Signaling) circuit and an SLVS (Scalable Low Voltage Signaling) circuit.

[0025] The bias generation circuit 60 has the function of generating a predetermined bias voltage that is supplied to the pixel unit 10, the memory unit 30, and the signal processing unit 50. The bias voltage generated by the bias generation circuit 60 will be described later.

[0026] The reference signal output circuit 70 is connected to the signal processing circuits 52 of each row of the signal processing unit 50. The reference signal output circuit 70 has the function of outputting a reference signal to the signal processing unit 50 for use in AD conversion in accordance with a control signal from the control circuit 90. The reference signal used in AD conversion may be a signal having a predetermined amplitude corresponding to the range of the pixel signal, and whose signal level changes over time. The reference signal is not particularly limited, but for example, a ramp signal whose signal level monotonically increases or decreases over time can be applied. The change in signal level does not necessarily have to be continuous and may be stepwise. Also, the change in signal level does not necessarily have to be linear with respect to time and may be curvilinear with respect to time (e.g., sine wave or cosine wave). The reference signal output circuit 70 may be configured to generate and output the reference signal, or it may be configured to buffer and output a reference signal generated outside the photoelectric converter.

[0027] The column control circuit 80 has the function of generating a control signal for reading pixel signals from the signal processing circuit 52 of the signal processing unit 50 in response to a control signal from the control circuit 90, and outputting the generated control signal to the signal processing circuit 52. The column control circuit 80 sequentially scans the signal processing circuit 52 of the signal processing unit 50 and sequentially outputs the pixel signals held in each to the outside of the photoelectric converter. The column control circuit 80 may be constructed using logic circuits such as shift registers and address decoders. The column control circuit 80 may use logic circuits such as shift registers and address decoders.

[0028] The control circuit 90 has the function of generating control signals to control the operation of each of the above-mentioned functional blocks and outputting the generated control signals to these functional blocks. At least a portion of the control signals for controlling the operation of these functional blocks may be configured to be supplied from outside the photoelectric converter 100.

[0029] In this specification, functional blocks excluding the pixel unit 10 and the memory unit 30 are sometimes collectively referred to as peripheral circuits. Peripheral circuits are typically functional blocks that drive the pixels 12 and process signals read from the pixels 12.

[0030] The power supply voltages for at least some of the transistors constituting the column control circuit 80 and the control circuit 90 are relatively low, such as 1.8V. In contrast, the power supply voltages for the transistors constituting the pixels 12, pixel memory 32, signal processing circuit 52, pixel vertical scanning circuit 20, memory vertical scanning circuit 40, bias generation circuits 64, 66, and reference signal output circuit 70 are relatively high, such as 3.3V. Here, the breakdown voltage of a transistor is mainly determined by the thickness of the gate insulating film, and the gate insulating film thickness of a transistor driven at 3.3V is thicker than that of a transistor driven at 1.8V.

[0031] The photoelectric converter 100 according to this embodiment can be configured as a stacked type photoelectric converter in which a plurality of substrates are stacked. Figure 2 is a schematic diagram showing the general configuration of the photoelectric converter according to this embodiment. The photoelectric converter 100 according to this embodiment can be configured, for example, as shown in Figure 2, by stacking three substrates, a first substrate 110, a second substrate 120, and a third substrate 130, and electrically connecting them to each other.

[0032] In the configuration example shown in Figure 2, the first substrate 110 can, for example, include a pixel unit 10, a pixel vertical scanning circuit 20, a memory vertical scanning circuit 40, and at least a portion of the control circuit 90. The second substrate 120 can, for example, include a memory unit 30, a pixel vertical scanning circuit 20, a memory vertical scanning circuit 40, a bias generation circuit 60, a column control circuit 80, and at least a portion of the control circuit 90. The third substrate 130 can, for example, include a signal processing unit 50, a reference signal output circuit 70, a bias generation circuit 60, and all or part of the column control circuit 80 and the control circuit 90.

[0033] Each of the first substrate 110, the second substrate 120, and the third substrate 130 may be provided with a pixel section 10, a memory section 30, and a signal processing section 50 so as to overlap in a plan view. In this specification, a plan view refers to viewing from a direction perpendicular to the light incident surface of the first substrate 110. If the light incident surface of the semiconductor layer is rough when viewed microscopically, the plan view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0034] The pixel vertical scanning circuit 20, the memory vertical scanning circuit 40, the bias generation circuit 60, the reference signal output circuit 70, the column control circuit 80, and the control circuit 90 can be arranged around the pixel section 10, the memory section 30, or the signal processing section 50 of each substrate in a plan view. These functional blocks may be provided on a single substrate or divided and provided on multiple substrates. Note that the placement of each functional block on each substrate is not limited to the example shown in Figure 2.

[0035] By configuring a stacked photoelectric converter 100, the integration density of elements can be increased, leading to improved functionality. In particular, by arranging the pixel section 10, the memory section 30, and the signal processing section 50 on separate substrates, the photoelectric converters can be arranged at high density without sacrificing the light-receiving area of ​​the photoelectric converters in each pixel 12, thereby improving photon detection efficiency. Furthermore, by arranging the signal processing section 50 on a separate substrate, the circuit area of ​​the signal processing section 50 can be increased, enabling the photoelectric converter to achieve higher functionality.

[0036] Although Figure 2 shows a configuration in which three substrates, the first substrate 110, the second substrate 120, and the third substrate 130, are stacked, a configuration with two or more substrates stacked may also be used. Furthermore, while Figure 2 assumes that the first substrate 110, the second substrate 120, and the third substrate 130 are diced chips, the first substrate 110, the second substrate 120, and the third substrate 130 are not limited to chips. For example, each of the first substrate 110, the second substrate 120, and the third substrate 130 may be wafers. In addition, the first substrate 110, the second substrate 120, and the third substrate 130 may be stacked in wafer form and then diced, or they may be individually formed into chips and then stacked and bonded.

[0037] Next, the assignment of each functional block to each circuit board in the photoelectric conversion device according to this embodiment will be explained using Figure 3. Figure 3 is a diagram illustrating the assignment of each functional block to each circuit board in the photoelectric conversion device according to this embodiment.

[0038] As described above, the photoelectric conversion device according to this embodiment is constructed by stacking three substrates: a first substrate 110, a second substrate 120, and a third substrate 130. The first substrate 110 contains the pixel section 10, a part of the pixel vertical scanning circuit 20, a part of the memory vertical scanning circuit 40, and a pixel control circuit 92, which is part of the control circuit 90, among the functional blocks described above. The second substrate 120 contains the memory section 30, another part of the pixel vertical scanning circuit 20, another part of the memory vertical scanning circuit 40, a bias generation circuit 64, and a memory control circuit 94, which is part of the control circuit 90, among the functional blocks described above. The third substrate 130 contains the signal processing section 50, a bias generation circuit 66, a reference signal output circuit 70, a column control circuit 80, and a signal processing control circuit 96, which is part of the control circuit 90, among the functional blocks described above.

[0039] The pixel control circuit 92 generates a control signal to drive the pixel vertical scanning circuit 20 in response to a signal input from outside the photoelectric converter. The pixel vertical scanning circuit 20 controls multiple pixels 12 of the pixel section 10 row by row in response to the control signal from the pixel control circuit 92. Each pixel 12 outputs a pixel signal, which is an analog signal corresponding to the amount of incident light, to the second substrate 120 via the signal output line 16 in response to the control signal from the pixel vertical scanning circuit 20. The pixel signals output from the pixels 12 are input to the corresponding pixel memory 32 among the multiple pixel memories 32 that constitute the memory section 30 of the second substrate 120.

[0040] The memory control circuit 94 generates control signals to drive the memory vertical scanning circuit 40 and the bias generation circuit 64 in response to signals input from outside the photoelectric converter. The memory vertical scanning circuit 40 controls the multiple pixel memories 32 of the memory unit 30 row by row in response to the control signals from the memory control circuit 94. Each pixel memory 32 holds the pixel signal input via the signal output line 16 in response to the control signal from the memory vertical scanning circuit 40, or outputs the pixel signal it holds to the third substrate 130 via the signal output line 36. The pixel signals output from the pixel memories 32 are input to the corresponding column signal processing circuits 52 among the multiple signal processing circuits 52 that constitute the signal processing unit 50 of the third substrate 130.

[0041] The signal processing control circuit 96 generates control signals to drive the column control circuit 80, the bias generation circuit 66, and the reference signal output circuit 70 in response to signals input from outside the photoelectric converter. The column control circuit 80, the bias generation circuit 66, and the reference signal output circuit 70 control the signal processing circuit 52 of each column in response to the control signals from the signal processing control circuit 96 and perform predetermined arithmetic processing on the pixel signals read from the memory unit 30. The pixel signals after arithmetic processing are output to the outside of the photoelectric converter via an output circuit (not shown).

[0042] Here, the pixel vertical scanning circuit 20 and the memory vertical scanning circuit 40 are provided across the first substrate 110 and the second substrate 120, as shown in Figure 3. More specifically, among the circuit elements constituting the pixel vertical scanning circuit 20 and the memory vertical scanning circuit 40, the N-type transistors are located on the first substrate 110, and the P-type transistors are located on the second substrate 120.

[0043] Furthermore, if the photoelectric conversion device is composed of two boards, for example, a first board 110 and a third board 130, the functional blocks arranged on the second board 120 can be distributed between the first board 110 and the third board 130. For example, the memory section 30, bias generation circuit 64, and memory control circuit 94 can be placed on the first board 110, and a portion of the pixel vertical scanning circuit 20 and memory vertical scanning circuit 40 can be placed on the third board 130. In this case, among the circuit elements constituting the pixel vertical scanning circuit 20 and memory vertical scanning circuit 40, the N-type transistors can be placed on the first board 110, and the P-type transistors can be placed on the third board 130.

[0044] Next, the circuit configuration of the pixel 12 and the pixel memory 32 will be explained in more detail using Figure 4. Figure 4 is an equivalent circuit diagram showing an example of the configuration of the pixel 12 and the pixel memory 32 in the photoelectric conversion device according to this embodiment.

[0045] Each of the pixels 12 constituting the pixel section 10 may be composed of, for example, a photoelectric conversion element PDA, PDB, a transfer transistor M1A, M1B, a reset transistor M2, an amplification transistor M3, and a selection transistor M4, as shown in Figure 4.

[0046] The photoelectric conversion elements PDA and PDB are, for example, photodiodes. The anode of the photoelectric conversion element PDA is connected to the ground voltage node (voltage SGND), and the cathode is connected to the source of the transfer transistor M1A. The anode of the photoelectric conversion element PDA is connected to the ground voltage node (voltage SGND), and the cathode is connected to the source of the transfer transistor M1B. The drains of the transfer transistors M1A and M1B are connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. Node FD, to which the drains of the transfer transistors M1A and M1B, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected, is a so-called floating diffusion section. The floating diffusion section contains a capacitive component (floating diffusion capacitance) and functions as a charge retainer. The floating diffusion capacitance may include the gate capacitance of the transistors, the pn junction capacitance, the wiring capacitance, etc. The drains of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a node to which the power supply voltage (voltage SVDD) is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the signal output line 16. The signal output line 16 is connected to node VREADP, which is an input node of the pixel memory 32, via connection CN11, which is one of the electrical connections between the first substrate 110 and the second substrate 120.

[0047] In the configuration of pixel 12 shown in Figure 2, the control line 14 for each row includes four signal lines connected to the gates of the transfer transistor M1A, M1B, M2, and M4. The gate of transfer transistor M1A is supplied with control signal TXA from the pixel vertical scanning circuit 20. The gate of transfer transistor M1B is supplied with control signal TXB from the pixel vertical scanning circuit 20. The gate of reset transistor M2 is supplied with control signal RES from the pixel vertical scanning circuit 20. The gate of selection transistor M4 is supplied with control signal SEL from the pixel vertical scanning circuit 20. If each transistor is an N-type transistor, a high-level control signal supplied from the pixel vertical scanning circuit 20 turns the corresponding transistor ON. Conversely, a low-level control signal supplied from the pixel vertical scanning circuit 20 turns the corresponding transistor OFF.

[0048] In this embodiment, the explanation assumes that electrons are used as the signal charge among the electron-hole pairs generated by the photoelectric conversion elements PDA and PDB upon light incidence. When electrons are used as the signal charge, each transistor constituting the pixel 12 may be composed of an N-type MOS transistor. However, the signal charge is not limited to electrons; holes may also be used as the signal charge. When holes are used as the signal charge, the conductivity type of each transistor will be the opposite conductivity type to that described in this embodiment. Note that the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function being considered. Some or all of the source and drain names used in this embodiment may also be referred to by their reverse names.

[0049] The photoelectric conversion elements PDA and PDB convert incident light into an amount of charge corresponding to the amount of light (photoelectric conversion) and store the resulting charge. When the transfer transistor M1A is turned on, it transfers the charge held by the photoelectric conversion element PDA to node FD. When the transfer transistor M1B is turned on, it transfers the charge held by the photoelectric conversion element PDB to node FD. The charge transferred from the photoelectric conversion elements PDA and PDB is held in the capacitance (stray diffusion capacitance) of node FD. As a result, node FD becomes potential corresponding to the amount of charge transferred from the photoelectric conversion elements PDA and PDB through charge-voltage conversion by the stray diffusion capacitance.

[0050] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the signal output line 16. The amplification transistor M3 is configured such that a voltage SVDD is supplied to its drain and a bias current is supplied to its source via the selection transistor M4, forming an amplification section (source follower circuit) with its gate as the input node. As a result, the amplification transistor M3 outputs a signal based on the voltage of node FD to the signal output line 16 via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 are output sections that output a pixel signal corresponding to the amount of charge held at node FD.

[0051] The reset transistor M2 controls the supply of a voltage (voltage SVDD) to the FD node for resetting the node FD, which acts as a charge holder. When the reset transistor M2 is turned on, it resets the node FD to a voltage corresponding to voltage SVDD. At the same time, by turning on the transfer transistor M1A, it is also possible to reset the photoelectric conversion element PDA to a voltage corresponding to voltage SVDD. Furthermore, by turning on the transfer transistor M1B at the same time, it is also possible to reset the photoelectric conversion element PDB to a voltage corresponding to voltage SVDD.

[0052] A pixel 12 equipped with multiple photoelectric conversion elements, as in this embodiment, can output multiple types of signals. Such a pixel 12 can output a first signal corresponding to the amount of charge generated by a first number of photoelectric conversion elements among the multiple photoelectric conversion elements, and a second signal corresponding to the amount of charge generated by a second number of photoelectric conversion elements greater than the first number among the multiple photoelectric conversion elements. For example, if the pixel 12 includes two photoelectric conversion elements PDA and PDB, the first signal is the SA signal described later, and the second signal is the SAB signal described later.

[0053] Each of the pixel memories 32 constituting the memory section 30 includes, for example, a current source switch transistor M11, a cascode transistor M12, a pixel current source transistor M13, and sampling transistors M14, M15, and M16, as shown in Figure 4. Furthermore, each of the pixel memories 32 also includes hold capacitors CN, CA, and CAB, a reset transistor M17, an amplification transistor M18, and a selection transistor M19.

[0054] Node VREADP is connected to the drain of the current source switch transistor M11, the sources of the sampling transistors M14, M15, and M16, the source of the reset transistor M17, and the gate of the amplification transistor M18. The source of the current source switch transistor is connected to the drain of the cascode transistor M12. The source of the cascode transistor M12 is connected to the drain of the pixel current source transistor M13. The drain of the sampling transistor M14 is connected to one terminal of the hold capacitance CN. The drain of the sampling transistor M15 is connected to one terminal of the hold capacitance CA. The drain of the sampling transistor M16 is connected to one terminal of the hold capacitance CAB. The source of the pixel current source transistor M13 and the other terminals of the hold capacitances CN, CA, and CAB are connected to the ground voltage node (voltage MGND). The drain of the reset transistor M17 and the drain of the amplification transistor M18 are connected to the power supply voltage node (voltage MVDD). The source of the amplification transistor M18 is connected to the drain of the selection transistor M19. The source of the selection transistor M19 is connected to the signal output line 36. The signal output line 36 is connected to node VLOUT of the signal processing circuit 52 via connection CN21, which is one of the electrical connections between the second board 120 and the third board 130.

[0055] In the configuration of the pixel memory 32 shown in Figure 2, each row of control lines 34 includes five signal lines connected to the gates of sampling transistors M14, M15, and M16, the gate of reset transistor M17, and the gate of selection transistor M19. The gate of sampling transistor M14 is supplied with the control signal SWN from the memory vertical scanning circuit 40. The gate of sampling transistor M15 is supplied with the control signal SWA from the memory vertical scanning circuit 40. The gate of sampling transistor M16 is supplied with the control signal SWAB from the memory vertical scanning circuit 40. The gate of reset transistor M17 is supplied with the control signal RESC from the memory vertical scanning circuit 40. The gate of selection transistor M19 is supplied with the control signal SELM from the memory vertical scanning circuit 40. If each transistor is an N-type transistor, a high-level control signal supplied from the memory vertical scanning circuit 40 turns the corresponding transistor ON. Conversely, a low-level control signal supplied from the memory vertical scanning circuit 40 turns the corresponding transistor OFF.

[0056] The current source switch transistor M11, the cascode transistor M12, and the pixel current source transistor M13 constitute a current source for supplying bias current to the amplification transistor M3 of the pixel 12. The gate of the current source switch transistor M11 is supplied with the control signal BLK from the memory vertical scanning circuit 40. The gate of the cascode transistor M12 is supplied with the voltage VGATE1 from the bias generation circuit 64. The gate of the pixel current source transistor M13 is supplied with the voltage VBIAS1 from the bias generation circuit 64.

[0057] Each of the signal processing circuits 52 constituting the signal processing unit 50 includes, for example, a current source switch transistor M21, a cascode transistor M22, and a pixel memory current source transistor M23, as shown in Figure 4. The signal processing circuit 52 may also include other circuits corresponding to predetermined arithmetic processing performed in the signal processing unit 50, such as an AD conversion circuit, but only the components related to the operation of the pixel memory 32 will be described here.

[0058] The drain of current source switch transistor M21 is connected to node VLOUT. The source of current source switch transistor M21 is connected to the drain of cascode transistor M22. The source of cascode transistor M22 is connected to the drain of pixel memory current source transistor M23. The source of pixel memory current source transistor M23 is connected to the ground voltage node (voltage AGND).

[0059] The current source switch transistor M21, the cascode transistor M22, and the pixel memory current source transistor M23 constitute a current source for supplying bias current to the amplification transistor M18 of the pixel memory 32. The gate of the current source switch transistor M21 is supplied with the control signal BLKM from the column control circuit 80. The gate of the cascode transistor M22 is supplied with the voltage VGATE2 from the bias generation circuit 66. The gate of the pixel memory current source transistor M23 is supplied with the voltage VBIAS2 from the bias generation circuit 66.

[0060] Node VLOUT is connected to the selection transistor M19 of multiple pixel memories 32 arranged in the same column.

[0061] When reset transistor M17 is turned on, it sets node VREADP to a voltage corresponding to voltage MVDD. When sampling transistor M14 is turned on, it writes the signal read from pixel 12 to node VREADP to hold capacitor CN, or reads the signal held by hold capacitor CN to node VREADP. When sampling transistor M15 is turned on, it writes the signal read from pixel 12 to node VREADP to hold capacitor CA, or reads the signal held by hold capacitor CA to node VREADP. When sampling transistor M16 is turned on, it writes the signal read from pixel 12 to node VREADP to hold capacitor CAB, or reads the signal held by hold capacitor CAB to node VREADP.

[0062] When the selector transistor M19 is turned on, it connects the amplifier transistor M18 to the signal output line 36. The amplifier transistor M18 is configured such that a voltage MVDD is supplied to its drain and a bias current is supplied to its source via the selector transistor M19, forming an amplifier section (source follower circuit) with its gate as the input node. As a result, the amplifier transistor M18 outputs a signal based on the voltage of node VREADP to the signal output line 36 via the selector transistor M19. In this sense, the amplifier transistor M18 and the selector transistor M19 are output sections that output a signal corresponding to the voltage of node VREADP.

[0063] In the configuration example in Figure 4, the voltage SGND of the ground voltage node of the first substrate 110, the voltage MGND of the ground voltage node of the second substrate 120, and the voltage AGND of the ground voltage node of the third substrate 130 were described as separate power supply voltages. This is because separating the power supplies that generate the voltages SGND, MGND, and AGND from each other reduces the impact of power supply fluctuations on other circuits. However, the power supplies that generate the voltages SGND, MGND, and AGND do not necessarily have to be separate and may be common. Also, the voltages SGND, MGND, and AGND may be the same or different. Furthermore, in the configuration example in Figure 4, the case in which one pixel 12 has two photoelectric conversion elements PDA and PDB is shown, but the number of photoelectric conversion elements in one pixel 12 may be one or three or more. Also, the cascode transistors M12 and M22 are transistors that suppress current changes due to fluctuations in the drain voltage of the pixel current source transistor M13 and the pixel memory current source transistor M23, and they do not necessarily have to be provided when the current change due to drain voltage fluctuations is small.

[0064] Next, an example configuration of the pixel vertical scanning circuit 20 and the memory vertical scanning circuit will be explained using Figure 5.

[0065] As described above, the pixel vertical scanning circuit 20 is a circuit that outputs control signals TXA, TXB, RES, and SEL for driving the pixels 12. The pixel vertical scanning circuit 20 generates control signals TXA, TXB, RES, and SEL based on the pixel scanning signal input from the pixel control circuit 92. The pixel control circuit 92 generates the pixel scanning signal based on a signal input from outside the photoelectric converter. Here, the pixel scanning signal is, for example, a 1.8V level signal, while the control signals TXA, TXB, RES, and SEL output by the pixel vertical scanning circuit 20 are, for example, 3.3V level signals. Therefore, the pixel vertical scanning circuit 20 is required to convert the 1.8V level pixel scanning signal into 3.3V level control signals TXA, TXB, RES, and SEL and output them.

[0066] Similarly, the memory vertical scanning circuit 40 is a circuit that outputs control signals BLK, SWN, SWA, SWAB, RESC, SELM for driving the pixel memory 32, as described above. The memory vertical scanning circuit 40 generates the control signals BLK, SWN, SWA, SWAB, RESC, SELM based on the memory scanning signal input from the memory control circuit 94. The memory control circuit 94 generates the memory scanning signal based on a signal input from outside the photoelectric converter. Here, the memory scanning signal is, for example, a 1.8V level signal, while the control signals BLK, SWN, SWA, SWAB, RESC, SELM output by the memory scanning circuit are, for example, 3.3V level signals. Therefore, the memory vertical scanning circuit 40 is required to convert the 1.8V level memory scanning signal into 3.3V level control signals BLK, SWN, SWA, SWAB, RESC, SELM and output them.

[0067] Figure 5 is a circuit diagram showing a part of the pixel vertical scanning circuit 20 in the photoelectric conversion device according to this embodiment. Figure 5(a) is a circuit diagram showing an example configuration of the block that outputs the control signal TXA in the pixel vertical scanning circuit 20. Figure 5(b) is an example of a circuit diagram in which the circuit in Figure 5(a) has been rewritten with transistor-level elements. Figure 5(c) is another example of a circuit diagram in which the circuit in Figure 5(a) has been rewritten with transistor-level elements. Note that the blocks that output the other control signals TXB, RES, and SEL may have the same configuration as the block that outputs the control signal TXA. The same may also be true for the blocks that output the control signals BLK, SWN, SWA, SWAB, RESC, and SELM of the memory vertical scanning circuit 40.

[0068] The pixel vertical scanning circuit 20 may be configured to include a voltage conversion circuit 22 and inverters 24 and 26. The voltage conversion circuit 22 has input terminals in and inb and an output terminal out. The output terminal out of the voltage conversion circuit is connected to the input terminal of inverter 24. The output terminal of inverter 24 outputs to the input terminal of inverter 26. The output terminal of inverter 26 is the output terminal of the control signal TXA.

[0069] The input terminal in of the voltage conversion circuit 22 receives the pixel scanning signal generated based on the output signal from the pixel control circuit 92. The input terminal inb of the voltage conversion circuit 22 receives the inverted signal of the pixel scanning signal. The voltage conversion circuit 22 converts the voltage value of the pixel scanning signal to a suitable voltage value as the control signal TXA and outputs it from the output terminal out. Inverters 24 and 26 buffer the output signal of the voltage conversion circuit 22 and output it as the control signal TXA.

[0070] Here, the voltage conversion circuit 22 and inverters 24,26 may be composed of a circuit that includes a complementary connection of an N-type transistor and a P-type transistor, a so-called CMOS (Complementary Metal Oxide Semiconductor) circuit.

[0071] The voltage conversion circuit 22 may be composed of N-type transistors MN1 and MN2 arranged on the first substrate 110 and P-type transistors MP1 and MP2 arranged on the second substrate 120, as shown in Figure 5(b), for example. The sources of the N-type transistors MN1 and MN2 are connected to the ground voltage node (voltage SGND). The drain of the N-type transistor MN1 is connected to the drain of the P-type transistor MP1 and the gate of the P-type transistor MP2 via connection CN12, which is one of the electrical connections between the first substrate 110 and the second substrate 120. The drain of the N-type transistor MN2 is connected to the drain of the P-type transistor MP2 and the gate of the P-type transistor MP1 via connection CN13, which is one of the electrical connections between the first substrate 110 and the second substrate 120. The sources of the P-type transistors MP1 and MP2 are connected to the power supply voltage node (voltage SVDD). Then, the gate of the N-type transistor MN1 becomes the input terminal in, the gate of the N-type transistor MN2 becomes the input terminal inb, and the connection node between the drain of the N-type transistor MN2 and the gate of the P-type transistor MP1 and the drain of the P-type transistor MP2 becomes the output terminal out.

[0072] The inverter 24 may be composed of an N-type transistor MN3 arranged on a first substrate 110 and a P-type transistor MP3 arranged on a second substrate 120, as shown in Figure 5(b). The source of the N-type transistor MN3 is connected to the ground voltage node (voltage SGND). The drain of the N-type transistor MN3 is connected to the drain of the P-type transistor MP3 via a connection CN15, which is one of the electrical connections between the first substrate 110 and the second substrate 120. The gate of the N-type transistor MN3 is connected to the gate of the P-type transistor MP3 via a connection CN14, which is one of the electrical connections between the first substrate 110 and the second substrate 120. The source of the P-type transistor MP3 is connected to the power supply voltage node (voltage SVDD). The connection node between the gate of the N-type transistor MN3 and the gate of the P-type transistor MP3 becomes the input terminal connected to the voltage conversion circuit 22, and the connection node between the drain of the N-type transistor MN3 and the drain of the P-type transistor MP3 becomes the output terminal.

[0073] The inverter 26 may be composed of an N-type transistor MN4 arranged on a first substrate 110 and a P-type transistor MP4 arranged on a second substrate 120, as shown in Figure 5(b). The source of the N-type transistor MN4 is connected to the ground voltage node (voltage SGND). The drain of the N-type transistor MN4 is connected to the drain of the P-type transistor MP4 via a connection CN17, which is one of the electrical connections between the first substrate 110 and the second substrate 120. The gate of the N-type transistor MN4 is connected to the gate of the P-type transistor MP4 via a connection CN16, which is one of the electrical connections between the first substrate 110 and the second substrate 120. The source of the P-type transistor MP4 is connected to the power supply voltage node (voltage SVDD). The connection node between the gate of the N-type transistor MN4 and the gate of the P-type transistor MP4 becomes the input terminal connected to the inverter 24, and the connection node between the drain of the N-type transistor MN4 and the drain of the P-type transistor MP4 becomes the output terminal.

[0074] The circuit shown in Figure 5(c) is similar to the circuit in Figure 5(b) in that the basic connection relationships of each element are the same, except that the configuration of the electrical connection between the first substrate 110 and the second substrate 120 is different.

[0075] In the circuit shown in Figure 5(c), the connection node between the gate of N-type transistor MN3 and the drain of N-type transistor MN2 is connected to the connection node between the gates of P-type transistors MP1 and MP3 and the drain of P-type transistor MP2 via connection section CN13. Additionally, the connection node between the gate of N-type transistor MN4 and the drain of N-type transistor MN3 is connected to the connection node between the gate of P-type transistor MP4 and the drain of P-type transistor MP3 via connection section CN15.

[0076] In the circuit shown in Figure 5(b), before the first substrate 110 and the second substrate 120 are joined, connection part CN14 is connected only to the gate of N-type transistor MN3, and connection part CN16 is connected only to the gate of N-type transistor MN4. In other words, the gates of N-type transistors MN3 and MN4 are floating. Therefore, if connection parts C14 and C16 are exposed to plasma during the manufacturing process of the first substrate 110, there is a possibility that dielectric breakdown of the gate insulating films of N-type transistors MN3 and MN4 may occur due to plasma-induced charge-up.

[0077] In this regard, in the circuit shown in Figure 5(c), before the first substrate 110 and the second substrate 120 are joined, the gates of the transistors connected to the connection points CN12, CN13, CN15, and CN17 are also connected to the drains of the other transistors. In other words, the gates of the N-type transistors MN3 and MN4 and the P-type transistors MP1, MP2, MP3, and MP4 are not in a floating state. Therefore, it is possible to suppress the introduction of plasma-induced damage to the gate insulating film during the manufacturing process of the first substrate 110 and the second substrate 120, thereby improving the manufacturing yield.

[0078] The circuit configurations of the voltage conversion circuit 22 and inverters 24 and 26, as well as the configuration of the connection between the first substrate 110 and the second substrate 120, are not necessarily limited to the examples shown in Figures 5(b) and 5(c). Furthermore, depending on the manufacturing process of the first substrate 110 and the second substrate 120, it may be possible to reduce the effects of plasma-induced damage, and the above description does not actively exclude the application of the configuration example in Figure 5(b).

[0079] In this explanation, we used the pixel vertical scanning circuit 20 and the memory vertical scanning circuit 40 as examples to describe a configuration in which N-type transistors and P-type transistors are placed on separate semiconductor substrates. However, similar configurations can be applied to other peripheral circuits composed of CMOS circuits.

[0080] By arranging the N-type and P-type transistors that constitute the CMOS circuit on separate semiconductor substrates, it is possible to prevent the formation of a PN junction between the P-type well where the N-type transistor is placed and the N-type well where the P-type transistor is placed. This prevents the formation of parasitic thyristor elements and improves resistance to latch-up caused by noise and other factors.

[0081] Furthermore, when N-type transistors and P-type transistors are arranged on the same semiconductor substrate, physical space is required to electrically separate the P-type well on which the N-type transistors are placed from the N-type well on which the P-type transistors are placed, which can be an obstacle to miniaturization. However, in the configuration of this embodiment, since the N-type transistors and P-type transistors are formed on separate semiconductor substrates that are physically separated, there is no need to provide space to separate the wells, and it is possible to reduce the layout area of ​​the peripheral circuits.

[0082] Furthermore, with the above configuration, it is possible to place the power supply wiring and ground wiring on separate semiconductor substrates, for example, as shown in Figures 5(b) and 5(c), where the power supply voltage line SVDD and the ground voltage line SGND are located. Therefore, since it is not necessary to arrange the power supply wiring and ground wiring in parallel for layout purposes, short-circuit failures between the power supply wiring and ground wiring can be reduced.

[0083] Next, the operation of the photoelectric conversion device according to this embodiment will be explained with reference to Figures 6 to 10.

[0084] Figure 6 is a schematic diagram showing the scanning image in the row scanning direction against time. In each figure in Figure 6, the vertical direction indicates the row scanning direction, and the horizontal direction indicates time. Period A, marked with a dot pattern, is the exposure period of pixel 12. Period B, marked with a crosshatch, is the pixel memory writing period, in which the signal from pixel 12 is read and written to the pixel memory 32. Region C, marked with a downward sloping diagonal line, is the pixel memory reading period, in which the signal from pixel memory 32 is read to the signal processing circuit 52. Note that the driving patterns in Figure 6 are examples, and the driving patterns of the photoelectric converter according to this embodiment are not limited to these.

[0085] In the driving pattern shown in Figure 6(a), a so-called global shutter operation is performed, in which the shutter operation defining the start and end of period A is performed simultaneously at all pixels 12. Period B is also performed simultaneously at all pixels 12 and pixel memory 32. Period C is performed sequentially row by row and column by column.

[0086] The multiple rows constituting the pixel section 10 and the memory section 30 may be divided into multiple (N) blocks, each containing two or more rows, and periods A and B may be executed on a block-by-block basis.

[0087] Figures 6(b) and 6(c) show a drive pattern in which periods A and B are executed while sequentially shifting the start times in block units. That is, in block 1, block 2, ..., block N, the start times of periods A and B are sequentially delayed by the length of period C (1 horizontal period). Period C is executed sequentially row by row, column by column, similar to the drive pattern in Figure 6(a).

[0088] The difference between the drive pattern in Figure 6(b) and the drive pattern in Figure 6(c) lies in the start timing of period C. Specifically, in the drive pattern in Figure 6(b), period C for each row is executed sequentially after period A and period B of block 1 have finished. In contrast, in the drive pattern in Figure 6(c), period C for each row is executed sequentially after period A and period B of all blocks have finished.

[0089] Furthermore, the block-level transfer operation of pixel signals from the pixel unit 10 to the memory unit 30 can be controlled by the control signals SEL and BLK of the selection transistor M4 and the current source switch transistor M11 in the circuit diagram of Figure 4.

[0090] For example, as shown in Figure 7, the pixel section 10 and the memory section 30 are divided into multiple (N) blocks blk1, blk2, blk3, ..., blkN in row units. The control signals of the selection transistor M4 of the pixels 12 belonging to each block blk1, blk2, blk3, ..., blkN are set to control signals SEL1, SEL2, SEL3, ..., SERN, respectively. The control signals of the current source switch transistor M11 of the pixel memory 32 belonging to each block blk1, blk2, blk3, ..., blkN are set to control signals BLK1, BLK2, BLK3, ..., BLKN, respectively. In this case, for example, as shown in Figure 8, the pixels 12 and pixel memory 32 should be driven sequentially so that the control signals SEL1, BLK1, SEL2, BLK2, SEL3, BLK3, ..., and SERN, BLKN are asserted in sequence.

[0091] Next, the write operation to the pixel memory 32 during period B will be explained using Figure 9. Figure 9 is a timing diagram showing the write operation to the pixel memory. Figure 9 shows the waveforms of the control signals RES, TXA, TXB, SEL, BLK, RESC, SWN, SWA, SWAB and the voltage VREADP of node VREADP. In Figure 9, the period up to just before time t1 is the charge accumulation period (period A) for the photoelectric conversion elements PDA and PDB, and the period from time t1 to time t10 is the write period (period B) to the pixel memory 32.

[0092] Immediately before time t1, the control signal RES is at a high level, and the reset transistor M2 of pixel 12 is on. As a result, node FD of pixel 12 is set (reset) to a voltage corresponding to voltage SVDD. Also, the control signal RESC is at a high level, and the reset transistor M17 of pixel memory 32 is on. As a result, the voltage of node VREADP is set to a voltage corresponding to voltage MVDD. Furthermore, the control signals SWN, SWA, and AWAB are on, and the sampling transistors M14, M15, and M16 are on. As a result, one end of the hold capacitors CN, CA, and CAB is set to a voltage corresponding to voltage MVDD. Note that the control signals TXA, TXB, SEL, and BLK are at a low level immediately before time t1.

[0093] At time t1, the memory vertical scanning circuit 40 controls the control signals RESC, SWN, SWA, and AWAB from high level to low level. As a result, the reset transistor M17 and sampling transistors M14, M15, and M16 of the pixel memory 32 are turned off, and the hold capacitors CN, CA, and CAB retain the voltage set immediately before time t1.

[0094] Also at time t1, the pixel vertical scanning circuit 20 controls the control signal SEL from a low level to a high level. The memory vertical scanning circuit 40 also controls the control signal BLK from a low level to a high level. As a result, the selection transistor M4 and the current source switch transistor M11 are turned on, supplying a bias current to the amplification transistor M3 of the pixel 12, and a signal corresponding to the voltage of node FD is output to the signal output line 16.

[0095] At the following time t2, the pixel vertical scanning circuit 20 controls the control signal RES from a high level to a low level. This turns off the reset transistor M2, and the node FD maintains a reset state with voltage SVDD. The voltage of node FD that settles after the reset transistor M2 is turned off is the reset voltage of node FD. A voltage corresponding to the reset voltage of node FD (noise signal voltage (hereinafter referred to as the N signal)) is output to node VREADP via the signal output line 16 and the connection part CN11.

[0096] Similarly, at time t2, the memory vertical scanning circuit 40 controls the control signal SWN from a low level to a high level. This turns on the sampling transistor M14, and the hold capacitor CN is connected to node VREADP, making it possible to write a signal corresponding to the voltage of node VREADP to the hold capacitor CN.

[0097] At the following time t3, the memory vertical scanning circuit 40 controls the control signal SWN from a high level to a low level. As a result, the sampling transistor M14 is turned off, and the N signal output to node VREADP is held in the hold capacitor CN.

[0098] At the following time t4, the pixel vertical scanning circuit 20 controls the control signal TXA from a low level to a high level. This turns on the transfer transistor M1A, and the charge held in the photoelectric conversion element PDA is transferred to node FD. Node FD then has a voltage corresponding to the amount of charge transferred from the photoelectric conversion element PDA.

[0099] At the following time t5, the pixel vertical scanning circuit 20 controls the control signal TXA from a high level to a low level. This turns off the transfer transistor M1A. A voltage corresponding to the amount of charge transferred from the photoelectric conversion element PDA is output to node VREADP via the signal output line 16 and the connector CN11. The voltage output to node VREADP after the transfer transistor M1A is turned off and the voltage at node FD has stabilized is the first image signal voltage (hereinafter referred to as the SA signal).

[0100] At the following time t5, the memory vertical scanning circuit 40 controls the control signal SWA from a low level to a high level. This turns on the sampling transistor M15, and the hold capacitor CA is connected to node VREADP, making it possible to write a signal corresponding to the voltage of node VREADP to the hold capacitor CA.

[0101] At the following time t6, the memory vertical scanning circuit 40 controls the control signal SWA from a high level to a low level. As a result, the sampling transistor M15 is turned off, and the SA signal output to node VREADP is held in the hold capacitor CA.

[0102] At the following time t7, the pixel vertical scanning circuit 20 controls the control signals TXA and TXB from low to high levels. This turns on the transfer transistors M1A and M1B, and the charge held in the photoelectric conversion elements PDA and PDB is transferred to node FD. In other words, the charge of photoelectric conversion element PDA and the charge of photoelectric conversion element PDB are added together at node FD. The voltage at node FD becomes a voltage corresponding to the amount of charge transferred from photoelectric conversion elements PDA and PDB.

[0103] At the following time t8, the pixel vertical scanning circuit 20 controls the control signals TXA and TXB from high level to low level. This turns off the transfer transistors M1A and M1B. A voltage corresponding to the amount of charge transferred from the photoelectric conversion elements PDA and PDB is output to node VREADP via the signal output line 16 and the connector CN11. The voltage output to node VREADP after the transfer transistors M1A and M1B are turned off and the voltage at node FD has stabilized is the second image signal voltage (hereinafter referred to as the SAB signal).

[0104] At the following time t9, the memory vertical scanning circuit 40 controls the control signal SWAB from a low level to a high level. This turns on the sampling transistor M16, and the hold capacitor CAB is connected to node VREADP, making it possible to write a signal corresponding to the voltage of node VREADP to the hold capacitor CAB.

[0105] At the following time t10, the memory vertical scanning circuit 40 controls the control signal SWAB from a high level to a low level. As a result, the sampling transistor M16 is turned off, and the SAB signal output to node VREADP is held in the hold capacitor CAB.

[0106] In this way, the N signal, SA signal, and SAB signal of each pixel 12 can be stored in the hold capacities CN, CA, and CAB of the pixel memory 32.

[0107] Next, the read operation from the pixel memory 32 to the signal processing circuit 52 during period C will be explained using Figure 10. Figure 10 is a timing diagram showing the read operation from the pixel memory 32 to the signal processing circuit 52. Figure 10 shows the waveforms of the control signals SELM(1), SELM(2), BLKM, RESC, SWN, SWA, and SWAB. In Figure 10, the period up to just before time t21 is the write period to the pixel memory 32 (period B), and the period from time t21 to time t30 is the read period for one row of pixel memory (period C). Figure 10 shows the read periods for two rows (the Nth row and the (N+1)th row).

[0108] Immediately before time t21, the control signal RESC is at a low level, and the reset transistor M17 of the pixel memory 32 is off. As a result, node VREADP is set to a voltage corresponding to the voltage MVDD. Also, the control signals SWN, SWA, and AWAB are on, and the sampling transistors M14, M15, and M16 are on. As a result, one end of the hold capacitors CN, CA, and CAB is set to a voltage corresponding to the voltage MVDD. Furthermore, the control signals SELM(N) and SELM(N+1) are at a low level, and the selection transistor M19 of the pixel memory 32 for the Nth and (N+1)th rows is off. Also, the control signal BLKM is at a low level, and the current source switch transistor M21 is off.

[0109] At time t21, the memory vertical scanning circuit 40 controls the control signal SELM(N) for the Nth row from a low level to a high level. The column control circuit 80 also controls the control signal BLKM supplied to the signal processing circuit for each column from a low level to a high level. As a result, the selection transistor M19 and the current source switch transistor M21 are turned on, supplying bias current to the amplification transistor M18 of the pixel memory 32, and a signal corresponding to the voltage of node VREADP is output to the signal output line 36.

[0110] During the period from time t21 to time t22, the memory vertical scanning circuit 40 controls the control signal RESC for the Nth row from a low level to a high level. This turns on the reset transistor M17 of the Nth row pixel memory 32, and sets the node VREADP of the Nth row pixel memory 32 to a voltage corresponding to the voltage MVDD.

[0111] During the period from time t23 to time t24, the memory vertical scanning circuit 40 controls the control signal SWN of the Nth row from a low level to a high level. This turns on the sampling transistor M14 of the pixel memory 32 of the Nth row, and the N signal held in the hold capacitor CN is output to node VREADP. A voltage corresponding to the N signal is output to node VLOUT via the signal output line 36 and the connector CN21.

[0112] The reason for setting node VREADP to a voltage corresponding to voltage MVDD before reading the N signal to node VREADP is to prevent the read signal from being affected by the state of node VREADP before the signal is read. The reason for setting node VREADP to a voltage corresponding to voltage MVDD during the periods from time t24 to time t25 and from time t27 to time t28, as described later, is the same. Note that although node VREADP is set to a voltage corresponding to voltage MVDD here, node VREADP may be set to any other power supply voltage.

[0113] During the period from time t24 to time t25, the memory vertical scanning circuit 40 controls the control signal RESC for the Nth row from a low level to a high level. This turns on the reset transistor M17 of the Nth row pixel memory 32, and the node VREADP of the Nth row pixel memory 32 is set again to a voltage corresponding to the voltage MVDD.

[0114] During the period from time t26 to time t27, the memory vertical scanning circuit 40 controls the control signal SWA of the Nth row from a low level to a high level. This turns on the sampling transistor M15 of the pixel memory 32 of the Nth row, and the SA signal held in the hold capacitor CA is output to node VREADP. A voltage corresponding to the SA signal is output to node VLOUT via the signal output line 36 and the connector CN21.

[0115] During the period from time t27 to time t28, the memory vertical scanning circuit 40 controls the control signal RESC for the Nth row from a low level to a high level. This turns on the reset transistor M17 of the Nth row pixel memory 32, and the node VREADP of the Nth row pixel memory 32 is set again to a voltage corresponding to the voltage MVDD.

[0116] During the period from time t29 to time t30, the memory vertical scanning circuit 40 controls the control signal SWAB for the Nth row from a low level to a high level. This turns on the sampling transistor M16 of the pixel memory 32 for the Nth row, and the SAB signal held in the hold capacitor CAB is output to node VREADP. A voltage corresponding to the SAB signal is output to node VLOUT via the signal output line 36 and the connector CN21.

[0117] At the following time t30, the memory vertical scanning circuit 40 controls the control signal SELM(N) for the Nth row from a high level to a low level. This completes the reading of the signal from the pixel memory 32 for the Nth row.

[0118] Similarly, from time t31 onward, the signal readout from the (N+1)th row of pixel memory 32 is performed in the same manner as during the period from time t21 to time t30. The signal readout from the pixel memory 32 of the other rows is performed in the same manner. The control signal BLKM is controlled from a high level to a low level when the signal readout from all rows of pixel memory 32 is completed.

[0119] In this way, the N signal, SA signal, and SAB signal of all pixels 12 held in the memory unit 30 can be read out row by row to the signal processing unit 50 of each column.

[0120] In this example, we have shown a drive method in which the SA signal and SAB signal are read from the pixel 12 as signals based on the charge of the photoelectric conversion elements PDA and PDB. However, the signals read from the pixel 12 are not limited to these. For example, it is also possible to drive the signal based on the charge read to node FD by simultaneously driving the transfer transistors M1A and M1B, or to drive the signal based on the SA signal based on the charge of the photoelectric conversion element PDA and the SB signal based on the charge of the photoelectric conversion element PDB.

[0121] Thus, in this embodiment, in a photoelectric converter composed of multiple substrates, the peripheral circuit is configured with a circuit that includes a complementary connection between a first-conductivity transistor provided on the first substrate and a second-conductivity transistor provided on the second substrate. Therefore, according to this embodiment, it is possible to prevent the formation of a PN junction between a P-type well where an N-type transistor is placed and an N-type well where a P-type transistor is placed on each of the first and second substrates. This prevents the formation of parasitic thyristor elements and improves resistance to latch-up caused by noise and the like. In addition, since there is no need to provide space to separate the wells, it is possible to reduce the layout area of ​​the peripheral circuit. Therefore, according to this embodiment, in a photoelectric converter composed of multiple substrates, the performance of the peripheral circuit can be improved, resulting in improved signal quality and cost reduction.

[0122] [Second Embodiment] A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Figures 11 to 15. Components similar to those in the photoelectric conversion device according to the first embodiment are denoted by the same reference numerals, and their descriptions are omitted or simplified.

[0123] The assignment of each functional block to each circuit board in the photoelectric conversion device according to this embodiment will be explained with reference to Figure 11. Figure 11 is a schematic diagram showing the assignment of each functional block to each circuit board in the photoelectric conversion device according to this embodiment.

[0124] The photoelectric conversion device according to this embodiment is constructed by stacking three substrates, a first substrate 110, a second substrate 120, and a third substrate 130, similar to the first embodiment. The first substrate 110 contains the pixel section 10, a part of the pixel vertical scanning circuit 20, a part of the pixel control circuit 92, a part of the memory vertical scanning circuit 40, a part of the memory control circuit 94, and a bias generation circuit 62, among the functional blocks described above. The second substrate 120 contains the memory section 30, another part of the pixel vertical scanning circuit 20, another part of the pixel control circuit 92, another part of the memory vertical scanning circuit 40, and another part of the memory control circuit 94, among the functional blocks described above. Furthermore, the second substrate 120 also contains a part of the signal processing unit 50, a part of the column control circuit 80, and a part of the signal processing control circuit 96. The third board 130 contains the remaining parts of the signal processing unit 50, the remaining parts of the column control circuit 80, the remaining parts of the signal processing control circuit 96, the bias generation circuits 64 and 66, and the reference signal output circuit 70, all of the functional blocks described above.

[0125] In the first embodiment, the pixel vertical scanning circuit 20 and the memory vertical scanning circuit 40 were provided across the first substrate 110 and the second substrate 120. In contrast, in this embodiment, the pixel vertical scanning circuit 20, the pixel control circuit 92, the memory vertical scanning circuit 40, and the memory control circuit 94 are provided across the first substrate 110 and the second substrate 120. Furthermore, in this embodiment, the signal processing unit 50, the column control circuit 80, and the signal processing control circuit 96 are provided across the second substrate 120 and the third substrate 130.

[0126] More specifically, the N-type transistors in the circuits constituting the pixel unit 10, pixel vertical scanning circuit 20, pixel control circuit 92, memory unit 30, memory vertical scanning circuit 40, bias generation circuit 62, and memory control circuit 94 are placed on the first substrate 110. The P-type transistors in the circuits constituting the pixel unit 10, pixel vertical scanning circuit 20, pixel control circuit 92, memory unit 30, memory vertical scanning circuit 40, and memory control circuit 94 are placed on the second substrate 120. The P-type transistors in the circuits constituting the signal processing unit 50, column control circuit 80, signal processing control circuit 96, and reference signal output circuit 70 are placed on the second substrate 120. The N-type transistors in the circuits constituting the signal processing unit 50, bias generation circuits 64, 66, column control circuit 80, signal processing control circuit 96, and reference signal output circuit 70 are placed on the third substrate 130. Note that if the photoelectric converter is distributed across two semiconductor substrates, the N-type transistors constituting each functional block should be placed on the first semiconductor substrate and the P-type transistors on the second semiconductor substrate.

[0127] By placing the N-type and P-type transistors that constitute each functional block on separate semiconductor substrates, as mentioned above, the formation of parasitic thyristor elements can be prevented, improving resistance to latch-up caused by noise and other factors. Furthermore, the physical space required to electrically separate the P-type and N-type wells is eliminated, reducing the layout area. Additionally, there is no need to arrange power and ground wiring in parallel, reducing the risk of short circuits between power and ground wiring.

[0128] Furthermore, by using either N-type or P-type transistors for each semiconductor substrate, the manufacturing process for each semiconductor substrate can be reduced, thereby lowering the manufacturing cost of the photoelectric converter.

[0129] Next, the circuit configuration of the pixel 12 and pixel memory 32 in the photoelectric conversion device according to this embodiment will be described in more detail with reference to Figure 12. Figure 12 is an equivalent circuit diagram showing an example of the configuration of the pixel 12 and pixel memory 32 in the photoelectric conversion device according to this embodiment.

[0130] N-type transistors are arranged on the first substrate 110, which are among the transistors that constitute each functional block. In the case of a pixel 12 that uses electrons as signal charge, as mentioned above, the pixel circuit can be constructed using N-type transistors. Therefore, the circuit configuration of the pixel section 10 arranged on the first substrate 110 may be the same as in the first embodiment. In the first embodiment, the current source circuit (current source switch transistor M11, cascode transistor M12, pixel current source transistor M13) that supplies bias current to the amplification transistor M3 is constructed using N-type transistors on the second substrate 120. Therefore, in this embodiment, these N-type transistors are moved from the second substrate 120 to the first substrate 110.

[0131] The first substrate 110 is equipped with N-type transistors, which constitute each functional block. In this embodiment, the sampling transistors M14, M15, M16, the reset transistor M17, and the amplification transistor M18 are made of P-type transistors. Furthermore, the current source circuit (current source switch transistor M21, cascode transistor M22, pixel memory current source transistor M23) that supplies bias current to the amplification transistor M18 is made of P-type transistors and is moved to the second substrate 120.

[0132] The amplification transistor M3 outputs a pixel signal corresponding to the voltage of node FD to the pixel memory 32 via the selection transistor M4. The pixel signal output to the pixel memory 32 is written to the hold capacitors CN, CA, and CAB via the sampling transistors M14, M15, and M16. The amplification transistor M18 outputs a pixel signal corresponding to the voltage of node VREADP, from which the pixel signals written to the hold capacitors CN, CA, and CAB have been read, to the signal processing circuit 52 via the selection transistor M19. In this way, the pixel 12 and the pixel memory 32 output the output of a two-stage source follower circuit, consisting of a source follower circuit that takes the signal of node FD as input and a source follower circuit that takes the signal of node VREADP as input, to the signal processing circuit 52 (node ​​VLOUT).

[0133] Generally, the transfer function of a two-stage source follower circuit is expressed by equation (1) below. Vout = Vin - ΔV1 - ΔV2 …(1) Here, Vin is the input voltage and Vout is the output voltage. Also, ΔV1 is the sum of the overdrive voltage and threshold voltage of the input transistor of the first-stage source follower circuit, and ΔV2 is the sum of the overdrive voltage and threshold voltage of the input transistor of the second-stage source follower circuit.

[0134] As can be seen from equation (1), the output voltage Vout is shifted to the lower voltage side by (ΔV1 + ΔV2) relative to the input voltage Vin, so the input / output range of the entire source follower circuit is significantly reduced.

[0135] In this regard, in the circuit configuration of this embodiment shown in Figure 12, by making the conductivity types of the amplification transistor M3 and the amplification transistor M18 opposite, it is possible to operate in such a way that the shift of ΔV1 is canceled out by the shift of ΔV2. Therefore, according to this embodiment, the input / output range of the entire circuit can be widened compared to the case in which a two-stage source follower circuit composed of transistors of the same conductivity type is configured.

[0136] Next, an example of the configuration of the signal processing circuit 52 in the photoelectric converter according to this embodiment will be described in more detail using Figure 13. Figure 13 is a circuit diagram showing a part of the signal processing circuit 52 in the photoelectric converter according to this embodiment. Figure 13 shows a circuit diagram of the comparator circuit 28 and its input section, which constitute a ramp-type AD conversion circuit, as an example of the circuits that make up the signal processing circuit 52. Figure 13(a) is an equivalent circuit diagram, and Figure 13(b) is an example of a circuit diagram in which Figure 13(a) is rewritten with transistor-level elements.

[0137] The ramp-type AD conversion circuit converts the pixel signal from an analog signal to a digital signal based on the result of comparing the pixel signal (voltage at node VLOUT) output from the pixel memory 32 with the reference signal ramp output from the reference signal output circuit 70. Specifically, the ramp-type AD conversion circuit outputs a count value as the digital value of the pixel signal, corresponding to the length of the period from the start of the comparison operation between the pixel signal and the reference signal ramp until the output signal, which is the result of the comparison, is inverted.

[0138] For example, as shown in Figure 13(a), the pixel signal (voltage at node VLOUT) is input to one of the input terminals of the comparator circuit 28 via input capacitor C1 and switch SW1. The reference signal ramp is input to the other input terminal of the comparator circuit 28 via input capacitor C2. The comparator circuit 28 compares the level of the pixel signal with the level of the reference signal ramp and outputs a signal according to the result of the comparison. For example, the comparator circuit 28 outputs a high-level signal when the level of the reference signal ramp is lower than the level of the pixel signal. Also, the comparator circuit 28 outputs a low-level signal when the level of the reference signal ramp is higher than the level of the pixel signal. Note that the relationship between the magnitude of the input signals and the levels of the output signals may be reversed.

[0139] Input capacitor C1 may be provided on the second board 120, for example, as shown in Figure 13(b). One terminal of input capacitor C1 is connected to the signal output line 36 (node ​​VLOUT). Input capacitor C2 may be provided on the third board 130. One terminal of input capacitor C2 is input to the reference signal ramp output from the reference signal output circuit 70.

[0140] Switch SW1 may consist of a P-type transistor MP5 provided on the second substrate 120 and an N-type transistor MN5 provided on the third substrate 130, as shown in Figure 13(b), for example. The source of the P-type transistor MP5 is connected to the other terminal of the input capacitor C1. The connection node between the other terminal of the input capacitor C1 and the source of the P-type transistor MP5 is connected to the drain of the N-type transistor MN5 via connection CN22, which is one of the electrical connections between the second substrate 120 and the third substrate 130. The drain of the P-type transistor MP5 is connected to the source of the N-type transistor MN5 via connection CN23, which is one of the electrical connections between the second substrate 120 and the third substrate 130. The control signal vlon is input to the gate of the N-type transistor MN5. The control signal vlonB, which is the inverted signal of the control signal vlon, is input to the gate of the P-type transistor MP5.

[0141] The comparator circuit 28 can be composed of, for example, P-type transistors MP6, MP7, and MP8 provided on the second substrate 120 and N-type transistors MN6, MN7, MN8, and MN9 provided on the third substrate 130, as shown in Figure 13(b). The sources of the P-type transistors MP6, MP7, and MP9 are connected to the power supply voltage node (voltage AVDD). The gates of the P-type transistors MP6 and MP7 and the drain of the P-type transistor MP6 are connected to the drain of the N-type transistor MN6 via connection CN24, which is one of the electrical connections between the second substrate 120 and the third substrate 130. The drain of the P-type transistor MP7 is connected to the drain of the N-type transistor MN7 via connection CN25, which is one of the electrical connections between the second substrate 120 and the third substrate 130. The sources of the N-type transistors MN6 and MN7 are connected to the drain of the N-type transistor MN8. The drain of the P-type transistor MP7 is also connected to the gate of the P-type transistor MP8. The drain of the P-type transistor MP8 is connected to the drain of the N-type transistor MN9 via connection CN26, which is one of the electrical connections between the second substrate 120 and the third substrate 130. The sources of the N-type transistors MN8 and MN9 are connected to the ground voltage node (voltage AGND).

[0142] The gate of N-type transistor MN6 is one input terminal of comparator circuit 28 and is connected to the connection node between the source of N-type transistor MN5 of switch SW1 and connector CN23. The gate of N-type transistor MN7 is the other input terminal of comparator circuit 28 and is connected to the other terminal of input capacitor C2. The gates of N-type transistors MN8 and MN9, which act as tail current sources, are input with the voltage VBIAS3 from bias generation circuit 66. The connection node between the drain of N-type transistor MN9 and connector CN26 becomes the output terminal of comparator circuit 28.

[0143] As described above, in this embodiment, the switch SW1 is configured with a complementary switch circuit including a P-type transistor MP5 arranged on the second substrate 120 and an N-type transistor MN5 arranged on the third substrate 130. By configuring the switch SW1 in this way, the on-resistance at low input voltages can be reduced compared to the case where the switch SW1 is configured with only the P-type transistor arranged on the second substrate 120, thereby expanding the operating range and reducing power consumption. Similar effects can also be obtained when the switch SW1 is configured with only the N-type transistor arranged on the third substrate 130.

[0144] Furthermore, in this embodiment, the comparator circuit 28 is also composed of P-type transistors MP6, MP7, and MP8 arranged on the second substrate 120 and N-type transistors MN6, NM7, MN8, and MN9 arranged on the third substrate 130. This makes it possible to construct a CMOS circuit that complementarily combines N-type and P-type transistors, and to construct a circuit that cannot be constructed using only the P-type transistors on the second substrate 120, thereby improving the degree of freedom in circuit design.

[0145] Other peripheral circuits, such as the pixel control circuit 92, memory control circuit 94, signal processing control circuit 96, and column control circuit 80, can be constructed by combining logic circuits. The logic circuits that make up these circuits may include NAND gates and NOR gates, but like the switch SW1 and comparator circuit 28 described above, NAND gates and NOR gates can also be constructed by complementaryly combining transistors with different conductivity types.

[0146] Figure 14 is a circuit diagram showing an example of a NAND gate configuration. A two-input NAND gate can be configured, for example, as shown in Figure 14, by including P-type transistors MP11 and MP12 arranged on a second board 120 and N-type transistors MN11 and MN12 arranged on a first board 110 or a third board 130. The sources of the P-type transistors MP11 and MP12 are connected to the power supply voltage node (voltage VDD). The drains of the P-type transistors MP11 and MP12 are connected to the drain of the N-type transistor MN11 via a connection CN33, which is one of the electrical connections between the second board 120 and the first board 110 or the third board 130. The source of the N-type transistor is connected to the drain of the N-type transistor MN12. The source of the N-type transistor is connected to the ground voltage node (voltage GND). The gate of the P-type transistor MP11 is connected to the gate of the N-type transistor MN12 via connection CN31, which is one of the electrical connections between the second substrate 120 and the first substrate 110 or the third substrate 130. The gate of the P-type transistor MP12 is connected to the gate of the N-type transistor MN11 via connection CN32, which is one of the electrical connections between the second substrate 120 and the first substrate 110 or the third substrate 130. The connection node between the gate of the N-type transistor MN11 and the gate of the P-type transistor MP12 becomes one input A, and the connection node between the gate of the N-type transistor MN12 and the gate of the P-type transistor MP11 becomes the other input B. In addition, the connection node between the drains of the P-type transistors MP11 and MP2 and the drain of the N-type transistor MN11 becomes the output OUT.

[0147] Figure 15 is a circuit diagram showing an example of a NOR circuit configuration. A two-input NOR circuit may be configured, for example, as shown in Figure 15, to include P-type transistors MP21 and MP22 arranged on a second board 120, and N-type transistors MN21 and MN22 arranged on a first board 110 or a third board 130. The source of the P-type transistor MP21 is connected to the power supply voltage node (voltage VDD). The drain of the P-type transistor MP21 is connected to the source of the P-type transistor MP22. The drain of the P-type transistor MP22 is connected to the drains of the N-type transistors MN21 and MN22 via a connector CN43, which is one of the electrical connections between the second board 120 and the first board 110 or the third board 130. The sources of the N-type transistors MN21 and MN22 are connected to the ground voltage node (voltage GND). The gate of the P-type transistor MP21 is connected to the gate of the N-type transistor MN21 via connection CN41, which is one of the electrical connections between the second substrate 120 and the first substrate 110 or the third substrate 130. The gate of the P-type transistor MP22 is connected to the gate of the N-type transistor NM22 via connection CN42, which is one of the electrical connections between the second substrate 120 and the first substrate 110 or the third substrate 130. The connection node between the gate of the N-type transistor NM21 and the gate of the P-type transistor MP21 becomes one input A, and the connection node between the gate of the N-type transistor MN22 and the gate of the P-type transistor MP22 becomes the other input B. In addition, the connection node between the drain of the P-type transistor MP22 and the drains of the N-type transistors MN21 and MN22 becomes the output OUT.

[0148] Therefore, peripheral circuits such as the pixel control circuit 92, memory control circuit 94, signal processing control circuit 96, and column control circuit 80 can also be constructed by complementaryly combining transistors of different conductivity types arranged on separate substrates.

[0149] Thus, according to this embodiment, similar to the first embodiment, in a photoelectric converter composed of multiple substrates, the performance of the peripheral circuits can be improved, resulting in improved signal quality and cost reduction. Furthermore, by unifying the conductivity type of the transistors placed on each substrate to either N-type or P-type, the manufacturing process for each substrate can be reduced, further lowering manufacturing costs.

[0150] [Third Embodiment] A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Figure 16. Components similar to those in the photoelectric conversion device according to the first or second embodiment will be denoted by the same reference numerals, and their descriptions will be omitted or simplified.

[0151] The photoelectric converter according to this embodiment is the same as the photoelectric converter according to the first or second embodiment, except that the configuration of the connection parts that electrically connect the semiconductor substrates is different. That is, in the photoelectric converter according to this embodiment, each of the connection parts that electrically connect the semiconductor substrates is composed of a plurality of connection parts arranged in parallel.

[0152] Figure 16 is a circuit diagram showing the configuration of this embodiment applied to the signal processing circuit 52 of the photoelectric converter according to the second embodiment. Specifically, in this embodiment, the connection section CN22 connecting the source of the P-type transistor MP5 and the drain of the N-type transistor MN5 is composed of two connection sections CN221 and CN222 arranged in parallel. Also, the connection section CN23 connecting the drain of the P-type transistor MP5 and the source of the N-type transistor MN5 is composed of two connection sections CN231 and CN232 arranged in parallel. Furthermore, the connection section CN24 connecting the gates of the P-type transistors MP6 and MP7, and the drain of the P-type transistor MP6 to the drain of the N-type transistor MN6, is composed of two connection sections CN241 and CN242 arranged in parallel. Also, the connection section CN25 connecting the drain of the P-type transistor MP7, the gate of the P-type transistor MP8 to the drain of the N-type transistor NM7 is composed of two connection sections CN251 and CN252 arranged in parallel. Furthermore, the connection section CN26, which connects the drain of the P-type transistor MP8 to the gate of the N-type transistor MN7 and the drain of the N-type transistor, is composed of two connection sections CN261 and CN262 arranged in parallel.

[0153] In the example configuration shown in Figure 16, each connection is composed of two connection parts arranged in parallel, but each connection may be composed of three or more connection parts arranged in parallel. Furthermore, it is not necessary for all connection parts of the photoelectric converter to be composed of multiple connection parts arranged in parallel; some connection parts may be composed of multiple connection parts arranged in parallel. In addition, the number of connection parts arranged in parallel may differ for each connection part.

[0154] By configuring the connection points that electrically connect semiconductor substrates with multiple connection points arranged in parallel, the redundancy of the connection points can be increased, and yield reductions caused by manufacturing defects in the connection points can be suppressed. Furthermore, by increasing the number of parallel connections in the connection point connected to the transistor gate compared to the number of parallel connections in other connection points, the possibility of gate input instability and through-current flow due to connection point defects can be reduced.

[0155] Thus, according to this embodiment, similar to the first embodiment, in a photoelectric conversion device composed of multiple substrates, the performance of the peripheral circuits can be improved, resulting in improved signal quality and cost reduction. Furthermore, by configuring the connection parts that electrically connect semiconductor substrates with multiple connection parts arranged in parallel, the redundancy of the connection parts can be increased, and a decrease in yield due to manufacturing defects in the connection parts can be suppressed.

[0156] [Fourth Embodiment] A photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to Figure 17. Components similar to those in the photoelectric conversion devices of the first to third embodiments will be denoted by the same reference numerals, and their descriptions will be omitted or simplified. Figure 17 is a schematic diagram showing the assignment of each functional block to each substrate in the photoelectric conversion device according to this embodiment.

[0157] The photoelectric conversion device according to this embodiment is constructed by stacking three substrates: a first substrate 110, a second substrate 120, and a third substrate 130, similar to the first to third embodiments. The first substrate 110 contains the pixel section 10, a part of the pixel vertical scanning circuit 20, and a part of the memory vertical scanning circuit 40, among the functional blocks described above. The second substrate 120 contains the memory section 30, another part of the pixel vertical scanning circuit 20, another part of the memory vertical scanning circuit 40, and a bias generation circuit 64, among the functional blocks described above. The third substrate 130 contains the signal processing unit 50, a bias generation circuit 66, a reference signal output circuit 70, a column control circuit 80, a pixel control circuit 92, a memory control circuit 94, and a signal processing control circuit 96, among the functional blocks described above. Thus, in the photoelectric conversion device according to this embodiment, the pixel control circuit 92 and the memory control circuit 94 are located on the same third substrate 130 as the signal processing control circuit 96 and the column control circuit 80.

[0158] Generally, the breakdown voltage of a transistor is determined primarily by the thickness of the gate insulating film; the thicker the gate insulating film, the higher the breakdown voltage of the transistor. On the other hand, since gate capacitance is proportional to the on-current, a thinner gate insulating film is preferable from the standpoint of transistor performance. Therefore, the thickness of the gate insulating film of each transistor is designed to be suitable for the required characteristics and driving voltage.

[0159] For example, among the functional blocks that constitute the photoelectric converter, the pixel control circuit 92, memory control circuit 94, signal processing control circuit 96, and column control circuit 80 are composed of transistors that operate at a relatively low drive voltage, such as 1.8V. In contrast, the pixel 12, pixel memory 32, signal processing circuit 52, pixel vertical scanning circuit 20, memory vertical scanning circuit 40, bias generation circuits 64, 66, and reference signal output circuit 70 are composed of transistors that operate at a relatively high drive voltage, such as 3.3V.

[0160] In the first to third embodiments, the pixel control circuit 92 and the memory control circuit 94 were arranged on the first substrate 110 and / or the second substrate 120. As a result, multiple types of transistors with different breakdown voltages (different gate insulating film thicknesses) are mixed on the first substrate 110 and the second substrate 120, which complicates the manufacturing process.

[0161] From this perspective, in the photoelectric converter according to this embodiment, functional blocks composed of transistors with low breakdown voltage are concentrated on the third substrate 130, while functional blocks composed of transistors with high breakdown voltage are arranged on the first substrate 110 and the second substrate 120. With this configuration, the first substrate 110 and the second substrate 120 can be composed solely of transistors with high breakdown voltage, thereby simplifying the manufacturing process of the first substrate 110 and the second substrate 120. This makes it possible to reduce the manufacturing cost of the photoelectric converter.

[0162] Thus, according to this embodiment, similar to the first embodiment, in a photoelectric converter composed of multiple substrates, the performance of the peripheral circuits can be improved, resulting in improved signal quality and cost reduction. Furthermore, by standardizing the transistors placed on each substrate to either low-voltage transistors or high-voltage transistors, the manufacturing process for each substrate can be reduced, further lowering manufacturing costs.

[0163] [Fifth Embodiment] A photoelectric conversion system according to a fifth embodiment of the present invention will be described with reference to Figure 18. Figure 18 is a block diagram showing the schematic configuration of the photoelectric conversion system according to this embodiment.

[0164] The photoelectric conversion device 100 described in the first to fourth embodiments above is applicable to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. Camera modules, which include optical systems such as lenses and imaging devices, are also included in photoelectric conversion systems. Figure 18 shows a block diagram of a digital still camera as an example of these.

[0165] The photoelectric conversion system 200 illustrated in Figure 18 includes an imaging device 201, a lens 202 for forming an optical image of a subject onto the imaging device 201, an aperture 204 for varying the amount of light passing through the lens 202, and a barrier 206 for protecting the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light onto the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any of the first to fourth embodiments, which converts the optical image formed by the lens 202 into image data.

[0166] The photoelectric conversion system 200 also includes a signal processing unit 208 that processes the output signal output from the imaging device 201. The signal processing unit 208 generates image data from the digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as needed before outputting the image data. The imaging device 201 may include an AD conversion unit that generates the digital signal processed by the signal processing unit 208. The AD conversion unit may be formed on the semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or on a semiconductor substrate separate from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. Alternatively, the signal processing unit 208 may be formed on the same semiconductor substrate as the imaging device 201.

[0167] The photoelectric conversion system 200 further includes a memory unit 210 for temporarily storing image data and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading data from the recording medium 214. The recording medium 214 may be built into the photoelectric conversion system 200 or it may be detachable.

[0168] Furthermore, the photoelectric conversion system 200 includes an overall control and calculation unit 218 that controls various calculations and the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from an external source, and the photoelectric conversion system 200 only needs to include at least an imaging device 201 and a signal processing unit 208 that processes the output signals output from the imaging device 201.

[0169] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0170] Thus, according to this embodiment, a photoelectric conversion system can be realized by applying the photoelectric conversion device 100 according to the first to fourth embodiments.

[0171] [Sixth Embodiment] A photoelectric conversion system and mobile body according to a sixth embodiment of the present invention will be described with reference to Figure 19. Figure 19 is a diagram showing the configuration of the photoelectric conversion system and mobile body according to this embodiment.

[0172] Figure 19(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any of the first to fourth embodiments above. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging device 310. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 318 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0173] The photoelectric conversion system 300 is connected to the vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to a warning device 340 that issues a warning to the driver based on the judgment result of the collision judgment unit 318. For example, if the collision judgment result of the collision judgment unit 318 indicates a high probability of collision, the control ECU 330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 340 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0174] In this embodiment, the photoelectric conversion system 300 images the area around the vehicle, for example, the front or rear. Figure 19(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0175] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive to prevent vehicles from straying from their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the vehicle itself, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0176] [Seventh Embodiment] A device according to the seventh embodiment of the present invention will be described with reference to Figure 20. Figure 20 is a block diagram showing the schematic configuration of the device according to this embodiment.

[0177] Figure 20 is a schematic diagram showing an instrument EQP including a photoelectric converter APR. The photoelectric converter APR has the functions of any of the first to fourth embodiments of the photoelectric converter 100. All or part of the photoelectric converter APR is a semiconductor device IC. The photoelectric converter APR in this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometering sensor, or a distance measuring sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including a photoelectric conversion unit are arranged in a matrix. The semiconductor device IC may have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0178] The photoelectric converter APR may have a stacked structure (chip stacking structure) comprising a first semiconductor chip equipped with multiple photoelectric conversion units and a second semiconductor chip equipped with peripheral circuits. The peripheral circuits on the second semiconductor chip can each be a column circuit corresponding to a pixel row of the first semiconductor chip. Alternatively, the peripheral circuits on the second semiconductor chip can each be a matrix circuit corresponding to a pixel or pixel block of the first semiconductor chip. Connections between the first and second semiconductor chips can be made using through-silicon vias (TSVs), direct bonding of conductors such as copper for inter-chip wiring, microbump connections between chips, or wire bonding.

[0179] The photoelectric converter APR may include a semiconductor device IC as well as a package PKG that houses the semiconductor device IC. The package PKG may include a substrate on which the semiconductor device IC is fixed, a cover made of glass or the like that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the substrate to terminals provided on the semiconductor device IC.

[0180] The EQP device may further comprise at least one of the following: an optical device OPT, a control unit CTRL, a processing unit PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric converter APR as a photoelectric converter, and is, for example, a lens, shutter, or mirror. The control unit CTRL controls the photoelectric converter APR and is, for example, a semiconductor device such as an ASIC. The processing unit PRCS processes the signals output from the photoelectric converter APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing unit PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or liquid crystal display device that displays information (images) obtained from the photoelectric converter APR. The memory device MMRY is a magnetic device or semiconductor device that stores information (images) obtained from the photoelectric converter APR. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN has movable parts or propulsion parts such as motors and engines. The device EQP displays signals output from the photoelectric converter APR on the display device DSPL, or transmits them to the outside using a communication device (not shown) provided by the device EQP. For this purpose, it is preferable that the device EQP further includes a memory device MMRY and a processing device PRCS, separate from the memory circuit and arithmetic circuit of the photoelectric converter APR.

[0181] The EQP (Equipment Equipped Device) shown in Figure 20 can be an electronic device such as an information terminal with imaging capabilities (e.g., a smartphone or wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). In a camera, the mechanical device MCHN can drive components of the optical device OPT for zooming, focusing, and shutter operation. The EQP can also be a transportation device (mobile object) such as a vehicle, ship, or aircraft. Furthermore, the EQP can be a medical device such as an endoscope or a CT scanner.

[0182] The mechanical device MCHN in transport equipment can be used as a mobile device. The device EQP as transport equipment is suitable for transporting the photoelectric converter APR, or for assisting and / or automating driving (operation) through its imaging function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing to operate the mechanical device MCHN as a mobile device based on information obtained from the photoelectric converter APR.

[0183] The photoelectric converter APR according to this embodiment can provide high value to its designers, manufacturers, distributors, buyers, and / or users. Therefore, by installing the photoelectric converter APR in the EQP (Equipment Equipment), the value of the EQP can also be increased. Thus, when manufacturing and selling the EQP, deciding to install the photoelectric converter APR of this embodiment in the EQP is advantageous in increasing the value of the EQP.

[0184] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0185] Furthermore, although the first to fourth embodiments described above describe a global shutter type photoelectric converter having a memory unit 30, the photoelectric converter to which the present invention can be applied is not limited thereto. For example, the transfer of pixel signals from the pixel unit 10 to the memory unit 30 does not necessarily have to be done all at once or in blocks, but may be done sequentially in row units. Also, the photoelectric converter does not necessarily have to have a memory unit 30, and may be a rolling shutter type photoelectric converter.

[0186] Furthermore, the circuit configuration of the pixel 12 shown in the above embodiment is illustrative and can be modified as appropriate. For example, although the above embodiment described a pixel 12 having multiple photoelectric conversion elements, the number of photoelectric conversion elements in each pixel 12 does not necessarily have to be multiple and may be one. Also, the pixel 12 does not necessarily have to have a selection transistor M4. In addition, the capacitance value of node FD may be configured to be switchable.

[0187] Furthermore, the photoelectric conversion systems shown in the fifth and sixth embodiments above are merely examples of photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied, and the photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 18 and 19(a).

[0188] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0189] It should be noted that the above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various forms without departing from its technical concept or its main features.

[0190] The above-disclosed embodiment includes the following configuration. (Composition 1) A pixel unit having a photoelectric conversion element and outputting a signal corresponding to the light incident on the photoelectric conversion element, It includes peripheral circuits for driving the pixel portion or processing signals output from the pixel portion, The peripheral circuit includes a circuit that includes a complementary connection between a first-conductivity transistor provided on the first substrate and a second-conductivity transistor provided on the second substrate. A photoelectric conversion device characterized by the following features. (Configuration 2) The peripheral circuit includes a pixel driving circuit that drives the pixel section. The pixel driving circuit is configured with a circuit that includes a complementary connection between a first transistor of the first conductivity type provided on the first substrate and a second transistor of the second conductivity type provided on the second substrate. A photoelectric conversion device according to configuration 1, characterized by the features described above. (Composition 3) The peripheral circuit further includes a first control circuit that controls the pixel driving circuit, The first control circuit is provided on the first substrate. A photoelectric conversion device according to configuration 2, characterized by the features described above. (Composition 4) The peripheral circuit further includes a first control circuit that controls the pixel driving circuit, The first control circuit is comprised of a circuit including a complementary connection between a third transistor of the first conductivity type provided on the first substrate and a fourth transistor of the second conductivity type provided on the second substrate. A photoelectric conversion device according to configuration 2, characterized by the features described above. (Composition 5) The peripheral circuit further includes a first control circuit that controls the pixel driving circuit, The first control circuit is provided on the third substrate. A photoelectric conversion device according to configuration 2, characterized by the features described above. (Composition 6) The system further includes a memory unit that holds the signals output from the aforementioned pixel unit, The peripheral circuit further includes a memory drive circuit provided on the second substrate for driving the memory section. A photoelectric conversion device according to any one of configurations 1 to 5, characterized by the above. (Composition 7) The system further includes a memory unit that holds the signals output from the aforementioned pixel unit, The peripheral circuit further includes a memory drive circuit that drives the memory section. The memory drive circuit is configured with a circuit that includes a complementary connection between a fifth transistor of the first conductivity type provided on the first substrate and a sixth transistor of the second conductivity type provided on the second substrate. A photoelectric conversion device according to any one of configurations 1 to 5, characterized by the above. (Composition 8) The pixel section has a seventh transistor of the first conductivity type that constitutes a source follower circuit and outputs a signal corresponding to the output of the photoelectric conversion element. The memory unit includes a holding unit that holds signals output from the pixel unit, and an eighth transistor of the second conductivity type that constitutes a source follower circuit and outputs a signal corresponding to the output of the holding unit. A photoelectric conversion device according to configuration 6 or 7, characterized by the above. (Composition 9) The peripheral circuit further includes a second control circuit that controls the memory drive circuit. The second control circuit is provided on the second substrate. A photoelectric conversion device according to any one of configurations 6 to 8, characterized by the above. (Composition 10) The peripheral circuit further includes a second control circuit that controls the memory drive circuit. The second control circuit is configured with a circuit that includes a complementary connection between the ninth transistor of the first conductivity type provided on the first substrate and the tenth transistor of the second conductivity type provided on the second substrate. A photoelectric conversion device according to any one of configurations 6 to 8, characterized by the above. (Composition 11) The peripheral circuit further includes a second control circuit that controls the memory drive circuit. The second control circuit is provided on the third board. A photoelectric conversion device according to any one of configurations 6 to 8, characterized by the above. (Composition 12) The memory unit is provided on the second substrate. A photoelectric conversion device according to any one of configurations 6 to 11, characterized by the above. (Composition 13) The peripheral circuit is provided on the third substrate and further includes a signal processing circuit that processes signals output from the pixel section. A photoelectric conversion device according to any one of configurations 1 to 12, characterized by the above. (Composition 14) The peripheral circuit further includes a third control circuit that controls the signal processing circuit. The third control circuit is provided on the third substrate. A photoelectric conversion device according to configuration 13, characterized by the features described above. (Composition 15) The transistor provided on the first substrate is a transistor of the first conductivity type, The transistor provided on the second substrate is a transistor of the second conductivity type. A photoelectric conversion device according to any one of configurations 1 to 14, characterized by the above. (Composition 16) The transistor provided on the third substrate is the first conductivity type transistor. A photoelectric conversion device according to configuration 5, 11, 13, or 14, characterized by the above. (Composition 17) Of the transistors constituting the peripheral circuit, the gate insulating film thickness of the transistors provided on the first and second substrates is thicker than the gate insulating film thickness of the transistor provided on the third substrate. A photoelectric conversion device according to configuration 5, 11, 13, or 14, characterized by the above. (Composition 18) The pixel portion is provided on the first substrate. A photoelectric conversion device according to any one of configurations 1 to 17, characterized by the above. (Composition 19) The peripheral circuit further includes a signal processing circuit that processes the signal output from the pixel unit, The signal processing circuit includes a circuit that includes a complementary connection between the 11th transistor of the first conductivity type provided on the first substrate and the 12th transistor of the second conductivity type provided on the second substrate. A photoelectric conversion device according to configuration 1, characterized by the features described above. (Composition 20) The peripheral circuit further includes a third control circuit that controls the signal processing circuit. The third control circuit is provided on the first substrate. A photoelectric conversion device according to configuration 19, characterized by the features described above. (Composition 21) The peripheral circuit further includes a third control circuit that controls the signal processing circuit. The third control circuit is configured with a circuit that includes a complementary connection between the 13th transistor of the first conductivity type provided on the first substrate and the 14th transistor of the second conductivity type provided on the second substrate. A photoelectric conversion device according to configuration 19, characterized by the features described above. (Composition 22) The aforementioned pixel portion is provided on the third substrate. A photoelectric conversion device according to any one of configurations 19 to 21, characterized by the above. (Composition 23) The system further includes a memory unit that holds the signals output from the aforementioned pixel unit, The memory unit is provided on the second substrate. A photoelectric conversion device according to any one of configurations 19 to 22, characterized by the above. (Composition 24) The system further includes a memory unit that holds the signals output from the aforementioned pixel unit, The pixel section and the memory section are provided on the first substrate. A photoelectric conversion device according to any one of configurations 19 to 21, characterized by the above. (Composition 25) The pixel section has a plurality of pixels, each having the photoelectric conversion element. A photoelectric conversion device according to any one of configurations 1 to 24, characterized by the above. (Composition 26) The first-conductivity transistor provided on the first substrate and the second-conductivity transistor provided on the second substrate are electrically connected via a plurality of connection points arranged in parallel. A photoelectric conversion device according to any one of configurations 1 to 25, characterized by the above. (Composition 27) A photoelectric conversion device according to any one of configurations 1 to 26, A signal processing device that processes the signal output from the aforementioned photoelectric converter and A photoelectric conversion system characterized by having the following features. (Composition 28) It is a mobile object, A photoelectric conversion device according to any one of configurations 1 to 26, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned photoelectric converter, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features. (Composition 29) A photoelectric conversion device according to any one of configurations 1 to 26, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A mechanical device controlled based on information obtained from the aforementioned photoelectric converter, A display device for displaying information obtained by the aforementioned photoelectric converter, and A memory device for storing information obtained by the aforementioned photoelectric converter, and at least one of the following: A device characterized by being equipped with the following features. [Explanation of Symbols]

[0191] PDA, PDB... Photoelectric conversion element 10...Pixel area 12... pixels 20... Pixel vertical scanning circuit 30...Memory section 32... Pixel memory 40…Memory vertical scanning circuit 50... Signal Processing Unit 52... Signal processing circuits 90...control circuit 100... Photoelectric converter 110...First board 120...Second board 130... Third board

Claims

1. A pixel unit having a photoelectric conversion element and outputting a signal corresponding to the light incident on the photoelectric conversion element, It includes peripheral circuits for driving the pixel portion or processing signals output from the pixel portion, The peripheral circuit includes a circuit that includes a complementary connection between a first-conductivity transistor provided on the first substrate and a second-conductivity transistor provided on the second substrate. A photoelectric conversion device characterized by the following features.

2. The peripheral circuit includes a pixel driving circuit that drives the pixel section. The pixel driving circuit is configured with a circuit that includes a complementary connection between a first transistor of the first conductivity type provided on the first substrate and a second transistor of the second conductivity type provided on the second substrate. The photoelectric conversion device according to claim 1, characterized by the features described above.

3. The peripheral circuit further includes a first control circuit that controls the pixel driving circuit. The first control circuit is provided on the first substrate. The photoelectric conversion device according to claim 2.

4. The peripheral circuit further includes a first control circuit that controls the pixel driving circuit. The first control circuit is configured with a circuit that includes a complementary connection between a third transistor of the first conductivity type provided on the first substrate and a fourth transistor of the second conductivity type provided on the second substrate. The photoelectric conversion device according to claim 2.

5. The peripheral circuit further includes a first control circuit that controls the pixel driving circuit. The first control circuit is provided on the third substrate. The photoelectric conversion device according to claim 2.

6. The system further includes a memory unit that holds the signals output from the aforementioned pixel unit, The peripheral circuit is provided on the second substrate and further includes a memory drive circuit that drives the memory section. The photoelectric conversion device according to any one of claims 1 to 5.

7. The system further includes a memory unit that holds the signals output from the aforementioned pixel unit, The peripheral circuit further includes a memory drive circuit that drives the memory section. The memory drive circuit is configured with a circuit that includes a complementary connection between a fifth transistor of the first conductivity type provided on the first substrate and a sixth transistor of the second conductivity type provided on the second substrate. The photoelectric conversion device according to any one of claims 1 to 5.

8. The pixel section has a seventh transistor of the first conductivity type that constitutes a source follower circuit and outputs a signal corresponding to the output of the photoelectric conversion element. The memory unit includes a holding unit that holds signals output from the pixel unit, and an eighth transistor of the second conductivity type that constitutes a source follower circuit and outputs a signal corresponding to the output of the holding unit. The photoelectric conversion device according to claim 6.

9. The peripheral circuit further includes a second control circuit that controls the memory drive circuit. The second control circuit is provided on the second substrate. The photoelectric conversion device according to claim 6.

10. The peripheral circuit further includes a second control circuit that controls the memory drive circuit. The second control circuit is configured with a circuit that includes a complementary connection between the ninth transistor of the first conductivity type provided on the first substrate and the tenth transistor of the second conductivity type provided on the second substrate. The photoelectric conversion device according to claim 6.

11. The peripheral circuit further includes a second control circuit that controls the memory drive circuit. The second control circuit is provided on the third board. The photoelectric conversion device according to claim 6.

12. The memory unit is provided on the second substrate. The photoelectric conversion device according to claim 6.

13. The peripheral circuit is provided on the third substrate and further includes a signal processing circuit that processes signals output from the pixel section. The photoelectric conversion device according to any one of claims 1 to 5.

14. The peripheral circuit further includes a third control circuit that controls the signal processing circuit. The third control circuit is provided on the third substrate. The photoelectric conversion device according to claim 13, characterized in that it is a photoelectric conversion device.

15. The transistor provided on the first substrate is a transistor of the first conductivity type, The transistor provided on the second substrate is a transistor of the second conductivity type. The photoelectric conversion device according to any one of claims 1 to 5.

16. The transistor provided on the third substrate is the first conductivity type transistor. The photoelectric conversion device according to claim 5, characterized in that it is a photoelectric device.

17. Of the transistors constituting the peripheral circuit, the thickness of the gate insulating film of the transistors provided on the first substrate and the second substrate is thicker than the thickness of the gate insulating film of the transistor provided on the third substrate. The photoelectric conversion device according to claim 5, characterized in that it is a photoelectric device.

18. The pixel portion is provided on the first substrate. The photoelectric conversion device according to any one of claims 1 to 5.

19. The peripheral circuit further includes a signal processing circuit that processes the signal output from the pixel unit, The signal processing circuit includes a circuit that includes a complementary connection between the 11th transistor of the first conductivity type provided on the first substrate and the 12th transistor of the second conductivity type provided on the second substrate. The photoelectric conversion device according to claim 1, characterized by the features described above.

20. The peripheral circuit further includes a third control circuit that controls the signal processing circuit. The third control circuit is provided on the first substrate. The photoelectric conversion device according to claim 19, characterized in that it is a photoelectric conversion device.

21. The peripheral circuit further includes a third control circuit that controls the signal processing circuit. The third control circuit is configured with a circuit that includes a complementary connection between the 13th transistor of the first conductivity type provided on the first substrate and the 14th transistor of the second conductivity type provided on the second substrate. The photoelectric conversion device according to claim 19, characterized in that it is a photoelectric conversion device.

22. The aforementioned pixel portion is provided on the third substrate. The photoelectric conversion device according to any one of claims 19 to 21, characterized by the above.

23. The system further includes a memory unit that holds the signals output from the aforementioned pixel unit, The memory unit is provided on the second substrate. The photoelectric conversion device according to any one of claims 19 to 21, characterized by the above.

24. The system further includes a memory unit that holds the signals output from the aforementioned pixel unit, The pixel section and the memory section are provided on the first substrate. The photoelectric conversion device according to any one of claims 19 to 21, characterized by the above.

25. The pixel section has a plurality of pixels, each having the photoelectric conversion element. The photoelectric conversion device according to any one of claims 1 to 5.

26. The first-conductivity transistor provided on the first substrate and the second-conductivity transistor provided on the second substrate are electrically connected via a plurality of connection points arranged in parallel. The photoelectric conversion device according to any one of claims 1 to 5.

27. A photoelectric conversion device according to any one of claims 1 to 5, A signal processing device that processes the signal output from the aforementioned photoelectric converter and A photoelectric conversion system characterized by having the following features.

28. It is a mobile object, A photoelectric conversion device according to any one of claims 1 to 5, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned photoelectric converter, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features.

29. A photoelectric conversion device according to any one of claims 1 to 5, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A mechanical device controlled based on information obtained from the aforementioned photoelectric converter, A display device for displaying information obtained by the aforementioned photoelectric converter, and A memory device for storing information obtained by the aforementioned photoelectric converter, and at least one of the following: A device characterized by being equipped with the following features.

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