Systems, circuits, and methods for reducing transients during mode changes in multilevel converters

Abstract

The present disclosure relates to a system, circuit, and method for reducing transients during a mode change in a multilevel converter. In one embodiment, the multilevel converter is capable of operating in a charge pump mode with open-loop control and in a regulation mode with closed-loop control. A control circuit for controlling a pulse-width modulation (PWM) signal of the multilevel converter includes a compensation signal generation circuit configured to generate a compensation signal, and a PWM circuit configured to generate a PWM signal having a target duty cycle based on the compensation signal when the multilevel converter is operating in the charge pump mode. The PWM signal having the target duty cycle is used to control the multilevel converter during a mode change from the charge pump mode to the regulation mode.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 387,986, filed December 19, 2022, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to switched-capacitor multilevel buck converters, and more particularly to systems, circuits, and methods for reducing transients during mode changes in multilevel converters. [Background technology]

[0003] Many electronic products, particularly mobile computing and / or communications products and components (e.g., notebook computers, ultrabook computers, tablet devices, LCD and LED displays), require multiple voltage levels. For example, power amplifiers for radio frequency transmitters may require relatively high voltages (e.g., 12 volts (V) or higher), while logic circuits may require lower voltage levels (e.g., 1-2 V). Other circuits may require intermediate voltage levels (e.g., 5-10 V). Various configurations of switched-capacitor power conversion circuits, sometimes known as "charge pumps," provide voltage conversion (i.e., step-up, step-down, or bidirectional) between a high-voltage side and a low-voltage side by the controlled movement of charge between capacitors in the circuit. Summary of the Invention [Means for solving the problem]

[0004] Embodiments of the present disclosure may provide a system, circuit, and method for reducing transients during a mode change in a multilevel converter. In one embodiment, the multilevel converter is capable of operating in a charge pump mode with open-loop control and in a regulation mode with closed-loop control. A control circuit for controlling a pulse-width modulation (PWM) signal of the multilevel converter includes a compensation signal generation circuit configured to generate a compensation signal, and a PWM circuit configured to generate a PWM signal having a target duty cycle based on the compensation signal when the multilevel converter is operating in the charge pump mode. The PWM signal having the target duty cycle is used to control the multilevel converter during a mode change from the charge pump mode to the regulation mode.

[0005] In another embodiment, a method for controlling a multilevel converter includes determining a duty cycle of a pulse-width modulation (PWM) signal configured to control the multilevel converter. The method also includes determining whether the duty cycle of the PWM signal is decreasing, increasing, or unchanged, or whether the duty cycle of the PWM signal is less than a target duty cycle or greater than a target duty cycle. The method further includes increasing the duty cycle of the PWM signal by increasing a parameter in response to determining that the duty cycle of the PWM signal is decreasing or determining that the duty cycle of the PWM signal is less than the target duty cycle. The method also includes decreasing the duty cycle of the PWM signal by lowering a parameter in response to determining that the duty cycle of the PWM signal is increasing or determining that the duty cycle of the PWM signal is greater than the target duty cycle.

[0006] In another embodiment, a system for reducing transients during a power conversion mode change includes a multilevel converter configured to provide an output voltage signal by operating in a charge pump mode or a regulation mode. The system also includes a control circuit configured to control the multilevel converter to operate with a 50% duty cycle in the charge pump mode with open-loop control or to operate with a variable duty cycle in the regulation mode with closed-loop control, and to generate a pulse-width modulated (PWM) signal having a target duty cycle when the multilevel converter is operating in the charge pump mode. The PWM signal having the target duty cycle is used to control the multilevel converter during a mode change from the charge pump mode to the regulation mode.

[0007] In yet another embodiment, a system for reducing transients during mode changes in a switched-capacitor multilevel buck converter is disclosed. The system includes a switched-capacitor-based buck converter and a control circuit for controlling the switched-capacitor-based buck converter. The control circuit is capable of open-loop and closed-loop control of the switched-capacitor-based buck converter. During open-loop control, the control circuit is configured to use feedback from an output of the switched-capacitor-based buck converter to control the duty cycle of one or more control signals to the switched-capacitor-based buck converter to, for example, approximately 33.3% or 66.6%.

[0008] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram of an exemplary switched-capacitor multi-level buck converter, according to an embodiment of the disclosure. [Figure 2] FIG. 1 is a block diagram illustrating exemplary aspects of the operation of a switched-capacitor multilevel buck converter in open-loop mode, according to an embodiment of the disclosure. [Figure 3A] FIG. 1 is a block diagram illustrating exemplary aspects of operation of a closed-loop voltage-mode switched-capacitor multilevel buck converter, according to an embodiment of the disclosure. [Figure 3B] FIG. 1 is a circuit diagram illustrating an example aspect of a controller for a switched-capacitor multilevel buck converter operating in closed-loop voltage mode, according to an embodiment of the disclosure. [Figure 4A] FIG. 1 is a block diagram illustrating exemplary aspects of operation of a closed-loop current-mode switched-capacitor multilevel buck converter, according to an embodiment of the disclosure. [Figure 4B] FIG. 1 is a circuit diagram illustrating an example embodiment of a controller for a switched-capacitor multilevel buck converter operating in closed-loop current mode, according to an embodiment of the disclosure. [Figure 5A-5B] FIG. 1 is a block diagram illustrating an example aspect of changing operating modes in a switched-capacitor multilevel buck converter, according to an embodiment of the disclosure. [Figure 6] FIG. 1 is a state flow diagram illustrating exemplary aspects of control of a switched capacitor circuit multilevel buck converter, according to an embodiment of the disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] The following disclosure provides many different exemplary embodiments or examples for implementing various features of the presented subject matter. Brief specific examples of components and configurations are described below to illustrate the disclosure. It should be understood that these are merely examples and are not intended to be limiting. Furthermore, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations described.

[0011] Many electronic products, particularly mobile computing and / or communication products and components (e.g., notebook computers, ultrabook computers, tablet devices, LCD and LED displays), require multiple voltage levels. For example, power amplifiers for radio frequency transmitters may require relatively high voltages (e.g., 12 volts (V) or higher), while logic circuits may require lower voltage levels (e.g., 1-2 V). Other circuits may require intermediate voltage levels (e.g., 5-10 V). Power conversion is often used to generate lower or higher voltages from a common power source, such as a battery, to meet the power requirements of various components in electronic products.

[0012] FIG. 1 is a circuit diagram 100 of an exemplary switched capacitor multilevel step-down converter circuit, according to embodiments of the disclosure. Various embodiments of the switched capacitor power converter circuit convert a high voltage side (e.g., input voltage V) to a low voltage side (e.g., input voltage V) by controlled transfer of charge between flying capacitors (e.g., 103a and 103b) in the circuit. IN 101) and the low-voltage side (for example, the output voltage V OUTThe multilevel step-down converter circuit 100 provides voltage conversion (e.g., step-down conversion) between the flying capacitors 103a and 103b and the switching element 104. The charge pump steps down the input voltage by storing a portion of the input voltage in each flying capacitor (e.g., 103a and 103b). Switches (e.g., 102a-102f) connected across each flying capacitor are typically used to implement charge transfer and configure the charge pump to provide the desired voltage conversion ratio. Controlling the charge transfer between the flying capacitors 103a and 103b typically utilizes circuit elements (e.g., diodes or FET transistors) acting as "switches." The switched-capacitor multilevel step-down converter circuit 100 may include an inductor 104, which configures the circuit 100 to operate as a buck converter. It will be appreciated that the principles of the present disclosure are applicable to any other type of step-down DC-DC converter (e.g., boost, buck-boost, or Cuk converter). Finally, the switched capacitor multilevel step-down converter circuit 100 may include a controller 105 that controls the operation of the switches 102a-102f. For example, the controller 105 may provide control signals (e.g., IN1, IN2, and IN3) that control the opening and closing timing of the switches 102a-102f to control charge transfer between the flying capacitors 103a and 103b. This allows the controller 105 to control the output voltage V OUT 108 and voltage step-down conversion ratio (V OUT 108 / V IN 101) can be controlled.

[0013] 2 is a block diagram 200 illustrating an example aspect of the operation of a switched-capacitor multilevel buck converter in open-loop mode, according to disclosed embodiments. In various embodiments, the controller 105 of the switched-capacitor multilevel buck converter 100 may operate in open-loop mode (sometimes referred to as a "charge pump" mode) or closed-loop mode (sometimes referred to as a "regulation" mode). For example, in open-loop mode, the controller 105 regulates the output voltage V OUTAlternatively, the controller 105 may determine the timing of opening and closing the switches 102a-102f to control the charge transfer between the flying capacitors 103a and 103b without using feedback from 108. Alternatively, the controller 105 may provide control signals IN1, IN2, and IN3 that open and close the switches 102a-102f with a fixed duty cycle (on-off ratio), such as 33.3% or 66.6% (see, e.g., element 210 in FIG. 2). For example, with reference to the four-level buck converter shown in FIG. 1, the control signals IN1, IN2, and IN3 may each have a 33.3% duty cycle (on) (120° out of phase with each other) and a duty cycle of 1 / 3×V IN 101 output voltage V OUT 108, or by giving each a 33.3% duty cycle (off) (i.e., a 66.6% duty cycle (on)) (120° out of phase with each other) and obtaining 2 / 3 × V IN 101 output voltage V OUT In such a scenario, the voltage V 108 shown in FIG. LX will have a 50% duty cycle and the switch state transitions will represent a 50% duty cycle. Those skilled in the art will understand how to set the duty cycle and phase of the control signals for the N-level converter to achieve each of the N levels in open-loop mode.

[0014] Referring to FIG. 1, in some embodiments of the switched capacitor multilevel step-down converter circuit 100, when the controller 105 provides fixed duty cycle control signals IN1, IN2, and IN3, the voltages V of the flying capacitors 103a and 103b, respectively, during operation are: C1 and V C2 are approximately 1 / 3 × V IN 101 and 2 / 3 x V IN 101, capacitors 103a and 103b and output capacitor C OUT 106 may be sized.

[0015] Furthermore, in open loop mode, the controller 105 regulates the output voltage V OUT 108 is about 1 / 3 x V IN 101 or 2 / 3 x V IN 2, the phases of the control signals IN1, IN2, and IN3 may be controlled so that the phases of the control signals IN1, IN2, and IN3 are equal to 101. For example, as shown in table 220 of FIG. IN 101 output voltage V OUT 108 (output voltage 0V, 1 / 3 × V IN 101, 2 / 3 x V IN 101 and V IN To implement level 2) of the four-level converter 101, the controller 105 in open-loop mode may close one of the switches 102a, 102b, and 102c (i.e., the switch connected to one terminal of the flying capacitors 103a and 103b) at a time while simultaneously opening the corresponding switch 102d, 102e, or 102f (i.e., the switch connected to the other terminal of the flying capacitors 103a and 103b).

[0016] As an example, the controller 105 may set IN1 and IN2 low (logic "0") while setting IN3 high (logic "1"). When the controller sets this {IN1 IN2 IN3} to the code {0 0 1}, the switch 102a is closed while the switches 102b and 102c are open. At the other terminals of the flying capacitors 103a and 103b, the switch 102f is open while the switches 102d and 102e are closed. In this configuration, the output voltage V OUT 108 is approximately 1 / 3 x V IN 101 (i.e., a conversion rate of 1 / 3 (level 2)).

[0017] Similarly, the controller 105 may set IN1 and IN3 low (logic "0") while setting IN2 high (logic "1"). If the controller sets this {IN1 IN2 IN3} to the code {0 1 0}, then switch 102b is closed while switches 102a and 102c are open. At the other terminals of the flying capacitors 103a and 103b, switch 102e is open while switches 102d and 102f are closed. In this configuration, the output voltage V OUT 108 is approximately 1 / 3 x V IN 101 (i.e., a conversion rate of 1 / 3 (level 2)).

[0018] Similarly, the controller 105 may set IN2 and IN3 low (logic "0") while setting IN1 high (logic "1"). If the controller sets this {IN1 IN2 IN3} to the code {1 0 0}, then switch 102c is closed while switches 102a and 102b are open. At the other terminals of flying capacitors 103a and 103b, switch 102d is open while switches 102e and 102f are closed. In this configuration, the output voltage V OUT 108 is approximately 1 / 3 x V IN 101 (i.e., a 1 / 3 (Level 2) conversion ratio). In some embodiments, the controller 105 sequentially cycles through the Level 2 codes {0 0 1}, {0 1 0}, and {1 0 0}, each with a 33% duty cycle, to achieve approximately 1 / 3×V IN 101 output voltage V OUT 108 (i.e., a conversion rate of 1 / 3 (level 2)) can be achieved.

[0019] Furthermore, in open loop mode, the controller 105 regulates the output voltage V OUT 108 is about 2 / 3 x V IN 2, the phases of the control signals IN1, IN2, and IN3 may be controlled so that the phases of the control signals IN1, IN2, and IN3 are equal to 101. For example, as shown in the table 230 of FIG. IN 101 output voltage VOUT 108 (output voltage 0V, 1 / 3 × V IN 101, 2 / 3 x V IN 101 and V IN To achieve level 3 of the four-level converter of 101, the controller 105 in open-loop mode may close two of the switches 102a, 102b, and 102c (i.e., the switches connected to one terminal of the flying capacitors 103a and 103b) at a time while simultaneously opening two corresponding switches 102d, 102e, or 102f (i.e., the switches connected to the other terminal of the flying capacitors 103a and 103b).

[0020] As an example, the controller 105 may set IN1 low (logic "0") while setting IN2 and IN3 high (logic "1"). When the controller sets this {IN1 IN2 IN3} to the code {0 1 1}, the switch 102c is opened while the switches 102a and 102b are closed. At the other terminals of the flying capacitors 103a and 103b, the switch 102d is closed while the switches 102e and 102f are opened. In this configuration, the output voltage V OUT 108 is approximately 2 / 3 x V IN 101 (i.e., a conversion rate of 2 / 3 (level 3)).

[0021] Similarly, the controller 105 may set IN2 low (logic "0") while setting IN1 and IN3 high (logic "1"). If the controller sets this {IN1 IN2 IN3} to the code {1 0 1}, then switch 102b is opened while switches 102a and 102c are closed. At the other terminals of the flying capacitors 103a and 103b, switch 102e is closed while switches 102d and 102f are open. In this configuration, the output voltage V OUT 108 is approximately 2 / 3 x V IN 101 (i.e., a conversion rate of 2 / 3 (level 3)).

[0022] Similarly, the controller 105 may set IN3 low (logic "0") while setting IN1 and IN2 high (logic "1"). If the controller sets this {IN1 IN2 IN3} to the code {1 1 0}, then switch 102a is opened while switches 102b and 102c are closed. At the other terminals of flying capacitors 103a and 103b, switch 102f is closed while switches 102d and 102e are open. In this configuration, the output voltage V OUT 108 is approximately 2 / 3 x V IN 101 (i.e., a 2 / 3 (Level 3) conversion ratio). In some embodiments, the controller 105 may generate approximately 2 / 3×V by sequentially cycling through the Level 3 codes {0 1 1}, {1 0 1}, and {1 1 0}, each with a 33% duty cycle (off) (i.e., a 66.6% duty cycle (on)). IN 101 output voltage V OUT 108 (i.e., a conversion rate of 2 / 3 (level 3)) can be achieved.

[0023] 3A is a block diagram illustrating an example aspect of the operation of a switched-capacitor multilevel buck converter in a closed-loop voltage mode, according to embodiments of the disclosure. In various embodiments, the controller 105 of the switched-capacitor multilevel buck converter 100 can operate in an open-loop mode (sometimes referred to as a "charge pump" mode) or a closed-loop mode (sometimes referred to as a "regulation" mode). For example, in the closed-loop mode, the controller 105 regulates the output voltage V OUT 108 may be used to determine when to open and close switches 102a-102f to control charge transfer between flying capacitors 103a and 103b. Thus, in some embodiments, controller 105 may provide variable duty cycle (on-off ratio) control signals IN1, IN2, and IN3 that open and close switches 102a-102f to maintain a constant output voltage V OUT 108 may be maintained.

[0024] 3A, in some embodiments of the switched-capacitor multilevel step-down converter circuit 100, the controller 105 operating in a closed-loop voltage mode may use pulse-width modulation techniques to vary the duty cycle of the control signals IN1, IN2, and IN3 that open and close the switches 102a-102f. For example, as shown in FIG. 3A (see, e.g., element 310), the controller 105 may control the output voltage V, which is maintained at a constant voltage, by comparing a voltage sawtooth waveform 306 to a COMP signal (representing a target output voltage). OUT 108. When operating in such a closed-loop voltage mode, the switched capacitor multilevel step-down converter circuit 100 operates between approximately 0 V and approximately V IN Output voltage V ranges between 101 and OUT Generates 108.

[0025] 3B is a circuit diagram 300 illustrating an example embodiment of a controller for a switched-capacitor multilevel buck converter operating in closed-loop voltage mode, according to an embodiment of the disclosure. In some embodiments, the controller 105 operating in closed-loop voltage mode controls the output voltage V to be maintained at a constant voltage. OUT The system may include a comparator 305 (i.e., a PWM circuit) that modulates the width of a generated pulse (e.g., a PWM signal) provided to a logic-to-PWM-to-level converter 340, which may provide a control signal to generate 108. Comparator 305 may compare a voltage sawtooth waveform 306 against a COMP signal, which modulates the width of the generated pulse. The COMP signal may be manipulated / controlled using several techniques, as discussed in more detail below.

[0026] 4A is a block diagram illustrating an example aspect of the operation of a switched-capacitor multilevel buck converter in a closed-loop current mode, according to embodiments of the disclosure. As noted above, in various embodiments, the controller 105 of the switched-capacitor multilevel buck converter 100 can operate in an open-loop mode (sometimes referred to as a "charge pump" mode) or a closed-loop mode (sometimes referred to as a "regulation" mode). For example, in the closed-loop mode, the controller 105 controls the output voltage V OUT 108 may be used to determine when to open and close switches 102a-102f to control charge transfer between flying capacitors 103a and 103b. Thus, in some embodiments, controller 105 may provide variable duty cycle (on-off ratio) control signals IN1, IN2, and IN3 that open and close switches 102a-102f to maintain a constant output voltage V OUT 108 may be maintained.

[0027] 4A, in some embodiments of the switched-capacitor multilevel step-down converter circuit 100, the controller 105 operating in a closed-loop current mode may use pulse-width modulation techniques to vary the duty cycle of the control signals IN1, IN2, and IN3 that open and close the switches 102a-102f. For example, as shown in FIG. 4A (see, e.g., element 410), the controller 105 may modulate the current I representing the inductor 104 with respect to the COMP signal. L By comparing the sawtooth waveform 406 of OUT 108. When operating in such a closed-loop current mode, the switched capacitor multilevel step-down converter circuit 100 operates between approximately 0 V and approximately V IN Output voltage V ranges between 101 and OUT Generates 108.

[0028] 4B is a circuit diagram 400 illustrating an example embodiment of a controller for a switched-capacitor multilevel buck converter operating in closed-loop current mode, according to an embodiment of the disclosure. In some embodiments, the controller 105 operating in closed-loop current mode provides a constant output voltage V OUT 108. The comparator 405 may include a comparator 405 (i.e., a PWM modulator) that modulates the width of the generated pulse (e.g., a PWM signal) provided to a logic-to-PWM-to-level converter 440, which may provide a control signal to generate the current I. The comparator 405 may be configured to modulate the width of the generated pulse by a COMP signal. L The COMP signal may be controlled using several techniques, as discussed in more detail below.

[0029] As described above with reference to FIGS. 2, 3A, 3B, 4A, and 4B, in a switched capacitor multilevel buck converter, the input voltage V IN 101 controls the output voltage V OUT 108 to a desired level, or by using a "charge pump" mode in an open loop. Depending on the specifics of the application, it may be desirable to operate the switched capacitor multilevel buck converter sometimes in "charge pump" mode, sometimes in "regulation" mode, and sometimes to transition between the two operating modes. However, the inventors note here that transitioning from one operating mode to another (e.g., from "charge pump" mode to "regulation" mode) may affect the output voltage V OUT 108, which can take an undesirably long time to recover depending on the system bandwidth, and the output voltage V OUT It was recognized that an overvoltage fault could occur on the 108.

[0030] In particular, with reference to FIG. 2, the controller 105, operating in an open-loop “charge pump” mode, generates an output voltage VOUT 108 to determine the timing of opening and closing switches 102a-102f to control charge transfer between flying capacitors 103a and 103b. Thus, controller 105 operating in “charge pump” mode may vary the duty cycle of control signals IN1, IN2, and IN3 that open and close switches 102a-102f without using any pulse-width modulation techniques, such as those shown in FIGS. 3A, 3B, 4A, and 4B. Nevertheless, rapid transition of controller 105 from “charge pump” mode to “regulation” mode (closed-loop current or voltage mode) may require the pulse-width modulation circuitry to be operational even when not being used in open-loop “charge pump” mode. Thus, in some embodiments, the pulse-width modulation circuitry may continue to operate to vary the duty cycle of control signals IN1, IN2, and IN3, even when not being used in open-loop “charge pump” mode.

[0031] When operating in this open loop "charge pump" mode, the pulse width modulation circuitry may undesirably modulate the width of the generated pulses by preconditioning the COMP signal to provide an extreme value. This is because when operating in open loop "charge pump" mode, the output voltage V OUT 108 may decrease with increasing load current. For example, for the pulse width modulation circuit shown in FIG. 3B, OUT A drop of 108 will result in a reduced output voltage V OUT 108 and the reference voltage V REF By comparing with 301, the output voltage V OUTTransconductance amplifier Gm303 may output a COMP signal that compensates for the drop in output voltage V108. For example, Gm303 may output a current signal proportional to the difference in input voltages, which may be converted to a voltage signal through the use of an output resistor and capacitor. However, because controller 105 is operating in an open-loop "charge pump" mode, the COMP signal is not used to vary the duty cycle of control signals IN1, IN2, and IN3 (see FIG. 1), and the COMP signal is not used to vary the duty cycle of the reduced output voltage V108. OUT Despite trying to compensate for 108, the output voltage V OUT 108 may remain low. This may cause the COMP signal to be relatively high in open loop "charge pump" mode. Similarly, for example, with respect to the pulse width modulation circuit shown in FIG. 4B, such an output voltage V OUT A drop of 108 will result in a reduced output voltage V OUT 108 and the reference voltage V REF By comparing with 401, the output voltage V OUT Transconductance amplifier Gm403 may output a COMP signal that compensates for the drop in output voltage V108. For example, Gm403 may output a current signal proportional to the difference in input voltages, which may be converted to a voltage signal through the use of an output resistor and capacitor. However, because controller 105 is operating in an open-loop "charge pump" mode, the COMP signal is not used to vary the duty cycle of control signals IN1, IN2, and IN3 (see FIG. 1), and the COMP signal is not used to vary the duty cycle of the reduced output voltage V108. OUT Despite trying to compensate for 108, the output voltage V OUT 108 may remain low, which may cause the COMP signal to go relatively high in open loop "charge pump" mode.

[0032] Because the COMP signal is compensated to the maximum extent possible during open-loop "charge pump" mode operation (e.g., the COMP signal is relatively high), the effect of operating the pulse width modulation circuit even when not being used in open-loop "charge pump" mode is to bias or pre-condition the pulse width modulation circuit to set a high duty cycle value for the control signals IN1, IN2, and IN3 when the switched capacitor multilevel buck converter transitions from "charge pump" mode to "regulation" mode. In various embodiments, this regulation may be to bias or pre-condition the pulse width modulation circuit to set a high duty cycle state in "regulation" closed-loop voltage mode control, or a high current state in "regulation" closed-loop peak or average current mode control when transitioning from open-loop "charge pump" mode. This biasing or pre-conditioning may increase the output voltage V OUT 108, which can take an undesirably long time to recover depending on the system bandwidth, and the output voltage V OUT An overvoltage fault may occur on 108.

[0033] Embodiments of the present disclosure can reduce and / or prevent the pulse width modulation circuit from driving the COMP signal to extreme or undesirable levels during open-loop "charge pump" mode operation. For example, during open-loop "charge pump" mode operation, controller 105 may set the COMP voltage near the voltage required for the switched-capacitor multilevel buck converter to transition from "charge pump" mode to "regulation" mode. For example, when transitioning from "charge pump" mode to "regulation" closed-loop voltage mode, controller 105 may set V LX The COMP voltage may be set so that the signal has a duty cycle of approximately 50%. As another example, when transitioning from a "charge pump" mode to a "regulated" closed-loop peak or average current mode, the controller 105 may LXThe COMP voltage may be set so that the duty cycle of the signal is less than about 50% (eg, preferably so that the linear range of COMP voltage versus duty cycle and slope compensation is less than 1).

[0034] 3B and 4B, to achieve the desired COMP voltage, the controller 105 controls the feedback voltage V at node FB of Gm303 / 403. FB is the reference voltage V REF A digitally controlled potentiometer (DCP) 302 / 402 (i.e., an adjustable resistor whose resistance is controlled by a digital code (e.g., a bit string)) may be used to adjust the resistance of a feedback resistance divider to be at or near 301 / 401 or to achieve the desired target COMP voltage. As the desired target COMP is approached, adjacent DCP codes are generated to maintain the desired target COMP voltage and duty cycle (e.g., 33.3%). Such a scheme may be advantageously employed in exemplary embodiments using a field programmable gate array. Alternatively, the controller 105 may adjust the reference voltage V 302 / 402 to achieve the desired target COMP voltage. REF In some alternatives, the digitally controlled VR EF The 301 / 401 can output voltage V without using a resistor divider. OUT 108. Such an approach may be advantageously employed in exemplary integrated circuit embodiments.

[0035] In yet another alternative, the controller 105 may include an analog circuit 307 / 407 that compares the target COMP voltage 308 / 408 with the current COMP signal and adjusts the current COMP signal to the desired target level. In some embodiments, the analog circuit 307 / 407 may be connected to the COMP terminal, for example, by closing switch 309 / 409, while the other components of the pulse width modulation circuit may be isolated, for example, by opening switch 304 / 404. For example, when transitioning from the "charge pump" mode to the "regulate" closed-loop voltage mode, the controller 105 may set the COMP voltage to the midpoint of the voltage sawtooth waveform 306. Similarly, when transitioning from the "charge pump" mode to the "regulate" closed-loop current mode, the controller 105 may measure the load current and accordingly determine the target COMP voltage, which may then be provided as the target COMP 408. It will be appreciated that during open-loop "charge pump" mode operation, any combination of the above techniques may be used to achieve the desired target COMP voltage.

[0036] 5A and 5B are block diagrams 500 illustrating an example aspect of changing operating modes in a switched capacitor multilevel buck converter, according to embodiments of the disclosure. Referring to FIG. 5A, in some embodiments, the controller 105 of the exemplary four-level switched capacitor buck converter 100 can operate in an open-loop "charge pump" mode or a closed-loop (voltage or current controlled) "regulation" mode. As shown in FIG. 5A, the four-level switched capacitor buck converter 100 operates in an open-loop "charge pump" mode or a closed-loop (voltage or current controlled) "regulation" mode. IN 101 and uses open-loop "charge pump" mode to provide four fixed output voltages V OUT 108 (e.g., 0 (level 1), 1 / 3 x V IN 101 (Level 2), 2 / 3 x V IN 101 (Level 3) and V IN 101 (Level 4)). In particular, a Level 2 or Level 3 output voltage V OUT108, the switched capacitor step-down converter circuit 100 may be operating in open-loop (OL) "charge pump" mode by using a fixed duty cycle of 33.3% or 66.6% for the control signals IN1, IN2, and IN3. As discussed above with reference to FIG. 2, in some embodiments, the controller 105 may generate approximately 1 / 3×V by sequentially cycling through the Level 2 codes {0 0 1}, {0 1 0}, and {1 0 0}. IN 101 output voltage V OUT 108 (i.e., a 1 / 3 (Level 2) conversion ratio). Similarly, in some embodiments, the controller 105 may achieve approximately 2 / 3×V by sequentially cycling through the Level 3 codes {0 1 1}, {1 0 1}, and {1 1 0}. IN 101 output voltage V OUT 108 (i.e., a conversion rate of 2 / 3 (level 3)) can be achieved.

[0037] Additionally, as shown in FIG. 5A, the switched capacitor step-down converter circuit 100 uses a closed-loop (voltage or current controlled) “regulation” mode to produce a variable output voltage V between fixed levels. OUT 108. For example, 0 (level 1) and 1 / 3 x V IN Between levels 101 (level 1) and 102 (level 2), the switched capacitor step-down converter circuit 100 operates in a closed loop "regulation" mode by using variable duty cycles (min-max) for the control signals IN1, IN2, and IN3 to provide a voltage between 0 and 1 / 3 × V. IN Output voltage V between 101-Δ OUT 108 may be continuously controlled, where Δ is the OUT 108 voltage boundary zone window. Similarly, 1 / 3 × V IN 101 (Level 2) and 2 / 3 x V IN Between levels 101 (level 3), the switched capacitor step-down converter circuit 100 operates in a closed loop "regulation" mode by using variable duty cycles (min-max) for the control signals IN1, IN2, and IN3, resulting in a 1 / 3 x VIN 101+Δ and 1 / 3×V IN Output voltage V between 101-Δ OUT 108 may be continuously controlled, where Δ is the OUT 108 voltage boundary zone window. In addition, 2 / 3 × V IN 101 (Level 3) and V IN Between levels 101 (level 4), the switched capacitor step-down converter circuit 100 operates in a closed loop "regulation" mode by using variable duty cycles (min-max) for the control signals IN1, IN2, and IN3, resulting in a 2 / 3×V IN 101+Δ and V IN Output voltage V between 101 OUT 108 may be controlled continuously.

[0038] Referring to FIG. 5B, level 2 (1 / 3×V IN 101) or Level 3 (2 / 3 x V IN During open-loop "charge pump" mode operation at 101, the controller 105 may set the COMP voltage near the voltage required for the switched capacitor multilevel buck converter to transition from "charge pump" mode to "regulation" mode. For example, around level 2 (1 / 3 x V IN 101±Δ) or around level 3 (2 / 3×V IN 101±Δ) from the “charge pump” mode to the “regulation” closed-loop voltage mode, the controller 105 adjusts the duty cycle of the switch state transition (e.g., V LX The COMP voltage may be set so that the duty cycle of the signal is about 50% (e.g., 50% ±Σ, where Σ is the boundary zone window of the equivalent duty cycle). As another example, the COMP voltage may be set to about level 2 (1 / 3 × V IN 101±Δ) or around level 3 (2 / 3×V IN 101±Δ) from “charge pump” mode to “regulation” closed loop peak or average current mode, the controller 105 LXThe COMP voltage may be set so that the duty cycle of the signal is less than about 50% (e.g., 50%-Σ, where Σ is the border zone window of the equivalent duty cycle) (e.g., preferably so that the linear range of COMP voltage versus duty cycle and slope compensation is less than 1).

[0039] As explained above with reference to FIGS. 3B and 4B, to achieve the desired COMP voltage, the controller 105 regulates the feedback voltage V at node FB of Gm303 / 403. FB is the reference voltage V REF A digitally controlled potentiometer DCP 302 / 402 may be used to adjust the resistance of the feedback resistor divider to be at or near 301 / 401 or to achieve the desired target COMP voltage. As the desired target COMP is approached, adjacent DCP codes are switched to adjust the desired target COMP voltage and V LX The duty cycle of the signal (e.g., 50%) can be maintained. Such a scheme can be conveniently employed in exemplary embodiments by using a field programmable gate array. Alternatively, a digitally controlled VR EF It is also possible to use the 301 / 401 with a fixed resistor divider. Another alternative is to use a digitally controlled VR EF The 301 / 401 can output voltage V without using a resistor divider. OUT 108. Such an approach may be advantageously employed in exemplary integrated circuit embodiments.

[0040] FIG. 6 shows the DCP code selection for DCP302 / 402 to control the resistance of the feedback resistor divider to achieve the desired target COMP voltage (or V to control the output of transconductance amplifier Gm303 / 403). REF6 is a state flow diagram 600 illustrating an exemplary embodiment of a digital selection of 301 / 401. In state 602, the "charge pump" mode may not be active (see 610), and therefore, no DCP code control may be performed. When the "charge pump" mode is activated, the duty cycle resulting from pulse width modulation (PWM DC) may be measured (see 620) (e.g., twice to detect PWM DC activity). The adjusted PWM DC may be measured by oversampling the PWM signal, with options for averaging over 1, 2, 4, 8, or N PWM cycles, where N is an integer (odd or even). For example, the PWM signal may be measured by oversampling 2, 4, 8, or N PWM cycles, where N is an integer (odd or even). For example, in one FPGA implementation, the PWM signal may be divided by a right shift operation to perform a division operation for averaging. k This can be advantageously averaged over the cycle.

[0041] The state of the controller 105 may then transition to state 604 where the PWM DC is unchanged (see 630). LXTo achieve the signal duty cycle (e.g., 50%), the controller 105 may determine whether the PWM DC should be decreased or increased. If the PWM DC is decreasing or is less than the target PWM DC (taking into account any hysteresis in the measurement results) (see 632), the state of the controller 105 may transition to state 608, where the controller 105 increases the PWM DC by incrementing the DCP code. If the PWM DC is decreasing or is not moving below the target PWM DC, the controller 105 may increment the DCP code (see 637). If the PWM DC is increasing or is greater than the target PWM DC (taking into account any hysteresis in the measurement results) (see 634), the controller 105 may transition to state 606, where the controller 105 decreases the PWM DC by decrementing the DCP code. The controller 105 may also decrement the DCP code if the PWM DC is increasing or not moving above the target PWM DC (see 639). The controller 105 may also transition between states 606 and 608 depending on whether the PWM DC is greater than the target PWM DC (taking into account any hysteresis in the measurement results) (see 636) or whether the PWM DC is less than the target PWM DC (taking into account any hysteresis in the measurement results) (see 638). As the desired target COMP is approached, the controller 105 switches between adjacent DCP codes to switch the state of the controller 105 between states 606 and 608, thereby increasing the desired target COMP voltage and V. LX The duty cycle of the signal (eg, 50%) can be maintained.

[0042] The above embodiments can be further described using the following clauses. 1. A control circuit for controlling a pulse width modulation (PWM) signal of a multilevel converter capable of operating in a charge pump mode with open-loop control and in a regulation mode with closed-loop control, comprising: a compensation signal generation circuit configured to generate a compensation signal; a PWM circuit configured to generate a PWM signal having a target duty cycle based on the compensation signal when the multi-level converter is operating in a charge pump mode, the PWM signal having the target duty cycle being used to control the multi-level converter in a mode change from the charge pump mode to a regulation mode; A control circuit comprising: 2. The compensation signal generating circuit a resistive voltage divider circuit configured to receive an output voltage signal from the multi-level converter, receive a digital code, and divide the output voltage signal to obtain a feedback signal having a voltage based on the digital code; a transconductance amplifier having a first input for receiving a reference voltage signal and a second input for receiving a feedback signal from the resistor divider circuit, the transconductance amplifier configured to generate a compensation signal based on the feedback signal; 2. The control circuit of claim 1, comprising: 3. The compensation signal generating circuit a resistor divider circuit configured to receive an output voltage signal from the multi-level converter and to divide the output voltage signal to obtain a feedback signal; a transconductance amplifier having a first input for receiving the adjustable voltage signal and a second input for receiving the feedback signal, the transconductance amplifier configured to generate a compensation signal based on the adjustable voltage signal; 2. The control circuit of claim 1, comprising: 4. The control circuit of clause 1, wherein the compensation signal generation circuit comprises an analog circuit that provides a compensation signal at a target voltage, the analog circuit having a first input that receives the target voltage signal and a second input that receives a loopback signal from the output of the analog circuit, and configured to generate the compensation signal based on the target voltage signal. 5. A control circuit described in any one of clauses 1 to 4, wherein when the multilevel converter is operating in voltage regulation mode, the PWM circuit is configured to generate a PWM signal having a target duty cycle based on the sawtooth signal and the compensation signal. 6. A control circuit according to any one of clauses 1 to 4, wherein when the multilevel converter is operating in current regulation mode, the PWM circuit is configured to generate a PWM signal having a target duty cycle with slope compensation based on the triangular signal and the compensation signal. 7. Receiving a PWM signal from a PWM circuit; Based on the PWM signal, operating in a charge pump mode with open loop control to provide an output voltage signal at one of a plurality of voltage levels; operating in a regulation mode with closed loop control to provide a variable voltage output voltage signal; generating a plurality of level control signals for controlling the multi-level converter to perform the above; 7. The control circuit of any one of clauses 1 to 6, further comprising a voltage level control circuit configured to: 8. The multilevel converter operates in charge pump mode with a 50% duty cycle to provide an output voltage signal; or 8. The control circuit of clause 7, wherein the multi-level converter operates in a regulation mode with an adjustable duty cycle to provide the output voltage signal. 9. The control circuit of clause 7, wherein the voltage level control circuit is configured to generate a plurality of level control signals having a fixed duty cycle to control the multi-level converter in a charge pump mode to provide an output voltage signal of one of a plurality of voltage levels, and a first level control signal of the level control signals is phase shifted from a second level control signal of the level control signals. 10. The control circuit of clause 7, wherein the voltage level control circuit is configured to generate a plurality of level control signals to control the multilevel converter in a regulation mode to provide an output voltage signal having a variable voltage between a first voltage level of the plurality of voltage levels minus a voltage boundary zone window value and the first voltage level plus the voltage boundary zone window value. 11. The control circuit of clause 10, wherein the multilevel converter operates at a duty cycle between 50% minus a duty cycle boundary zone window value and 50% plus a duty cycle boundary zone window value. 12. A method for controlling a multilevel converter, comprising: determining a duty cycle of a pulse width modulation (PWM) signal configured to control the multi-level converter; determining whether the duty cycle of the PWM signal is decreasing, increasing, or unchanged, or whether the duty cycle of the PWM signal is less than or greater than a target duty cycle; In response to determining that the duty cycle of the PWM signal is decreasing or that the duty cycle of the PWM signal is less than a target duty cycle, increasing the parameter; In response to determining that the duty cycle of the PWM signal is increasing or that the duty cycle of the PWM signal is greater than a target duty cycle, decreasing the duty cycle of the PWM signal by lowering the parameter; A method comprising: 13. The step of determining the duty cycle of the PWM signal comprises: measuring the PWM signal to obtain a first duty cycle at a first time and a second duty cycle at a second time, the first and second times being times when the multi-level converter is in a charge pump mode; determining a duty cycle of the PWM signal based on the first duty cycle and the second duty cycle; 13. The method of claim 12, comprising: 14. The step of determining whether the duty cycle of the PWM signal is less than the target duty cycle includes determining whether the duty cycle of the PWM signal is less than the target duty cycle minus a hysteresis value; 14. The method of claim 12 or 13, wherein determining whether the duty cycle of the PWM signal is greater than a target duty cycle comprises determining whether the duty cycle of the PWM signal is greater than the target duty cycle plus a hysteresis value. 15. The duty cycle of the PWM signal is a first duty cycle of the PWM signal, and the method comprises: After determining whether the first duty cycle of the PWM signal is decreasing, increasing, or unchanged, or whether the first duty cycle of the PWM signal is less than or greater than the target duty cycle, determining a second duty cycle of the PWM signal; determining at least one of whether a second duty cycle of the PWM signal is decreasing, increasing, or stationary, or whether the second duty cycle of the PWM signal is less than a target duty cycle or greater than a target duty cycle; In response to determining that the second duty cycle of the PWM signal is decreasing or that the second duty cycle of the PWM signal is less than the target duty cycle, increasing the parameter to increase the duty cycle of the PWM signal; In response to determining that the second duty cycle of the PWM signal is increasing or that the second duty cycle of the PWM signal is greater than the target duty cycle, decreasing the duty cycle of the PWM signal by lowering the parameter; 13. The method of clause 12, further comprising: 16. The method of any of clauses 12 to 15, wherein the target duty cycle is 50%. 17. A system for reducing transients during a change of power conversion mode, comprising: a multi-level converter configured to operate in a charge pump mode or a regulation mode to provide an output voltage signal; controlling the multilevel converter to operate at a 50% duty cycle in a charge pump mode with open loop control or to operate at a variable duty cycle in a regulation mode with closed loop control; generating a pulse width modulation (PWM) signal having a target duty cycle when the multi-level converter is operating in a charge pump mode, the PWM signal having the target duty cycle being used to control the multi-level converter in a mode change from the charge pump mode to a regulation mode; a control circuit configured to: A system comprising: 18. A control circuit a compensation signal generation circuit configured to generate a compensation signal for generating the PWM signal; a PWM circuit configured to generate a PWM signal having a target duty cycle based on the compensation signal; The system according to clause 17, comprising 19. A compensation signal generating circuit a resistive voltage divider circuit configured to receive an output voltage signal from the multi-level converter, receive a digital code, and divide the output voltage signal to obtain a feedback signal having a voltage based on the digital code; a transconductance amplifier having a first input for receiving a reference voltage signal and a second input for receiving a feedback signal from the resistor divider circuit, the transconductance amplifier configured to generate a compensation signal based on the feedback signal; 19. The system of claim 18, comprising: 20. A compensation signal generating circuit a resistor divider circuit configured to receive an output voltage signal from the multi-level converter and to divide the output voltage signal to obtain a feedback signal; a transconductance amplifier having a first input for receiving the adjustable voltage signal and a second input for receiving the feedback signal, the transconductance amplifier configured to generate a compensation signal based on the adjustable voltage signal; 19. The system of claim 18, comprising: 21. A system for reducing transients during mode changes in a switched-capacitor multilevel converter, comprising: A switched-capacitor based converter; a control circuit for controlling the switched capacitor based converter, the control circuit being capable of open-loop and closed-loop control of the switched capacitor based converter; Equipped with A system in which a control circuit in open loop control is configured to control the duty cycle of switch state transitions to approximately 50% using feedback from the output of a switched-capacitor-based converter.

[0043] The terms used herein generally have their ordinary meanings in the art and in the particular context in which each term is used. The use of examples herein, including examples of any term described herein, is illustrative only and does not limit the scope and meaning of the disclosure or any exemplified term in any way. Likewise, the disclosure is not limited to the various embodiments provided herein.

[0044] The terms "first," "second," etc. may be used herein to describe various elements, but these elements are not limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of its associated listed items.

[0045] Spatial terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to facilitate the description of the relationship between one illustrated element or feature and another. These spatial terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the drawings. Other orientations of the device (such as rotated 90 degrees or other orientations) are contemplated, and the spatial descriptors used herein should be interpreted accordingly.

[0046] In this disclosure, the term “coupled” may also be referred to as “electrically coupled,” and the term “connected” may also be referred to as “electrically connected.” “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

[0047] The foregoing outlines features of several embodiments so that those skilled in the art may more fully appreciate aspects of the present disclosure. Those skilled in the art will readily appreciate that this disclosure may be used as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. 1. A control circuit for controlling a pulse width modulation (PWM) signal of a multilevel converter capable of operating in a charge pump mode with open loop control and in a regulation mode with closed loop control, comprising: a compensation signal generation circuit configured to generate a compensation signal; a PWM circuit configured to generate a PWM signal having a target duty cycle based on the compensation signal when the multi-level converter is operating in the charge pump mode, the PWM signal having the target duty cycle being used to control the multi-level converter in a mode change from the charge pump mode to the regulation mode; and The control circuit comprises:

2. The compensation signal generating circuit receiving an output voltage signal from the multi-level converter; receiving a digital code; Dividing the output voltage signal to obtain a feedback signal having a voltage based on the digital code; a resistive voltage divider circuit configured to: a first input for receiving a reference voltage signal and a second input for receiving the feedback signal from the resistor divider circuit; configured to generate the compensation signal based on the feedback signal. Transconductance amplifier and The control circuit of claim 1 , comprising:

3. The compensation signal generating circuit receiving an output voltage signal from the multi-level converter; Dividing the output voltage signal to obtain a feedback signal; a resistive voltage divider circuit configured to: a first input for receiving an adjustable voltage signal and a second input for receiving the feedback signal; configured to generate the compensation signal based on the signal of the adjustable voltage. Transconductance amplifier and The control circuit of claim 1 , comprising:

4. The compensation signal generating circuit an analog circuit providing the compensation signal at a target voltage, a first input for receiving a signal of the target voltage and a second input for receiving a loopback signal from the output of the analog circuit; configured to generate the compensation signal based on the signal of the target voltage. The control circuit of claim 1 comprising the analog circuit.

5. 5. The control circuit according to claim 1, wherein the PWM circuit is configured to generate the PWM signal having the target duty cycle based on a sawtooth signal and the compensation signal when the multilevel converter is operating in a voltage regulation mode.

6. 5. The control circuit according to claim 1, wherein the PWM circuit is configured to generate the PWM signal having the target duty cycle with slope compensation based on a triangle signal and the compensation signal when the multilevel converter is operating in a current regulation mode.

7. receiving the PWM signal from the PWM circuit; Based on the PWM signal, operating in said charge pump mode with open loop control to provide an output voltage signal at one of a plurality of voltage levels; operating in said regulation mode with closed loop control to provide said output voltage signal at a variable voltage; generating a plurality of level control signals for controlling the multi-level converter to The control circuit of claim 1 , further comprising a voltage level control circuit configured to:

8. the multi-level converter operates in the charge pump mode with a 50% duty cycle to provide the output voltage signal; or 8. The control circuit of claim 7, wherein the multi-level converter operates with an adjustable duty cycle in the regulation mode to provide the output voltage signal.

9. 8. The control circuit of claim 7, wherein the voltage level control circuit is configured to generate the plurality of level control signals having a fixed duty cycle to control the multilevel converter to provide the output voltage signal at one of the plurality of voltage levels in the charge pump mode, and wherein a first level control signal of the level control signals is phase shifted from a second level control signal of the level control signals.

10. The voltage level control circuit, in the regulation mode, a first voltage level of the plurality of voltage levels minus a voltage boundary zone window value; the first voltage level plus the voltage boundary zone window value; 8. The control circuit of claim 7, configured to generate the plurality of level control signals to control the multi-level converter to provide the output voltage signal having the variable voltage between .

11. 11. The control circuit of claim 10, wherein the multilevel converter operates at a duty cycle between 50% minus a duty cycle boundary zone window value and 50% plus the duty cycle boundary zone window value.

12. 1. A method for controlling a multi-level converter, comprising: determining a duty cycle of a pulse width modulated (PWM) signal configured to control the multi-level converter; The duty cycle of the PWM signal is decreasing, increasing, or unchanged; or The duty cycle of the PWM signal is less than a target duty cycle or is greater than the target duty cycle; determining at least one of: increasing the duty cycle of the PWM signal by increasing a parameter in response to determining that the duty cycle of the PWM signal is decreasing or that the duty cycle of the PWM signal is less than the target duty cycle; decreasing the duty cycle of the PWM signal by lowering the parameter in response to determining that the duty cycle of the PWM signal is increasing or that the duty cycle of the PWM signal is greater than the target duty cycle; The method comprising:

13. determining the duty cycle of the PWM signal measuring the PWM signal to obtain a first duty cycle at a first time and a second duty cycle at a second time, the first and second times being times when the multi-level converter is in a charge pump mode; determining the duty cycle of the PWM signal based on the first duty cycle and the second duty cycle; 13. The method of claim 12, comprising:

14. determining whether the duty cycle of the PWM signal is less than the target duty cycle comprises determining whether the duty cycle of the PWM signal is less than the target duty cycle minus a hysteresis value; 14. The method of claim 12 or 13, wherein determining whether the duty cycle of the PWM signal is greater than the target duty cycle comprises determining whether the duty cycle of the PWM signal is greater than the target duty cycle plus the hysteresis value.

15. 13. The method of claim 12, wherein the duty cycle of the PWM signal is a first duty cycle of the PWM signal, After determining at least one of whether a first duty cycle of the PWM signal is decreasing, increasing, or unchanged, or whether the first duty cycle of the PWM signal is less than a target duty cycle or greater than the target duty cycle, determining a second duty cycle of the PWM signal; the second duty cycle of the PWM signal is decreasing, increasing, or stationary; or the second duty cycle of the PWM signal is less than the target duty cycle or greater than the target duty cycle; determining at least one of: increasing the duty cycle of the PWM signal by increasing the parameter in response to determining that the second duty cycle of the PWM signal is decreasing or that the second duty cycle of the PWM signal is less than the target duty cycle; decreasing the duty cycle of the PWM signal by lowering the parameter in response to determining that the second duty cycle of the PWM signal is increasing or that the second duty cycle of the PWM signal is greater than the target duty cycle; The method further comprises:

16. The method of any of claims 12 to 15, wherein the target duty cycle is 50%.

17. 1. A system for reducing transients during a change in power conversion mode, comprising: a multi-level converter configured to operate in a charge pump mode or a regulation mode to provide an output voltage signal; controlling the multilevel converter to operate at a 50% duty cycle in the charge pump mode with open loop control or to operate at a variable duty cycle in the regulation mode with closed loop control; generating a pulse width modulation (PWM) signal having a target duty cycle when the multilevel converter is operating in the charge pump mode, the PWM signal having the target duty cycle being used to control the multilevel converter in a mode change from the charge pump mode to the regulation mode; a control circuit configured to: The system comprising:

18. The control circuit a compensation signal generating circuit configured to generate a compensation signal for generating the PWM signal; a PWM circuit configured to generate the PWM signal having the target duty cycle based on the compensation signal; 20. The system of claim 17, comprising:

19. The compensation signal generating circuit receiving the output voltage signal from the multi-level converter; receiving a digital code; Dividing the output voltage signal to obtain a feedback signal having a voltage based on the digital code; a resistive voltage divider circuit configured to: a first input for receiving a reference voltage signal and a second input for receiving the feedback signal from the resistor divider circuit; configured to generate the compensation signal based on the feedback signal. Transconductance amplifier and 20. The system of claim 18, comprising:

20. The compensation signal generating circuit receiving the output voltage signal from the multi-level converter; Dividing the output voltage signal to obtain a feedback signal; a resistive voltage divider circuit configured to: a first input for receiving an adjustable voltage signal and a second input for receiving the feedback signal; configured to generate the compensation signal based on the signal of the adjustable voltage. Transconductance amplifier and 20. The system of claim 18, comprising:

Images