Gate driver circuit

Abstract

The gate driver circuit includes a pull-up circuit (118), a pull-down circuit (126), a level shifter circuit (116), and a drive strength control circuit (144). The pull-up circuit (118) includes a pull-up output, a first signal input, and a first enable input. The pull-up output is coupled to the gate drive output. The first signal input is coupled to the drive signal input. The pull-down circuit (126) includes a pull-down output, a second signal input, and a second enable input. The pull-down output is coupled to the gate drive output. The second signal input is coupled to the drive signal input. The level shifter circuit (116) includes a shifter output and a drive strength input. The shifter output is coupled to the first enable input and the second enable input. The drive strength control circuit (144) includes a drive strength output coupled to the drive strength input.

Description

[Technical Field]

[0001] A DC-DC converter is an electronic circuit that converts an input direct current (DC) supply voltage into one or more DC output voltages that are either higher or lower in magnitude than the input DC supply voltage. A DC-DC converter that produces an output voltage that is lower than the input voltage is called a buck converter or step-down converter. A DC-DC converter that produces an output voltage that is higher than the input voltage is called a boost converter or step-up converter.

[0002] Some DC-DC converter topologies include a switching transistor coupled to an energy storage inductor / transformer at a switch node. Electrical energy is transferred to a load through the energy storage inductor / transformer by alternately opening and closing the switch as a function of a switching signal. The amount of electrical energy transferred to the load is a function of the on / off duty cycle of the switch and the frequency of the switching signal. DC-DC converters are widely used to power electronic devices, especially battery-powered devices such as cell phones, laptop computers, and other electronic systems where efficient use of power is desirable.

[0003] To reduce switching losses in power transistors, the switching transistors must be switched on and off very quickly. Because the control terminals of the switching transistors can exhibit significant capacitance, gate driver circuits can be used to buffer input signals and drive the control terminals of the switching transistors. The gate driver circuits receive low-power input signals, buffer the input signals, and generate high-current signals that quickly charge or discharge the input capacitance of the power transistors. Examples of power transistors that can use gate drive circuits include insulated gate bipolar transistors and metal-oxide-semiconductor field-effect transistors. Summary of the Invention

[0004] Described herein is a gate driver circuit that uses a single level shifter to control both the sink strength and the source strength of a high-side switching transistor. In one example, the gate driver circuit includes a pull-up circuit, a pull-down circuit, a level shifter circuit, and a drive strength control circuit. The pull-up circuit includes a pull-up output, a first signal input, and a first enable input. The pull-up output is coupled to the gate drive output. The first signal input is coupled to the drive signal input. The pull-down circuit includes a pull-down output, a second signal input, and a second enable input. The pull-down output is coupled to the gate drive output. The second signal input is coupled to the drive signal input. The level shifter circuit includes a shifter output and a drive strength input. The shifter output is coupled to the first enable input and the second enable input. The drive strength control circuit includes a drive strength output coupled to the drive strength input.

[0005] In another example, a gate driver circuit includes a pull-up circuit, a pull-down circuit, a level shifter circuit, and a drive strength control circuit. The pull-up circuit is configured to provide a current to the gate drive output in response to a drive signal at the drive signal input and an enable signal at the enable input. The pull-down circuit is configured to draw a current from the gate drive output in response to the drive signal and the enable signal. The level shifter circuit is connected to the pull-up circuit and the pull-down circuit. The level shifter circuit is configured to generate the enable signal by level-shifting the drive strength control signal. The drive strength control circuit is connected to the level shifter circuit. The drive strength control circuit is configured to set the drive strength control signal to a first state or a second state with respect to an edge of the drive signal.

[0006] In a further example, a DC-DC converter circuit includes a high-side transistor, a low-side transistor, a modulation circuit, and a high-side gate driver circuit. The high-side transistor has a control terminal. The low-side transistor is coupled to the high-side transistor. The modulation circuit is connected to the high-side transistor and the low-side transistor. The modulation circuit is configured to generate a modulation signal. The high-side gate driver circuit is connected between the high-side transistor and the modulation circuit. The high-side gate driver circuit includes a pull-up circuit, a pull-down circuit, a level shifter circuit, and a drive strength control circuit. The pull-up circuit is configured to provide a current to the control terminal in response to the modulation signal and an enable signal. The pull-down circuit is configured to draw a current from the control terminal of the high-side transistor in response to the modulation signal and the enable signal. The level shifter circuit is connected to the pull-up circuit and the pull-down circuit. The level shifter circuit is configured to generate the enable signal by level-shifting a drive strength control signal. The drive strength control circuit is connected to the level shifter circuit. The drive strength control circuit is configured to set the drive strength control signal to a first state or a second state on an edge of the modulation signal. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic level diagram of an example gate driver circuit with a single level shifter applied to a DC-DC converter.

[0008] [Figure 2] FIG. 2 is a block diagram of an example drive strength control circuit suitable for use in the gate driver circuit of FIG. 1.

[0009] [Figure 3] 3 is a timing diagram illustrating the operation of the driver strength control circuit of FIG. 2. [Figure 4] 3 is a timing diagram illustrating the operation of the driver strength control circuit of FIG. 2. [Figure 5]3 is a timing diagram illustrating the operation of the driver strength control circuit of FIG. 2.

[0010] [Figure 6] 2 is a block diagram of an example memory module including a DC-DC converter with the gate driver circuit of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0011] Efficiency is an important consideration in DC-DC converters. To increase efficiency, gate drivers provide fast turn-on and turn-off of the DC-DC converter power transistors, which provide low on-resistance. However, fast turn-on and turn-off increases ringing, which is caused by the drain-source voltage (V) across the power transistor. DS ) to increase V DS If the ringing overvoltage exceeds the safe operating voltage of the transistor, the power transistor may be damaged. The breakdown voltage of the power transistor may be reduced in relation to its specific on-resistance, which increases the likelihood of transistor damage due to ringing overvoltage.

[0012] When powering a larger load, ringing and stress on the power transistor increase. To protect the power transistor, ringing can be controlled by reducing the driver strength when the load increases. In gate drivers that control high-side power transistor switching, a level shifter converts the logic signal that controls the drive strength (e.g., high or low drive strength) from a low-voltage domain to a high-voltage domain. Some high-side gate driver circuits provide independent control of drive strength during turn-on and turn-off of the high-side power transistor using two level shifters. One level shifter controls the drive strength used to turn on the high-side transistor, and the other level shifter controls the drive strength used to turn off the high-side power transistor. The use of two level shifters increases circuit area and cost.

[0013] The gate driver circuit described herein uses a single level shifter to individually control the drive strengths that turn the high-side power transistors on and off. A drive strength control circuit generates an enable signal based on a load-related status signal. The enable signal may enable a higher or lower drive strength only during high-side power transistor turn-on, only during high-side power transistor turn-off, or during both turn-on and turn-off. The turn-on and turn-off drive strengths may be selected by a drive code stored in the gate driver circuit.

[0014] FIG. 1 is a schematic level diagram of an exemplary gate driver circuit 102 applied to a DC-DC converter 100. For clarity, various components of the DC-DC converter 100 (e.g., output feedback circuit elements) are omitted from FIG. 1. More specifically, the DC-DC converter 100 includes a high-side transistor 108, a low-side transistor 110, an inductor 112, and an output capacitor 114. The high-side transistor 108 and the low-side transistor 110 may be n-channel metal-oxide semiconductor field-effect transistors (MOSFETs). The drain of the high-side transistor 108 is coupled to a power supply voltage terminal. The source of the high-side transistor 108 is coupled to the inductor 112, which is coupled to the output capacitor 114. The drain of the low-side transistor 110 is connected to the source of the high-side transistor 108, and the source of the low-side transistor 110 is connected to a ground terminal. The gate of the high-side transistor 108 is connected to the gate drive circuit 102. The gate of the low-side transistor 110 is coupled to the gate driver 106. A pulse width modulation (PWM) logic circuit 104 is coupled to the gate driver circuit 102 and the gate driver 106 to control the switching of the high-side transistor 108 and the low-side transistor 110. The PWM logic circuit 104 receives a PWM signal 150 provided by a pulse width modulator (not shown) and generates a high-side drive signal (HDRV) and a low-side drive signal (LDRV) based on the PWM signal 150.

[0015] The gate driver circuit 102 is coupled between the PWM logic circuit 104 and the high-side transistor 108. The gate driver circuit 102 includes a level shifter circuit 116, a pull-up circuit 118, a pull-down circuit 126, a pull-up circuit 134, a pull-down circuit 140, and a drive strength control circuit 144. The pull-up circuit 118 and the pull-up circuit 134 provide current to the gate drive terminal 146 and the gate of the high-side transistor 108 to turn on the high-side transistor 108. The pull-down circuit 126 and the pull-down circuit 140 sink current from the gate drive terminal 146 and the gate of the high-side transistor 108 to turn off the high-side transistor 108.

[0016] The pull-up circuit 134 and the pull-down circuit 140 are coupled to the PWM logic circuit 104 via a drive signal input 148 of the gate driver circuit 102. The pull-up circuit 134 includes a transistor 136 and a driver 138. The transistor 136 is a pull-up transistor and includes a first current terminal (e.g., source) coupled to the power supply terminal and a second current terminal (e.g., drain) coupled to the gate drive terminal 146. A control terminal (e.g., gate) of the transistor 136 is coupled to a first output of the driver 138. The pull-down circuit 140 includes a transistor 142 coupled to the driver 138. The transistor 142 is a pull-down transistor and includes a first current terminal (e.g., drain) coupled to the gate drive terminal 146 and a second current terminal (e.g., source) coupled to the ground terminal. A control terminal (e.g., gate) of the transistor 142 is coupled to a second output of the driver 138. An input of driver 138 is coupled to a drive signal input 148 and to PWM logic circuit 104. Transistor 136 may be a P-channel field effect transistor (PFET) and transistor 142 may be an N-channel field effect transistor (NFET).

[0017] The pull-up circuit 118 and the pull-down circuit 126 are coupled to a drive signal input 148 via a driver 138. The pull-up circuit 118 includes a transistor 120, a driver 124, and a logic gate 122. The transistor 120 is a pull-up transistor including a first current terminal (e.g., source) coupled to a power supply terminal and a second current terminal (e.g., drain) coupled to a gate drive terminal 146. A control terminal (e.g., gate) of the transistor 120 is coupled to the output of the driver 124. An input of the driver 124 is coupled to the output of the logic gate 122. A first input of the logic gate 122 is coupled to the drive signal input 148 via the driver 138. A second input of the logic gate 122 serves as an enable input for the pull-up circuit 118 and is coupled to the output of the level shifter circuit 116. 1, logic gate 122 turns on transistor 120 based on the output of driver 138 and the output of level shifter circuit 116 being a logic low. The output of the level shifter is an enable signal that, when a logic low, allows transistor 120 to drive high-side transistor 108. Transistor 120 may be a PFET.

[0018] The pull-down circuit 126 includes a transistor 128, a driver 132, and a logic gate 130. The transistor 128 is a pull-down transistor and includes a first current terminal (e.g., drain) coupled to a gate drive terminal 146 and a second current terminal (e.g., source) coupled to a ground terminal. A control terminal (e.g., gate) of the transistor 128 is coupled to the output of the driver 132. An input of the driver 132 is coupled to the output of the logic gate 130. A first input of the logic gate 130 is coupled to a drive signal input 148 via a driver 138. A second input of the logic gate 130 serves as an enable input for the pull-down circuit 126 and is coupled to the output of the level shifter circuit 116. In the example of the pull-down circuit 126 shown in FIG. 1 , the logic gate 130 turns on the transistor 128 based on the output of the driver 138 being a logic high and the output of the level shifter circuit 116 being a logic low. The output of the level shifter is an enable signal that, when logic low, enables transistor 128 to drive high-side transistor 108. Transistor 128 may be an NFET.

[0019] The input of the level shifter circuit 116 is coupled to the drive strength output of the drive strength control circuit 144. The drive strength control circuit 144 generates a drive strength control signal 152. The level shifter circuit 116 shifts the drive strength control signal 152 from the low-voltage domain of the drive strength control circuit 144 to the high-voltage domain of the pull-up circuit 118 and the pull-down circuit 126. The drive strength control circuit 144 activates the drive strength control signal 152 to enable or disable the pull-up circuit 118 and the pull-down circuit 126 on each edge (rising and falling edge) of the PWM signal 150 based on the load powered by the DC-DC converter 100 and the edge control value stored in the gate driver circuit 102. When the pull-up circuit 118 is enabled, the turn-on drive strength is greater than when the pull-up circuit 118 is disabled. When the pull-down circuit 126 is enabled, the turn-off drive strength is greater than when the pull-down circuit 126 is disabled. By default, both the pull-up circuit 118 and the pull-down circuit 126 are enabled to provide fast turn-on and turn-off.

[0020] In one example of the gate driver circuit 102, the drive strength control circuit 144 controls the drive strength as shown in Table 1. In Table 1, "OC" is overcurrent. The drive strength control circuit 144 may provide different driver strength control in other examples. [Table 1]

[0021] 2 is a block diagram of an example drive strength control circuit 144. The drive strength control circuit 144 includes a high on (HON) input, an edge select (SEL_WEAK_EDGE) input, a low on (LON) input, a PWM input, an overcurrent (OC_RAW) input, a latch 202, a selector circuit 204, a latch 206, a pulse generation circuit 208, a latch 210, a logic gate 212, and a latch 214. A high on (HON) signal received at the high on input indicates whether the gate-to-source voltage of the high-side transistor 108 is sufficient to turn on the high-side transistor 108. A low on signal received at the low on input indicates whether the gate-to-source voltage of the low-side transistor 110 is sufficient to turn on the low-side transistor 110. A PWM signal 150 is received at the PWM input. An overcurrent signal (OC_RAW) received at the overcurrent input indicates that the DC-DC converter 100 is overloaded and the current flowing through the load exceeds a predetermined threshold. The edge select input may be a multi-bit edge select input that receives an edge control value (e.g., a multi-bit edge control value SEL_WEAK_EDGE) that indicates whether a high drive strength or a low drive strength should be applied to turn the high-side transistor 108 on and turn the high-side transistor 108 off.

[0022] The latch 202 may be a D-type flip-flop and generates the drive strength control signal 152 that is provided to the level shifter circuit 116. The latch 202 includes a latch output coupled to the input of the level shifter circuit 116. The clock input of the latch 202 is coupled to the high on input. The data input of the latch 202 is coupled to a logic high voltage source (e.g., a logic high voltage terminal). The reset input of the latch 202 is coupled to the selector output of the selector circuit 204. For any switching cycle, if the reset input of the latch 202 is logic high, the drive strength control signal 152 is set high on the rising edge of the high on signal. This allows the turn-on and turn-off drive strength to be lowered for successive cycles until the reset input of the latch 202 is set to logic low by the output of the selector circuit 204. The selector circuit 204 includes a select control input (e.g., a multi-bit select control input) coupled to the output of the non-volatile memory 216 (or a register coupled to the non-volatile memory 216) for receiving an edge control value. Selector circuit 204 routes a signal from one of its data inputs to its output based on an edge control value. A first selector input of selector circuit 204 is coupled to a logic high voltage source. A second selector input of selector circuit 204 is coupled to a logic low voltage source (e.g., a logic low voltage terminal or a ground terminal). A third selector input of selector circuit 204 is coupled to the output of latch 206. A fourth selector input of selector circuit 204 is coupled to the output of latch 210. Some implementations of selector circuit 204 may include different numbers of selector inputs.

[0023] If the edge control value selects the connection of the first data input of selector circuit 204 to the output of selector circuit 204, latch 202 is never reset (until the edge control value is changed), and drive strength control signal 152 disables pull-up circuit 118 and pull-down circuit 126 on both edges of PWM signal 150 to provide slow turn-on and slow turn-off of high-side transistor 108.

[0024] If the edge control value selects the connection of the second data input of selector circuit 204 to the output of selector circuit 204, latch 202 is always reset (until the edge control value is changed), and drive strength control signal 152 enables pull-up circuit 118 and pull-down circuit 126 on both edges of PWM signal 150 to provide fast turn-on and fast turn-off of high-side transistor 108.

[0025] When the edge control value selects the connection of the third data input of selector circuit 204 to the output of selector circuit 204, selector circuit 204 sends the output of latch 206 to the reset input of latch 202. Latch 206 may be a D-type flip-flop and includes a clock input coupled to the PWM input, a data input coupled to the overcurrent input, and a reset input coupled to the output of pulse generator circuit 208. The pulse input of pulse generator circuit 208 is coupled to the low on input. Pulse generator circuit 208 outputs a pulse (low-going pulse) at the pulse output in response to the rising edge of the low on signal. The output of latch 206 (SLOW_HS_FALL) is set on the rising edge of PWM signal 150 if the overcurrent signal is high and reset on the rising edge of the low on signal. Based on the output of latch 206, if an overcurrent is detected, drive strength control signal 152 enables pull-up circuit 118 on the rising edge of a low on signal and disables pull-down circuit 126 on the rising edge of a high on signal to provide a fast turn-on and a slow turn-off of high-side transistor 108. The operation of drive strength control circuit 144 when selection circuit 204 selects the output of latch 206 is further described in conjunction with FIG.

[0026] When the edge control value selects the connection of the fourth data input of selector circuit 204 to the output of selector circuit 204, selector circuit 204 sends the output of latch 210 to the reset input of latch 202. Latch 210 may be a D-type flip-flop and includes a clock input coupled to the output of latch 206 and a data input coupled to a logic high voltage source. The reset input of latch 210 is coupled to the output (gate output) of logic gate 212. A first input of logic gate 212 is coupled to the output of pulse generation circuit 208. A second input of logic gate 212 is coupled to the output of latch 214. Latch 214 may be a D-type flip-flop and includes a clock input coupled to a high on input via an inverter and a data input coupled to the output of latch 206. The output of latch 210 (SLOW_HS_BOTH) is set on the rising edge of SLOW_HS_FALL (output by latch 206), indicating an overcurrent condition exists, and remains set until reset by the output of latch 214. The output of latch 214 is set on the falling edge of the high ON signal when SLOW_HS_FALL is high, indicating an overcurrent condition exists, and remains set while the overcurrent condition persists. SLOW_HS_BOTH remains high as long as the output of latch 214 is high. SLOW_HS_BOTH is reset when the output of latch 214 goes low. Based on the output of latch 210, drive strength control signal 152 disables pull-up circuit 118 and pull-down circuit 126 on the rising edge of the high ON signal for all consecutive cycles while an overcurrent condition exists, and then pull-up circuit 118 and pull-down circuit 126 are enabled on the rising edge of the low ON signal. Thus, selecting the fourth data input of selector circuit 204 provides a slow turn-on and a slow turn-off of high-side transistor 108. The operation of drive strength control circuit 144 when select circuit 204 selects the output of latch 210 is further described in conjunction with FIG.

[0027] FIG. 3 is a timing diagram illustrating the operation of drive strength control circuit 144, in which the drive strength is reduced only during turn-off of high-side transistor 108 during an overcurrent condition. At rising edge 302 of PWM signal 150, overcurrent signal (OC_RAW) is high in FIG. 3, which sets latch 206. OC_HFET, output by selector circuit 204, goes high and latch 202 is not held reset. Latch 202 remains reset from the previous assertion of OC_HFET, and drive strength control signal 152 is low to enable pull-up circuit 118 while high-side transistor 108 is turned on (shown as HDRV going high). A rising edge 304 of high on signal (HON) sets latch 202, and drive strength control signal 152 goes high, disabling pull-down circuit 126 while turning high-side transistor 108 off. At the rising edge 306 of the low on signal (LON), latch 206 is reset, SLOW_HS_FALL and OC_FET go low, latch 202 is reset, and drive strength control signal 152 goes low, enabling high drive strength on the next turn-on of high-side transistor 108.

[0028] 4 is a timing diagram illustrating the operation of drive strength control circuit 144, in which the drive strength is weakened during both turn-on and turn-off of high-side transistor 108 under an overcurrent condition. At rising edge 402 of PWM signal 150, overcurrent signal (OC_RAW) is high in FIG. 4, which sets latch 206. The rising edge of SLOW_HS_FALL output by latch 206 sets latch 210. SLOW_HS_BOTH generated by latch 210 goes high, OC_HFET output by selector circuit 204 goes high, and latch 202 is not held reset. Latch 202 remains reset from the previous assertion of OC_HFET, and drive strength control signal 152 is low to enable pull-up circuit 118 while high-side transistor 108 is turned on (HDRV is shown high) in the early PWM cycle of FIG. 4.

[0029] SLOW_HS_BOTH and drive strength control signal 152 remain high until the rising edge of the low on signal following the overcurrent signal goes low at the rising edge of PWM signal 150. At rising edge 406 of drive strength control signal 152, the overcurrent signal is high, so OC_HFET and drive strength control signal 152 remain high, disabling pull-up circuit 118 and pull-down circuit 126. At rising edge 407 of drive strength control signal 152, the overcurrent signal is low, and SLOW_HS_FALL remains low. At falling edge 408 of the high on signal, latch 214 is reset, and at rising edge 409 of the low on signal, latch 210 is reset. OC_HFET goes low, latch 214 is reset, and drive strength control signal 152 goes low, enabling pull-up circuit 118 for high drive strength the next time high-side transistor 108 turns on.

[0030] FIG. 5 is a timing diagram illustrating the operation of one implementation of drive strength control circuit 144, which provides weak drive strength only during turn-on of high-side transistor 108. At rising edge 502 of PWM signal 150, overcurrent signal (OC_RAW) is high in FIG. 5, and OC_HFET goes high. After low-side transistor 110 is turned on, OC_HFET goes low, as shown by rising edge 504 of the low-on signal, and drive strength control signal 152 goes high, disabling pull-up circuit 118 upon the next turn-on of high-side transistor 108. At rising edge 505 of PWM signal 150, overcurrent signal is high, and OC_HFET goes high. At rising edge 507 of the high-on signal, turn-on of high-side transistor 108 with weakened gate drive is completed, and drive strength control signal 152 goes low, allowing high-side transistor 108 with high drive strength to turn off.

[0031] 6 is a block diagram of an example memory module 600. The memory module 600 includes a DC-DC converter 602, a memory 604, and a buffer circuit 606. The DC-DC converter 602 receives an input voltage V and generates an output voltage V for powering the memory 604 and / or the buffer circuit 606. The buffer circuit 606 may include static or dynamic random access memory. The buffer circuit 606 may buffer signals provided between the memory 604 and a module input / output interface (not shown). The DC-DC converter 602 includes a gate driver circuit 102 that provides variable drive strength to the high-side switching transistor of the DC-DC converter 602 to reduce ringing while using a single level shifter to reduce circuit area and cost.

[0032] In this description, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal that controls device B to perform a certain action, then (a) in a first example, device A is coupled to device B by a direct connection, or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0033] Also, as used herein, "based on" means "based at least in part on." Thus, if X is based on Y, X can be a function of Y and any number of other factors.

[0034] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the configuration and / or layout of hardware components, through the device's interconnections, or through a combination thereof.

[0035] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless otherwise noted, these terms are used generally to refer to an interconnection between, or termination of, a device element, circuit element, integrated circuit, device, or other electronic or semiconductor component.

[0036] A circuit or device described herein as including particular components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only the semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacture, e.g., by an end user and / or third party, to form the described structure.

[0037] While the use of particular transistors is described herein, other transistors (or equivalent devices) may be substituted with little or no modification to the remaining circuit elements. For example, field-effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Additionally, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0038] In the claims, reference may be made to a transistor's control input and its current terminals. In the context of a FET, the control input is the gate and the current terminals are the drain and source. In the context of a BJT, the control input is the base and the current terminals are the collector and emitter.

[0039] As used herein, a FET is "on" means that a conducting channel for the FET exists and a drain current can flow through the FET. As used herein, a FET is "off" means that a conducting channel does not exist and no drain current flows through the FET. However, an "off" FET may have current flowing through the body diode of the transistor.

[0040] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to that available before the component was replaced. A component shown as a resistor, unless otherwise noted, generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the depicted resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

[0041] While certain elements of the described examples are included in an integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit, and / or some features illustrated as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are (1) incorporated in / on a semiconductor substrate, (2) incorporated within a single semiconductor package, (3) incorporated within the same module, and / or (4) incorporated within / on the same printed circuit board.

[0042] Use of the term "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings herein. As used herein, unless otherwise specified, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of that parameter.

[0043] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the claims of the invention.

Claims

1. A gate driver circuit, A pull-up circuit, a pull-up output coupled to the gate drive output; a first signal input coupled to the drive signal input; a first enable input; and the pull-up circuit including: A pull-down circuit, a pull-down output coupled to the gate drive output; a second signal input coupled to the drive signal input; a second enable input; and the pull-down circuit including: A level shifter circuit, a shifter output coupled to the first enable input and the second enable input; a drive strength input; and the level shifter circuit, a drive strength control circuit including a drive strength output coupled to said drive strength input; a gate driver circuit including:

2. 2. The gate driver circuit of claim 1, wherein the pull-up circuit comprises: A transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal is connected to a power supply terminal; the transistor, the second current terminal of which is coupled to the gate drive output; A logic gate having a gate output, a first input, and a second input, the first input is coupled to the drive signal input; the second input is coupled to the shifter output; the logic gate, the gate output coupled to the control terminal; a gate driver circuit including:

3. 2. The gate driver circuit of claim 1, wherein the pull-down circuit comprises: A transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal is coupled to the gate drive output; the transistor, the second current terminal of which is coupled to a ground terminal; A logic gate having a gate output, a first input, and a second input, the first input is coupled to the drive signal input; the second input is coupled to the shifter output; the logic gate, the gate output coupled to the control terminal; a gate driver circuit including:

4. 2. The gate driver circuit of claim 1, the pull-up circuit is a first pull-up circuit, the gate driver circuit includes a second pull-up circuit; the second pull-up circuit includes a transistor having a first current terminal, a second current terminal, and a control terminal; In the transistor, the first current terminal is coupled to a power supply terminal; the second current terminal is coupled to the gate drive output; the control terminal is coupled to the drive signal input; Gate driver circuit.

5. 2. The gate driver circuit of claim 1, the pull-down circuit is a first pull-down circuit, the gate driver circuit includes a second pull-down circuit; the second pull-down circuit includes a transistor having a first current terminal, a second current terminal, and a control terminal; In the transistor, the first current terminal is coupled to the gate drive output; the second current terminal is coupled to a ground terminal; the control terminal is coupled to the drive signal input; Gate driver circuit.

6. 2. The gate driver circuit of claim 1, wherein the drive strength control circuit comprises: High on input and a multi-bit edge select input; a first latch, a first latch output coupled to the drive strength output; a first clock input coupled to the high on input; a first data input coupled to the logic high voltage terminal; a first reset input; and the first latch including: A selector circuit, a selector output coupled to the first reset input; a multi-bit select control input coupled to said multi-bit edge select input; a first selector input coupled to the logic low voltage terminal; a second selector input coupled to the logic high voltage terminal; the selector circuit including: a gate driver circuit including:

7. 7. The gate driver circuit of claim 6, the selector circuit includes a third selector input; The drive strength control circuit a pulse width modulation (PWM) input; Overcurrent input and Low on input and a second latch, a second latch output coupled to the third selector input; a second clock input coupled to the PWM input; a second data input coupled to the overcurrent input; a second reset input; and the second latch including: A pulse generating circuit, a pulsed input coupled to the low-on input; a pulse output coupled to the second reset input; the pulse generating circuit, a gate driver circuit including:

8. 8. The gate driver circuit of claim 7, the selector circuit includes a fourth selector input; The drive strength control circuit a third latch, a third latch output; and a third clock input coupled to the high on input; a third data input coupled to the second latch output; the third latch including: a fourth latch, a fourth latch output coupled to the fourth selector input; a fourth clock input coupled to the second latch output; a fourth data input coupled to the logic high voltage terminal; a fourth reset input coupled to the pulse output and to the third latch output; the fourth latch including a gate driver circuit including:

9. A gate driver circuit, a pull-up circuit configured to provide a current to the gate drive output in response to a drive signal at the drive signal input and to provide an enable signal at the enable input; a pull-down circuit configured to draw current from the gate drive output in response to the drive signal and the enable signal; a level shifter circuit coupled to the pull-up circuit and the pull-down circuit, the level shifter circuit configured to generate the enable signal by level-shifting a drive strength control signal; a drive strength control circuit coupled to the level shifter circuit, the drive strength control circuit configured to set the drive strength control signal to a first state or a second state of an edge of the drive signal; a gate driver circuit including:

10. 10. The gate driver circuit of claim 9, the pull-up circuit is a first pull-up circuit, the pull-down circuit is a first pull-down circuit, The gate driver circuit a second pull-up circuit configured to provide a current to the gate drive output in response to the drive signal; a second pull-down circuit configured to draw current from the gate drive output in response to the drive signal; Including, Gate driver circuit.

11. 10. The gate driver circuit of claim 9, the gate driver circuit is configured to provide an edge control value; The gate driver circuit, wherein the drive strength control circuit is configured to set the drive strength control signal to the first state or the second state based on the edge control value.

12. 12. The gate driver circuit of claim 11, the first state disables the pull-up circuit and the pull-down circuit; the second state enables the pull-up circuit and the pull-down circuit; the drive strength control circuit is configured to set the drive strength control signal to the first state during a rising edge of the drive signal and during a falling edge of the drive signal based on the edge control value.

13. 12. The gate driver circuit of claim 11, the first state disables the pull-up circuit and the pull-down circuit; the second state enables the pull-up circuit and the pull-down circuit; the drive strength control circuit is configured to set the drive strength control signal to the second state during a rising edge of the drive signal and during a falling edge of the drive signal based on the edge control value.

14. 12. The gate driver circuit of claim 11, the first state disables the pull-up circuit and the pull-down circuit; the second state enables the pull-up circuit and the pull-down circuit; the drive strength control circuit is configured to set the drive strength control signal to the second state during a rising edge of the drive signal and to the first state during a falling edge of the drive signal based on the edge control value.

15. 12. The gate driver circuit of claim 11, the first state disables the pull-up circuit and the pull-down circuit; the second state enables the pull-up circuit and the pull-down circuit; the drive strength control circuit is configured to set the drive strength control signal to the first state during a rising edge of the drive signal and to the second state during a falling edge of the drive signal based on the edge control value.

16. A DC-DC converter circuit, a high-side transistor having a control terminal; a low-side transistor coupled to the high-side transistor; a modulation circuit coupled to the high-side transistor and the low-side transistor, the modulation circuit configured to generate a modulation signal; a high-side gate driver circuit connected between the high-side transistor and the modulation circuit; Including, the high-side gate driver circuit a pull-up circuit configured to provide a current to the control terminal in response to the modulation signal and an enable signal; a pull-down circuit configured to draw current from the control terminal of the high-side transistor in response to the modulation signal and the enable signal; a level shifter circuit coupled to the pull-up circuit and the pull-down circuit, the level shifter circuit configured to generate the enable signal by level-shifting a drive strength control signal; a drive strength control circuit coupled to the level shifter circuit, the drive strength control circuit setting the drive strength control signal to a first state or a second state with respect to an edge of the modulation signal; Including, DC-DC converter circuit.

17. 17. The DC-DC converter circuit according to claim 16, the pull-up circuit is a first pull-up circuit, the pull-down circuit is a first pull-down circuit, the high-side gate driver circuit a second pull-up circuit configured to provide a current to the control terminal of the high-side transistor in response to the modulation signal; a second pull-down circuit configured to draw current from the control terminal of the high-side transistor in response to the modulation signal; Including, DC-DC converter circuit.

18. 17. The DC-DC converter circuit according to claim 16, the high side gate driver circuit is configured to store an edge control value; the drive strength control circuit is configured to set the drive strength control signal to the first state or the second state based on the edge control value. DC-DC converter circuit.

19. 19. The DC-DC converter circuit of claim 18, the first state disables the pull-up circuit and the pull-down circuit; the second state enables the pull-up circuit and the pull-down circuit; the drive strength control circuit is configured to set the drive strength control signal to the second state during a rising edge of the modulation signal and to the first state during a falling edge of the modulation signal based on the edge control value. Gate driver.

20. 19. The DC-DC converter circuit of claim 18, the first state disables the pull-up circuit and the pull-down circuit; the second state enables the pull-up circuit and the pull-down circuit; the drive strength control circuit is configured to set the drive strength control signal to the first state during a rising edge of the modulation signal and to the second state during a falling edge of the modulation signal based on the edge control value.

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