Method and apparatus for increasing skin depth and reducing eddy currents in non-magnetic hybrid materials using electroless plating techniques

Abstract

This application presents a method and apparatus for closed-porosity hybrid materials. These closed porosity provides high dielectric strength. The hybrid materials referred to in this application are materials, usually metallic, that have an incomplete insulating layer (hybrid insulating layer). This insulating layer contains through-porosity that allows the metal layer to be physically connected through the insulating layer. The closed porosity is formed by electroless plating (also known as controlled autocatalytic deposition) of a metal layer onto the hybrid insulating layer.

Description

[Technical Field]

[0001] The present disclosure relates to a method and apparatus for increasing the skin depth and reducing eddy currents in non-magnetic hybrid materials using electroless plating techniques. [Background technology]

[0002] The process of layering metal with thin, fully insulating layers to reduce eddy currents has been used in manufacturing since 1885. Today, designers strive to make circuit components smaller, cheaper, and lighter. In power supplies, for example, one of the easiest ways to achieve component miniaturization is, in theory, to increase the operating frequency; roughly doubling the frequency reduces the required inductance by a factor of two.

[0003] However, due to the skin effect, the resistivity of a metal, such as copper, increases with frequency. This phenomenon is widely known as the "skin effect," and the industry has standardized the skin effect performance of metals with the term "skin depth," which is defined as the depth from the surface to the point where the current density drops off by 1 / e, or 37%, moving inward.

[0004] At 60 Hz, the skin depth of copper wire is about 8.4 mm, at 60 kHz the skin depth of copper wire is about 266 μm, and at 6 MHz the skin depth of copper wire is about 26.6 μm. Therefore, simply increasing the frequency from 60 Hz to 6 MHz reduces the skin depth by about 8.4 mm.

[0005] For conventional materials, increasing the surface area of ​​a conductor is more effective at lowering impedance at high frequencies than continually increasing the conductor thickness beyond the skin depth. Common methods for increasing metal surface area include using thinner and wider metal layers or stacking metal layers. Higher frequencies require thinner metal layers. However, this poses economic challenges. Fabricating fine layer structures requires expensive precision deposition equipment using relatively slow deposition techniques, as well as the use of large amounts of photoresist, masks, or dry film (often involving one or more patterning steps per layer). Alternatively, using less precise but faster plating techniques still requires one or two dry film passes per layer, thereby increasing product costs to the point where they are limited to niche applications that can justify their high cost.

[0006] Fortunately, through dielectric layer plating, hybrid materials with inherent skin depths have been developed. While these hybrid materials solve many of the challenges associated with high frequency materials, they also have their own limitations.

[0007] These hybrid materials, fabricated by processes such as chemical combustion vapor deposition (CCVD), have dramatically reduced the cost of embedding insulating layers into composite metals. In one CCVD method, this is achieved by igniting silicon precursor chemicals with a burner flame, triggering a chemical reaction that produces high-temperature silicon dioxide (SiO2) nanoparticles. These SiO2 particles then fall like snow onto the deposition target, forming a layer. The newly formed SiO2 layer is composed of randomly distributed SiO2 particles. As more deposits accumulate, the SiO2 layer becomes thicker. By controlling the thickness and spread of SiO2, it is possible to achieve some control over the coverage of the underlying metal layer, but currently it is always less than 100%. The lack of complete coverage means that the SiO2 layer is an "imperfect" insulating layer. In microelectronics manufacturing, this imperfection provides a significant advantage, as it allows metal layers to be electroplated through the SiO2 layer. Thus, in a plating method incorporating CCVD, there are no additional steps between plating the metal layer and depositing the SiO2 insulator, other than cleaning and drying steps.

[0008] The advantages of the SiO2 imperfect layer primarily relate to the ease with which it can be formed into a composite material with an insulating layer, significantly reducing costs compared to the additional processing steps required to create an SiO2 insulating layer for electroplating using alternative methods. The imperfect SiO2 layer deposited by CCVD is a sufficient insulator to reduce eddy current losses to economically competitive levels, even in applications using high-frequency currents. Furthermore, the process for depositing the imperfect SiO2 layer, despite being deposited at high temperatures, requires only a few seconds of high-temperature heating, making it compatible with low-temperature materials (e.g., dry films, photoresists, and various other epoxy resins and materials) used on wafers, semiconductor packages, and printed circuit boards during manufacturing or as part of the final product.

[0009] However, the SiO2 layer is an imperfect layer and therefore an imperfect insulator. Therefore, in applications where it is beneficial to further reduce the current flowing perpendicular to the layers in the composite (while maintaining low resistivity for currents flowing parallel to the layers in the composite), it would be beneficial to further increase the insulating strength of the imperfect SiO2 layer. However, to ensure that the benefits of the hybrid material are maintained, it is necessary to maintain some of the unique and useful properties of the imperfect insulating layer. However, creating an ideal, more perfect insulating layer is difficult because the unique and useful properties of the layer are derived from the imperfections. Summary of the Invention

[0010] This application presents a method for producing a pinched void insulation layer with enhanced dielectric strength and the resulting device by closing the voids. As used herein, a "hybrid material" refers to a material having a pinched void insulation layer, which is an insulation layer containing through-holes. These through-holes are typically filled with a non-insulating material that interconnects the layers through the insulation layer. The method described herein increases the dielectric strength of a pinched void insulation layer without relying on relatively expensive insulating polymers or epoxy films, or coatings applied at temperatures, pressures, or process conditions that are incompatible with epoxy plastics for semiconductor packages, semiconductor wafers, or printed circuit boards. Thus, the device of the present invention is a hybrid material having at least one pinched void hybrid insulation layer. This hybrid material can be molded into various components, some of which may contain wiring or traces. The improved dielectric strength increases the insulation layer's ability to reduce eddy current formation, thereby improving the overall composite skin depth of the component into which the hybrid material is incorporated.

[0011] The method includes depositing a hybrid insulating layer over a layer of an electrical component. Following the formation of the hybrid insulating layer, a subsequent metal layer is formed by electroless plating over the previously deposited hybrid insulating layer. Electroless plating occurs at least until the thickness of the new metal layer begins to close the voids in the hybrid insulating layer. Electroless plating may continue to produce the component layer, or electroplating or other means may be used to finish the subsequent component metal layer.

[0012] The resulting device is a hybrid material with a closed-void insulating layer that can be formed into a component or component part. Unlike traditional hybrid insulating layers, where electroplated metal is subsequently deposited, some voids are filled, but not all voids are completely filled with electroless-plated metal. These voids may contain air, liquid, and oxides of the surrounding metal, and in most cases contain some aspect of the electroless or pre-electroless plating environment. The resistivity of the closed voids is much higher than that of copper or other metals, which differs from standard electroplating, where the voids are filled with metal. The result is an improved resistivity for the insulating layer of the hybrid material, improving its function as an insulator. Experimental data suggests that the increase in resistivity when subsequent layers are formed electrolessly, as in the present invention, is at least two orders of magnitude higher than when a layer is formed by electroless deposition of SiO2 followed by electroplating.

[0013] Accordingly, an exemplary embodiment presented herein is a method for manufacturing a closed void hybrid material for an electrical component, the method including creating a conductive material layer, forming an incomplete insulating layer on the conductive material layer, and forming a layer on a portion of a surface of the incomplete insulating layer by controlled autocatalytic deposition until at least one closed void is produced.

[0014] The incomplete insulating layer may be, but is not limited to, an incomplete grain insulating layer, and may have a coverage of 90-99.99% and a thickness of 10 nm-5 μm. The metal layer may be, but is not limited to, palladium, copper, nickel, nickel-phosphorus, silver, aluminum, iron, cobalt, titanium, or an alloy of any of these materials.

[0015] The conductive material layer can be fabricated on a substrate core, carrier, wafer, or film, such as at least one of epoxy, fiberglass, Ajinomoto® build-up film, silicone, polymer, various films, or a core the same as or similar to any core used in the printed circuit board, semiconductor package, semiconductor wafer, or lamination industries.

[0016] It will be appreciated that the above-described layering steps may be repeated, for example, by forming an intermediate incomplete insulating layer on the surface of a metal layer and performing the following steps at least once in the order described: forming an additional metal layer on the surface of the additional incomplete insulating layer; and forming an additional insulating layer on the surface of the additional metal layer. It will also be appreciated that a metal layer may be electroplated onto the surface portion of the incomplete insulating layer that has not undergone controlled autocatalytic deposition (thus only a portion of the particle insulating layer is subjected to electroless plating).

[0017] Additionally, the resulting material can be used in conjunction with subtractive manufacturing processes, which can be utilized to pattern copper clad and occluded hybrid materials into wires, traces, or ground planes.

[0018] The occluded hybrid insulating layer can be used in combination with a conventional hybrid insulating layer to create a hybrid material having a blend of insulating layers. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a cross-sectional view of a particle hybrid insulating layer on a conductive material. [Figure 2] FIG. 2 is a cross-sectional view of metal deposited by electroless plating on a particle insulating layer. [Figure 3] FIG. 3 is a cross-sectional view of a closed interparticle void. [Figure 4] FIG. 4 is a cross-sectional view of unblocked interparticle voids. [Figure 5] FIG. 5 is a cross-sectional view of a partially blocked interparticle void. [Figure 6] FIG. 6 is a cross-sectional view of a closed non-interparticle void space. [Figure 7] FIG. 7 is a cross-sectional view of an electroplated metal layer on a particle hybrid insulating layer that previously underwent electroless plating. [Figure 8] FIG. 8 is a flow chart illustrating cross-sectional views of steps in a removed part manufacturing process incorporating the method of the present invention. [Figure 9] FIG. 9 is a flow chart illustrating cross-sectional views of steps in an additive part manufacturing process incorporating the method of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0020] The present invention involves forming an electrical component with a hybrid insulating material, where the hybrid insulating layer is sealed by an electroless insulation process. The method of the present invention is particularly useful for achieving high frequency conductive components by providing a robust, low-cost insulating layer that can reduce eddy currents and increase the effective skin depth of the component. This method is advantageous for replacing copper or other hybrid material-based components for high frequencies in the GHz (gigahertz) range because the insulation resistance of the insulating layer of the present invention can be twice or even more than that of conventional hybrid materials, and the skin depth of the closed void hybrid material is greater than that of conventional hybrid materials.

[0021] It is worth briefly discussing the physical properties of common hybrid materials. Hybrid materials have an incomplete insulating layer. This insulating layer can be produced by several methods, but the two most economically feasible methods are chemical combustion vapor deposition (CCVD) and inkjet printing. In CCVD, the insulating layer contains particles with randomly located voids between these particles, although the voids can be controlled to some extent by controlling the thickness of the insulating layer. In inkjet printing, the insulating layer is generally a solid insulating sheet with intentionally located voids. In both methods of producing an incomplete insulating layer, voids exist that penetrate the insulating layer, and these voids are filled when subsequent non-insulating layers are formed. Such hybrid materials have a much higher vertical resistivity than typical bulk materials.

[0022] For example, the overall increase in vertical resistivity in a copper-based SiO2-based hybrid material is a function of [copper thickness (Tc) × 1.68 μohm.cm] and [thickness of the copper-penetrated insulating layer (TC iSO ) × 1.68 μohm.cm × 20 (95% area coverage)], [thickness of copper (Tc)] and [thickness of SiO2 layer penetrated by copper (TC iSO )] and for a conductive material with a copper layer coverage of 95% by the SiO2 layer, it is expressed by the following formula:

[0023] JPEG2026500982000002.jpg21129

[0024] Silicon dioxide is an excellent insulator, and as a result, the parallel combination of the impedance of copper and SiO2 in the pores, measured vertically, is practically equal to the impedance of copper in the pores. Thus, at 95% coverage, the impedance increase compared to the absence of SiO2 is approximately 20 times, or 1 / (1-95%). According to the present invention, the impedance increase of this hybrid material can be further doubled relative to bulk copper.

[0025] Presented herein is a method for connecting layers via an insulating layer, filling some voids (voids that penetrate through layers) while eliminating some voids. This is achieved by forming high-resistance voids, thereby increasing the strength of the insulating layer, and then forming an electroless plating layer on top of the hybrid insulating layer. This is because, unlike electroplating, which does not form metal on the insulating layer, electroless plating can deposit metal on the insulating layer. Given the random nature and shape of the voids in the particle hybrid layer, some voids will be filled while others will remain. In a hybrid insulating layer formed by printing, the voids may be printed in a way that at least some of the voids are filled.

[0026] After the electroless process has filled or presumed to fill at least some of the voids, subsequent layers can be completed using electroplating or other forms of plating, if desired. Thus, a combination of high resistance electroless plating and less expensive but lower resistance electroplating to deposit metal on the hybrid insulator can be used to achieve a desirable balance of economy and performance.

[0027] A preferred insulating material with hybrid materials is CCDV SiO2 due to its well-studied nature, non-toxic and relatively inert properties, and low cost. Any oxide or form produced can be used to form a more highly resistive layer in a composite metal with some degree of success.

[0028] Although copper is the preferred electroless plating material, various electroless copper surface preparation materials, such as palladium, are available. Many materials available for electroless plating include, but are not limited to, nickel and nickel-phosphorus and their various surface preparation formulations. These electroless plating materials are acceptable and may be the preferred choice for some applications, as some of these materials have higher resistivity and other superior mechanical, electrical, and thermal properties compared to electroless copper, which may be economically advantageous.

[0029] For particulate-based hybrid insulating layers, the void closure occurs randomly. FIG. 1 shows a conductive material layer 101 having a hybrid insulating layer 102 on its upper surface. The conductive material layer 101 can be copper or any metal or conductor that can be used for the same purpose as copper. In the exemplary embodiment shown in FIG. 1, the conductive layer is copper, the hybrid insulating layer 102 is SiO2, and the SiO2 is randomly distributed. (This random distribution occurs because SiO2 snow-like accumulation occurs as a result of the combustion reaction in the CCVD process.) Note that some SiO2 particles become embedded in the metal layer due to the heat of the particles as combustion products. Also, the SiO2 particles that make up the SiO2 layer 102 can accumulate in any random pattern; this illustration shows only one example of a pattern that the SiO2 particles can form.

[0030] Between the SiO2 particles there are several large through voids 111. These through voids 111 have holes that go all the way through the cross section of the hybrid insulating layer 102. There may also be other significant voids 112, but these do not go all the way through the cross section of the SiO2 layer 102 and may or may not be blocked depending on how they are formed.

[0031] 2 shows an electroless copper layer plated on the hybrid insulating layer 102 and conductive material layer 101 of FIG. 1. Thin layers 120 and 121 can be seen formed on the exposed surface portion of the hybrid insulating layer and on the top surface of the conductive material layer, respectively. The electroless plated metal layer on the conductive material layer 101 is layer 120, and the electroless copper layer deposited on the hybrid insulating layer is metal layer 121. When the electroless layer grows to a sufficient thickness during plating, it closes many of the voids 111 and 112, preventing any closed voids from receiving further deposition. Thus, voids 111 and 112 are closed.

[0032] The voids closed by electroless plating are not necessarily pure air gaps, as they contain some environmental substances, which can be controlled by controlling the environment during or before plating.

[0033] 3 focuses on an exemplary inter-particle void 311 that extends from top to bottom. The top of void 311 is closed by electroless plating before the volume below the void is filled, thus leaving a void in the hybrid insulating layer that is not filled.

[0034] 4 focuses on an exemplary void 411 that narrows from top to bottom, where electroless plating does not close the void 411, and the void 411 will be filled with metal 121 either by electroplating or electroless plating if the void is narrow enough.

[0035] However, not all voids have a uniform width. Figure 5 shows void 511 having a narrower plugged point 520 below the initial opening, and widening from plugged point 520 again to form lower region 521. Plugged point 520 of void 511 is closed with metal 121 by electroless plating, and only the space above the plugged point is plated with metal. When a void has a structure that has a portion narrow enough to be closed by the initial electroless plating and then widens from that portion, an insulating void of the present invention is formed.

[0036] This principle of controlling which voids are closed can be utilized in more controlled manufacturing processes, such as inkjet printing. In the inkjet printing method for forming a hybrid insulating layer, the hybrid insulating layer is formed by printing, and the voids are systematically designed and positioned. As shown in Figure 6, if void 611 is positioned so that opening 620 is narrower than the rest of the void, that portion will be closed by electroless plating if opening 620 is sufficiently narrow.

[0037]

[0013] Figure 7 shows the hybrid insulating layer of Figure 2 once a subsequent metal layer has been built on the insulating layer. The subsequent metal layer may be built by, but is not limited to, electroplating or electroless plating. The steps shown in Figures 1, 2, and 7 may be repeated until the desired component is built.

[0038] The particulate hybrid insulating layer of the present invention is incomplete, consisting of loosely dispersed particles embedded within the metal layer. That is, the hybrid insulating layer of the present invention is not a complete, monolithic insulating layer. Therefore, the hybrid insulating layer of the present invention is highly susceptible to subtractive manufacturing processes, including etching and drilling. In subtractive manufacturing processes, even if the particles are SiO2, they behave like dust. For example, in an etching process, silicon dioxide (SiO2) particles are washed away, and in a drilling process, the silicon dioxide does not provide a resistant barrier to the drill and is removed along with the metal.

[0039] Regarding acid etching, the occluded hybrid insulating layer may be in the form of particles with through-pores, allowing the etching acid to etch through the pores. This property allows any etching acid to be used, and it is useful for etching the metal around the insulator. Therefore, when etching, it is only necessary to use an etching acid suitable for etching the metal layer.

[0040] The non-grain hybrid insulating layer is not easily integrated with subtractive manufacturing methods because it is not grain morphology and is resistant to etching and puncturing.

[0041] However, because plugged particle layers are easy to integrate into subtractive manufacturing workflows, they are useful for constructing substrate cores with copper cladding. Figure 8 shows an overview of the general process of the present invention, incorporated into a "plating workflow" in which a substrate core with copper cladding is formed and then etched.

[0042] Step 1 shows the starting core. The starting core is coated with copper cladding. Step 2 shows the initial copper cladding layer deposited on the core. Both sides of the substrate core may be coated with the first copper layer and all subsequent layers.

[0043] After the first copper layer is deposited, a silicon dioxide layer is deposited by CCVD, as shown in step 3. Then, a subsequent copper layer is deposited by electroless plating, as shown in step 4. Steps 3 and 4 may be repeated until the desired number of layers is achieved, with the final result of a certain number of such repetitions being shown in step 5.

[0044] This completes the copper-clad core. However, to demonstrate the ease of removal fabrication, a removal workflow is included in Figure 8, where step 6 shows the pattern laid out for the removal process. Step 8 shows the removal process performed, and step 8 also shows the removed pattern and the completion of the process. No additional steps are required for cores with hybrid materials that are not required in the typical removal process for non-CCVD-based cores. Blocked insulating hybrid cores may even be easier to process than traditional hybrid cores because removal can occur more quickly through the blocked, hollowed-out voids.

[0045] Electroless plating therefore offers a simple method of creating a base for components formed by subtractive manufacturing methods (including, but not limited to, chemical etching, laser drilling or cutting, or mechanical drilling or cutting). However, the additive manufacturing process is more complex, as a dry film must be removed after each electroless plating step. An exemplary embodiment of this process is shown in FIG.

[0046] Step 1 in Figure 9 involves preparing a dry film for patterning. In step 2, the dry film is patterned. In step 3, an initial conductive material is deposited. In step 4, a CCVD process is performed to form an incomplete insulating layer. In step 5, electroless plating is performed. It will be appreciated that electroless plating forms a metal layer on all particles. Because the particles in step 4 are deposited on the dry film and the edges of the dry film, it may be beneficial to replace the dry film before starting electroplating.

[0047] When an electroless process is immediately followed by an electroplating process, the electroless layer acts as a seed layer, allowing the electroplated layer to grow horizontally and vertically, preventing subsequent particle layers from forming as an edge-to-edge layer of the component. Therefore, before forming the copper layer by electroplating, the dry film is often replaced, as shown in step 6 of Figure 9, which adds a repetitive step. This dry film replacement requires replacing the dry film pattern, which destroys the smooth sidewalls that are characteristic of hybrid materials.

[0048] Therefore, it may be beneficial to fabricate a hybrid material with at least one conventional hybrid insulating layer and at least one electroless insulating layer. By arranging these two types of layers, it is possible to significantly increase the vertical resistivity compared to the bulk material and conventional hybrid material while minimizing edge misalignment. For example, a configuration with one closed hybrid insulating layer for every 100 conventional hybrid insulating layers is possible, or any other layer configuration is also possible. However, it should be noted that the need for a new dry film process does not necessarily mean that another surface treatment step is required for the formation of the next layer, and this process still involves fewer steps than conventional laminate material processes.

[0049] It will be appreciated that the blocked insulating layer increases the vertical resistivity of the hybrid material, without requiring a change in the materials used or an increase in the thickness of the insulating layer itself. This allows the blocked hybrid material to maintain the same ease of packaging and use as conventional hybrid materials. The blocked hybrid material also maintains the same small size as its conventional hybrid counterpart. In fact, due to the increased resistivity, in theory, blocked hybrid conductors may actually be smaller than conventional hybrid cores for the same frequency applications.

[0050] It also makes sense that if resistivity is increased, fewer insulating layers can be provided in the hybrid material. However, at high frequencies, eddy currents are generated at a higher density, and insulating layers need to be placed closer together regardless of their thickness, so reducing the number of layers is not a likely outcome (although in some cases using low frequencies, for example, reducing the number of insulating layers may be more cost-effective and practical). Therefore, instead of reducing the number of insulating layers, a closed hybrid core may be able to accommodate more and thinner insulating layers within the core for further performance improvement at high frequencies.

[0051] In all cases of encapsulated hybrid insulation layers and components, it may be beneficial to shock the component or layer after it has been constructed. In at least one exemplary embodiment, the resulting component is subjected to a shocking process. The shock process may be a thermal shock process.

[0052] The results of this electroless plating method include higher performance hybrid materials that allow the hybrid materials to handle higher frequencies, contain more layers, and even be smaller—all while requiring the use of additional materials and maintaining the positive benefits of hybrid materials (e.g., ease of subtractive fabrication).

[0053] The drawings and figures show multiple embodiments and are intended to illustrate specific embodiments, but do not limit the scope, number, or type of embodiments of the present invention. The present invention can incorporate numerous types and specific embodiments. All figures are prototypes and schematics, and the final product may be further refined by those skilled in the art. Nothing should be construed as essential or required unless specifically stated. Additionally, the articles "a" and "an" may be understood to mean "one or more," and when only one is intended, the term "one" or other similar expression is used. Additionally, terms such as "has," "have," and "having" are intended to be open-ended terms. The term "metal" is defined as a metal or an alloy thereof and is used herein to refer only to non-magnetic metals.

Claims

1. 1. A method for producing a closed porosity hybrid material for an electrical component, comprising: forming a layer of conductive material; forming an incomplete insulating layer on the layer of conductive material; forming a layer on a portion of the surface of the incomplete insulating layer by controlled autocatalytic deposition until at least one closed void is created; A method comprising:

2. The method of claim 1 , wherein the imperfect insulating layer is an imperfect grain insulating layer.

3. The method of claim 1 , wherein the fabrication of the conductive material layer is performed on a substrate core, carrier, wafer, or film.

4. The method of claim 3 , wherein the substrate core is one or more of an epoxy, fiberglass, Ajinomoto® build-up film, silicone, or polymer substrate core.

5. forming an intermediate partial insulating layer on a surface of the metal layer; forming an additional metal layer on a surface of the additional incomplete insulating layer, and forming an additional insulating layer on a surface of the additional metal layer, at least once in the order listed; The method of claim 1 further comprising:

6. The method of claim 4 further comprising forming a pattern in the resulting layer by a subtractive manufacturing process.

7. The method of claim 1, wherein the metal layer is palladium, copper, nickel-phosphorus, silver, aluminum, titanium, or an alloy of any of these materials.

8. The method of claim 6 further comprising patterning the occluded hybrid material into wires, traces, or ground planes.

9. 10. The method of claim 1, further comprising electroplating a metal layer onto surface portions of the incomplete insulating layer that have not been subjected to controlled autocatalytic deposition.

10. 2. The method of claim 1, wherein the incomplete insulating layer has a coverage of 90 to 99.99% and a thickness of 10 nm to 5 μm.

11. A closed pore type hybrid material, a conductive material layer; at least one closed-void type imperfect insulating layer embedded in a conductive material; A hybrid material comprising:

12. The apparatus of claim 11 , further comprising a substrate operatively connected to a lower surface of the layer of conductive material.

13. 13. The apparatus of claim 12, further comprising at least one metal layer having an additional closed-void imperfect insulating layer embedded therein and operably connected to a surface of the substrate opposite the closed-void hybrid material.

14. 12. The device of claim 11, further comprising the closed-gap hybrid material integrated into a wire, trace, or ground plane.

15. 12. The device of claim 11, wherein the metal layer is a palladium, copper, nickel, nickel phosphorous, silver, aluminum, iron, cobalt, titanium material or an alloy of any of these materials.

16. The apparatus of claim 11 further comprising the closed-void incomplete insulating layer having at least one void filled with metal.

17. The device of claim 11 , wherein the imperfect insulating layer is an imperfect grain insulating layer.

18. The apparatus of claim 11 , further comprising the hybrid material operably connected to a substrate, a core, a carrier, or a wafer.

19. 12. The device of claim 11, wherein the core is one or more of the group consisting of epoxy, fiberglass, Ajinomoto® build-up film, silicone, polymer, various films, and cores the same as or similar to any core used in the printed circuit board, semiconductor package, semiconductor wafer, or lamination industries.

20. The device of claim 11 , wherein the conductive material is copper metal.

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