Systems and methods for manufacturing printed circuit boards

Abstract

Systems and methods are disclosed for overcoming technical challenges associated with machining and manufacturing printed circuit boards. In some embodiments, these systems and methods include processes for removing or reducing defects in initially fabricated printed circuit board (PCB) traces. Exemplary methods include processes for removing or reducing burrs in laser-micromachined PCB traces, which may be electrically isolated from one another. In some cases, a material is deposited on the PCB traces, forming a conductive layer that electrically connects all or most of the PCB traces and provides the electrical connection to remove or reduce defects in the PCB traces.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to U.S. Provisional Patent Application No. 63 / 436,971, entitled "METHOD FOR MANUFACTURING ULTRA-HIGH-DENSITY MINIATURIZED PRINTED CIRCUIT BOARDS," filed January 4, 2023, the entire contents of which are incorporated herein by reference.

[0002] [Field of the Invention] It relates to the technical field of printed circuit board (PCB) machining and manufacturing. [Background technology]

[0003] Printed circuit boards (PCBs) are often used in electronic products. The current trend is toward miniaturization of electronic devices, leading to smaller printed circuit boards, smaller trace widths, and smaller spacing. Additionally, Moore's Law has slowed significantly over the past decade, leading to the development of alternative methods of manufacturing chips, such as heterogeneous integration of chiplets and advanced packaging, further creating a demand for smaller trace widths and spacing on printed circuit boards (PCBs).

[0004] Traditional PCB manufacturing processes are considered to have reached their limits in reducing the width and spacing of PCB traces. On the other hand, state-of-the-art PCB manufacturing processes use photolithography and wet chemical etching. Wet chemical etching is an isotropic etchant, typically etching material at the same rate in both the vertical and horizontal directions, limiting the aspect ratio of the depth to width of the etched trench to 1:2 or less. When etching 18 μm-thick copper to create PCB traces, gaps of 50 μm or more often occur between traces. The trapezoidal cross-section of PCB traces can cause signal distortion in high-speed RF applications. Furthermore, existing PCB manufacturing processes are prone to environmental pollution due to the use of various toxic chemicals, including resists, developers, and etchants.

[0005] While laser micromachining offers a potential technical solution to this problem, it has been limited to the production of PCBs with large trace widths and spacings due to the generation of burrs during laser micromachining. Indeed, these burrs typically range in size from a few microns to approximately 50 μm and do not cause short circuits when the trace width and spacing are much larger than the burrs. Furthermore, because the burrs are much smaller than the PCB traces, they can be removed by wet etching without completely etching away the traces. However, when trace spacings fall below approximately 50 μm and the burr size becomes the same size as the trace spacing, the burrs can cause short circuits between traces. Furthermore, when multiple PCB trace layers are stacked to produce multilayer boards, burrs can penetrate the insulating layers used to separate the conductive trace layers, potentially causing short circuits between the trace layers. Sharp burrs can also cause electrical discharges, resulting in breakdown of the insulating layers used between the conductive layers and the traces.

[0006] Burr removal is difficult because trace widths and spacings become narrower and the burr size approaches the same size as the PCB trace width and spacing. Using wet etching to remove the burr also etches the PCB traces. On the other hand, using physical abrasion destroys the already fragile PCB traces. Thus, the burrs generated during the laser micromachining process limit the width and spacing of the PCB traces.

[0007] Electrolytic deburring, electropolishing, and plasma electrolytic polishing (PeP) can remove burrs without etching the fine structures. However, these methods can conduct electricity to the fine structures (such as PCB traces) that need to be deburred. Printed circuit boards have many electrically isolated traces (electrically isolated islands), typically hundreds. It is not practical to conduct electricity through high-density PCB traces using an array probe.

[0008] When deburring by known electro-deburring, electro-polishing, or plasma electrolytic polishing (PeP), only the burrs are removed from the electrically conductive traces (e.g., see FIG. 1D), and the burrs remain on the other electrically isolated traces (e.g., see FIGS. 1D-1F). Therefore, in a practical sense, known electro-deburring, electro-polishing, or plasma electrolytic polishing (PeP) cannot be used to remove burrs from small-dimension laser-micromachined PCB traces. Summary of the Invention

[0009] Described herein are systems and methods for overcoming technical problems associated with machining and manufacturing printed circuit boards or PCBs. In certain embodiments, the systems and methods include a process for removing or reducing defects in initially fabricated printed circuit board (PCB) traces. The method includes, for example, removing or reducing burrs on laser-micromachined PCB traces (which may be electrically isolated from one another). In certain embodiments, a material is first deposited on the PCB traces, thereby creating an electrically conductive layer that electrically connects all or most of the PCB traces and removes or reduces defects in the PCB traces (e.g., reduces or removes burrs formed by laser micromachining). Presented herein is an electrically isolated microstructure deburring (EID) process for deburring laser-micromachined PCB traces, e.g., deburring traces that are electrically isolated from one another.

[0010] Embodiments are also presented regarding processes for improving the machining and manufacturing of multilayer boards, where each group of layers in a multilayer board includes rounds for depositing material over PCB traces, conductive layers for electrically connecting all or most of the PCB traces, and conductive layers for removing or reducing defects in the PCB traces (such as reducing or removing burrs formed in laser micromachining of layers in a multilayer board) that can remove or reduce defects in the layers from the deposited material.

[0011] In one embodiment, a method includes depositing a conductive layer on traces formed on a PCB, the traces being electrically isolated from one another and electrically connecting at least a portion of the traces after the conductive layer is deposited. For example, the method may also include applying a current to the conductive layer to reduce or remove defects (e.g., burrs) on or within the traces. In one embodiment, the PCB is micromachined using laser micromachining. In some instances, defects due to laser micromachining exist. And, in some instances, at least some of the defects are burrs. Thus, in one embodiment, a method includes depositing a conductive layer on traces formed on a laser micromachined PCB, the traces being electrically isolated from one another and the conductive layer electrically connecting at least a portion of the traces after the conductive layer is deposited. Such a method may also include applying a current to the conductive layer to reduce or remove burrs on the traces.

[0012] In some cases, this may include creating traces. For example, this method may include laser micromachining of PCB traces. In some cases, at least some of the traces are not connected by a deposited conductive layer. In such cases, the electrical connection is made by another method known or foreseeable to those skilled in the art. In such cases, defects or burrs may or may not be reduced or eliminated in examples where a conductive layer is not deposited.

[0013] In some embodiments, one or more steps of the methods described herein may be repeated to fabricate a multilayer substrate. In some embodiments, this may involve repeating the laser micromachining of PCB traces for each of multiple layers of the multilayer substrate. In some embodiments, this may involve repeating the deposition of a conductive layer on traces formed on the laser micromachined PCB for each of multiple layers of the multilayer substrate. In some cases, this may involve applying a current to the conductive layer to reduce or remove burrs on the traces for each of multiple layers of the multilayer substrate. In other embodiments, this may involve repeating an EID process (e.g., a process that includes the aforementioned subprocesses of depositing a conductive layer on traces and applying a current to the conductive layer to reduce or remove burrs on the traces). In some cases, this may involve forming vias between multiple layers of the multilayer substrate after repeating the laser micromachining of PCB traces and the EID process.

[0014] For example, in one embodiment, a method for reducing or eliminating burrs on printed PCB traces may use an EID process. In this case, the PCB traces are electrically isolated from each other before performing the EID process. The EID process may include, as a first sub-process, depositing a conductive layer on the PCB traces, such that the conductive layer electrically connects at least a portion of the PCB traces. The EID process may also include, as a second sub-process, applying a current or voltage to the conductive layer to reduce or eliminate the burrs.

[0015] In some cases, the reduction or removal of burrs depends on the voltage and electrolyte used when applying current to the conductive layer. Furthermore, when the aforementioned second sub-process is used, the reduction or removal of burrs by the second sub-process depends on the voltage and electrolyte used in the second sub-process. In some embodiments, the voltage used in the second sub-process, or a similar process, is determined based on the composition of the wiring, the conductive layer, or a combination thereof. In some embodiments, the second sub-process, or a similar process, includes electrolytic polishing of the trace. In some embodiments, the second sub-process, or a similar process, includes electrolytic deburring of the trace. In some embodiments, the second sub-process, or a similar process, includes plasma electrolytic polishing of the trace.

[0016] In some embodiments, the first sub-process includes using PVD, CVD, ALD, or any combination thereof. In some embodiments, the first sub-process includes using electroless copper. In some embodiments, the first sub-process includes using liquid metal ink. In some embodiments, the first sub-process includes using electroplating to increase the thickness of the conductive layer.

[0017] In some embodiments, the conductive layer may be removed using chemical etching after the EID process or a similar process. In some embodiments, the conductive layer may include a conductive coating layer (thin film). In some embodiments, an exemplary method includes forming PCB traces on an insulating substrate. In some embodiments, a conductive layer is deposited on the PCB traces, such that the conductive layer electrically connects all of the PCB traces.

[0018] In summary, the systems and methods (or techniques) disclosed in this specification can provide specific technical solutions to at least overcome the technical problems mentioned in this specification, as well as other technical problems not described in this specification but recognized by those skilled in the art.

[0019] These and other important aspects of the present invention are described in more detail in the detailed description that follows. The present invention is not limited to the methods and systems described herein. Other embodiments may be used, and changes may be made to the described embodiments, without departing from the scope of the claims that follow the detailed description. It is to be understood that, within the scope of this application, the various aspects, embodiments, examples, and alternatives described herein, as well as their individual features, may be considered independently or in any possible combination. When a feature is described with reference to a single aspect or embodiment, it is to be understood that such feature is applicable to all aspects and embodiments, unless otherwise specified or unless such features are mutually incompatible. [Brief explanation of the drawings]

[0020] It is believed that the present invention will be better understood from the following detailed description and accompanying drawings of various embodiments of the present disclosure.

[0021] [Figure 1] 1A-1F illustrate the individual known process steps of an electrolytic deburring process, with the operational sequence beginning with the step in FIG. 1A and ending with the step in FIG. 1F. [Figure 2] 2A-2K illustrate the individual process steps of an electrically isolated microstructure deburring technology process according to one embodiment of the present disclosure, with the operational sequence starting with the step in FIG. 2A and ending with the step in FIG. 2K. [Figure 3] 3A through 3O illustrate the individual process steps for fabricating a printed circuit board by laminating conductive and dielectric laminates in accordance with certain embodiments of the present disclosure and defining PCB traces by laser micromachining followed by deburring techniques of electrically isolated microstructures, with the operational sequence beginning with the step in FIG. 3A and ending with the step in FIG. 3O. [Figure 4]FIG. 4 illustrates a multi-layer substrate with air gaps between traces for various applications, such as high speed applications, in accordance with an embodiment of the present disclosure. [Figure 5] FIG. 5 illustrates PCB layers fabricated on either side of a PCB core with voids filled with dielectric material in one embodiment of the present disclosure. [Figure 6] 6A through 6M illustrate the individual process steps for fabricating a printed circuit board by depositing conductive and dielectric layers and using laser micromachining followed by electrically isolated microstructure deburring techniques to define PCB traces on the conductive layers in one embodiment of the present disclosure, shown in an operational sequence beginning with the step in FIG. 6A and ending with the step in FIG. 6M. [Figure 7] FIG. 7 illustrates the layers of a PCB fabricated on either side of a core in one embodiment of the present disclosure. [Figure 8] 8A-8F illustrate the individual process steps for manufacturing a double-sided printed circuit board in one embodiment of the present disclosure, showing an operating sequence starting with the step in FIG. 8A and ending with the step in FIG. 8F. [Figure 9] 9A-9G illustrate the individual process steps for manufacturing a multilayer printed circuit board by stacking double-sided printed circuit board laminates, and in one embodiment of the present disclosure, illustrate an operating sequence beginning with the step in FIG. 9A and ending with the step in FIG. 9G. Details of the invention

[0022] The following detailed description illustrates the best currently contemplated modes for carrying out exemplary embodiments of the invention. This description is not to be taken in a limiting sense, but is intended merely to illustrate the general principles of the invention, since the scope of the invention is most clearly defined by the appended claims.

[0023] SUMMARY OF THE INVENTION Embodiments of the present invention provide improved systems, apparatus, and methods for manufacturing printed circuit boards (PCBs).

[0024] The details of example embodiments of the present invention are described below with reference to the drawings. While reference is made herein to exemplary embodiments, it should be understood that the present invention is not limited to such example embodiments. The present invention encompasses numerous alternatives, modifications, and equivalents, as will become apparent from a review of the following detailed description and the other parts of this disclosure.

[0025] Described herein are systems and methods for overcoming technical challenges associated with machining and manufacturing circuit boards (e.g., PCB processing methods shown in FIGS. 2A-2K, 3A-3O, 4, 5, 6A-6M, 7, 8A-8F, and 9A-9G). In some embodiments, the systems and methods include processes for removing or reducing defects in initially fabricated PCB traces. For example, the methods may include processes for removing or reducing burrs in laser-micromachined PCB traces, which may be electrically isolated from one another. In certain embodiments, a material is deposited over the initially formed PCB traces, which deposition forms a conductive layer that electrically connects all or most of the PCB traces, providing electrical connections for removing or reducing defects in the PCB traces (e.g., reducing or removing burrs formed by laser micromachining). In accordance with certain embodiments, disclosed herein is an EID process for deburring laser-micromachined PCB traces, e.g., deburring traces that are electrically isolated from one another. See, e.g., FIGS. 2A-2K.

[0026] Also disclosed herein, in accordance with certain embodiments, is a process for improving the processing and manufacturing of multilayer boards, e.g., Figures 3A-3O. Each layer of a multilayer board can be provided with a conductive layer that electrically connects all or most of the PCB traces and an electrical connection that removes or reduces defects in the PCB traces by depositing material over the PCB traces and treating the deposited material to remove or reduce defects in the layer (e.g., reducing or removing burrs formed by laser micromachining of the layers of the multilayer board).

[0027] In some of the methods and other embodiments described herein, a conductive coating layer (thin film) is deposited on the laser-micromachined PCB traces. See, for example, FIG. 2B. This deposition forms a conductive layer that electrically connects all or most of the isolated PCB traces of the laser-micromachined PCB traces and provides electrical connection (or current flow) for electrical deburring. In some cases, the deposition forms a conductive layer that electrically connects all or most of the isolated PCB traces of the laser-micromachined PCB traces, thereby electrically deburring all or most of the generated burrs. See, for example, FIG. 2D.

[0028] For purposes of this disclosure, deburring techniques for electrically isolated microstructures are processes for deburring isolated and isolated locations (e.g., structures that are not electronically connected). Alternatively, or in addition to deburring techniques for electrically isolated microstructures, electrolytic deburring, electropolishing, and PeP can be used to deburr electrically connected or monolithic conductive structures (or continuous structures). However, printed circuit boards often have many electrically isolated traces (e.g., PCB traces may be conductive island structures on an insulating substrate), and if the traces are very small, electrolytic deburring, electropolishing, or plasma electrolytic polishing cannot be used to deburr such PCB traces. Conversely, deburring techniques for electrically isolated microstructures can be used to deburr very small, electrically isolated traces.

[0029] In some examples, this specification discloses a novel technology called electrically isolated microstructure deburring technology. This technology overcomes the limitations of the aforementioned electrolytic deburring, electrolytic polishing, and plasma electrolytic polishing, enabling deburring of island PCB traces. In some examples, this specification also describes an electrolytic deburring process for deburring multiple electrically isolated island PCB traces (e.g., traces) formed on an insulating substrate. In such a process, a conductive coating layer (thin film) is deposited on the island (or island) traces, electrically bridging most or all of the traces. The conductive layer electrically connecting the traces is used as an electrode in an electrochemical cell. An electrical connection is made to the conductive layer, and an appropriate cell voltage waveform is applied to deburr the PCB traces. Deburring is achieved using various mechanisms at the electrodes, such as electrolytic polishing, electrolytic deburring, and plasma electrolytic polishing, while the conductive film is periodically regenerated by electroplating with a reversed voltage (see Figure 2H). The conductive layer is then removed by etching, electrically isolating the PCB traces.

[0030] Electrolytic deburring, electrolytic polishing, and plasma electrolytic polishing, to name a few, involve an anode (usually the area to be deburred), a cathode, and an electrolyte. The difference lies in the mechanism of the electrode used to remove the burr, which varies depending on the voltage and electrolyte used.

[0031] Electropolishing is an electrochemical and reverse electroplating process for surface smoothing. In this process, the metal part requiring surface smoothing is used as the anode in an electrochemical cell. By applying the appropriate cell voltage, a high-resistivity viscous layer, or polishing film, forms around the anode. The polishing film creates a high-resistance path between the anode and the electrolyte, but "peaks" or "mountains" on the anode surface penetrate the polishing film, creating localized low-resistance paths. The low resistance of the sharp points results in a higher current density, which accelerates the metal dissolution rate at the sharp points compared to recesses and flat areas, resulting in a smoother surface. If the burrs are small and comparable to the surface roughness of the part, the electropolishing process can be used to remove them.

[0032] In this disclosure, electrolytic deburring is an electrochemical and reverse electroplating process for removing burrs from metal parts. In this process, the metal part to be deburred is used as the anode in an electrochemical cell. By applying an appropriate cell voltage (usually higher than the electropolishing voltage), a current density proportional to the electric field is obtained. Because the burr has a sharp structure, the electric field is concentrated at the burr, resulting in a higher current density. The high current density at the sharp portion dissolves the metal more quickly at the sharp portion compared to the flat portion, thereby removing the burr. This process can be used when the burr is much larger than the surface roughness of the part. In both electropolishing and electrolytic deburring, the high current density at the burr (or sharp portion) dissolves the metal more quickly at the sharp portion compared to the recessed or flat portion, thereby removing the burr. However, the mechanism behind the high current density at the burr (or sharp portion) differs between electropolishing and electrolytic deburring. In electropolishing, the current density is higher at the burr (ridge or hill). This is because the burr penetrates the high-resistance polishing film, and the thin polishing film on top of it reduces resistance and increases the current density. In electrolytic deburring, the current density is high at the burr because a high electric field is concentrated at the burr. The electric field is concentrated due to the sharp structure of the burr.

[0033] In this disclosure, plasma electrolytic polishing (PeP) is a process used for surface smoothing. In this process, the metal part to be smoothed is used as the anode in an electrochemical cell. A high cell voltage is used to generate an electrical discharge and plasma at the sharp burr. Evaporation of the electrolyte and ionization of the vapor form an electrical discharge or plasma at the burr. The generated plasma removes the burr by plasma etching it.

[0034] In one embodiment, the EID process involves depositing a thin layer of conductive coating onto a laser-micromachined printed circuit board. This conductive coating layer (thin film) is typically substantially thinner than the printed circuit board's wiring pattern, allowing the conductive layer to be etched away without significantly etching the printed circuit board's wiring pattern. The thickness of the conductive layer is typically 1 / 10 to 1 / 1000 of the thickness of the printed circuit board's wiring pattern (depending on the thickness of the printed circuit board's wiring pattern). For example, a 100 nm thick conductive layer can be used for a 25 micrometer thick printed circuit board trace. The thickness of the conductive layer must be balanced to ensure a current conduction path for deburring while not being so thick that it significantly alters the dimensions of the printed circuit board trace during subsequent etching steps. The thickness of the conductive layer depends on several parameters, as explained below.

[0035] For a given printed circuit board design, the number of burrs on a laser micromachined PCB trace will vary depending on the board design, trace thickness, and the laser micromachining parameters used. The number of burrs present on the PCB traces will determine the deburring current required to completely remove them in an electrically isolated microstructure deburring technology process.

[0036] The deburring current depends on the effective electrical conductivity between the burr and the electrode contact on the conductive layer, which is determined by two factors: 1) the conductivity through the deposited conductive coating layer (thin film) and 2) the conductivity through the PCB trace.

[0037] The conductance of a PCB trace is determined by the board design (trace layout, trace thickness, etc.), which determines the thickness of the conductive layer to achieve sufficient deburring current. In summary, the number of burrs on a trace determines the deburring current, and the deburring current, along with the PCB trace layout, determines the thickness of the conductive coating layer (thin film). The following list summarizes the relationship between thickness t and other parameters: 1) tα number of burrs, 2) tα1 / deburring time, 3) tα trace spacing, 4) tα1 / trace width.

[0038] Next, an anodic electrical connection is formed on the conductive coating layer (thin film) (see, for example, Figure 2D), and the burrs are removed using electrolytic deburring, electrolytic polishing (for small burrs, for example), or plasma electrolytic polishing. Because the conductive layer electrically connects almost all of the wiring on the PCB, burrs can be removed from almost all of the wiring on the PCB (see, for example, Figure 2E).

[0039] In some embodiments, for certain conductive layer materials, electrolytic deburring (e.g., electrolytic deburring, electropolishing, or plasma electrolytic polishing) can partially remove the conductive coating. For such materials, the thickness of the conductive layer can be increased by reversing the voltage of the electrochemical cell and electroplating the conductive film (see, e.g., Figure 2G). In the electroplating cycle, cell parameters are set to maximize uniform electroplating, while in the deburring cycle, parameters are set to maximize selective electrochemical etching of the burrs. After the deburring process, the thin conductive coating is etched using methods such as flash wet chemical etching or plasma etching to electrically isolate the PCB traces (e.g., Figure 2I). Because the conductive coating is much thinner than the thickness of the PCB traces, it is removed without etching away the PCB traces.

[0040] In one embodiment, one or more of the aforementioned techniques are used to fabricate multilayer substrates (e.g., multilayer ultra-high density PCBs). This process involves forming PCB traces on a metal-insulator laminate substrate using laser micromachining, followed by the electrolytic deburring process disclosed herein (see, e.g., Figure 3B). A second metal-insulator layer is then laminated onto the substrate layer (see, e.g., Figure 3D). Laser vias (e.g., via drilling) are then formed in the second metal-insulator layer (see, e.g., Figure 3E), and via filling is performed using electroless plating followed by electroplating to electrically connect the two laminate layers (see, e.g., Figure 3F). Next, printed circuit board traces are formed on the second metal laminate layer using laser micromachining followed by electrolytic deburring (see, e.g., Figure 3G). The process steps shown in Figures 3D-3G can be repeated to achieve any desired number of PCB layers, forming a multilayer laminate structure. Figure 3H shows a schematic diagram of the completed multilayer substrate.

[0041] In one embodiment, the printed circuit board manufacturing process provides advantages over known printed circuit board manufacturing processes, including: 1) ultra-high density printed circuit board routing; 2) vertical walls of PCB traces resulting in better signal integrity; 3) tight control of trace impedance for high speed data propagation applications; 4) creation of printed circuit boards with traces using a variety of materials, such as metals, alloys, and conductive polymers; 5) PCBs with air gaps between traces for high speed data propagation applications; and 6) high aspect ratio PCB traces for high density and high current applications.

[0042] In some embodiments, the ultra-high density, compact PCBs can be used as substrates for ultra-high density wiring in advanced semiconductor packaging, space-constrained mobile and wearable devices, applications requiring tightly controlled impedance such as 5G and 6G applications, and high-density flexible cables. Furthermore, this electrically isolated microstructure deburring technology process can also be used to deburr other island structures found in other applications, such as microelectromechanical systems (MEMS) and microfluidics.

[0043] Specifically, FIGS. 1A-1F illustrate known process steps in an electrolytic deburring process, showing the steps in FIG. 1A through FIG. 1F in operational order. The steps in FIGS. 1A-1F are known prior art processes, and many of the technical challenges associated with this known prior art are overcome by the solutions described herein; however, one or more of the steps illustrated in FIGS. 1A-1F are not necessarily required. FIGS. 1A-1F may be combined with aspects of certain embodiments of the present disclosure, and in some cases, when combined with certain aspects of certain embodiments of the present disclosure, the combination is novel. FIG. 1A illustrates a printed circuit board having laser-micromachined traces 102, where a burr 104 has been created on the traces by the laser micromachining process. As shown, the laser-micromachined traces 102 are formed on an insulating substrate 106 that is part of the printed circuit board. FIG. 1B illustrates the configuration of a known electrolytic deburring process. The process includes a laser-micromachined PCB including an anode 108 and a cathode 110. Also included is an electrolyte 112, a power source 114, and electrical connections 116. FIG. 1C shows that electrical connections 116a are formed only to the outer edge traces 102a, while the isolated traces 102b are electrically disconnected from each other and from the outer edge traces (shown schematically in FIG. 1C). In FIG. 1C, the power source 114 is turned on, current is flowing through the outer edge traces 102a, and the traces are the anodes 108. FIGS. 1D and 1E show that when a voltage is applied to perform electrolytic deburring, electropolishing, or PeP, only the burrs 104a on the outer edge traces 102a of the laser-micromachined PCB traces are deburred, while the burrs 104b on the isolated traces 102b are not. FIGS. 1D and 1E show the results of applying a voltage to perform electrolytic deburring, electropolishing, or PeP. Only the burrs 104a present on the outer edge traces 102a of the laser micromachined PCB traces are deburred, while the burrs 104b present on the isolated traces 102b are not deburred. Figure 1F shows that conventional electrical deburring processes are not suitable for deburring laser micromachined PCB traces.This is because the isolated traces 102b cannot be deburred using this process, only the outer edge traces 102a are deburred.

[0044] In one embodiment, a novel process for deburring laser etched or laser micromachined PCB traces (eg, deburring electrically isolated PCB traces) is presented.

[0045] In one embodiment, the method comprises the following steps.

[0046] In the first step, PCB traces are formed as a metal-insulator laminate on an insulating layer 206 by patterning the top metal layer using a laser micromachining process. The trace width 203 is determined by the laser tool path, and the trace spacing 205 is determined by the laser spot size used in the laser micromachining process. A smaller spot size allows for closer trace spacing, while a larger spot size allows for faster etching rates by varying the spot size in real time. Laser etching or laser micromachining processes can be used to form PCB traces 202 on a variety of insulating layer 206 substrates, including FR4, polyimide, glass, ceramic, and silicon.

[0047] In the second step, as shown in FIG. 2B, a conductive coating layer (thin film) 207 is deposited on the laser-micromachined PCB. The conductive coating layer (thin film) 207 can be selected from any suitable conductive material selected from the group consisting of copper, liquid metal ink, graphite, etc. The conductive coating layer (thin film) 207 can be deposited on the PCB traces 202 and the insulating layer 206 substrate using a deposition process selected from the group consisting of electroless plating, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, spray coating, dip coating, or similar methods. The conductive coating layer (thin film) 207 can be selected from the same material as the PCB traces 202 or from a different conductive material. The conductive coating layer (thin film) 207 electrically connects all or most of the isolated PCB traces 202b and provides electrical connection (or current flow) for electrolytic deburring. The deposited conductive coating layer (thin film) 207 may not need to be coated uniformly on the laser micromachined printed circuit board if the conductive material overlaps sufficiently to ensure electrical connection with all or most of the traces 202, especially the isolated PCB traces 202b.

[0048] In a third step, anodic electrical connections are made to the conductive coating layer (thin film) 207 and electrolytic deburring is performed (see, for example, FIG. 2C). Electrical connections to the conductive coating layer (thin film) 207 can be made at multiple locations using an electrode array across the entire PCB area. This ensures a uniform voltage across the conductive coating layer (thin film) 207 and a low resistance electrical connection to the traces 202 and the separate PCB traces 202b.

[0049] In the fourth step, electrolytic deburring is performed using electrolytic deburring (e.g., see FIG. 2D), plasma electrolytic polishing (e.g., see FIG. 2F), or electrolytic polishing. Electrolytic deburring or electrolytic polishing processes are used when the conductive coating layer (thin film) 207 is selected from the same material as the printed circuit board traces 202. Electrolytic deburring is used when the burrs 204 are large, and electrolytic polishing is used when the burrs 204 are comparable in surface roughness to the printed circuit board traces 202.

[0050] In one embodiment, plasma electrolytic polishing is used when the material of the conductive coating layer (thin film) 207 is different from the material of the PCB trace 202, or when the resistance of the conductive coating layer (thin film) 207 or the PCB trace 202 is higher than the resistance of the electrolytic deburring or electropolishing process. Plasma electrolytic polishing uses a higher voltage than electrolytic deburring or electropolishing, and therefore has less effect on the resistance change of the conductive coating layer (thin film) 207 compared to the electrolytic deburring and electropolishing processes. In addition, plasma electrolytic polishing does not cause anodic dissolution of the anode (e.g., the traces of a printed circuit board), so it can achieve high selectivity for removing the burr 204 without etching the conductive coating layer (thin film) 207. Furthermore, plasma electrolytic polishing uses an environmentally friendly electrolyte 212.

[0051] In one embodiment of this method, an electrical island deburring voltage waveform is used.

[0052] For certain conductive coating materials, the conductive coating layer (thin film) 207 may be partially removed by chemical reaction between the electrolyte 212 used for deburring and the conductive coating layer (thin film) 207, or by anodic dissolution during the electrolytic deburring or electropolishing process (see, for example, FIG. 2G). The amount of thickness reduction of the conductive coating layer (thin film) 207 can be estimated by measuring the resistance of the conductive coating layer (thin film) 207 or by using optical inspection.

[0053] For such materials, the thickness of the conductive coating layer (thin film) 207 can be increased by reversing the voltage of the electrochemical cell and electroplating on the conductive coating layer (thin film) 207, as shown schematically in FIG. 2H. During the electroplating cycle, cell parameters such as voltage, current, duration, electrode configuration, and electrolyte flow rate are set to maximize uniform electroplating of the conductive coating layer (thin film) 207. Meanwhile, during the deburring cycle, these parameters are set to maximize selective electrochemical etching of the burr 204 without etching away the conductive coating layer (thin film) 207. For example, during the electroplating cycle, a low voltage and wide electrode spacing can be used to achieve uniform plating, while during electrolytic deburring, a high voltage and narrow electrode spacing can be used to perform plasma electropolishing to selectively remove the burr 204. Electroplating can also be performed in a separate electrochemical cell using a different electrolyte 212 than the deburring electrolyte 212.

[0054] The deburring current is monitored to determine whether the burrs 204 have been removed. The current increases as the number of burrs 204 increases and gradually decreases as the burrs 204 are removed. When all or most of the burrs 204 have been removed, the deburring current saturates to a low value. Alternatively, an optical inspection system within the electrochemical cell can be used to determine whether all or most of the burrs 204 have been removed. After deburring, the burrs 204 can be inspected using other inspection techniques and devices, such as optical profilometers, scanning electron microscopes, and X-rays, to confirm that all or most of the burrs 204 have been removed. If burrs 204 remain, the PCB can be deburred again.

[0055] In the fifth step, after all or most of the burrs 204 have been removed (see, for example, FIG. 2I), the conductive coating layer (thin film) 207 is removed using flash wet chemical etching, plasma etching, or a similar method to electrically insulate the PCB traces 202 (see, for example, FIG. 2J). Because the conductive coating layer (thin film) 207 is much thinner than the thickness of the PCB traces 202, it is etched away more quickly without significantly affecting the PCB traces 202. Alternatively, the thickness of the conductive coating layer (thin film) 207 can be reduced by uniform anodic dissolution prior to etching. FIG. 2K shows the PCB traces 222 after the burrs have been removed. The gaps G between the PCB traces can be filled with an insulating material.

[0056] In some embodiments, with certain conductive materials or deposition processes, the deposited conductive coating layer (thin film) 207 may not be applied uniformly on the laser micromachined PCB, leaving some PCB traces 202 electrically isolated. In such situations, multiple applications of the conductive coating layer (thin film) 207 material followed by electrolytic deburring can be repeated to cover all or most of the PCB traces 202.

[0057] In one embodiment, the fourth step involves removing the burrs 204 by electrical deburring.

[0058] In some embodiments, the fourth step involves removing burrs 204 using an electropolishing process.

[0059] In one embodiment, in the fourth step, the burrs 204 are removed using a PeP process (see, for example, FIG. 2F). The voltage used in PeP is higher than the voltage used in an electrolytic deburring or electropolishing process. This high voltage creates a plasma skin around the burrs 204, which is then plasma etched. The burrs 204 have sharp edges that generate a higher plasma discharge than the smooth areas of the PCB traces 202, and are therefore selectively etched.

[0060] In one embodiment, a combination of plasma electrolytic polishing, electrolytic deburring, and electrolytic polishing is used to remove burrs 204 from laser etched or laser micromachined PCB traces 202.

[0061] In an embodiment, for certain materials of the conductive coating layer (thin film) 207, the conductive coating layer (thin film) 207 may be partially removed by a chemical reaction between the conductive coating layer (thin film) 207 and the electrolyte 212 used for deburring or by anodic dissolution caused by the electrolytic deburring process. For such materials, the thickness of the conductive coating layer (thin film) 207 can be increased by reversing the voltage of the electrochemical cell and electroplating on the conductive coating layer (thin film) 207.

[0062] A positive cycle of the voltage of the power supply 214 removes burrs from the PCB trace 202, and a negative cycle of the voltage of the power supply 214 uniformly deposits electroplating material onto the conductive coating layer (thin film) 207. Note that deburring involves selective etching of the burrs 204, while electroplating involves uniform deposition of thin film conductive material.

[0063] In an electrically isolated microstructure deburring technology cycle, electrochemical cell parameters such as voltage, current, pulse width, voltage or current waveform, electrode configuration, electrolyte flow rate, electrolyte concentration, and bath temperature are set to maximize deburring effectiveness (e.g., selectively remove burrs 204 without etching other portions of trace 202). In contrast, in an electroplating cycle, these parameters are set to ensure uniform electroplating. An example of such parameter changes would be using a higher voltage and electrodes closer together for deburring and a lower voltage and electrodes farther apart for uniform electroplating.

[0064] In one embodiment, if the electrolyte 212 used for deburring is different from the electrolyte 212 used for electroplating, the laser micromachined printed circuit board can be moved to a separate cell for electroplating. After electroplating, the PCB is returned to the deburring cell for the electroplating process.

[0065] 2A-2K illustrate an example implementation of these steps. Figure 2A shows a printed circuit board having laser-micromachined traces 202, where the traces 202 have laser-micromachined burrs 204, according to one embodiment of the present disclosure. The laser-micromachined traces 202 include outer edge traces 202a and electrically isolated aisle traces 202b. The PCB includes an insulating layer 206.

[0066] 2B shows a conductive coating layer (thin film) 207 deposited on the laser micromachined PCB 200, including deposited on the traces 202, burrs 204, and insulating layer 206. The conductive coating layer (thin film) 207 can be deposited using PVD, CVD, ALD, electroless copper, liquid metal ink, or similar methods according to certain embodiments of the present disclosure.

[0067] FIG. 2C illustrates electroplating being used to increase the thickness of the conductive coating layer (thin film) 207 or to deposit a different conductive coating on top of an already deposited layer, according to an embodiment of the present disclosure.

[0068] 2D illustrates electrolytic deburring performed by applying a positive voltage to the PCB trace 202 (acting as the anode) and a negative voltage to the cathode, according to an embodiment of the present disclosure. The voltage value depends on the selected deburring material and electrolyte 212. A thin conductive coating 207 provides electrical connection to all or most of the isolated traces 202b for electrolytic deburring, electropolishing, or PeP processing.

[0069] FIG. 2E is a schematic diagram illustrating deburring of all or most of the PCB traces 202 using electro-deburring or electro-polishing, according to an embodiment of the present disclosure.

[0070] 2F illustrates an alternative or combined process to that shown in FIG. 2E, in which burrs 204 may also be removed using a plasma electropolishing process according to certain embodiments of the present disclosure. A high voltage power supply 215 provides a voltage used for PeP that is higher than the voltage used for the electrolytic deburring or electropolishing process. The burrs have sharp edges, and the high voltage generates a plasma discharge 217 around the burrs 204, causing the burrs to be plasma etched.

[0071] 2G illustrates an electrolytic deburring process that selectively etches burrs 204 without significantly affecting other components, according to certain embodiments of the present disclosure. For certain conductive coating materials, the electrolytic deburring process can reduce the conductive coating thickness of conductive coating layer (thin film) 207, as shown schematically in FIG. 2G. FIG. 2G illustrates partially etched-away burrs 204a and reduced conductive coating material 207a.

[0072] 2H illustrates electroplating with the voltage of power supply 214 reversed to increase the thickness of the coating. This results in a thicker coating 207b and renewed conductive coating. Note that, according to certain embodiments of the present disclosure, the values ​​of voltage, current, and other electrochemical cell parameters for electroplating are different from those for electrolytic deburring. In this example, trace 202 or coating 207b is the cathode, and PCB 210 is the anode.

[0073] 2I is a schematic diagram illustrating the completion of an electrolytic deburring process, in which voltage and polarity are varied to achieve electrolytic deburring, electropolishing, or plasma electropolishing, according to certain embodiments of the present disclosure, and trace 202 is either nearly completely deburred or completely deburred.

[0074] FIG. 2J illustrates that after the electrically isolated microstructure deburring technology process, the conductive coating layer (thin film) 207 is removed using chemical etching, including the use of an etchant 220, in accordance with an embodiment of the present disclosure.

[0075] FIG. 2K is a schematic diagram illustrating an electronic island deburred PCB 222 having deburred traces 202 according to an embodiment of the present disclosure.

[0076] In some embodiments, multilayer substrate fabrication is used using the processes described above. In some embodiments, multilayer substrate fabrication is used using the laser micromachining and electrolytic deburring processes described above.

[0077] For example, a multilayer printed circuit board can be manufactured according to the procedure shown in FIGS. 3A to 3O.

[0078] 3A illustrates a first conductor-insulator laminate for use as a PCB laminate. According to an embodiment of the present disclosure, the first conductor-insulator laminate includes a first conductive layer 302. The first conductive layer 302 can be a conductive metal (e.g., copper), a conductive polymer, etc., deposited on an insulating material 304. The insulating material 304 can be selected from ceramic, FR4, glass, etc.

[0079] 3B shows PCB traces 306 and alignment marks 308 formed on conductive layer 302 using a laser micromachining and subsequent electrically isolated microstructure deburring technology process in accordance with an embodiment of the present disclosure. The PCB layer is a composite of conductive layer 302, insulating material 304, and PCB traces 306, and may be referred to herein as the first PCB layer.

[0080] FIG. 3C shows that the gaps G between the PCB traces 306 are filled with one or more of a dielectric 310 and / or insulator material 310 .

[0081] 3D shows an upper conductor-insulation layer (second PCB layer) formed on the first, or preceding, conductor-insulation layer. The second PCB layer includes an upper conductive layer 302′, an upper insulating layer 304′, and an upper layer cutout 312 positioned to cover an alignment mark 308 of the lower conductor-insulation laminate. The upper conductor-insulation layer is stacked on top of the lower conductor-insulation layer. In this case, the second PCB layer is stacked on top of the first PCB layer, according to an embodiment of the present disclosure.

[0082] 3E illustrates a via 314 that may be drilled using a laser micromachining process according to certain embodiments of the present disclosure. The via 314 terminates in the conductive layer 302 of the first PCB layer and is used to form an electrical connection between the upper and lower conductor-insulation layers. In the illustrated embodiment, the via 314 provides a conductive path between the upper and lower conductive layers 302′ and 302. An electrolytic deburring process may also be used to remove burrs (not shown) from the via 314.

[0083] 3F illustrates a thin conductive seed layer 318 deposited over the via hole walls 314, the lower conductive layer 302, and the upper conductive layer 302′ in an embodiment of the present disclosure. The thin conductive seed layer 318 can be deposited using electroless plating, atomic layer deposition (ALD), or other deposition methods.

[0084] 3G illustrates an embodiment of the present disclosure in which electroplating is used to apply a thick conductive layer 320 to improve electrical conductivity over an initial thin conductive seed layer 318. The metal of the thick conductive layer 320 is deposited on the via walls and conducts electricity between the underlying first PCB layer and the overlying second PCB layer.

[0085] FIG. 3H shows that, according to an embodiment of the present disclosure, the top trace 306′ is formed using laser micromachining followed by electrically isolated microstructure deburring techniques, as previously described.

[0086] FIG. 3I illustrates gaps G' between overlying PCB traces 306' filled with dielectric and insulator material 324 according to an embodiment of the present disclosure.

[0087] Figures 3J-3N illustrate that subsequent PCB layers can be formed by repeating the steps described in Figures 3D-3H. According to certain embodiments of the present disclosure, vias 314 can also be drilled between multiple PCB layers, as shown in Figure 3K.

[0088] FIG. 3O illustrates the fully fabricated multi-layer substrate after removing excess areas including alignment marks 308 and overlying notches 312 according to an embodiment of the present disclosure.

[0089] In one embodiment, building a printed circuit board layer by layer using laser micromachining and electrically isolated microstructure deburring technology process includes the following steps:

[0090] The first step is to prepare a rigid or flex substrate consisting of a conductor-insulator dielectric (see, for example, the conductive layer 302 and insulating layer 304 shown in FIG. 3A). As previously mentioned, the conductive layer 302 can be made of a conductive material such as copper, and the insulating layer 304 can be made of an insulating material such as glass, FR4, or ceramic. The conductive layer 302 can be used to fabricate traces 306 by laser micromachining followed by electrolytic deburring.

[0091] The second step is to use laser micromachining to machine alignment marks 308 and machine traces 306 on the conductive layer 302. Then, an electrically isolated microstructure deburring technology process is used to deburr the traces 306 of the laser micromachined printed circuit board (see, for example, FIG. 3B). This layer is hereinafter referred to as the first PCB layer.

[0092] The third step involves filling the gaps G between the PCB traces 306 with a dielectric 310 (see, for example, the dielectric 310 shown in FIG. 3C). It is also possible to omit this step and provide air gaps between the PCB traces 306.

[0093] In a fourth step, a conductor-insulator laminate layer (a second PCB layer) with cutout windows 312 for alignment marks is laminated onto the first PCB layer (eg, as shown in FIG. 3D).

[0094] The fifth step is to align the design of the second PCB layer to the first PCB layer using the first PCB layer alignment marks 308 visible through the second PCB layer cutouts 312. Next, a laser micromachining process is used to form one or more vias 314 in the second PCB layer. The vias 314 terminate in a conductive layer of the first PCB layer (see, e.g., hole stop 316), as shown schematically in FIG. 3E.

[0095] The sixth step involves applying a thin conductive layer 318 over the second PCB layer and vias 314 while masking the alignment marks 308 on the first PCB layer (see, e.g., FIG. 3F). The thin conductive layer 318 can be composed of any conductive material (e.g., copper, liquid metal ink, conductive polymer, etc.) and can be deposited using various deposition processes, such as electroless plating, PVD, sputtering, CVD, ALD, spin coating, spray coating, and dip coating. Electroplating can also be used to apply a thick conductive layer 320 over the thin conductive layer 318 (see FIG. 3G) to increase the conductance of one or more vias 314. The metal deposited on the one or more via walls forms an electrical connection between the first PCB layer and the second PCB layer (see, e.g., via filling 322).

[0096] The seventh step involves laser micromachining traces 306' on the conductive layer 320 above the second PCB layer and removing burrs (not shown) from the laser-micromachined printed circuit board traces using a disclosed electrically isolated microstructure deburring technology process (see, e.g., FIG. 3H). Also shown in FIG. 3I is a dielectric 324 that can fill gaps G between the traces. Subsequent overlying PCB layers are constructed by repeating the steps shown in FIGS. 3J-3N. During layer construction, one or more vias 314 can be formed between layers, as shown in FIG. 3K. FIG. 3N illustrates the layer configuration for a four-layer board. Also shown in FIG. 3N is a PCB with deburred traces 326.

[0097] In an eighth step, once the layer build is complete, the PCB is cut to size and the areas containing the alignment marks 308 are removed. Figure 3O shows the completed ultra-high density multi-layer PCB after the PCB has been cut to size and the areas containing the alignment marks 308 are removed.

[0098] In a conventional PCB stack-up process, each new upper layer is aligned with an alignment mark placed on the top layer of the PCB stack. As a result, layer alignment errors increase as the number of layers increases. However, in the disclosed method, all layers can be aligned with the same alignment mark 308 placed on the first layer as a reference. As a result, errors do not accumulate as the number of layers increases.

[0099] In one embodiment, PCB traces 306, 306', . . . 306n with air gaps are used.

[0100] In one embodiment, the step shown in FIG. 3C is omitted, and PCB traces 404, 404′, ... 404n are created with air gaps 402 between them (see, for example, FIG. 4). In this example, the thermal and electrical issues associated with the dielectric 310 used to fill the gaps 402 between the PCB traces 404, 404′, ... 404n are eliminated. Furthermore, air has the lowest dielectric constant, resulting in faster data propagation speeds in the PCB traces 404, 404′, ... 404n. These PCBs with air gaps between the traces 404, 404′, ... 404n are suitable for high-density interconnection in heterogeneous integration of chiplets.

[0101] In one embodiment, a layer-by-layer stacking method (see Figure 5) is used on both sides of the core laminate.

[0102] In one embodiment, vias 314 are drilled into the conductive insulator laminates before lamination. This allows for various via shapes. In FIG. 3D, the conductive insulator laminates (302', 304') are laminated first, and then the vias are drilled in FIG. 3E. This method allows for vias to be drilled only from the top, resulting in vias that are wide at the top and narrow toward the bottom (not shown). The vias shown have vertical walls. However, if vias 314 are drilled first into the conductive insulator laminates 302', 304', drilling from both the top and bottom allows for vias 314 to be created that are 1) wide at the top and narrow at the bottom, or 2) narrow at the bottom and wide at the top. After vias 314 are drilled, they are laminated. In summary, in some embodiments, step FIG. 3D (laminate first) precedes step FIG. 3E (drill vias then), and in other embodiments, step FIG. 3E (drill first) precedes FIG. 3D (laminate then).

[0103] In one embodiment, the disclosed laser etching or laser micromachining followed by electrolytic deburring is combined with conventional wet chemical etching or semi-additive processes. Conventional wet chemical etching or semi-additive processes are first used to form printed circuit board traces 404, 404', ... 404n with wide trace widths and spacings. For traces that are too small to be fabricated using conventional printed circuit board manufacturing processes, the traces are left connected, and then these small traces are formed using laser micromachining and electrolytic deburring processes. This allows for the creation of large traces using conventional printed circuit board manufacturing processes, and then the creation of small traces using the laser micromachining process of the present invention. This combines the high throughput of existing technology with the benefits of narrow trace widths and spacings achieved through the features of the present invention.

[0104] Additionally, using laser micromachining techniques, narrower trace widths and spacing, the traces 404, 404', . . . 404n can be machined and deburred using an electrically isolated microstructure deburring technology process.

[0105] Additionally, multilayer boards can be manufactured using some of the methods disclosed herein or standard printed circuit board manufacturing processes.

[0106] For example, Figure 4 illustrates a multi-layer board with air gaps 404 between traces 402 for high-speed applications, according to certain embodiments of the present disclosure. Air has the lowest dielectric constant, enabling high data propagation speeds in PCB traces. These PCBs are suitable for high-density interconnects in heterogeneous integration of chiplets. Figure 4 also illustrates vias 406 connecting the traces, insulating layers 408 between the traces, and a printed circuit board core 410.

[0107] 5 illustrates an embodiment of a PCB core with layers of PCB laminated to both sides and gaps filled with dielectric material 502. In the example of FIG. 5, the vias include machined vias 504 that provide electrical continuity through core 510 and laser micromachined vias 506 that provide electrical continuity through insulating layer 508.

[0108] An advantage of the process described herein is that while conventional processes can be used for low-density printed circuit board traces and layers, the disclosed printed circuit board manufacturing process can be used for manufacturing high-density traces and layers, such as manufacturing printed circuit boards for mounting electrical circuit components with or without high-density ball grid array (BGA) fanout. Existing printed circuit board manufacturing processes can be used to pattern the low-density printed circuit board traces and layers, while laser micromachining can be used to pattern the BGA pads and high-density traces and layers.

[0109] For example, Figures 6A through 6M illustrate the deposition of dielectric and conductive layers and the use of laser micromachining, followed by deburring techniques to define PCB traces with electrically isolated microstructures, showing the individual process steps for manufacturing a printed circuit board, starting with the step in Figure 6A and ending with the step in Figure 6M, according to one embodiment of the present disclosure.

[0110] 6A illustrates a conductor-insulator laminate for use as a laminate substrate in a printed circuit board, according to an embodiment of the present disclosure, in which a conductive layer 602 made of a metal (e.g., copper), a conductive polymer, etc. is formed on an insulating material 604 made of ceramic, FR4, glass, etc.

[0111] FIG. 6B illustrates how laser micromachining followed by deburring of electrically isolated microstructures can be used to create PCB traces 606 and alignment marks 608 on conductor insulators of either rigid or flex substrates, according to an embodiment of the present disclosure.

[0112] 6C illustrates depositing a dielectric material onto the previous layer (PCB traces) to form a dielectric layer 610 (e.g., liquid polyimide) while masking alignment mark areas 608, according to an embodiment of the present disclosure. This masking includes providing windows 612 to expose alignment marks 608. When building a PCB stack, an insulating layer (also called a dielectric) 610 is deposited onto the previous traces to separate them from the conductive layer traces that are applied to the dielectric layer 610 in subsequent layers of the PCB stack.

[0113] 6D illustrates the use of laser micromachining to drill a via 614, ensuring that the hole stops at the underlying PCB trace 606 where electrical connection is required, according to an embodiment of the present disclosure. A first-layer alignment mark 608 visible through a window 612 in the dielectric layer 610 is used to align the via 614 with the bottom layer and determine the location of the via 614 in the upper conductive layer 610.

[0114] 6E shows the deposition of a conductive coating layer (thin film) 616 (or seed layer) on the dielectric layer 610 and the via hole 614 while masking the alignment mark 608 area. Various deposition methods can be used to deposit the conductive layer 618, such as electroless plating, PVD, sputtering, CVD, ALD, spin coating, spray coating, and dip coating.

[0115] FIG. 6F illustrates electroplating being used to plate a conductive material 618 onto the seed layer 616 to increase the thickness of the conductive coating layer (thin film) 616, according to an embodiment of the present disclosure.

[0116] FIG. 6G illustrates how laser micromachining followed by deburring of electrically isolated microstructures can be used to create PCB traces 620 on the conductive layer 618 deposited in the previous step.

[0117] 6H-6L illustrate building subsequent layers of a PCB by repeating the steps shown in FIGS. 6C-6G according to an embodiment of the present disclosure.

[0118] FIG. 6H illustrates depositing a dielectric material 622 (such as liquid polyimide) over the previous layer (PCB trace layer) while masking the alignment mark 608 area, according to an embodiment of the present disclosure.

[0119] Figure 61 shows the use of laser micromachining to drill vias 624. Note that according to an embodiment of the present disclosure, during the process of stacking layers, vias 624 are formed between multiple layers, as shown in Figure 61.

[0120] FIG. 6J illustrates depositing a conductive coating layer (thin film) 626 (or seed layer) over the dielectric layer 626 and the holes of the vias 624 while masking the alignment mark areas, according to an embodiment of the present disclosure.

[0121] 6K illustrates a method of electroplating a conductive material 628 onto a seed layer 626 to increase the thickness of the conductive layer, according to an embodiment of the present disclosure. The layer configuration of a three-layer printed circuit board is shown schematically in FIG. 6L.

[0122] Figure 6M shows that after the layer build is complete, the printed circuit board is cut to size to remove the area containing alignment mark 608 and overlying alignment cutout 612. Figure 6M is a schematic representation of a completed ultra-high density multilayer printed circuit board in accordance with an embodiment of the present disclosure.

[0123] In one embodiment, the PCB may comprise a liquid polymer as a dielectric layer and an electrodeposited conductive material on one or more PCB trace layers. In this example, the conductive layer is an electrodeposited conductive material and the insulating layer is a liquid polymer. The process of building a multilayer board includes the following steps:

[0124] First, the process uses laser micromachining followed by electrically isolated microstructure deburring techniques to create PCB traces 606 and alignment marks 608 on conductor insulators formed as rigid or flex substrates, as shown in Figure 6B.

[0125] Second, the process involves depositing a polymer insulator and dielectric material film 610 (such as liquid polyimide) over the previous layer while masking the alignment mark 608 area, as shown in Figure 6C.

[0126] Third, the process includes drilling one or more vias 614 using laser micromachining so that the vias 614 terminate in the PCB trace layer where electrical connection is required (see, for example, FIG. 6D ). The first layer alignment marks visible through the cutouts 612 in the dielectric layer 610 are used to align the via hole design file to the alignment marks 608 on the bottom layer of the printed circuit board structure to determine the location of the vias 614.

[0127] Fourth, as shown in FIG. 6E, a conductive coating layer (thin film) 616 (or seed layer) is deposited on the dielectric layer 610 and vias 614 while masking the alignment mark 608 area. As mentioned above, various deposition methods can be used to deposit the conductive layer, such as electroless plating, PVD, sputtering, CVD, ALD, spin coating, spray coating, and dip coating. In some cases, as shown in FIG. 6F, an electroplating method is used to plate a conductive material 618 on the seed layer 616 to increase the thickness of the conductive layer. In some examples, as shown in FIG. 6G, laser micromachining is followed by electrolytic deburring to form printed circuit board traces 620 on the conductive layer deposited in the previous step. To stack subsequent PCB layers, the steps shown in FIGS. 6C to 6G are repeated. Note that during the layer stacking process, vias 614 can be formed between multiple layers, as shown in FIG. 6G.

[0128] The layer structure of a three-layer printed circuit board is shown schematically in Figure 6L. Once the layer structure is complete, the PCB is cut to size and the area containing the alignment marks 608 is removed. Figure 6M shows the completed ultra-high density multi-layer board. It will be appreciated that this process can also be used to form PCB layers on both sides of a high density multi-layer board core, as shown in Figure 7. In this case, the core 700 will be one or two layers thick of insulation material 604 for a single-sided printed circuit board construction.

[0129] In some embodiments, double-sided printed circuit boards (Double-Sided Boards) are used. For example, Figure 7 illustrates PCB layers being laminated on both sides of a core 710 in accordance with some embodiments of the present disclosure. The PCB layers include traces 702, laser micromachined vias 704, machined vias 706, dielectric 708, and core 710. Figure 7 also illustrates PCB layers being laminated on both sides of core 710 by depositing dielectric and conductive layers and forming PCB traces 702 by laser micromachining followed by electropolishing in accordance with some embodiments of the present disclosure.

[0130] 8A-8F show individual process steps for manufacturing a high density double-sided printed circuit board 800, with the procedure starting with the step in FIG. 8A and ending with the step in FIG. 8F.

[0131] 8A illustrates starting with a double-sided conductor-insulator-conductor rigid or flexible laminate according to one embodiment of the present disclosure. The double-sided conductor-insulator-conductor laminate includes a first conductive layer 802, a second conductive layer 804, and an insulating layer 806 disposed between the conductive layers. The first conductive layer 802 is laminated to a first side of the insulating layer 806. The second conductive layer 804 is laminated to a second side of the insulating layer 806, opposite the first side of the insulating layer.

[0132] 8B shows the use of laser micromachining to drill via 808. Burrs (not shown) are removed from via 808 using electrolytic deburring, as described in other embodiments.

[0133] 8C illustrates the deposition of a conductive coating layer (thin film) 810 (or seed layer) on each of the first conductive layer 802, the second conductive layer 804, and the via 808. Various deposition methods can be used to deposit the conductive coating layer (thin film) 810, such as electroless plating, PVD, sputtering, CVD, ALD, spin coating, spray coating, and dip coating.

[0134] FIG. 8D illustrates the use of electroplating to plate a conductive material 812 onto the conductive coating layer (thin film) 810, increasing the thickness of the conductive coating layer (thin film) 810 and filling the via 808.

[0135] FIG. 8E illustrates how laser micromachining followed by deburring of electrically isolated microstructures can be used to create PCB traces 814 and alignment marks 816 on a double-sided printed circuit board 800.

[0136] Figure 8F illustrates cutting the printed circuit board to size and removing the area containing the alignment marks 816. Figure 8F is a schematic illustration of a completed ultra-high density two-layer printed circuit board 800, according to an embodiment of the present disclosure.

[0137] In one embodiment, a high-density two-layer printed circuit board 800 is fabricated using the following process, as shown in FIGS. 8A-8F. First, as shown in FIG. 8B, vias 808 are drilled in a conductor-insulator-conductor rigid or flexible laminate using laser micromachining. As previously described, burrs (not shown) are removed from the vias 808 using an electrically isolated microstructure deburring technique. Next, as shown in FIG. 8C, a conductive coating layer (thin film) (or seed layer) 810 is deposited. Various deposition methods can be used to deposit the conductive coating layer (thin film) 810, including electroless plating, PVD, sputtering, CVD, ALD, spin coating, spray coating, and dip coating. Alternatively, as shown in FIG. 8D, electrodeposition can be applied to plate additional conductive material 812 on top of the seed layer 810 to increase the thickness of the conductive seed layer 810 and fill the vias 808. The vias 808 electrically connect the two conductive layers 802, 804 of the conductor-insulator-conductor laminate 800. Next, using the laser micromachining techniques previously described, followed by electrolytic deburring, PCB traces 814 and alignment marks 816 are formed on both the first conductive layer 802 and the second conductive layer 804, as shown in Figure 8E. Finally, the printed circuit board 800 is cut to size, and the areas containing the alignment marks 816 are removed. Figure 8F shows the completed ultra-high density two-layer printed circuit board 800.

[0138] In one embodiment, a multi-layer printed circuit board with mechanical or laser vias 808 is used.

[0139] For example, double-sided printed circuit boards 800 are fabricated as described in the embodiment shown in Figures 8A-8F. These double-sided printed circuit boards 800 are stacked to create a multi-layer board. Vias 808 are formed to electrically connect each PCB layer.

[0140] 9A through 9G illustrate the individual process steps for fabricating a multilayer board 900 by stacking double-sided printed circuit board laminates, with the sequence beginning with the step in FIG. 9A and ending with the step in FIG. 9G.

[0141] Figure 9A shows an alternative step in creating the double-sided board 900 described in Figure 8 and using a dielectric 904 to fill the gaps between the traces 902. For layers using low density PCB traces 902, the traces 902 can also be created using conventional printed circuit board manufacturing processes. Figure 9A shows a laminated double-sided printed circuit board.

[0142] 9B shows a four-layer board 900 made by stacking two double-sided printed circuit boards. Between the first and second printed circuit boards is either an insulating layer 906 or a dielectric layer 906. An adhesive layer (not shown) may be applied to either the insulating layer 906 or the dielectric layer 906 to bond the first and second printed circuit boards.

[0143] 9C illustrates the application of a protective coating or film 910 to both sides of the joined first and second printed circuit boards, i.e., the build-up substrate. The protective coating or film 910 is applied to mask one or more selected areas of the exterior surface of the build-up substrate, allowing for the selective application of thin film conductors 916, as described below.

[0144] 9D illustrates drilling one or more vias 912, 912′ using laser micromachining or mechanical milling, as previously described. It will be appreciated that one or more vias 912, 914 may extend into the build-up substrate to provide electrical conductivity between conductive layers on a layer of a first PCB, or through the build-up substrate to provide electrical conductivity between a layer of a first PCB and a layer of a second PCB.

[0145] 9E illustrates the deposition of a conductive coating layer (thin film) (or seed layer) 916. The deposited conductive coating layer (thin film) 916 covers the walls of the holes of one or more vias 912, 912′, as well as a protective coating 920, according to an embodiment of the present disclosure.

[0146] 9F illustrates electroplating a conductive material onto the seed layer 916 to fill the vias 912, 912′ according to an embodiment of the present disclosure. The protective coating 920 is then removed, leaving the conductive material only in the vias 912, 912′. The vias 912, 912′ provide electrical connections between the PCB trace layers 904.

[0147] Figure 9G illustrates cutting the printed circuit board to size and removing the area containing the alignment marks 816, according to an embodiment of the present disclosure. Figure 9G schematically illustrates the completed ultra-high density two-layer board 900.

[0148] In this embodiment, multiple double-sided boards 800 are first fabricated using the process steps described in the previous embodiment shown in Figures 8A-8F, and a dielectric 906 is used to fill the gaps between the traces. For layers using low-density PCB traces 902, the traces 902 can also be fabricated using conventional printed circuit board manufacturing processes. Next, as shown in Figure 9A, the double-sided boards 800 are stacked using a dielectric 904 and a dielectric and adhesive layer 906. Figure 9B shows a four-layer board 900 fabricated by stacking two double-sided printed circuit boards 800. Then, as shown in Figure 9C, a protective coating 910 or film is applied to both sides of the PCB stack. Next, vias 912, 912' are drilled using laser micromachining (e.g., laser micromachined vias 912) or mechanical milling (e.g., mechanically milled vias 912'), as shown in Figure 9D. Fourth, a conductive coating layer (thin film) 916 is deposited on the opposing outer surfaces of the PCB stack. A conductive coating layer (thin film) 916 can cover not only the walls of the via holes but also the protective coating 910, as shown in FIG. 9E. In this embodiment, as described above, electrodeposition can also be used to plate additional conductive material onto the seed layer and fill the vias 912, 912′. Next, as shown in FIG. 9F, the protective coating 920 is removed, leaving the conductive material only in the vias 912, 912′. The vias 912, 912′ provide electrical connections between selected PCB trace layers 902. Finally, the PCB 900 is cut to size, and the area containing the alignment marks 920 is removed. FIG. 9G shows the completed ultra-high density four-layer board 900 after the printed circuit board has been cut to size and the area containing the alignment marks 920 has been removed.

[0149] In some embodiments, printed circuit boards with three-dimensional wiring can also be fabricated.

[0150] For example, consider a printed circuit board with three-dimensional wiring. First, a thin film layer of conductive material 916 is embossed to form the desired three-dimensional shape. Next, the conductive material sheet with the three-dimensional structure is attached or laminated onto an insulating substrate. Finally, laser micromachining is used to process the printed circuit board wiring into the embossed shape, forming the three-dimensional printed circuit board wiring. Burrs created during the laser micromachining process are then removed using a deburring technique for electrically isolated microstructures.

[0151] Conventional printed circuit board manufacturing processes are limited to creating two-dimensional printed circuit board traces. However, the printed circuit board manufacturing process disclosed in this example can be used to manufacture printed circuit boards with three-dimensional traces. Such printed circuit boards can be used to interconnect chiplets in three-dimensional space.

[0152] In one embodiment, a high-density, high-current-carrying printed circuit board is used. For example, a method for manufacturing a printed circuit board with a wiring thickness of more than 100 μm is described. In this method, wiring with a thickness of more than 100 μm is laminated on an insulating substrate such as FR4, glass, or ceramic. Next, laser micromachining is used to create gaps with a high aspect ratio (10:1 to 20:1) between the wiring. A similar process can be used to manufacture multilayer boards.

[0153] In conventional PC manufacturing processes, etching the traces on a 250-μm-thick printed circuit board using wet chemical etching results in 250-μm gaps between the traces, resulting in low wiring density. However, using the process described in this example, it is possible to laser micromachine the traces on a 100-μm-to-250-μm-thick printed circuit board with trace spacing of just 5-μm to 10-μm, resulting in high-density, high-current-carrying printed circuit boards. These PCBs are particularly useful as substrates for ASICs (application-specific integrated circuits), which use both high-density and high-current-carrying traces.

[0154] Recall that burrs have been a significant obstacle to reducing the line widths and spacings of printed circuit board traces formed using laser micromachining. The methods and systems disclosed herein enable burr removal, thereby enabling the formation of fine line widths and spacings of printed circuit board traces by laser micromachining. By enhancing the laser micromachining process and using the disclosed electrically isolated microstructure burr removal process, sub-micrometer line widths and spacings can be readily achieved.

[0155] In some embodiments, ultra-high density, small size PCBs can be used as substrates for advanced semiconductor packaging such as System-in-Package (SiP), heterogeneous integration of chiplets, fan-out packaging, etc. Additionally, small size PCBs can be used in applications requiring controlled impedance routing such as space-constrained devices like mobile and wearable devices, 5G or 6G applications, modules, and high density PCB flex cables.

[0156] The electrically isolated microstructure deburring technology process disclosed herein can be used to deburr island structures found in other applications, such as MEMS devices, microfluidics, and other microstructures fabricated using other microfabrication processes such as micromilling, EDM, etc.

[0157] Advantages of certain embodiments include the following advantages over known printed circuit board manufacturing processes: The disclosed printed circuit board manufacturing process can be used to manufacture ultra-high density printed circuit boards with wiring densities 10 times or more greater than those manufactured using conventional processes. The disclosed printed circuit board manufacturing process can also be used to manufacture PCB traces with vertical walls, thereby improving signal integrity. Conventional printed circuit board manufacturing processes result in PCB traces with trapezoidal cross sections, which can cause signal loss during high-speed signal propagation. The disclosed printed circuit board manufacturing process also has tighter manufacturing tolerances than current technology, allowing for better control of trace impedance used in high-speed data propagation applications, such as 5G and 6G.

[0158] The disclosed printed circuit board manufacturing process can be used to manufacture printed circuit boards using a variety of materials, including metals, alloys, and conductive polymers. Conventional printed circuit board manufacturing processes use wet chemical etching to form printed circuit board traces, and are currently limited to the manufacture of printed circuit boards using only copper. The disclosed printed circuit board manufacturing process can also manufacture printed circuit boards with air gaps between traces. Air has the lowest dielectric constant, allowing for the fastest data transmission through printed circuit board traces. Furthermore, the disclosed printed circuit board manufacturing process enables the manufacture of printed circuit board traces with high aspect ratios (10:1 to 20:1), enabling the manufacture of high-density, high-current-carrying printed circuit boards. The disclosed printed circuit board manufacturing process is also chemical-free and environmentally friendly, producing no hazardous chemical waste and significantly reducing water consumption. Conventional printed circuit board manufacturing processes use photolithography and wet chemical etching to create PCB traces, and various chemicals, such as photoresists, developers, and etchants, are used. These processes not only generate hazardous chemical waste but also consume large amounts of water and energy.

[0159] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific embodiments. It will be apparent that various changes may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. 1. A method for reducing one or more defects from a plurality of traces on a printed circuit board (PCB), comprising: The method includes the steps of: depositing a conductive coating layer (thin film) on at least a portion of a plurality of the traces formed on the PCB, the plurality of traces being electrically insulated from one another, and after the conductive coating layer (thin film) is deposited, the conductive coating layer (thin film) electrically connects at least a portion of the one or more defects on the traces; and applying a current of a first polarity to the conductive coating layer (thin film) to reduce or eliminate the one or more defects on the plurality of traces.

2. 10. The method of claim 1, The method further comprises applying a current of a second polarity to the conductive coating layer (thin film) to electroplate the conductive coating layer (thin film), thereby increasing the thickness of the conductive coating layer (thin film).

3. 3. The method of claim 2, applying a current of said first polarity to said conductive coating layer (thin film) to further reduce or eliminate said one or more defects on said plurality of traces.

4. 10. The method of claim 1, The method further comprises the step of removing the conductive coating layer (thin film) by etching or stripping.

5. 4. The method of claim 3, wherein at least some of the defects include burrs.

6. 1. An electrically isolated microstructure deburring (EID) process for reducing or eliminating one or more defects occurring on one or more traces formed on a substrate of a printed circuit board (PCB), comprising: the one or more wirings include at least some island-shaped wirings electrically isolated from each other; The EID process includes: depositing a conductive layer on the one or more printed circuit board traces, the conductive layer electrically connecting at least a portion of the one or more printed circuit board traces and at least a portion of the one or more defects; and passing an electrical current through the conductive layer to reduce or eliminate the one or more defects in the wiring of the one or more printed circuit boards.

7. 7. The process of claim 6, The process wherein the defect comprises a burr.

8. 8. The process according to claim 6 or 7, the conductive layer is deposited over a plurality of traces of the printed circuit board to electrically connect the plurality of traces.

9. A process according to any one of claims 6 to 8, comprising: The process, wherein the deposition of the conductive layer is performed by a method selected from electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, atomic layer deposition (ALD), liquid metal ink, or a combination thereof.

10. A process according to any one of claims 6 to 9, comprising: The process wherein applying an electric current to the conductive layer comprises at least one of electrolytic deburring, electropolishing, and plasma electropolishing.

11. A process according to any one of claims 6 to 10, comprising: the conductive layer is formed to a predetermined thickness to electrically connect the plurality of traces.

12. 12. The process of claim 11, The process wherein the predetermined thickness is determined based on the number of burrs, trace width, trace spacing, and deburring time.

13. A process according to any one of claims 6 to 12, comprising: The process is characterized in that the conductive layer is removed by etching after the electrolytic deburring step.

14. 14. The process of claim 13, The process wherein the conductive layer is configured to have a thickness substantially thinner than the traces of the printed circuit board.

15. A process according to any one of claims 6 to 14, comprising: The process further comprises the step of at least partially removing the conductive layer by applying the current and increasing the thickness of the conductive layer again by electroplating.

16. 16. The process of claim 15, A process characterized in that the electroplating step is carried out using an electrolyte different from that used for the electrolytic deburring.

17. A process according to any one of claims 6 to 16, comprising: A process comprising repeating the deposition of the conductive layer and the electrolytic deburring step multiple times.

18. A process according to any one of claims 6 to 17, comprising: The conductive layer is energized with a pulsed voltage or current waveform to selectively remove the defects.

19. A process according to any one of claims 6 to 18, comprising: The process is characterized in that it is applied to the manufacturing process of multilayer printed circuit boards.

20. 20. The process of claim 19, The process of claim 6, wherein the multilayer printed circuit board comprises a plurality of layers formed by repeating the process of claims 6 to 18.

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