Structures and processes for void-free hybrid bonding

Abstract

An apparatus for bonding a first substrate to a second substrate includes a heatable mounting stage configured to accommodate a first semiconductor substrate on its upward-facing surface and a first stack of semiconductor materials on the first semiconductor substrate; a heatable bonding head configured to accommodate a second semiconductor substrate on its downward-facing surface and a second stack of semiconductor materials on the second semiconductor substrate; and a collet positioned on the downward-facing surface of the heatable bonding head and configured to receive the second semiconductor substrate and the second stack of semiconductor materials. The heatable bonding head is configured to deformably accommodate the second semiconductor substrate and the second stack of semiconductor materials relative to the collet when a vacuum is applied thereto. The heatable bonding head is configured to be pressed against the heatable mounting stage to bond the semiconductor materials.

Description

[Background technology]

[0001] FIELD OF THE INVENTION The exemplary embodiments described herein relate generally to apparatus and methods for substrate bonding, and more particularly to apparatus and methods for improving the yield and reliability of copper / dielectric hybrid bonds in semiconductor devices.

[0002] The miniaturization of microelectronics and associated systems, as applied to semiconductor devices, involves an increase in the density of functional units (such as microcontrollers, memory components, sensors, and the like) on a chip (system on chip: SOC). Although techniques for increasing lateral density have improved due to advances in resolution capabilities associated with lithography, physical and technological limits have been reached to the point where further increases in density and reduced spacing are difficult, if not impossible, to achieve. In an effort to improve these limits, 2.5D and 3D technologies have been developed in which functional units (each with its optimized yield and process) are aligned and bonded with other functional units of the same or even different types in a stacked arrangement, resulting in the formation of vertical networks. As systems and devices become smaller, the spacing between functional units also decreases, which presents challenges for integrating functional units using three-dimensional integration.

[0003] In manufacturing semiconductor devices, a process of interfacially bonding two or more substrates together may be performed. This substrate bonding process may be performed to increase the density of functional units within the semiconductor device. For example, a semiconductor device having a stacked module structure may be advantageous for reducing the wiring length between modules, and may provide high-speed signal processing along with increased density.

[0004] During the manufacturing of stacked semiconductor devices, productivity can be improved in the process of bonding wafer-shaped stacks and then dicing the stacked semiconductor structures into chip (die) shapes. The substrate bonding process can be performed using a wafer-to-wafer method, which involves directly bonding two wafers with an appropriate interconnect medium between them. The wafer-to-wafer method can be performed using a bonding device that includes a bonding chunk that supports the wafers and a component that presses the wafers together. While wafer-to-wafer stacking is an efficient method, not all devices can be stacked in wafer shape due to die size and larger wafer size formats. Additionally, wafer stacking lacks known-good-die (KGD) capabilities. Only high-yield, simple-structure devices, such as image sensors, utilize wafer-level bonding.

[0005] Therefore, it is more preferable to first dice the wafer into dies (chips) and then stack them in die form (die-to-die connection, D2D), or equivalently, stack dies on a wafer (die-to-wafer, D2W). Especially if known good die (KGD) can be selected before stacking, this is the preferred method for 3D stacking, since each functional unit can be optimized separately.

[0006] The conventional technique for die stacking is through solder bumps (controlled collapsing chip connection, C4). C4 connections are used in chip-to-laminate (board) connections where the typical distance between solder is about 100 micrometers (μm), mainly due to the difference in coefficient of thermal expansion (CTE) between the chip and the organic laminate. This solder IO pitch can be reduced to 30 μm or less when applied to 3DI (where Si-to-Si stacking is present and there is no CTE difference).

[0007] More recently, a solderless IO bonding method has been developed in which only Cu IO pads within a dielectric surface matrix are used for bonding. This is called Cu / dielectric hybrid bonding, and as opposed to solder connections through solder melting, bonding is achieved in a surface monolayer, requiring a solder joint height of several microns.

[0008] Compared to solder bonding, Cu / dielectric hybrid bonding has several key advantages. It is compatible with Si back-end-of-line (BEOL) processing, and the bonded interface can withstand higher post-bonding temperatures (400°C) and is BEOL compatible. Solder bonding is part of the packaging process, not the silicon process. With solder bonding, post-bonding temperatures are typically 250°C or less. Cu / dielectric bonding is achieved through non-melting Cu diffusion bonding, which allows Cu / dielectric bonding to have much finer IO pitches (center-to-center distance between IO pads), typically less than 10 μm. Although solder bonding requires solder melting, it typically works at IO pitches of 30 μm or larger.

[0009] Unlike solder bonding through melting, Cu / dielectric bonding undergoes a two-stage bonding process. Prior to bonding, the surfaces must be activated with surface silanols, which are active molecules for bonding (silanols act like molecular glue). The first stage occurs at room temperature (or near room temperature). During this first stage, the dielectrics are attracted to each other through hydrogen bonding (via the surface silanols). To avoid affecting this dielectric bonding, the Cu pad must be slightly recessed, by a few nanometers, from the dielectric surface. Because the dielectric bonding occurs via surface silanols, a flat surface with a roughness of less than approximately 0.3 nanometers (nm) is required.

[0010] The second step in hybrid bonding is annealing, which is typically performed at 200-400°C for at least an hour. At this temperature, surface silanols (in hydrogen bonding) are converted to oxide bonds by releasing water molecules. In addition, at high temperatures, the Cu pads expand by a few nanometers to contact each other and form bonds through solid-state diffusion between the Cu pads.

[0011] In bonding processes, metals (such as copper) can be bonded to metals, metals can be bonded to dielectric materials, and dielectric materials can be bonded to other dielectric materials. However, voids that form between the bonded materials typically lead to mismatches and defects in the final semiconductor device.

[0012] The formation of such voids generally results from the presence of moisture between the bonding surfaces, especially when oxides are involved in the bonding process. In previous and current experiments, several sources of moisture have been identified.

[0013] One such source is the oxide junction itself, which undergoes a silanol-silanol condensation reaction in which water is produced as a leaving group when the oxide junction is formed. Si-OH+OH-Si->Si-O-Si+H2O Water then forms voids in the dielectric-to-dielectric bond if it is not able to adequately leave the bond surface.

[0014] In a further example, water condensation on silica surfaces can be said to be the cause of voids. Unlike water dew (volume), which condenses near freezing temperatures (0°C), surface water condenses at much higher temperatures, around 25°C. Based on the work of Zhuravlev, models were constructed to explain the surface chemistry of amorphous silica using analysis of the processes of dehydration (removal of physically adsorbed water), dehydroxylation (removal of silanol groups from the silica surface), and rehydroxylation (restoration of the hydroxyl film). Using these models, it was determined that both multilayer adsorption of wafer molecules at and below 25°C and monolayer adsorption at around 100°C are responsible for void formation. This was confirmed by nuclear magnetic resonance studies of water on silica.

[0015] Since the oxide bonding occurs at the surface monolayer level, these moisture sources can easily interfere with and overwhelm the proper formation of the oxide bonding at different bonding stages, resulting in various bonding voids.

[0016] For dielectric-to-dielectric bonding, experiments have shown that defects such as large voids occur when the die is thick (highly rigid) and at approximately 20°C (room temperature). Tilting the thicker die resulted in a reduction in the amount of large voids, but resulted in damage to the edge of the die. Such voids are primarily due to the inability of surface moisture to migrate quickly away from the bonding surface.

[0017] It has also been determined that bulk oxides (such as tetraethyl orthosilicate (TEOS) and low-temperature oxide (LTO)) contain internal (bulk) moisture, as evidenced by IR spectroscopy. This bulk moisture is reversible between Si-OH and Si-O-Si upon heating. This reversal of Si-O-Si to Si-OH allows for significant moisture release at high temperatures (above 450 °C), leading to blown-out defects even in the case of initially void-free TEOS bonds (at 300 °C). These voids result from moisture trapped inside the oxide bulk and outgassing at higher temperatures (450 °C). Summary of the Invention

[0018] In one exemplary embodiment, an apparatus for bonding a first substrate to a second substrate includes a heatable mounting stage configured to accommodate a first semiconductor substrate on its upward-facing surface and a first stack of semiconductor materials on the first semiconductor substrate; a heatable bonding head configured to accommodate a second semiconductor substrate on its downward-facing surface and a second stack of semiconductor materials on the second semiconductor substrate; and a collet disposed on the downward-facing surface of the heatable bonding head and configured to receive the second semiconductor substrate and the second stack of semiconductor materials. The heatable bonding head is configured to have a vacuum applied thereto to deformably accommodate the second semiconductor substrate and the second stack of semiconductor materials relative to the collet. The heatable bonding head is configured to be pressed against the heatable mounting stage to bond the second stack of semiconductor materials to the first stack of semiconductor materials. The heatable bonding stage is configured to have a vacuum applied thereto to planarize and secure the first semiconductor substrate during bonding.

[0019] In another exemplary embodiment, a method includes the steps of: providing a bond head and a stage; providing an upper substrate having a silicon die device with the silicon die device having a first layer of tetraethyl orthosilicate on the silicon die device and a first layer of silicon carbonitride on the first layer of tetraethyl orthosilicate; positioning the upper substrate under a collet extending from a downward-facing surface of the bond head; vacuum-adhering the upper substrate to the downward surface of the bond head through the collet, thereby deforming the upper substrate to have a downward-facing convex surface; and placing a lower substrate on the stage. providing a second layer of tetraethyl orthosilicate on the upward facing surface of the lower substrate and a second layer of silicon carbonitride on the second layer of tetraethyl orthosilicate; isothermally heating at least one of the bonding head or the stage to control thermal deformation between the silicon die device on the upper substrate and the lower substrate; pressing the bonding head against the stage to bond the first layer of silicon carbonitride to the second layer of silicon carbonitride; releasing the vacuum; and retracting the bonding head from the stage.

[0020] In another exemplary aspect, a method for forming a semiconductor structure includes fabricating an upper wafer, the upper wafer having a silicon substrate, a first layer of tetraethyl orthosilicate, and a first layer of silicon carbonitride; applying a surface protective coating to the upper wafer; thinning the upper wafer; attaching the upper wafer onto a dicing tape and dicing the upper wafer; peeling off the surface protective coating; picking an upper die comprising a portion of the upper wafer from the dicing tape; applying a vacuum to the picked upper die through a collet on a bonding head so that the picked upper die has a convex outer surface; applying a vacuum to a lower wafer having a second layer of tetraethyl orthosilicate and a second layer of silicon carbonitride against a stage; isothermally heating at least one of the bonding head or the stage; and bonding the picked upper die to the lower wafer having the second layer of tetraethyl orthosilicate and the second layer of silicon carbonitride on the stage. [Brief explanation of the drawings]

[0021] The above and other aspects of the exemplary embodiments will become more apparent in the following detailed description when read in conjunction with the accompanying drawing figures.

[0022] [Figure 1] FIG. 1A is a schematic diagram of an exemplary joining device having a collet.

[0023] FIG. 1B is a schematic diagram of an alternative exemplary collet for a joining device.

[0024] [Figure 2] 1B is a schematic diagram of an exemplary embodiment of the bonding apparatus of FIG. 1A along with an exemplary embodiment of a semiconductor structure fabricated using the bonding apparatus.

[0025] [Figure 3] 1 is a method flow of one exemplary process for fabricating a semiconductor structure.

[0026] [Figure 4] 1 is a schematic representation of a comparison between die-to-wafer bonding and wafer-to-wafer bonding.

[0027] [Figure 5] 1 is a schematic representation of a silanol bond. DETAILED DESCRIPTION OF THE INVENTION

[0028] The words "exemplary" and example are used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" or "example" is not necessarily to be construed as preferred or advantageous over other embodiments. All embodiments described in this detailed description are example embodiments provided to enable any person skilled in the art to make or use the invention and do not limit the scope of the invention, which is defined by the claims.

[0029] Exemplary embodiments described herein are directed to apparatus and methods for improving copper / dielectric bonding in semiconductor devices. Such bonding improvements enable high-density input / output (IO) connections to be created on chip structures while reducing back-end-of-line (BEOL) processing and improving 3D integration (3Di) stacking of functional units within the structures. High-density IO connections in copper / dielectric hybrid bonding refer to Cu bond pads approximately 1 μm in size, with a pad-to-pad distance of 10 μm. In the examples disclosed herein, for solder bonding, the bond pads are approximately 10 μm in size and the pad-to-pad distance is approximately 20 μm. The 1 μm dimension can also refer to the pad-to-pad distance in advanced hybrid bonding. In this case, the pad size can be approximately 0.5 μm in diameter. In either case, hybrid bonding relative to IO density has a much higher per-unit area than solder bonding.

[0030] 1A, one exemplary apparatus for improving hybrid bonding in semiconductor structures is generally designated 100 and will hereinafter be referred to as "bonding apparatus 100." Bonding apparatus 100 includes a stage 110, a bonding head 120, and a collet 130 affixed to bonding head 120, all of which cooperate to form a wafer product or hybrid semiconductor structure including copper and dielectric materials that may ultimately result in a semiconductor device. Collet 130 includes a plate 128 attached to bonding head 120 on an upward-facing side of plate 128 and a protrusion 134 extending from a downward-facing surface of plate 128 by about 10 micrometers (μm) to about 20 μm. The plate may cover only a portion of bonding head 120.

[0031] 1A, the stage 110 is configured to mount a stack of semiconductor materials on the upper bonding head facing surface. Both the stage 110 and the bonding head 120 are configured to be heated in a controlled manner to about 40°C to about 60°C using a heater 140. However, it is possible to heat only the bonding head 120 or only the stage 110. Furthermore, for die-to-die (D2D) and die-to-wafer (D2W) hybrid bonding, operational benefits can be obtained from using a temperature difference between the bonding head 120 and the stage 110 due to the smaller bonding footprint. If tighter alignment accuracy (e.g., less than 0.1 μm) is desired, it may be preferable to use isothermal heating (same temperature between the bonding head 120 and the stage 110). Such flexibility may not be available for wafer-to-wafer bonding.

[0032] The bond head 120 is also configured to have a vacuum 150 applied to it to allow an upper die to be held against the lower stage-facing surface of the bond head 120 or to secure a lower wafer / die (either the lower wafer or the lower die) during the bonding process, thereby flattening the wafer / die. A vacuum may also be applied to the stage 110. Either of the wafers / dies may be held in place by electrostatic forces, with or without a vacuum. Any suitable pressure mechanism 160 may be used to press the bond head 120 against the stage 110.

[0033] 1B, another exemplary collet 131 that can be attached to the bond head 120 can include a rounded or otherwise curved surface 132. In any embodiment, the size and shape of the collet will depend on the size and thickness of the target die.

[0034] Referring now to FIG. 2, a semiconductor structure (designated 200) can be formed in the bonding apparatus 100 using a Si chip as the top die 210 (or in a wafer-to-wafer process), a first layer of TEOS (or other type of oxide dielectric (bulk)), and a first layer of bonding interface material SiCN (or SiON, SiO, etc.) covering the TEOS (without SiCN, the TEOS can absorb bulk moisture through the reverse oxide bond, as explained above). Si-OH+OH-Si<-Si-O-Si+H2O SiCN is a highly hydrophobic material and an effective moisture barrier, forming a hermetic seal on top of the TEOS. Without SiCN, moisture can move freely in and out of the TEOS. With SiCN, all moisture (in the bulk and on the surface) no longer affects the bonding interface, making the structure much more stable at higher temperatures. TEOS / SiCN forms a hybrid bond with Cu vias, with Cu via sizes ranging from 0.1 μm to 3 μm and via spacings between 2 to 10 times the via size.

[0035] As shown, semiconductor structure 200 can be formed by bonding an upper layer to a lower layer using bonding apparatus 100. The upper layer includes a silicon device as top die 210, a first layer of TEOS, and a first layer of SiCN as a first stack. The lower die includes a second silicon device or wafer 220, along with a second layer of TEOS and a second layer of SiCN as a second stack. Top die 210 can be a silicon substrate having a thickness of about 30 to 200 μm or thinned to about 30 to 200 μm. This thickness allows top die 210 to be vacuum-attached to bonding head 120 over collet 130, which can result in the upper layer being deflected by about 10 μm to about 20 μm by the protruding collet 130, allowing the upper layer to maintain a convex shape on the side opposite collet 130. The convex shape of the upper layer allows moisture to escape rather than being trapped, as would be the case with a thicker die that is not bent into a convex shape.

[0036] The temperatures of both the bonding head 120 and the stage 110 are raised to approximately 40°C to approximately 60°C. This allows the bonding head 120 and the stage 110 to be maintained at the same temperature to reduce the thermal mismatch between the molecular structures of the materials, especially for fine-pitch IOs, and to remove adsorbed surface moisture. As shown by the Zhuravlev model, at 25°C and below (slightly above room temperature), moisture condenses into multilayer adsorbates on the bonding surfaces. Bonding without removing such moisture leaves "small voids" at the interface, typically less than 50 μm in size and as small as 0.5 μm at the interface. Raising the bonding temperature to 40°C to 60°C reduces the surface moisture content to less than a single molecular layer, allowing moisture to be pushed out of the interface along the convex surface. While silanols are stable up to 190°C, moisture trapped between and on silanols completely desorbs at 120°C. At 25°C and below, "small" voids due to multilayer moisture adsorption can be removed. As an example, large voids (due to flat surface traps) are removed by the convex surface, "small voids" (condensed moisture) are removed by increasing the bonding temperature, and bulk moisture (blow-through) is removed by the SiCN hermetic seal.

[0037] A first layer of TEOS (which can generally be a BEOL structure), a first layer of SiCN, a second layer of TEOS (or generally BEOL), and a second layer of SiCN are used for the bonding surfaces. The SiCN in each stack is a layer approximately 1000 angstroms (Å) thick (approximately 100 nanometers), and the TEOS in each stack is a layer approximately 1 μm thick. SiCN is a better stopping layer than oxide in chemical-mechanical polishing (CMP) operations and has a thin, bondable surface native oxide (approximately 1 nanometer (nm)). SiCN-SiCN bonding is achieved through this surface native oxide. SiCN also has a more consistent bonding energy than oxide. The bulk of the oxide (TEOS) contains approximately 25% moisture, which diffuses toward the bonding surface and can cause pop-up defects at high temperatures (approximately 450°C). Since SiCN is impermeable to moisture, it therefore prevents the moisture in TEOS from diffusing to the bonding interface, thereby preventing pop-up defects.

[0038] In operation of the bonding apparatus 100 to form the semiconductor structure 200, the bonding head 120, to which the upper layer is vacuum-attached, is pressed against the lower layer on the stage 110. The bonding force is approximately 0.1 grams (g) to approximately 1000 g. The bonding dwell time is approximately 0.1 seconds to approximately 5 seconds. After the desired dwell time, the vacuum is released and the bonding head 120 is retracted. This low-temperature bond is a weak bond primarily due to van der Waals forces between the -OH groups of the upper and lower substrates. The bonding then utilizes a high-temperature anneal for Cu-Cu diffusion and to strengthen the oxide bond covalently. This annealing process requires approximately 1 to 4 hours at temperatures between 200°C and 400°C. However, experiments have shown that when TEOS alone is used, annealing at higher temperatures can result in large (blow-through) voids at the bonded interface. The use of a SiCN / TEOS bilayer can prevent such high-temperature blow-through. The cause of the blow-through voids is attributed to bulk moisture adsorption in TEOS. By using SiCN on TEOS, such adsorbed outgassing can be eliminated.

[0039] Referring now to FIG. 3 , the flow of one exemplary method for forming semiconductor structure 200 is generally shown at 300, hereafter referred to as “method 300.” In method 300, an upper wafer and a lower wafer are fabricated, as shown in step 310. Cu pads and a dielectric film (e.g., TEOS, SiCN, SiON, etc.) used for hybrid bonding are formed in this step. In step 320, a surface protective coating is applied to the upper wafer, and in step 330, the upper wafer is thinned as needed (e.g., using a grinding tool and CMP). For die-level hybrid bonding, the wafer is placed on a dicing tape and diced. For wafer-level hybrid bonding, dicing tape attachment is not required. In step 340, the surface protective coating is stripped after dicing and before the bonding process. In step 350, an activation and cleaning step is performed. Since silanols act as the “glue” in oxide bonding, activation refers to fixing silanols to the surface. The cleaning process removes all contaminants, leaving only the surface silanols. In step 360, for die-level hybrid bonding, one die from the top wafer is picked from the dicing tape and vacuum-sucked through a collet on the bonding head, creating a convex surface extending approximately 10 μm to approximately 20 μm from the surface of the bonding head. For wafer-level hybrid bonding, the wafer is attached to the bonding collet as is. In step 370, the temperature of both the bonding head and stage is adjusted to 40°C (or higher). In step 380, for die-level hybrid bonding, the top die wafer is bonded to the bottom wafer (or die). In step 390, a high-temperature anneal can be performed for Cu and Cu diffusion and to strengthen the oxide bond through covalent bonding. This annealing process takes approximately 1 to 4 hours at 200°C to 400°C. The bottom die 110 is substrate-like and is typically part of a larger, heavier, more rigid, and thicker bonded pair to serve as a support structure.

[0040] 4, a comparison of die-to-wafer and wafer-to-wafer bonding is shown generally at 400. As shown at 410, multiple dies 420 are bonded to an underlying wafer 430. As shown at 440, a single upper wafer 450 is bonded to the underlying wafer 430.

[0041] Referring now to Figure 5, an illustration 500 showing ideal silanol bonding is compared with an illustration showing actual silanol bonding (with moisture). This comparison is based on the Zhuravlev model. The top panel shows the "ideal" bonded surface. The bottom panel shows the "actual" bonded surface dominated by moisture.

[0042] Some exemplary embodiments of the apparatus and methods disclosed herein offer several important high-value attributes. First, hybrid bonding is a new direction in 3Di stacking, allowing for a significant reduction in IO pitch (approximately 1 μm, which is for IO pitch, which is the distance between IO centers) compared to previously used solder microbump technology (approximately 5 μm, also IO center-to-center). Second, because moisture is involved in the bonding process, it also forms voids at the interface of the bulk and bonding material, thus leading to defects in the final product. This is an industry-wide problem that the apparatus and methods disclosed herein address. The exemplary methods disclosed herein solve the problem of voids at the interface and improve the technology for three-dimensional stacking of functional units.

[0043] In one embodiment, an apparatus for bonding a first substrate to a second substrate includes a heatable mounting stage configured to accommodate a first semiconductor substrate on its upward-facing surface and a first stack of semiconductor materials on the first semiconductor substrate; a heatable bonding head configured to accommodate a second semiconductor substrate on its downward-facing surface and a second stack of semiconductor materials on the second semiconductor substrate; and a collet disposed on the downward-facing surface of the heatable bonding head and configured to receive the second semiconductor substrate and the second stack of semiconductor materials. The heatable bonding head is configured to have a vacuum applied thereto to deformably accommodate the second semiconductor substrate and the second stack of semiconductor materials relative to the collet. The heatable bonding head is configured to be pressed against the heatable mounting stage to bond the second stack of semiconductor materials to the first stack of semiconductor materials. The heatable bonding stage is configured to have a vacuum applied thereto to planarize and secure the first semiconductor substrate during bonding.

[0044] The collet may be attached to a central portion of the downward-facing surface of the heatable bonding head and may extend from 5 micrometers to 50 micrometers from the downward-facing surface. At least one of the heatable mounting stage and the heatable bonding head may be configured to be heated to 25°C to 100°C. The pressure applied by the heatable bonding head against the heatable mounting stage may be 0.1 grams to 1000 grams. The downward-facing surface of the collet may be curved.

[0045] In another aspect, a method includes the steps of providing a bond head and a stage; providing an upper substrate having a silicon die device with the silicon die device having a first layer of tetraethyl orthosilicate on the silicon die device and a first layer of silicon carbonitride on the first layer of tetraethyl orthosilicate; positioning the upper substrate under a collet extending from a downwardly facing surface of the bond head; vacuum-adhering the upper substrate over the collet to the downwardly facing surface of the bond head, thereby deforming the upper substrate to have a downwardly facing convex surface; and vacuum-adhering the lower substrate to the stage. providing a second layer of tetraethyl orthosilicate on the upward facing surface of the lower substrate and a second layer of silicon carbonitride on the second layer of tetraethyl orthosilicate; isothermally heating at least one of the bonding head or the stage to control thermal deformation between the silicon die device on the upper substrate and the lower substrate; pressing the bonding head against the stage to bond the first layer of silicon carbonitride to the second layer of silicon carbonitride; releasing the vacuum; and retracting the bonding head from the stage.

[0046] The method may further include thinning the silicon die device to 30 to 200 micrometers. Vacuum adsorbing the upper substrate over the collet onto the downward-facing surface of the bonding head, thereby deforming the upper substrate to have a downwardly convex surface, may allow moisture to evaporate from the upper substrate and from the first layer of tetraethyl orthosilicate through the first layer of silicon carbonitride. Isothermally heating at least one of the bonding head or the stage may include heating to 40°C to 60°C. The first layer of tetraethyl orthosilicate and the second layer of tetraethyl orthosilicate may each be about 0.5 micrometers to about 5 micrometers thick. The first layer of silicon carbonitride and the second layer of silicon carbonitride may each be about 0.05 micrometers to about 0.2 micrometers thick. The method may further include annealing the bonded material at a temperature of 200°C to 400°C for a time period of 1 hour to 4 hours. Pressing the bonding head against the stage may include pressing the bonding head with a pressure of 0.1 grams to 1000 grams.

[0047] In another aspect, a method for forming a semiconductor structure includes fabricating an upper wafer, the upper wafer having a silicon substrate, a first layer of tetraethyl orthosilicate, and a first layer of silicon carbonitride; applying a surface protective coating to the upper wafer; thinning the upper wafer; attaching the upper wafer onto a dicing tape and dicing the upper wafer; peeling off the surface protective coating; picking an upper die comprising a portion of the upper wafer from the dicing tape; applying a vacuum to the picked upper die through a collet on a bonding head such that the picked upper die has a convex outer surface; applying a vacuum to a lower wafer having a second layer of tetraethyl orthosilicate and a second layer of silicon carbonitride relative to a stage; isothermally heating at least one of the bonding head or the stage; and bonding the picked upper die to the lower wafer having the second layer of tetraethyl orthosilicate and the second layer of silicon carbonitride on the stage.

[0048] The method may further include activating the bonding surface by using plasma treatment and deionized water rinsing after peeling off the surface protective coating and before picking the upper die from the dicing tape. Isothermally heating at least one of the bonding head or the stage may include heating to 40°C to 60°C. Bonding the picked upper die to the lower wafer having the second layer of tetraethyl orthosilicate and the second layer of silicon carbonitride on the stage may include pressing the bonding head against the stage with a pressure of 0.1 grams to 1000 grams. The method may further include releasing the applied vacuum. The method may further include retracting the bonding head from the stage. The method may further include annealing the bonded upper die and lower wafer.

[0049] In the foregoing description, numerous specific details have been set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide a thorough understanding of the exemplary embodiments disclosed herein. However, it will be understood that the exemplary embodiments disclosed herein may be practiced by those skilled in the art without these specific details. Additionally, details of well-known structures or processing steps may be omitted or not described to avoid obscuring the presented embodiments. When an element is referred to as being "on" or "over" another element, such as a layer, region, or substrate, it will be understood that it may be directly above the other elements, or that intervening elements may be present. In contrast, when an element is referred to as being "directly above" or "directly above" / over another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will also be understood that it may be directly below or below the other elements, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0050] The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the form disclosed. Many modifications and variations will become apparent to those skilled in the art without departing from the scope of the invention. The embodiments have been chosen and described to best explain the principles and practical applications of the invention and to enable others skilled in the art to understand the invention in various embodiments with various modifications that are suitable for the particular uses contemplated.

Claims

1. 1. An apparatus for bonding a first substrate to a second substrate, comprising: a heatable mounting stage configured to receive a first semiconductor substrate on an upward facing surface and a first stack of semiconductor material on the first semiconductor substrate; a heatable bonding head configured to receive a second semiconductor substrate on its downward facing surface and to receive a second stack of semiconductor material on the second semiconductor substrate; and a collet disposed on the downwardly facing surface of the heatable bonding head and configured to receive the second semiconductor substrate and the second stack of semiconductor materials; Equipped with the heatable bonding head is configured to have a vacuum applied thereto to deformably accommodate the second semiconductor substrate and the second stack of semiconductor material relative to the collet; the heatable bonding head is configured to be pressed against the heatable mounting stage to bond the second stack of semiconductor material to the first stack of semiconductor material; the heatable bonding stage is configured to have a vacuum applied thereto to planarize and secure the first semiconductor substrate during bonding; Device.

2. 10. The apparatus of claim 1, wherein the collet is attached to a central portion of the downwardly facing surface of the heatable bonding head and extends from the downwardly facing surface by between 5 micrometers and 50 micrometers.

3. The apparatus of claim 1 , wherein at least one of the heatable mounting stage and the heatable bonding head is configured to be heated to between 25°C and 100°C.

4. The apparatus of claim 1 , wherein the pressure applied by the heatable bonding head to the heatable mounting stage is between 0.1 grams and 1000 grams.

5. The apparatus of claim 1 , wherein the downwardly facing surface of the collet is curved.

6. providing a bonding head and stage; providing an upper substrate having a silicon die device with a first layer of tetraethyl orthosilicate on the silicon die device and a first layer of silicon carbonitride on the first layer of tetraethyl orthosilicate; positioning the upper substrate under a collet extending from a downwardly facing surface of the bond head; vacuum-adsorbing the upper substrate onto the downward-facing surface of the bonding head through the collet, thereby deforming the upper substrate to have a downward-facing convex surface; vacuum-adsorbing a lower substrate onto the stage; providing a second layer of tetraethyl orthosilicate on the upwardly facing surface of the lower substrate and a second layer of silicon carbonitride on the second layer of tetraethyl orthosilicate; isothermally heating at least one of the bonding head or the stage to control thermal deformation between the silicon die device on the upper substrate and the lower substrate; pressing the bond head against the stage to bond the first layer of silicon carbonitride to the second layer of silicon carbonitride; releasing the vacuum; and Retracting the bonding head from the stage A method for providing the above.

7. The method of claim 6 further comprising thinning the silicon die device to between 30 and 200 micrometers.

8. 7. The method of claim 6, wherein vacuum adhering the upper substrate over the collet to the downward-facing surface of the bond head, thereby deforming the upper substrate to have a downward-facing convex surface, allows moisture to wick from the upper substrate and from the first layer of tetraethyl orthosilicate through the first layer of silicon carbonitride.

9. The method of claim 6, wherein isothermally heating at least one of the bond head or the stage comprises heating to between 40°C and 60°C.

10. 7. The method of claim 6, wherein the first layer of tetraethyl orthosilicate and the second layer of tetraethyl orthosilicate are each about 0.5 micrometers to about 5 micrometers thick.

11. 7. The method of claim 6, wherein the first layer of silicon carbonitride and the second layer of silicon carbonitride are each about 0.05 micrometers to about 0.2 micrometers thick.

12. 7. The method of claim 6, further comprising annealing the joined materials at a temperature between 200° C. and 400° C. for a time between 1 hour and 4 hours.

13. The method of claim 6, wherein pressing the bonding head against the stage comprises pressing the bonding head with a pressure between 0.1 grams and 1000 grams.

14. fabricating an upper wafer, the upper wafer having a silicon substrate, a first layer of tetraethyl orthosilicate, and a first layer of silicon carbonitride; applying a surface protective coating to the top wafer; thinning the top wafer; attaching the upper wafer to a dicing tape and dicing the upper wafer; stripping the surface protective coating; picking a top die comprising a portion of the top wafer from the dicing tape; applying a vacuum to the picked upper die through a collet on a bonding head such that the picked upper die has a convex outer surface; applying a vacuum to the lower wafer having the second layer of tetraethyl orthosilicate and the second layer of silicon carbonitride relative to the stage; isothermally heating at least one of the bond head or the stage; and bonding the picked upper die to the lower wafer having the second layer of tetraethyl orthosilicate and the second layer of silicon carbonitride on the stage; 1. A method for forming a semiconductor structure, comprising:

15. 15. The method of claim 14, further comprising activating a bonding surface by using plasma treatment and deionized water rinsing after peeling off the surface protective coating and before picking the top die from the dicing tape.

16. 15. The method of claim 14, wherein isothermally heating at least one of the bond head or the stage comprises heating to between 40°C and 60°C.

17. 15. The method of claim 14, wherein bonding the picked upper die to the lower wafer having the second layer of tetraethyl orthosilicate and the second layer of silicon carbonitride on the stage comprises pressing the bonding head against the stage with a pressure of 0.1 grams to 1000 grams.

18. 18. The method of claim 17, further comprising releasing the applied vacuum.

19. The method of claim 18 further comprising retracting the bond head from the stage.

20. 20. The method of claim 19, further comprising annealing the bonded top die and bottom wafer.

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