semiconductor substrate

Abstract

A method for manufacturing a semiconductor substrate. The method includes providing a single-crystal diamond base layer. Then, the method forms a beryllium oxide (BeO) layer on the single-crystal diamond base layer. Then, the method forms a gallium nitride (GaN) layer on the BeO layer. In some embodiments, the method forms a surfactant on the single-crystal diamond base layer and the BeO layer.

Description

[Technical Field]

[0001] Priority This patent application claims priority to U.S. Provisional Patent Application No. 63 / 436,992, filed January 4, 2023, entitled "SEMICONDUCTOR SUBSTRATE" and naming John P. Ciraldo as inventor, the disclosure of which is incorporated herein by reference in its entirety.

[0002] Exemplary embodiments of the present invention relate generally to semiconductors, and more particularly, various embodiments of the present invention relate to semiconductor substrate fabrication.

[0003] Background technology Semiconductor devices generate heat during operation. Excessive heat limits the operating rating of the semiconductor device. Gallium nitride (GaN) is an important material for many semiconductor applications, especially power electronics applications with high power or high frequency requirements. The rating of a GaN semiconductor device is constrained by the heat generated by the device during operation. Increasing the rate at which heat is dissipated from the GaN semiconductor device can increase the power rating or frequency rating of the GaN semiconductor device. One way to dissipate heat is to use a highly thermally conductive substrate.

[0004] Summary of the Invention According to one embodiment of the present invention, a method for manufacturing a semiconductor substrate includes providing a single-crystal diamond base layer, epitaxially growing a single-crystal beryllium oxide (BeO) layer on the single-crystal diamond base layer, and epitaxially growing a single-crystal gallium nitride (GaN) layer on the BeO layer.

[0005] In various embodiments, the single-crystal diamond base layer has a grain size greater than 1 mm. The base layer 110 may have a thickness of 50-1100 microns, 200-650 microns, or 300-550 microns, among other thickness ranges. The inventors have found that thinner layers of diamond are not rigid and can undesirably break easily and be difficult to handle. While thicker diamonds can be grown, the inventors have also found that the thermal management value of thicker diamonds (e.g., greater than 550 microns, and especially greater than 1100 microns) in semiconductor applications is reduced.

[0006] The GaN layer 130 may comprise a single GaN crystal. The GaN layer may be epitaxially grown as a seed layer to a thickness of about 10 nm to about 2 microns. This GaN seed layer 130 may form a "template" that can be shipped to an end user. The GaN seed layer 130 may be grown using a first growth method, such as hydride vapor phase epitaxy (HVPE). Additional GaN layers 130 may be grown on top of the seed GaN layer 130, for example, by a customer who receives the template. The seed GaN layer 130 may advantageously reduce defects in subsequent GaN layers 130 grown thereon. The subsequent GaN layers 130 may be grown using a second growth method, such as metalorganic chemical vapor deposition (MOCVD), CVD, and / or ALD. It may be useful to have a GaN seed layer 130 on the surface during the growth of the subsequent GaN layers 130. The subsequent GaN layers 130 may be grown to a thickness of about 2 microns to about 5 microns. Preferably, the total thickness of all GaN layers 130 is about 5 microns or less. Although GaN layers 130 can be grown at different times and using different methods, the entire thickness of all GaN layers 130 grown contiguously can be considered a single semiconductor layer 130.

[0007] In various embodiments, the surface of the BeO layer or the single-crystal diamond base layer can be patterned. The surface of the BeO layer can be patterned to provide elongated lateral overgrowth of a GaN layer on the pattern. The BeO layer can be epitaxially grown to a thickness in the range of 3 to 500 nm, or in the range of 5 to 15 nm, among others.

[0008] In particular, the method can provide a surfactant on the BeO layer prior to epitaxially growing the single-crystal GaN layer. Similarly, the method can provide a surfactant on the single-crystal diamond base layer prior to epitaxially forming the BeO layer. The surfactant can have a surfactant lattice constant value between the BeO and GaN lattice constant values.

[0009] According to one embodiment of the present invention, a semiconductor substrate includes a single-crystal diamond-based layer. The substrate also includes a single-crystal beryllium oxide (BeO) layer formed on the single-crystal diamond-based layer. A single-crystal gallium nitride (GaN) layer is formed on the BeO layer.

[0010] In various embodiments, the single crystal diamond base layer is configured to include a grain size greater than 1 mm. The GaN layer may be a seed layer configured to receive an additional GaN layer. The GaN layer may include a single GaN crystal.

[0011] The device may include a surfactant located at the interface between the single-crystal diamond base layer and the BeO layer or the interface between the BeO layer and the GaN layer. The surfactant may include iridium or titanium. The surfactant may have a surfactant lattice constant value between the BeO lattice constant value and the GaN lattice constant value. The top surface of the BeO layer and / or the single-crystal diamond base layer may be patterned.

[0012] According to another embodiment, a method fabricates a semiconductor substrate. The method provides a single-crystal diamond base layer. Next, a beryllium oxide (BeO) layer is epitaxially grown on the single-crystal diamond base layer. The growth surface of the BeO layer is patterned before epitaxially growing a gallium nitride (GaN) layer on the growth surface. The pattern is configured to provide elongated lateral overgrowth of the GaN layer when the GaN layer is epitaxially grown on the BeO layer. In various embodiments, the GaN layer is single crystalline. The single-crystal diamond base layer can have a grain size greater than 1 mm.

[0013] The method can epitaxially grow a single-crystal GaN layer on the BeO layer. In some embodiments, the method can provide a surfactant on the BeO layer. The surfactant can have a surfactant lattice constant value between the BeO and GaN lattice constant values.

[0014] Those skilled in the art will more fully appreciate the advantages of various embodiments of the present invention from the following detailed description, which proceeds with reference to the drawings summarized immediately below. [Brief explanation of the drawings]

[0015] [Figure 1] 1A and 1B are diagrams illustrating a semiconductor substrate according to an exemplary embodiment; [Figure 2] 1A and 1B are diagrams illustrating schematic cross-sectional views of integrated semiconductor substrates according to exemplary embodiments; [Figure 3A] 1A and 1B are diagrams illustrating a substrate according to an exemplary embodiment; [Figure 3B] 1A and 1B are diagrams illustrating a substrate according to an exemplary embodiment; [Figure 4] 1A-1D illustrate a process for manufacturing a semiconductor substrate according to various embodiments.

[0016] MODE FOR CARRYING OUT THE INVENTION In exemplary embodiments, a single-crystal gallium nitride semiconductor is grown on diamond. Because diamond has very high thermal conductivity, the overall substrate offers an advantageous improvement over known substrates. The substrate includes a single-crystal diamond base layer, a single-crystal beryllium oxide (BeO) intermediate layer epitaxially grown on the diamond, and a single-crystal gallium nitride (GaN) layer grown on the beryllium oxide layer. In some embodiments, the growth surface of the BeO layer or the GaN layer may be patterned and / or have a surfactant thereon. Details of exemplary embodiments are described below.

[0017] FIG. 1 schematically illustrates a semiconductor substrate 100 according to an exemplary embodiment. The semiconductor substrate may include a gallium nitride (GaN) layer 130. In some embodiments, the GaN layer 130 is a material configured to allow for GaN growth and may include a semiconductor material or another type of material. For example, the GaN layer 130 may include a seed layer made of GaN. As known in the art, a semiconductor device is an electronic component that utilizes the electrical properties of semiconductors. Semiconductors are typically crystalline solids with specific atomic arrangements.

[0018] Various embodiments may advantageously use the methods described herein to fabricate semiconductor substrate 100, such as diodes, transistors, integrated circuits, semiconductor memory, and / or optoelectronic devices.

[0019] While GaN offers many advantages as a semiconductor material, GaN faces certain challenges and limitations. Some of the key issues associated with GaN semiconductors include: Cost: GaN-based devices can be more expensive to manufacture than traditional silicon-based devices. Raw materials such as gallium are more expensive, and the manufacturing process for GaN is more complex. Material quality: Achieving high-quality GaN crystals is difficult, and defects in the crystal structure can affect device performance. Thermal Management: Although GaN has relatively high thermal conductivity, heat management remains a concern, especially in high-power applications. Efficient thermal management is critical to prevent overheating and maintain the reliability and performance of GaN devices. Reliability issues: GaN devices can experience reliability issues, including premature failure, especially under certain operating conditions. Ensuring long-term stability and reliability is the focus of ongoing research and development efforts. Integration challenges: Integrating GaN with existing silicon-based technologies can be difficult. While advances are being made in the fabrication of hybrid devices, achieving seamless integration and compatibility remains an area of ​​active research. Process complexity: Manufacturing GaN-based devices involves complex processes, including precise control of epitaxial growth and doping. These process complexities contribute to high manufacturing costs and challenges in scaling up production.

[0020] The most common semiconductor material is silicon, although others such as germanium and gallium arsenide are also used. As explained further below, GaN offers many advantages over other semiconductor materials such as silicon carbide. Advantages include higher voltage, higher power capacity, and higher current throughput. In battery terms, this equates to faster charging. Overall, there are fewer losses in the electronics. This can also favorably affect the gate length of the device (i.e., how many devices can be accommodated on a chip).

[0021] A major problem with semiconductor devices is the buildup of heat within the device, resulting in reduced performance. To address this, computers can dynamically change voltage and reduce the chip's performance. However, there are other situations (e.g., high-power devices) where reduced performance is undesirable. For example, the Tesla Model S Plaid electric vehicle (EV) is known for its sudden acceleration. EVs can overheat, resulting in reduced performance.

[0022] In various embodiments, it is highly desirable to remove heat from the semiconductor substrate 100. The ability to extract heat from the substrate 100 depends on the conductivity of the material extracting the heat from the device / junction and the distance that material is away from the junction. In some embodiments, the ability to extract heat from the substrate 100 can be expressed by the following equation, where:

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[0023] Simply put, near the junction, the thermal conductivity is 1 / r 2 Therefore, exemplary embodiments advantageously apply a single molecule or atom thick surfactant 140, 150 and / or grow a thin BeO layer 120 (while still providing enough material for epitaxial growth) to reduce the distance of the diamond layer 110 from the GaN layer 130.

[0024] Exemplary embodiments use bulk diamond material to aid in thermal management. Diamond has highly desirable thermal conductivity properties. The inventors have discovered that single-crystal GaN can be grown on single-crystal diamond by epitaxially growing a single-crystal interface layer 120 of BeO between the diamond and the GaN. The interface layer 120 is preferably thin (e.g., less than 1 micron thick) so that the distance between the GaN and the diamond is small. Exemplary embodiments may also be used to grow polycrystalline stacks (e.g., polycrystalline diamond, BeO, and / or GaN).

[0025] This advantageously alleviates the need for complex / thick heterostacks and / or diamond bonding methods for bonding diamond to GaN. Exemplary embodiments advantageously solve one or more of the above problems by epitaxially growing single-crystal GaN on a single-crystal diamond layer. Specifically, a diamond-based layer 110 is provided. The diamond-based layer 110 is oriented so that the top surface of the diamond is a base growth plane 115. A BeO layer 120 is grown on the base growth plane 115. The BeO layer 120 also defines an intermediate growth plane 125, upon which a GaN layer 130 is grown.

[0026] By growing single crystal GaN, exemplary embodiments offer several advantages over polycrystalline or other crystalline GaN structures. For example, single crystal GaN produced using the processes described herein advantageously offers the following: High purity and quality: Single-crystal GaN exhibits higher purity and superior crystalline quality compared to its polycrystalline counterpart. This results in fewer crystal defects and a more uniform structure, contributing to improved electrical and optical performance of the device. Improved electron mobility: GaN's single-crystal structure allows for better control over the arrangement of atoms, leading to improved electron mobility. This property is important for high-frequency and high-power applications because it improves the speed and efficiency of electronic devices. Better thermal conductivity: Single-crystal GaN generally has better thermal conductivity than polycrystalline materials. This is important for applications where efficient heat dissipation is critical, as it helps prevent electronic devices from overheating and maintain reliability. Enhanced optoelectronic properties: Single-crystal GaN is often used in the development of optoelectronic devices such as high-brightness LEDs and laser diodes. The precise crystal structure allows for better control of light-emitting properties, resulting in improved efficiency and performance. Low dislocation density: Single-crystal GaN can have a lower dislocation density compared to polycrystalline forms. Dislocations can adversely affect the electrical and optical properties of semiconductor devices, so reducing their density is beneficial to device performance. Uniform electrical properties: The single-crystal structure provides uniform electrical properties throughout the material, contributing to the consistency and reliability of GaN devices. This is especially important in applications where precise control of electronic properties is crucial. Increased breakdown voltage: Single-crystal GaN can exhibit a higher breakdown voltage compared to polycrystalline forms. This property is advantageous for power electronics applications, as it allows the device to withstand higher voltages without damage.

[0027] While single-crystal GaN offers these advantages, it is notable that producing high-quality single-crystal GaN can be technically challenging and expensive. Researchers and manufacturers continue to explore ways to improve crystal growth techniques and reduce production costs, making single-crystal GaN more accessible for a wider range of applications.

[0028] Some embodiments allow for the growth of single-crystal GaN on a different non-diamond-based structure 110. Growing GaN on BeO on a single-crystal diamond heterostructure has the advantage of high thermal conductivity, since diamond has high thermal conductivity. Therefore, it is highly desirable to provide a substrate with GaN bonded to single-crystal diamond.

[0029] Some other embodiments can bond GaN to diamond by growing GaN on a non-diamond material such as silicon carbide, removing the single-crystal GaN material from the non-diamond-based structure, transferring the GaN in a vacuum, and then bonding the GaN to the diamond. This process undesirably requires grinding away the non-diamond-based structure and then directly attaching the GaN to the diamond to enhance thermal conductivity. This process is undesirably complex and has several drawbacks, including reduced device reliability.

[0030] Various embodiments advantageously use one or more intermediate layers 120 (eg, one or more epitaxial layers 120) to epitaxially grow the GaN layer 130 on the diamond layer 110.

[0031] 2 shows a schematic cross-sectional view of an integrated semiconductor substrate 100 configured to have high thermal conductivity and electrical insulation. The semiconductor substrate 100 is configured as an epitaxial heterostructure in that at least one layer is grown on a layer of a different material. It should be understood that the dimensions shown in the drawing are not drawn to scale.

[0032] The semiconductor substrate 100 has a base layer 110 that forms a surface on which other materials can be epitaxially grown. Among other things, the base layer 110 can comprise a diamond material (e.g., natural or lab-grown diamond). Preferably, the base layer is monocrystalline, and the layers grown thereon can also be monocrystalline. Diamond can have a continuous, unbroken crystal lattice without grain boundaries, also known as a single crystal or monocrystalline structure. In some embodiments, the grains of a monocrystalline structure have at least one dimension of at least 1 mm. For example, the base layer 110 can comprise monocrystalline diamond, upon which other layers of the semiconductor substrate are formed. The base layer 110 can be configured as, among other things, a wafer. The base layer 110 can have a thickness of 50 to 1100 microns, 200 to 650 microns, or 300 to 500 microns, among other thickness ranges.

[0033] In various embodiments, the semiconductor substrate 100 can include a surfactant 140 configured to aid in lattice relaxation or the epitaxial formation of the epitaxial layer 120 on the base layer 110. The surfactant 140 can be provided in the form of a fractional monolayer applied to the base layer 110 (i.e., on the growth surface 115 or the growth surface 125) before the growth of a subsequent layer (e.g., before the growth of the epitaxial layer 120 or the GaN layer 130). For example, the surfactant can be applied using physical vapor deposition (e.g., sputtering or thermal evaporation) or atomic layer deposition (ALD). The surfactant 140 can aid in the formation of the monocrystalline epitaxial layer 120 on the monocrystalline base layer 110. The surfactant 140 can have a lattice constant between the lattice constants of the two layers it contacts (e.g., between the lattice constant of the base layer 110 and the lattice constant of the epitaxial layer 120).

[0034] In some embodiments, surfactant 140 may include iridium or titanium, among others. Surfactant 140 may be a monolayer, i.e., having a thickness of one molecule or less, or in some cases, a thickness of one atom or less. In some embodiments, surfactant 140 may include multiple materials deposited between base layer 110 and epitaxial layer 120. Surfactant 140 may be configured as a partial monolayer, as shown in FIG. 1, where surfactant 140 covers only a portion of base layer 110, upon which epitaxial layer 120 is formed. In some embodiments, surfactant 140 is a partial monolayer that covers 10-75% of the surface of base layer 110 facing the epitaxial layer. In some embodiments, surfactant 140 is a partial monolayer that covers 25-50% of the surface of base layer 110 facing the epitaxial layer.

[0035] It is clear that even with surfactant 140, epitaxial layer 120 and base layer 110 are in intimate contact. Layers 110 and 120 are atomically bonded except in a few places where the bond is interrupted by atoms from surfactant 140. However, some embodiments may not include surfactant 140. In such embodiments, the growth between epitaxial layer 120 and base layer 110 may be pseudomorphic.

[0036] 3A-3B schematically illustrate a substrate 100 according to an exemplary embodiment. As shown, in addition to or instead of surfactants 140, 150, exemplary embodiments can pattern growth surface 115 or 125. For example, growth surface 125 can include a pattern 160 that is etched into growth surface 125, resulting in voids / gaps 165 in surface 125.

[0037] While FIG. 3A shows the etched surface 125 as forming small square gaps 165, one skilled in the art will appreciate that various widths, pitches, dimensions, number of gaps 165, distance between gaps 165, etc., can be used to form the desired pattern for GaN growth. For example, instead of square gaps 165, the etched gaps 165 can be V- or U-shaped. Preferably, the size of the gaps 165 is small enough so that the growth on the surface does not fill the gaps 165. Instead, elongated lateral overgrowth may occur over the gaps 165, as shown in FIG. 3B. The process of elongated lateral overgrowth is described in co-pending U.S. patent application Ser. No. 18 / 229,053, which is incorporated herein by reference in its entirety. As shown in FIG. 3B, when the GaN layer 130 is epitaxially grown on the pattern 160, the gaps 165 can remain, but GaN material will grow across the gaps. GaN material grown across the gap provides significantly reduced stress / high quality GaN material.

[0038] Although shown on a BeO layer 120, in some embodiments, the diamond-based layer 110 (e.g., growth surface 115) can include a physical pattern 160 configured to increase the surface energy of the exposed surface 115 upon which a subsequent layer 120 is formed. The physical pattern can be formed on the exposed surface 115 of the base layer 110, or it can be a physical pattern formed on a material formed on the base layer 110. For example, the pattern 160 can include a lithographic or etched pattern. The pattern 160 can include a pillar or cone shape. The pillars can have a circular or polygonal cross-section.

[0039] The epitaxial layer 120 is epitaxially grown on the base layer 110. Therefore, the epitaxial layer 120 can be formed on the base layer 110 using a semiconductor material that is not inherently compatible with the base layer 110. The epitaxial layer 120 can have a thickness in the range of 3 to 500 nm, or in the range of 5 to 15 nm, among others. In some embodiments, the epitaxial layer 120 is formed directly on the base layer 110 without an intermediate layer. While BeO is thermally conductive, it is not as thermally conductive as diamond. Therefore, exemplary embodiments preferably limit the thickness of the BeO layer 120. However, sufficient structure is required to allow for the subsequent growth of the semiconductor GaN layer 130. The inventors have found that BeO films less than 3 nm are ineffective for subsequent epitaxial growth and are prone to failure. Furthermore, the inventors have found that increasing the thickness of the BeO film beyond 500 nm significantly and undesirably affects the thermal conductivity of the diamond layer.

[0040] Exemplary embodiments may form layers on other layers of substrate 100, such as forming epitaxial layer 120 on base layer 110 using atomic layer deposition, liquid phase epitaxy, molecular beam epitaxy, pulsed laser deposition, high power impulse magnetron sputtering (HiPIMS), metalorganic chemical vapor deposition (MOCVD), standard chemical vapor deposition, or other techniques, among other methods. Those skilled in the art may use still other known techniques to form epitaxial layer 120 on base layer 110.

[0041] The epitaxial formation of epitaxial layer 120 on base layer 110 can involve crystal growth or material deposition, where a new crystalline layer of epitaxial layer 120 is formed with one or more defined orientations relative to base layer 110, which acts as a crystalline seed layer. Epitaxial deposition results in the deposited epitaxial layer 120 having a crystalline structure with a similar lattice constant as base layer 110 or a multiple thereof, which in the preferred embodiment is single crystalline.

[0042] The epitaxial layer 120 may include or consist of a material with high thermal conductivity. The epitaxial layer 120 may include or consist of beryllium oxide (BeO), thereby enabling the epitaxial formation of GaN on the diamond-based layer 110 using a material with high thermal conductivity. In other embodiments, the epitaxial layer may include BeO as well as an additive such as iridium or titanium. When epitaxially formed on the single-crystal diamond-based layer 110, the BeO epitaxial layer 120 will also be single-crystalline.

[0043] The semiconductor substrate 100 has another surfactant 150 configured to aid in lattice relaxation or epitaxial formation of a material layer 13, such as a semiconductor layer 130, on the epitaxial layer 120. The surfactant 150 may be configured to have a lattice constant between the lattice constants of the epitaxial layer 120 and the semiconductor layer 130. In some embodiments, the substrate 100 does not include the surfactant 150, and the semiconductor layer 130 is grown directly on the epitaxial layer 120 without the surfactant 150.

[0044] Surfactant 150 can include, among other things, iridium or titanium. Surfactant 150, like other surfactants 140, can be a monolayer, including a partial monolayer. Surfactant 150 can have multiple materials deposited between semiconductor layer 130 and epitaxial layer 120. As shown in FIG. 1, as a partial monolayer, surfactant 150 can cover only a portion of epitaxial layer 120 upon which semiconductor layer 130 is formed. In some embodiments, surfactant 150 is a partial monolayer covering at least 10% of the surface of epitaxial layer 120 facing the seed layer. In some embodiments, surfactant 150 is a partial monolayer covering 10-75% of the growth surface 125 of epitaxial layer 120. In some embodiments, surfactant 140 is a partial monolayer covering 25-50% of the growth surface 125 of epitaxial layer 120.

[0045] As alluded to above, semiconductor layer 130 is configured to facilitate the deposition of semiconductors onto semiconductor substrate 100. For example, semiconductor layer 130 may be comprised of GaN configured to receive an additional GaN semiconductor layer. The total thickness of semiconductor layer 130 may be between about 2 microns and about 6 microns, among other thicknesses. In general, it is desirable to keep the total thickness of GaN layer 130 thin because heat is typically generated near surface 135 of GaN layer 130 (e.g., near or at the PN junction of some devices further away from diamond layer 110). Thus, the thicker the GaN layer 130, the greater the distance between the heat generation point of GaN layer 130 and diamond layer 110. In some embodiments, semiconductor layer 130 comprises a single GaN crystal.

[0046] In some embodiments, the semiconductor substrate 100 may include more or fewer layers. For example, the semiconductor substrate 100 may not include the surfactant 140, the surfactant 150, and / or the semiconductor layer 130. In another example, the semiconductor substrate 100 may include the base layer 110, the surfactant 140, and the epitaxial layer 120. In another example, the semiconductor substrate 100 may include the base layer 110, the epitaxial layer 120, and the semiconductor layer 130. In yet another example, the semiconductor substrate 100 may include the base layer 110 and the epitaxial layer 120 having a patterned growth surface 125. Such an arrangement may be referred to as a template and can be sent off-site for growing GaN thereon.

[0047] 4 illustrates an exemplary process 400 for manufacturing a semiconductor substrate 100 according to various embodiments. It should be understood that several variations and modifications to the process 400 are possible, including, for example, omitting one or more steps of the process 400, adding additional conditions and steps, or separating operations and conditions into separate processes. Furthermore, some of the steps may be performed in a different order than shown, or simultaneously. Accordingly, those skilled in the art may modify the process accordingly.

[0048] Process 400 begins at step 401, where a base layer 110 of a semiconductor substrate 100 is provided. Base layer 110 may include or consist of a single crystal structure, such as a single crystal diamond layer. When implemented as diamond, substrate 100 may be formed from natural and / or laboratory-grown diamond, preferably in the form of a wafer for batch semiconductor processing.

[0049] In step 402, the process provides a surfactant 140 on the base layer 110 to aid in the epitaxial growth of the epitaxial layer 120 on the base layer 110. The surfactant 140 may include a thin layer of an additive such as iridium or titanium, among other things.

[0050] In step 403, the process may additionally or alternatively with respect to step 402 form a physical pattern 160 in the additive or base layer 110 using lithography or ion etching, among others. In certain embodiments, no pattern 160 is used and operation 203 is omitted.

[0051] In step 404, epitaxial layer 120 is epitaxially formed on base layer 110 during operation. For example, a layer of BeO may be epitaxially formed on single crystal diamond base layer 110. If the process uses steps 402 and / or 403, the BeO layer may be epitaxially grown on pattern 160 (e.g., using elongated lateral overgrowth) and / or grown on surfactant 140.

[0052] In step 405, similar to step 402, a surfactant 150 can be provided on the epitaxial layer 120 to aid in the formation of the semiconductor layer 130. Forming the surfactant 150 on the epitaxial layer 120 aids in the epitaxial growth of the semiconductor layer 130. The surfactant 150 can include a thin layer of an additive, such as iridium or titanium, among other things.

[0053] In step 406, the process may form a pattern 160 in epitaxial layer 120, in addition to or alternatively to step 405. The pattern used in step 406 may or may not be the same as the pattern used in step 403.

[0054] Next, step 407 grows semiconductor layer 130. Optionally, after step 406, the device is considered a "template" and can be shipped off-site for growth of GaN layer 130. The customer can simply grow GaN on the prepared template. Alternatively, the GaN layer can be grown in the same CVD chamber as the previous epitaxial growth.

[0055] Semiconductor layer 130 is formed on epitaxial layer 120 and surfactant 150 to aid in the epitaxial formation of another semiconductor layer on semiconductor substrate 100. For example, if a GaN semiconductor is grown using MOCVD, GaN semiconductor layer 130 is formed on epitaxial layer 120 using a technique other than MOCVD, such that the MOCVD grown layer is deposited on semiconductor substrate 100. Semiconductor layer 130 can have a thickness of 1 to 100 nm, among other thicknesses.

[0056] In process 400, instead of forming a semiconductor substrate on a semiconductor, a semiconductor is formed on a semiconductor substrate 100. Some advantages of forming a layer of semiconductor substrate 100 on a base layer 110 of single crystal diamond, rather than growing the semiconductor substrate 100 on a semiconductor, may include: 1. Process 400, in exemplary embodiments, illustrates that it generates less waste compared to other processes. Process 400 does not require the formation of a sacrificial layer for growing GaN, and therefore does not require the steps of growing GaN on a sacrificial layer and then transferring the GaN semiconductor from the sacrificial layer to the diamond layer. 2. The semiconductor substrate 100 formed by the process 400 can have a single crystal diamond structure that has greater heat transfer capabilities than polycrystalline diamond formed by other methods. 3. The process 400 does not require mechanical thinning to achieve the desired thickness of each layer of the semiconductor substrate 100.

[0057] It is contemplated that various aspects, features, processes, and operations from various embodiments may be used in any of the other embodiments unless expressly stated to the contrary. The particular operations illustrated may be implemented by a computer executing a computer program product on a non-transitory computer-readable storage medium, the computer program product including instructions that cause the computer to perform one or more of the operations or issue commands to other elements to perform one or more operations.

[0058] While the present disclosure has been illustrated and described in detail in the drawings and the foregoing description, it is to be considered illustrative and not restrictive, with the understanding that only certain exemplary embodiments have been shown and described, and that all changes and modifications within the spirit of the disclosure are desired to be protected. The use of words such as "preferred," "preferably," "preferred," or "more preferred" as used in the above description indicates that the feature so described may be more desirable, but it is to be understood that such words may not be necessary, and embodiments lacking them may be contemplated as being within the scope of the present disclosure, the scope of which is defined by the following claims. When reading the claims, the use of words such as "a," "an," "at least one," or "at least one portion" does not intend to limit the scope of the claim to a single item unless specifically stated to the contrary in the claim. The term "of" can mean an association or connection with another item, as well as belonging to or connecting with other items as informed by the context in which it is used. Terms such as "coupled to," "coupled with," and the like include indirect connections and connections, and further include, but do not require, direct connections or connections unless expressly stated to the contrary. When the terms "at least a portion" or "a portion" are used, an item can include part or all of the item, unless specifically stated to the contrary. Unless expressly stated to the contrary, the terms "or" and "and / or" in a list of two or more list items can refer to each individual list item or a combination of the list items. Unless expressly stated to the contrary, the transitional word "having" is an open-ended term and has the same meaning as the transitional word "including."

[0059] The embodiments of the present invention described above are intended to be merely illustrative, and numerous variations and modifications will be apparent to those skilled in the art. Such variations and modifications are intended to be within the scope of the present invention as defined by any of the appended claims. It should be understood, however, that no limitation of the scope of the present disclosure is hereby created, and that the present disclosure includes and protects such variations, modifications, and further applications of the exemplary embodiments as would occur to one skilled in the art having the benefit of this disclosure.

Claims

1. A method for manufacturing a semiconductor substrate, comprising: providing a single crystal diamond base layer; epitaxially forming a single crystal beryllium oxide (BeO) layer on the single crystal diamond base layer; epitaxially growing a single-crystal gallium nitride (GaN) layer on the BeO layer; A method comprising:

2. 2. The method of claim 1, wherein the single crystal diamond base layer has a grain size greater than 1 mm.

3. The method of claim 1 , wherein the GaN layer comprises a single GaN crystal.

4. The method of claim 1 , comprising providing a surfactant on the BeO layer prior to epitaxially growing the single-crystalline GaN layer.

5. 2. The method of claim 1, comprising providing a surfactant on the single crystal diamond base layer before epitaxially growing the BeO layer.

6. The method of claim 5 , wherein the surfactant comprises a surfactant lattice constant value between a BeO lattice constant value and a GaN lattice constant value.

7. 6. The method of claim 5, wherein forming the surfactant comprises patterning a surface of the BeO layer or the single crystal diamond-based layer.

8. A semiconductor substrate, a single crystal diamond base layer; a single-crystal beryllium oxide (BeO) layer formed on the single-crystal diamond base layer; a single-crystal gallium nitride (GaN) layer formed on the BeO layer; A semiconductor substrate comprising:

9. 9. The semiconductor substrate of claim 8, wherein the single crystal diamond-based layer is configured to include a grain size greater than 1 mm.

10. The semiconductor substrate of claim 8 , wherein the GaN layer is a seed layer configured to receive an additional GaN layer.

11. The semiconductor substrate of claim 8 , wherein the GaN layer comprises a single GaN crystal.

12. 9. The semiconductor substrate of claim 8, comprising a surfactant located at the interface between the single crystal diamond base layer and the BeO layer, or located at the interface between the BeO layer and the GaN layer.

13. The semiconductor substrate of claim 12 , wherein the surfactant has a surfactant lattice constant value between a BeO lattice constant value and a GaN lattice constant value.

14. 13. The semiconductor substrate of claim 12, wherein the top surface of the BeO layer and / or the single crystal diamond based layer is patterned.

15. A method for manufacturing a semiconductor substrate, comprising: providing a single crystal diamond base layer; epitaxially growing a beryllium oxide (BeO) layer on the single crystal diamond base layer; patterning the growth surface of the BeO layer prior to epitaxially growing a gallium nitride (GaN) layer on the growth surface, the patterning being configured to provide elongated lateral overgrowth of the GaN layer; A method comprising:

16. 16. The method of claim 15, wherein the single crystal diamond base layer has a grain size greater than 1 mm.

17. 16. The method of claim 15, comprising epitaxially growing a single-crystal GaN layer on the BeO layer.

18. The method of claim 15 further comprising providing a surfactant on the BeO layer.

19. 20. The method of claim 18, wherein the surfactant has a surfactant lattice constant value between the BeO and GaN lattice constant values.

20. 20. The method of claim 18, wherein the surfactant comprises iridium or titanium.

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