Reducing leakage power of volatile memories

Abstract

A system and method for reducing the amount of power leaked by volatile memory in memory units of a memory system. In one aspect, the memory system includes a volatile memory including a plurality of memory units. The memory system includes a descriptor queue configured to maintain a sequence of descriptors corresponding to received memory access requests. The descriptor queue includes a memory access pointer indicating a current descriptor being processed and a power management pointer indicating one or more subsequent descriptors for an active state transition. The memory system includes a memory controller configured to process the descriptors based on the memory access pointer and access the memory units of the descriptors in response to the received memory access requests. The memory system includes a power manager configured to selectively transition each memory unit between an active state and a low power state.

Description

[Technical Field]

[0001] TECHNICAL FIELD This disclosure relates to computer memory and reducing the amount of power leaked by volatile computer memory. [Background technology]

[0002] Volatile memory is a type of computer memory that retains data when power is applied but loses that data when power is lost. Two exemplary types of volatile memory are dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM requires periodic refreshing to maintain its data, while SRAM requires constant power to maintain its data.

[0003] SRAM transistors have multiple sources of leakage power. Because there can be large amounts of SRAM on a system-on-chip (SoC) and on other types of integrated circuits, the constant power demands of SRAM can result in large amounts of wasted power and associated negative thermal characteristics. Summary of the Invention

[0004] This specification relates to reducing the amount of power leaked by volatile memory, particularly SRAM and other types of volatile memory where the memory may be accessed in any order. Physical memory units can be placed in a low-power state to reduce the amount of leakage power when the memory units are not being accessed. However, it takes some time to transition the memory units from the low-power state to an active state where the memory units can be accessed. If the memory units do not transition to the active state until a request to access data stored in the memory units is received, the transition time adds latency and imposes backpressure on the memory system. The techniques described herein reduce the power leakage of volatile memory without such latency and backpressure, even in situations where memory accesses are random and do not follow any schedule or prescribed pattern.

[0005] In general, one innovative aspect of the subject matter described herein can be embodied in a memory system comprising: a volatile memory including a plurality of memory units; and a descriptor queue configured to maintain a sequence of descriptors, each corresponding to a received memory access request for performing a memory access operation at a respective memory unit of the plurality of memory units, the descriptor queue including a memory access pointer indicating a current descriptor being processed and a power management pointer indicating one or more subsequent descriptors for an active state transition; and a memory controller configured to process descriptors in the descriptor queue based on the memory access pointer and access the memory units of the descriptors to respond to received memory access requests corresponding to the descriptors in the descriptor queue; and a power manager configured to selectively transition each memory unit between an active state and a low power state, including monitoring the power management pointer to identify one or more subsequent descriptors; and transitioning the respective memory unit from the low power state to the active state for each of the one or more subsequent descriptors before the one or more subsequent descriptors have been processed by the memory controller. Other embodiments of this aspect include corresponding systems, apparatus, and computer programs configured to perform the actions of the methods encoded on computer storage devices.

[0006] These and other embodiments may each optionally include one or more of the following features. In some aspects, the descriptor queue includes a first-in, first-out queue, with each descriptor being removed from the descriptor queue after the memory controller performs the memory access operation indicated by the descriptor. The volatile memory may include static random access memory (SRAM). The descriptor queue may include a queue manager configured to update the descriptor queue to include a descriptor for each newly received memory access request, to update the memory access pointer after each descriptor is processed by the memory controller, and to update the power management pointer after each descriptor is processed by the memory controller.

[0007] In some implementations, the one or more subsequent descriptors include a number of descriptors selected based on an amount of time it takes the memory unit to transition from a low power state to an active state. The number of descriptors may be based on a number of memory access operations that the memory controller can complete within the amount of time. The number of descriptors may be based on a number of processing unit clock cycles of a processor communicatively coupled to the volatile memory that occur during the amount of time.

[0008] In some implementations, the descriptor queue includes one or more additional power management pointers that point to a subsequent additional set of descriptors for the active state transition. The subsequent additional set of descriptors includes an additional number of descriptors selected based on the amount of time required for the memory unit corresponding to each additional descriptor to transition from the low power state to the active state. The additional number of descriptors may be based on the number of memory access operations that the memory controller can complete within the length of time.

[0009] In some aspects, the power manager is configured to determine whether the respective memory unit of the current descriptor is a subsequent descriptor for an active state transition, to leave the respective memory unit of the current descriptor in an active state after processing the current descriptor whenever the respective memory unit of the current descriptor is a subsequent descriptor for an active state transition, and to transition the respective memory unit of the current descriptor from the active state to a low power state whenever the respective memory unit of the current descriptor is not a subsequent descriptor for an active state transition.

[0010] In general, another innovative aspect of the subject matter described herein can be embodied in a method executed by a memory controller configured to manage a volatile memory including multiple memory units. The method includes accessing a descriptor queue, the descriptor queue including a sequence of descriptors each corresponding to a received memory access request, each descriptor corresponding to a memory access operation for a respective one of the multiple memory units indicated by the descriptor, the descriptor queue further including a memory access pointer indicating a current descriptor for processing and a power management pointer indicating one or more subsequent descriptors for active state transition. The method includes identifying one or more subsequent descriptors based on the power management pointer, transitioning each subsequent descriptor in a low power state from the low power state to an active state, and accessing one or more memory units of each subsequent descriptor when the memory access pointer reaches the subsequent descriptor in the descriptor queue. Other embodiments of this aspect include corresponding systems, apparatus, and computer programs configured to perform the actions of the method encoded on a computer storage device.

[0011] These and other implementations may each optionally include one or more of the following features: In some aspects, accessing one or more memory units for each subsequent descriptor includes performing a memory access operation for the subsequent descriptor.

[0012] In some implementations, the method includes updating the memory access pointer and the power management pointer to point to a different descriptor each time a memory access operation for the descriptor is performed and the descriptor is removed from the descriptor queue.

[0013] In some aspects, the method includes performing a memory access operation for a current descriptor; removing the current descriptor from a descriptor queue in response to performing the memory access operation for the current descriptor; updating a memory access pointer to point to a next descriptor in the descriptor queue following the current descriptor; and updating one or more subsequent descriptors for an active state transition by updating a power management pointer in response to performing the memory access operation for the current descriptor.

[0014] In some aspects, the method includes determining whether a respective memory unit of the current descriptor is a subsequent descriptor for an active state transition; whenever the respective memory unit of the current descriptor is a subsequent descriptor for an active state transition, leaving the respective memory unit of the current descriptor in an active state after processing the current descriptor; and whenever the respective memory unit of the current descriptor is not a subsequent descriptor for an active state transition, transitioning the respective memory unit of the current descriptor from the active state to a low power state.

[0015] In some aspects, the method includes identifying each descriptor between the memory access pointer and the power management pointer as one or more subsequent descriptors.

[0016] In some aspects, the method includes controlling the power management pointer to identify a particular number of subsequent descriptors based on the length of time it takes the memory unit to transition from the low power state to the active state.

[0017] In some aspects, the descriptor queue comprises a first-in-first-out queue, with each descriptor being removed from the descriptor queue after the memory controller performs the memory access operation indicated by the descriptor.

[0018] In some aspects, the volatile memory includes static random access memory (SRAM). The descriptor queue can include a queue manager configured to update the descriptor queue to include a descriptor for each newly received memory access request, update the memory access pointer after each descriptor is processed by the memory controller, and update the power management pointer after each descriptor is processed by the memory controller.

[0019] In some implementations, the one or more subsequent descriptors include a number of descriptors selected based on the length of time it takes the memory unit to transition from the low power state to the active state. The number of descriptors may be based on the number of memory access operations the memory controller can complete within the length of time. The number of descriptors may be based on the number of processing unit clock cycles of a processor communicatively coupled to the volatile memory that occur during the length of time.

[0020] In some aspects, the method includes determining that a particular descriptor corresponding to a particular memory unit is not in the descriptor queue, and transitioning the particular memory unit to a lower power state in response to determining that the particular descriptor corresponding to the particular memory unit is not in the descriptor queue.

[0021] The subject matter described herein can be implemented in particular embodiments to achieve one or more of the following advantages: By managing the low-power state of volatile memory so that the memory unit transitions to an active state before being accessed, the leakage power of the memory unit is reduced, which also reduces the amount of waste heat generated by the leakage power. A power management pointer and descriptor queue, which can be implemented as a first-in, first-out (FIFO) unit, can be used to identify memory units that are about to be accessed (e.g., within a specified amount of time) and transition the memory unit just before it is accessed (e.g., within one, two, or another suitable number of clock cycles). This further reduces the amount of time the memory unit is in the active state and the associated heat. This also ensures that the memory unit is in the active state at the time the memory controller accesses the memory unit, reducing latency and backpressure. The use of power management pointers and descriptor queues allows these just-in-time transitions regardless of the order in which memory requests are received, thus enabling the use of low-power techniques in all situations, not just those in which memory access patterns are known or conform to predefined patterns.

[0022] The details of one or more embodiments of the subject matter herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0023] [Figure 1] 1 illustrates an exemplary memory system in which a memory controller controls access to a volatile memory and transitions memory units of the volatile memory between active and low power states. [Figure 2] 10 illustrates an exemplary state of a descriptor queue. [Figure 3]1 illustrates a flow diagram of an exemplary process for transitioning a memory unit between an active state and a low power state. [Figure 4] 1 illustrates a flow diagram of an exemplary process for accessing a memory unit and transitioning the memory unit between an active state and a low power state. DETAILED DESCRIPTION OF THE INVENTION

[0024] Like reference symbols and designations in the various drawings indicate like elements.

[0025] FIG. 1 illustrates an exemplary memory system 100 in which a memory controller 110 controls access to a volatile memory 150 and transitions memory units 152 (e.g., 152-1 through 152-N) of the volatile memory 150 between active and low-power states. The memory system 100 can be part of (e.g., integrated with) or coupled to a system-on-chip (SOC), which can be installed on or integrated into any suitable computing device. Because the techniques described herein are particularly suited to reducing power leakage in the volatile memory 150 with reduced latency and backpressure, the memory system 100 can be particularly beneficial when installed in a mobile host device or other device that relies on battery power or other limited power sources. For example, reducing power leakage in a portable device (e.g., a smartphone, a smartwatch or another wearable computing device, a tablet computer, or a laptop computer) can improve the battery performance and operability of the portable device for extended periods without access to an external power source.

[0026] Memory system 100 includes a memory controller 110, a power manager 120 configured to transition memory units 152 between active and low-power states to satisfy memory access requests, and volatile memory 150. Examples of volatile memory 150 include cache memory and random access memory, such as dynamic random access memory (DRAM) and static random access memory (SRAM). The power management and memory access techniques described herein can be used with volatile memory, such as SRAM, that requires a constant amount of power to retain data.

[0027] Each memory unit 152 is a physical instance of memory, e.g., a smaller partition of a larger memory system or device. The physical instance of memory in a memory unit can transition to different power states, e.g., from an active state to a low-power state and from a low-power state to an active state. The power state of a physical instance of memory can transition independently of the power states of other physical instances of memory units. For example, a memory unit 152 can be a group of memory cells, such as one or more rows of memory cells, one or more columns of memory cells, or one or more memory banks. The memory units 152 can be grouped or clustered based on their characteristics or other factors, including power state, operating parameters, computing application, latency in transitioning between low-power and active states, and read / write speeds. In some implementations, each memory unit 152 is a group of cells that have the same power state (e.g., active state or low-power state) and transition between power states together. For example, a bank or row of memory cells can receive power from the same portion of a power distribution circuit and therefore always have the same power state. The memory system 100 may include any number “N” of memory units 152 .

[0028] Each memory unit 152 may include a group of memory circuits that are powered together and are both in the same power state. A memory device may be partitioned into any number of banks, rows, and rows of banks in any number of ways. As an example, a memory device having an 8 megabyte (MB) capacity may be partitioned into eight individual banks of equal size, such as 1 MB per bank. In this example, each bank may be a memory unit 152. Each memory bank may be a vertical partition of the memory device that may contain a single physical instance of memory or multiple physical instances of memory. For example, a 1 MB memory bank may contain a 1 MB physical instance. As another example, a 1 MB memory bank may be partitioned into eight physical instances of memory, such that each physical instance of memory contains 128 kB of memory. In this example, each 128 kB instance of memory may be a memory unit 152.

[0029] The active state of a memory unit 152 is a state in which memory cells of the memory unit 152 can be accessed by the memory controller 110. The power manager 120 can transition the memory unit 152 into a low-power state to reduce power consumption and leakage power of the memory unit 152 when the memory unit 152 is not being accessed. Exemplary low-power states include light sleep, deep sleep, and power gating. The power manager 120 can transition the memory unit 152 between an active state and a low-power state by sending power state instructions to the memory unit 152. As an example, the power manager 120 can provide one or more power state instructions (e.g., a series of instructions) to one or more memory units 152 to wake up (e.g., transition from a low-power state to an active state) or power down (e.g., transition from an active state to a low-power state). The power state instructions can include input signals to the memory unit that enable the transition. The specific instructions can vary based on the type of volatile memory 150 used and the memory management technique of the memory system 100.

[0030] Power manager 120 includes and / or maintains status table 122 to store data indicating the current power state of each memory unit 152. Status table 122 includes a cell for each memory unit 152, where a value or label stored in the cell indicates the current power state of memory unit 152. For example, if the possible states are "active" and "low power," the cell of memory unit 152 may include a label indicating "active" or "low power," or a value representing "active" or "low power," such as a value of "1" for active and a value of "0" for low power. Other values ​​may also be used.

[0031] Power manager 120 may maintain status table 122 based on power state commands that power manager 120 sends to memory unit 152 and / or based on feedback received from volatile memory 150. For example, if power manager 120 sends a power state command to memory unit 152-3 to transition from an active state to a low power state, power manager 120 may update the cells of memory unit 152-3 from active to a low power state, i.e., from 0 to 1, using the example labels and values ​​above. In another example, power manager 120 may wait for feedback indicating that memory unit 152-3 has successfully transitioned from the active state to the low power state.

[0032] Memory controller 110 includes memory access engine 112, descriptor queue 114, and queue manager 116. Memory controller 110 can be implemented in hardware and / or software, and descriptor queue 114 and queue manager 116 may be additional memory or hardware and / or software of memory system 100.

[0033] Memory controller 110 is configured to receive memory access requests from agents 105 (e.g., agents 105-1 through 105-N). Agents 105 may be hardware devices or software components (e.g., applications or modules) that provide data for storage in volatile memory 150 and / or request data stored in volatile memory 150. Exemplary agents include an operating system (OS) of a computing device, applications running on the computing device, integrated circuits (ICs) communicatively coupled to memory system 100, processor cores (e.g., central processing units (CPUs), digital signal processors, graphics processing units (GPUs), etc.), and external interfaces.

[0034] A memory access request may be to request data from or store data in volatile memory 150. Each memory access request may include a descriptor and, if the request is to store data, the data to be stored. The descriptor of a memory access request may include data identifying a memory location, such as a memory address, and a memory operation, such as a read / write. The memory location identifies a location in memory where the memory operation is to be performed. In some implementations, the memory location may not directly identify a memory unit 152. For example, each memory unit 152 may be a physical instance of memory and correspond to a distinct logical memory address assigned to the physical instance. In such an example, the memory controller 110 may be configured to translate the memory location to a corresponding memory unit 152 and / or to a specific location (e.g., a group of cells) within the memory unit 152.

[0035] In one example, agent 105 can send to memory controller 110 a memory access request corresponding to a write request to store data in volatile memory 150. The memory access request includes the data to be stored and a descriptor containing data identifying the memory location where the data is to be stored and the write operation. Queue manager 116 can store the descriptor in descriptor queue 114.

[0036] In another example, agent 105 may send to memory controller 110 a memory access request corresponding to a read request to retrieve data stored in volatile memory 150. In this example, the memory access request includes a descriptor containing data identifying the memory location from which the data is to be retrieved and the read operation. Similar to the above example, queue manager 116 may store the descriptor in descriptor queue 114.

[0037] Descriptor queue 114 is configured to store descriptors received from agent 105. In some implementations, a descriptor in a descriptor queue may be a number of bits, such as 24 bits, where all but one bit of the descriptor describes a memory location, such as a 23-bit value, while the remaining bits describe an operation, such as a read or write. Other numbers of bits can also be used for each portion of the descriptor. Descriptor queue 114 can be implemented as a FIFO queue in which descriptors are processed in the order they are received by memory controller 110. In other words, descriptor queue 114 can be a FIFO unit. Descriptor queue 114 includes multiple queue locations, including a first location where the current descriptor being processed can be stored and a last location where the last descriptor currently in descriptor queue 114 being processed can be stored. Each newly received descriptor can be added to the end of the queue, which becomes the new last queue location.

[0038] Queue manager 116 may be configured to manage descriptors stored in descriptor queue 114 and pointers to descriptors within descriptor queue 114. For example, queue manager 116 may be configured to add a descriptor to descriptor queue 114 (e.g., to a tail or last position within descriptor queue 114) upon receiving a memory access request that includes the descriptor. Additionally, queue manager 116 may be configured to remove descriptors from descriptor queue 114 as the descriptors are processed by memory access engine 112, as described below.

[0039] Descriptor queue 114 includes one or more memory access pointers that point to the next descriptor in a sequence of descriptors to be processed. As described below with reference to FIG. 2, descriptor queue 114 may include a read access pointer for read operations and a write access pointer for write operations. For example, read and write operations may be processed in groups. A read access pointer may point to the next read operation to be processed, and a write access pointer may point to the next write operation to be processed. In some implementations, the descriptor queue includes a single memory access pointer for the next descriptor, regardless of the type of operation.

[0040] Descriptor queue 114 also includes a power management pointer that points to one or more subsequent descriptors that will cause the memory unit to transition to an active state if the memory unit is not already in an active state. When a descriptor is about to be processed, e.g., within a specified number of queue positions from the first position in descriptor queue 114, power manager 120 can transition memory unit 152 corresponding to the descriptor (e.g., memory unit 152 indicated by the memory location of the descriptor) to an active state if memory unit 152 is currently in a low power state. Power manager 120 and power management pointers are described in more detail below.

[0041] The memory access engine 112 is configured to process the descriptors using the memory access pointers and perform memory operations on the descriptors. Each time the memory access engine 112 finishes processing a descriptor, the memory access engine 112 may notify the queue manager 116. In response, the queue manager 116 may remove the processed descriptor from the descriptor queue 114 and update the descriptor queue 114 so that the descriptor that was in the second position is now in the first position, and each other descriptor moves up one position in the descriptor queue 114. By removing the processed descriptor from the descriptor queue 114 and updating it with the next descriptor to be processed, the queue manager 116 maintains a FIFO scheme for processing the descriptors in the descriptor queue 114.

[0042] The memory access engine 112 may process the descriptor by identifying the operation of the descriptor and the memory location of the descriptor. The memory access engine 112 may then perform the operation on the memory unit 152 corresponding to the memory location. For example, if the operation is a read operation, the memory access engine 112 may open the memory unit 152, read the appropriate data from the memory unit 152, and send the data to the agent 105 that sent the memory access request. If the operation is a write operation, the memory access engine 112 may open the memory unit 152 and write the data to the memory unit 152. In some implementations, the memory access engine 112 may be referred to as a direct memory access engine for the coupled volatile memory device.

[0043] Power manager 120 is configured to monitor power management pointers in descriptor queue 114 and selectively transition memory unit 152 between an active state and a low-power state. Power manager 120 can use the power management pointers to identify subsequent descriptors for which memory unit 150 should be in an active state (e.g., descriptors after the current descriptor being processed). For each of these subsequent descriptors, power manager 120 can identify the corresponding memory units 152 and transition them to an active state if they are not already in an active state. In this way, when a descriptor reaches the first position in descriptor queue 114, the corresponding memory unit 152 is in an active state and memory access engine 112 can immediately access memory unit 152. This reduces latency in performing memory operations for memory access requests and, therefore, reduces backpressure on memory system 110.

[0044] The power manager 120 can also be configured to transition the memory unit 152 back to a lower power state after it has been accessed for a processed descriptor. For example, the power manager 120 can be configured to monitor a memory access pointer to identify the descriptor being processed. When the memory access pointer transitions to a different descriptor, the power manager 120 can determine that the previous descriptor has been processed. In another example, the memory access engine 112 can be configured to notify the power manager 120 when a descriptor has been completely processed. Such a notification can include the descriptor, or at least the memory location of the descriptor.

[0045] Before memory unit 152 transitions back to a low power state, power manager 120 may evaluate the descriptor queue to determine, for example, whether memory unit 152 will be accessed again soon, within the time period it takes for memory unit 152 to transition back to an active state when memory unit 152 transitions to a low power state. For example, it may take three clock cycles for a memory unit to transition from a low power state to an active state, and memory access engine 112 may be capable of processing one descriptor per clock cycle. In this example, if there are descriptors for the same memory unit 152 in the first three positions of descriptor queue 114, power manager 120 may maintain memory unit 152 in the active state, so that this descriptor can be processed without delay when it reaches the first position of descriptor queue 114. In some implementations, power manager 120 performs this evaluation by determining whether any descriptors between the memory access pointer and the power management pointer are for that memory unit 152.

[0046] A power transition of memory unit 152 to an active state may include activating memory unit 152 to the active state (e.g., executing a wake-up routine), which may include increased power consumption. A power transition to a low power state may include powering down the memory unit to a low power state, which may include reduced power consumption. In some implementations, the low power states may be distinguished between a light sleep state, which reduces power consumption, and a deep sleep state, which further reduces power consumption compared to the light sleep state. As an example, a deep sleep state of memory unit 152 may result in significant power savings compared to the light sleep state, but may also increase latency, e.g., additional processing unit clock cycles, additional processing time, additional memory access operations, etc., required to transition to the active state.

[0047] Figure 2 shows exemplary states of descriptor queue 214. Descriptor queue 214 is an example of descriptor queue 114 described with reference to Figure 1, and stages A-C show how memory access pointers and power management pointers can be used to process descriptors and transition memory units between active and low power states.

[0048] Referring to stage A, descriptor queue 214 includes descriptors 1 through 13, with descriptor 1 in first position 221 and descriptor 13 in last position 222. As described above, each descriptor may include a memory location (e.g., a memory address) corresponding to a memory unit in volatile memory and an operation (e.g., read or write). The read access pointer is a memory access pointer configured to track descriptors for memory access requests that include instructions to read data from memory unit 150. The write access pointer is a memory access pointer configured to track descriptors for memory access requests that include instructions to write data to memory unit 150. The power management pointer is configured to indicate the number of subsequent descriptors following the current descriptor being processed, e.g., by the read access pointer in the illustrated example.

[0049] In this example, the descriptor queue 214 includes both a read access pointer and a write access pointer. The memory access unit 112 can be configured to process the descriptor indicated by the access pointer higher in the descriptor queue 214.

[0050] The number of subsequent descriptors read ahead of the read access pointer may be based on the amount of time it takes for memory unit 152 to transition from a low power state to an active state. In some implementations, the amount of time used is the minimum amount of time for the transition to occur. The amount of time may be based on and / or expressed as the number of clock cycles of a hardware processor that performs the memory access operation.

[0051] In some implementations, the number of subsequent descriptors that transition to the active state and are therefore pointed to by the power management pointer can be determined based on the length of time it takes memory unit 152 to transition from a low power state to an active state and / or the number of memory access operations the memory unit can perform per clock cycle. For example, memory access engine 112 may be capable of performing one memory operation per clock cycle. Furthermore, it may take at least five clock cycles for memory unit 152 to transition from a low power state to an active state. In this example, the power management pointer may point to a descriptor that is five positions below the currently processed descriptor in descriptor queue 214. For example, as shown in stage A of FIG. 2, the power management pointer points to descriptor 6, which is five positions below descriptor 1.

[0052] Power manager 120 may monitor the power management pointer and identify as subsequent descriptors all descriptors between the highest access pointer in the descriptor queue (e.g., the read access pointer of stage A) and the power management pointer. Power manager 120 may transition memory unit 152 corresponding to each subsequent descriptor to the active state if the memory unit 152 is not already in the active state.

[0053] Any number of power management pointers may be used to determine the corresponding group of subsequent descriptors for transition to the active state. For example, some memory units 152 may have different amounts of time required to transition from a lower power state to the active state. In another example, there may be different amounts of transition time depending on the low power state. For example, transitioning from a deep sleep state to the active state may take longer than transitioning from a light sleep state to the active state. The descriptor queue 214 may include power management pointers for different transition times (e.g., for different groups of memory units, each having a different transition time) and / or for each low power state. Each power management pointer may indicate the sequence of subsequent descriptors in which the memory unit 152 corresponding to the descriptor is transitioned to the active state.

[0054] As an example, a first power management pointer and a first group of subsequent descriptors may correspond to a first set of memory units 152 in volatile memory 150 belonging to one cluster. The first set of memory units 152 may require a first number of clock cycles to transition from a low power state to an active state. A second power management pointer and a second group of subsequent descriptors may correspond to a second set of memory units 152 in volatile memory 150 belonging to another cluster. The second set of memory units 152 may require a second number of clock cycles to transition from a low power state to an active state. The first power management pointer and the second power management pointer may have different numbers of subsequent descriptors that read ahead of the memory access pointer due to the difference in transition times.

[0055] Queue manager 116 may manage each power management pointer based on the respective number of descriptors and the descriptor corresponding to memory unit 152 for that power management pointer. For example, if the number of descriptors in the first set of memory units and first power management pointer is three, queue manager 116 may operate the first power management pointer such that the first power management pointer points to the third descriptor (not including the current descriptor being processed) in descriptor queue 214 that corresponds to memory unit 152 in the first set of memory units.

[0056] In some implementations, all pointers, e.g., read access pointer, write access pointer, and power management pointer, may be initialized to start at the top of the descriptor queue 214, e.g., before the agent 105 submits a memory access request. Upon receiving memory access requests, the memory access engine 112 may group the memory access requests by operation, e.g., read, write, etc., so that each pointer for the operation can track the group of operations. For example, the read access pointer may start tracking read memory accesses, and the write access pointer may start tracking write memory accesses.

[0057] Referring again to stage A, descriptor queue 214 indicates a read access pointer that points to a first descriptor, e.g., descriptor 1, while the power management pointer points to descriptor 6. The write access pointer simultaneously points to descriptor 12. In this example, descriptors 1 through 11 correspond to read operations, and descriptors 12 and 13 correspond to write operations.

[0058] The memory access engine 112 may monitor the read access pointer and the write access pointer to obtain the next descriptor for performing a memory operation. For example, the memory access engine 112 may obtain descriptor 1 from the descriptor queue 214 and perform the read operation corresponding to descriptor 1 based on the read access pointer indicating that descriptor 1 is the next read descriptor and that the read access pointer is higher in the descriptor queue 214 than the write access pointer.

[0059] Power manager 120 can monitor the power management pointers to identify a descriptor that will transition the corresponding memory unit to the active state. Power manager 120 can identify each descriptor between the top memory access pointer and the power management pointer (inclusive) as a subsequent descriptor. Power manager 120 can transition memory units 152 corresponding to each of these subsequent descriptors to the active state. In this example, power manager 120 can transition memory units 152 corresponding to descriptors 2-6 to the active state based on the power management pointer pointing to descriptor 6. Memory units 152 corresponding to subsequent descriptors, e.g., descriptors 2-6 in stage A, remain in the active state at least until memory access engine 112 has completed processing the descriptor, e.g., completed the memory operation corresponding to the descriptor.

[0060] As an example, the number of subsequent descriptors being scanned by the power management pointer can be particularly advantageous when the number of memory units 152 in the volatile memory 150 exceeds the number of descriptors between the memory access pointer and the power management pointer. For example, a volatile memory device such as an SRAM may have 32 memory units, e.g., an SRAM bank, with five subsequent descriptors in the descriptor queue 114 between the memory access pointer and the power management pointer. For example, assuming all five descriptors being scanned correspond to five memory units 152, out of the 32 memory units in the volatile memory, up to 27 memory units will be in a power-saving state.

[0061] Referring to stage B, the read access pointer is incremented, e.g., by queue manager 116, after descriptors 1-3 are processed by memory access engine 112. Queue manager 116 also increments the power management pointer for each processed descriptor. As shown, the power management pointer now points to descriptor 9, e.g., five descriptors after the currently accessed descriptor 4, maintaining the same number of subsequent descriptors in descriptor queue 214. In stage B, power manager 120 transitions descriptors 7-9 to the active state just as descriptors 4-6 transitioned to the active state in stage A.

[0062] Referring to stage C, the read access pointer is incremented after processing descriptors 4-7. Similarly, the power management pointer is incremented to point to descriptor 12. In stage C, power manager 120 transitions descriptors 10-12 to the active state just as descriptors 7-9 transitioned to the active state in stage A.

[0063] If the power management pointer points to a descriptor, e.g., descriptor 12 of descriptor queue 214, power manager 120 determines the memory address of the physical instance in volatile memory, e.g., determines the memory unit(s) corresponding to the descriptor that needs to transition to the active state. As an example, if a scanned descriptor having a scanned descriptor value points to memory unit 152 in volatile memory 150 that is currently in the active state, power manager 120 ensures that memory unit 152 remains active until the scanned descriptor is processed by memory access engine 112.

[0064] The address read ahead of the memory access pointer is used to determine which memory units need to transition to the active state. Other memory units with addresses not determined by the number of subsequent descriptors scanned by the power management pointer, or the current location of the memory access pointer, may remain in a low power state.

[0065] 3 shows a flow diagram of an example process 300 for transitioning a memory unit between an active state and a low power state. Process 300 can be performed by a memory system, such as memory system 100 of FIG. 1. For ease of explanation, process 300 is described as being performed by components of memory system 100.

[0066] A descriptor is received based on the power management pointer (302). For example, power manager 120 may identify one or more descriptors between (inclusive of) the descriptor at the first position in descriptor queue 114 and the descriptor pointed to by the power management pointer. Power manager 120 may transition memory units corresponding to these descriptors to an active state before the descriptors are processed, thereby preventing memory access engine 112 from having to wait to perform a memory access operation when the descriptor is processed. As described above, each descriptor may include data indicating a memory location at which the memory access operation is to be performed.

[0067] Power manager 120 determines whether memory unit 152 corresponding to the memory address of the descriptor is in an active state (304). As described above, power manager 120 may maintain status table 122 for memory unit 152. Power manager 120 may access status table 122 to determine whether memory unit 152 is in an active state. For example, power manager 120 may access a cell corresponding to memory unit 152 to obtain a label or value for the current state of memory unit 152. If memory unit 152 is in an active state, power manager 120 may keep the memory unit in an active state (306).

[0068] If memory unit 152 is not in the active state, power manager 120 may transition memory unit 152 to the active state (308). Power manager 120 may then keep memory unit 152 in the active state at least until a memory access operation of the memory unit is performed.

[0069] A determination is made (310) whether memory unit 152 has been accessed by the memory access engine. For example, memory access unit 112 may be configured to notify power manager 120 of each descriptor processed. In another example, power manager 120 may be configured to monitor a memory access pointer to determine when a descriptor has been processed. If memory unit 152 has not been accessed, process 300 may return to operation (306), and memory unit 152 may remain active until accessed.

[0070] To determine whether to return memory unit 152 to a lower power state, power manager 120 checks whether any of the subsequent descriptors, e.g., scanned descriptors, that are transitioned to the active state contain a memory address that points to memory unit 152 (312). For example, the memory access pointer and the power management pointer may indicate the number of subsequent descriptors for which the corresponding memory unit 152 should be in the active state. If the descriptor between the memory access pointer and the scan pointer points to the same memory unit 152 on which the memory access operation was just performed, power manager 120 maintains the memory unit in the active state. This prevents backpressure that would be caused if memory unit 152 were transitioned to a low power state if memory unit 152 is accessed again in an amount of time less than the amount of time it takes for memory unit 152 to transition from the low power state to the active state.

[0071] If power manager 120 determines that none of the subsequent descriptors between the memory access pointer and the power management pointer contain a memory location corresponding to memory unit 152, power manager 120 may transition memory unit 152 to a lower power state (314). Otherwise, process 300 may return to operation 306 where power manager 120 keeps memory unit 152 active so that descriptors corresponding to memory unit 152 can be processed without delay.

[0072] 4 shows a flow diagram of an example process 400 for accessing a memory unit and transitioning the memory unit between an active state and a low power state. Process 400 can be performed by a memory system, such as memory system 100, to manage volatile memory 150 to satisfy received memory access requests from one or more agents 105.

[0073] The memory controller 110 accesses (402) a descriptor queue, such as the descriptor queue 114. The descriptor queue 114 includes a sequence of descriptors, a memory access pointer, and a power management pointer. The queue manager 116 may be configured to update the descriptor queue with descriptors when the memory controller 110 receives a new memory access request. In some implementations, the memory access engine 114 of the memory controller 110 may be configured to process the new memory request. The descriptor queue may be a FIFO queue populated with descriptors corresponding to memory access operations from the agent device of the agent 105. The memory access engine 112 may be configured to read the sequence of descriptors from the sequence of descriptors based on the memory access pointer that accesses the memory address and the operation included in the descriptor.

[0074] The memory controller 110 identifies one or more subsequent descriptors in the descriptor queue 114 to transition to the active state (404). The power manager 120 can use the power management pointer to determine which subsequent descriptors the corresponding memory units should transition to the active state before the descriptors are processed by the memory access engine 114. As noted above, the number of subsequent descriptors identified can be based on the amount of time it takes for the memory units to transition from a low power state to the active state, for example, in terms of the number of clock cycles.

[0075] In some implementations, queue manager 116 maintains a distance in terms of the number of descriptors between the memory access pointer and the power management pointer. The number of descriptors of this distance can be based on the amount of time it takes memory unit 152 to transition from a low power state to an active state and / or the number of descriptors that can be processed simultaneously. The amount of time for the transition can be expressed as a number of clock cycles of a processor of memory system 100 or a processor of a system that includes and / or is communicatively coupled to memory system 100.

[0076] For example, if memory system 100 can process one descriptor per clock cycle and it takes memory unit 152 three clock cycles to transition from a low power state to an active state, then the distance between the memory access pointer and the power management pointer may be three descriptors. In this way, the power management pointer moves to a new descriptor every clock cycle and remains three descriptors ahead of the memory access pointer, such that the new descriptor has three clock cycles to transition to the active state before it reaches the head of descriptor queue 114.

[0077] In this way, each descriptor's memory unit 152 has enough time to transition to the active state before being processed by memory controller 110, but does not transition memory units 152 prematurely, causing them to remain in the active state longer than warranted. This reduces the amount of time memory units 152 are in the active state, thereby reducing the amount of leakage power, as well as the latency and backpressure caused by memory units 152 not being in the active state when the top of descriptor queue 114 is reached.

[0078] Power manager 120 transitions (406) the memory units corresponding to the identified subsequent descriptors that are currently in a low power state to an active state.

[0079] The memory controller 110 accesses one or more memory units for each subsequent descriptor when the memory access pointer points to the subsequent descriptor in the descriptor queue (408). The queue manager 116 is configured to update the memory access pointer and the power management pointer after each descriptor in the subsequent descriptor is processed by the memory controller 110. In some aspects, accessing the one or more memory units for each subsequent descriptor includes performing a memory access operation associated with the subsequent descriptor (e.g., reading data from a memory unit, writing data to a memory unit).

[0080] Embodiments of the subject matter and functional operations described herein can be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, or computer hardware, including the structures disclosed herein and their structural equivalents, or one or more combinations thereof. Embodiments of the subject matter described herein can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a tangible, non-transitory program carrier for execution by or to control the operation of a data processing apparatus. Alternatively or additionally, the program instructions can be encoded in an artificially generated propagated signal, such as a mechanically generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a receiving device suitable for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random-access or serial-access memory device, or one or more combinations thereof.

[0081] The processes and logic flows described herein may be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be performed by, and apparatus may be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array), or an ASIC (application specific integrated circuit), or a GPGPU (general purpose graphics processing unit).

[0082] A computer suitable for executing a computer program can include, e.g., be based on, a general-purpose or special-purpose microprocessor, or both, or any other type of central processing unit. Generally, the central processing unit receives instructions and data from a read-only memory, a random-access memory, or both. The basic components of a computer are a central processing unit for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also includes one or more mass storage devices, such as magnetic disks, magneto-optical disks, or optical disks, for storing data, or is operatively connected to receive data from or transmit data to them, or both. However, a computer need not have such devices. Furthermore, a computer can be incorporated into other devices, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name just a few.

[0083] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, by way of example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0084] While this specification contains many specific implementation details, these should not be construed as limiting the scope or claimable content of any invention, but rather as descriptions of features that may be inherent in particular embodiments of a particular invention. Certain features described herein as separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented in multiple embodiments, either separately or in any suitable subcombination. Furthermore, even if features may be described above as functioning in a particular combination and originally claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to subcombinations or variations of the subcombination.

[0085] Similarly, while operations are shown in the figures in a particular order, this should not be understood as requiring such operations to be performed in the particular order shown or in sequential order, or that all of the illustrated operations be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated into a single software product or packaged into multiple software products.

[0086] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims may be performed in a different order and still produce desirable results. By way of example, the processes depicted in the accompanying figures do not necessarily require the particular order shown or sequential order to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

1. 1. A memory system comprising: a volatile memory including a plurality of memory units; a descriptor queue configured to maintain a sequence of descriptors each corresponding to a received memory access request for performing a memory access operation at a respective memory unit of the plurality of memory units, the descriptor queue including a memory access pointer indicating a current descriptor being processed and a power management pointer indicating one or more subsequent descriptors for an active state transition, the memory system further comprising: a memory controller configured to process the descriptors in the descriptor queue based on the memory access pointers and to access the memory units of the descriptors to respond to received memory access requests corresponding to the descriptors in the descriptor queue; a power manager configured to selectively transition each memory unit between the active state and the low power state, including monitoring the power management pointer to identify the one or more subsequent descriptors and transitioning the respective memory unit from the low power state to the active state for each of the one or more subsequent descriptors before the one or more subsequent descriptors have been processed by the memory controller; A memory system comprising:

2. 2. The memory system of claim 1, wherein the descriptor queue comprises a first-in, first-out queue, and wherein each descriptor is removed from the descriptor queue after the memory controller performs the memory access operation indicated by the descriptor.

3. 3. The memory system of claim 1, wherein the volatile memory comprises a static random access memory (SRAM).

4. The descriptor queue includes a queue manager, the queue manager comprising: updating the descriptor queue to include a descriptor for each newly received memory access request; updating the memory access pointer after each descriptor is processed by the memory controller; 10. A memory system according to any preceding claim, configured to update the power management pointer after each descriptor is processed by the memory controller.

5. 10. The memory system of claim 1, wherein the one or more subsequent descriptors include a number of descriptors selected based on an amount of time it takes a memory unit to transition from the low power state to the active state.

6. 6. The memory system of claim 5, wherein the number of descriptors is based on a number of memory access operations that the memory controller can complete within the amount of time.

7. 6. The memory system of claim 5, wherein the number of descriptors is based on a number of processing unit clock cycles of a processor communicatively coupled to the volatile memory that occur during the amount of time.

8. 10. A memory system according to any preceding claim, wherein the descriptor queue includes one or more additional power management pointers that indicate additional sets of subsequent descriptors for active state transitions.

9. 9. The memory system of claim 8, wherein the subsequent additional set of descriptors includes an additional number of descriptors selected based on an amount of time it takes a memory unit corresponding to each additional descriptor to transition from the low power state to the active state.

10. 10. The memory system of claim 9, wherein the additional number of descriptors is based on the number of memory access operations the memory controller is able to complete within the length of time.

11. The power manager determining whether the respective memory unit of the current descriptor is a subsequent descriptor for an active state transition; leaving the respective memory units of the current descriptor in the active state after processing the current descriptor whenever the respective memory units of the current descriptor are subsequent descriptors for an active state transition; 10. The memory system of claim 9, further comprising: a memory controller configured to transition the respective memory unit of the current descriptor from the active state to the low power state whenever the respective memory unit of the current descriptor is not a subsequent descriptor for an active state transition.

12. 1. A method performed by a memory controller configured to manage a volatile memory comprising a plurality of memory units, the method comprising: accessing a descriptor queue, the descriptor queue comprising: a descriptor queue including a sequence of descriptors each corresponding to a received memory access request, each descriptor corresponding to a memory access operation for a respective memory unit of the plurality of memory units indicated by said descriptor, said descriptor queue further comprising: a memory access pointer indicating the current descriptor for processing; a power management pointer that points to one or more subsequent descriptors for active state transitions, the method further comprising: identifying the one or more subsequent descriptors based on the power management pointer; transitioning each subsequent descriptor in a low power state from said low power state to said active state; accessing the one or more memory units for each subsequent descriptor when the memory access pointer reaches the subsequent descriptor in the descriptor queue; A method comprising:

13. 13. The method of claim 12, wherein accessing the one or more memory units for each subsequent descriptor comprises performing the memory access operation for the subsequent descriptor.

14. 14. The method of claim 12 or 13, further comprising updating the memory access pointer and the power management pointer to point to a different descriptor each time the memory access operation for a descriptor is performed and the descriptor is removed from the descriptor queue.

15. performing the memory access operation for the current descriptor; and removing the current descriptor from the descriptor queue in response to performing the memory access operation of the current descriptor; updating the memory access pointer to point to the next descriptor in the descriptor queue following the current descriptor; updating the one or more subsequent descriptors for an active state transition by updating the power management pointer in response to performing the memory access operation of the current descriptor; The method of any one of claims 12 to 14, further comprising:

16. determining whether the respective memory unit of the current descriptor is a subsequent descriptor for an active state transition; leaving the respective memory units of the current descriptor in the active state after processing the current descriptor whenever the respective memory units of the current descriptor are subsequent descriptors for an active state transition; transitioning the respective memory unit of the current descriptor from the active state to the low power state whenever the respective memory unit of the current descriptor is not a subsequent descriptor for an active state transition; 16. The method of claim 15, further comprising:

17. The method of any of claims 12 to 16, further comprising identifying each descriptor between the memory access pointer and the power management pointer as the one or more subsequent descriptors.

18. 20. The method of claim 17, further comprising controlling the power management pointer to identify a particular number of subsequent descriptors based on a length of time it takes a memory unit to transition from the low power state to the active state.

19. 13. The method of claim 12, wherein the descriptor queue comprises a first-in, first-out queue, and each descriptor is removed from the descriptor queue after the memory controller performs the memory access operation indicated by the descriptor.

20. The method of claim 12 , wherein the volatile memory comprises static random access memory (SRAM).

21. The descriptor queue includes a queue manager, the queue manager comprising: updating the descriptor queue to include a descriptor for each newly received memory access request; updating the memory access pointer after each descriptor is processed by the memory controller; 13. The method of claim 12 configured to update the power management pointer after each descriptor is processed by the memory controller.

22. 22. The method of claim 12, wherein the one or more subsequent descriptors include a number of descriptors selected based on the length of time it takes a memory unit to transition from the low power state to the active state.

23. 23. The method of claim 22, wherein the number of descriptors is based on the number of memory access operations the memory controller can complete within the length of time.

24. 23. The method of claim 22, wherein the number of descriptors is based on a number of processing unit clock cycles of a processor communicatively coupled to the volatile memory that occur during the length of time.

25. determining that a particular descriptor corresponding to a particular memory unit is not in the descriptor queue; in response to determining that the particular descriptor corresponding to a particular memory unit is not in the descriptor queue, transitioning the particular memory unit to the low power state; The method of any of claims 12 to 24, further comprising:

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