Device, system and method for out-of-band delivery of error reports

Abstract

An exemplary computing device includes an in-band processor and an out-of-band controller. The exemplary computing device also includes a machine check architecture including a pipeline and a plurality of error detectors. The error detectors are configured to detect errors occurring in the plurality of circuits and report the errors via the pipeline to the in-band processor and the out-of-band controller. Various other devices, systems, and methods are also disclosed.

Description

[Background technology]

[0001] Machine check architectures are often used to report errors to an operating system running on a processor. In some examples, the operating system running on the processor logs the error and forwards a copy of the error to an out-of-band controller (e.g., a baseboard management controller). This forwarding of a copy of the error constitutes out-of-band work for the operating system and / or processor, which can lead to performance degradation of substantial in-band workloads (e.g., user applications). Accordingly, the present disclosure identifies and addresses the need for additional and improved devices, systems, and methods for out-of-band delivery of error reports generated by machine check architectures.

[0002] The accompanying drawings illustrate several exemplary embodiments and are a part of this specification, and together with the following description, these drawings demonstrate and explain various principles of the present disclosure. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of a portion of an example computing device that facilitates out-of-band delivery of error reports in accordance with one or more embodiments of the present disclosure. [Figure 2] FIG. 1 is a block diagram of an example machine check architecture that facilitates out-of-band delivery of error reports in accordance with one or more embodiments of the present disclosure. [Figure 3] FIG. 1 is a block diagram of an example computing device that facilitates out-of-band delivery of error reports in accordance with one or more embodiments of the present disclosure. [Figure 4] FIG. 1 illustrates an exemplary computing device that facilitates out-of-band delivery of error reports in accordance with one or more embodiments of the present disclosure. [Figure 5]FIG. 1 is a block diagram of an example embodiment involving a computing system that facilitates out-of-band delivery of error reports in accordance with one or more variations of the present disclosure. [Figure 6] 1 is a flowchart of an example method for out-of-band delivery of error reports, in accordance with one or more embodiments of the present disclosure. [Figure 7] FIG. 1 is a block diagram of a portion of an example in-band processor implementing a bank of machine check architecture in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0004] Throughout the drawings, like reference numerals and descriptions indicate similar, but not necessarily identical, elements. While the exemplary embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

[0005] This disclosure describes various devices, systems, and methods for out-of-band delivery of error reports. In some examples, traditional delivery of error reports to an out-of-band controller (e.g., a baseboard management controller) can impair and / or degrade the performance of the processor forwarding the error reports. In addition to forwarding error reports to the out-of-band controller, such processors often elevate reporting privileges above those of typical user applications, thus causing the processor to operate in system management mode. Unfortunately, system management mode creates security vulnerabilities that may allow malware to gain control of the processor.

[0006] Additionally, machine check architectures often include shadow registers accessible to both the operating system and the out-of-band controller to change the state of the error report. These shadow registers can create race conditions between the operating system and the out-of-band controller, potentially resulting in undesirable results and / or sequencing. As described in more detail below, the devices, systems, and methods described herein can extend and / or augment the machine check architecture so that a reporting entity (e.g., a memory controller, a central processing unit, etc.) can simultaneously send error reports to the processor and the out-of-band controller.

[0007] For example, the machine-check architecture extension block and / or circuitry may constitute and / or represent a single unified interface that includes a fork that creates two independent and / or parallel lanes for simultaneously reporting errors to the processor and the out-of-band controller. In doing so, the machine-check architecture extension block and / or circuitry facilitates error reporting to both the processor and the out-of-band controller without requiring an operating system running on the processor to extend its in-band workload capabilities for out-of-band error reporting, thereby improving performance of user applications running on the processor. Furthermore, the machine-check architecture extension block and / or circuitry facilitates error reporting to both the processor and the out-of-band controller without elevating the processor to system management mode or creating a race condition between the operating system and the out-of-band controller, thereby improving processor security and / or mitigating inconsistencies or inconsistencies between the operating system and the out-of-band controller due to race conditions.

[0008] In some examples, a computing device includes an in-band processor and an out-of-band controller. In such examples, the computing device includes a machine check architecture including a pipeline and multiple error detectors. In one example, the error detector is configured to detect errors occurring in the multiple circuits and report the errors via the pipeline to the in-band processor and the out-of-band controller.

[0009] In some examples, the pipeline includes a unified lane configured to carry the error report toward the in-band processor and the out-of-band controller. In such examples, the pipeline includes a fork configured to split the unified lane into a first lane and a second lane. In one example, the first lane carries a first copy of the error report toward the in-band processor and the second lane carries a second copy of the error report toward the out-of-band controller.

[0010] In some examples, the machine check architecture comprises at least one in-band register configured to receive a first copy of the error report via a first lane and store the first copy of the error report for access by the in-band processor. In such examples, the machine check architecture comprises at least one out-of-band register configured to receive a second copy of the error report via a second lane and store the second copy of the error report for access by the out-of-band controller.

[0011] In some examples, the in-band processor is configured to access the first copy of the error report via an in-band register and is restricted from accessing the second copy of the error report via an out-of-band register. Additionally or alternatively, the in-band processor comprises an operating system configured to retrieve the first copy of the error report from the in-band register.

[0012] In some examples, the out-of-band controller is configured to access the second copy of the error report via an out-of-band register and is restricted from accessing the first copy of the error report via an in-band register. Additionally or alternatively, the out-of-band controller comprises a baseboard management controller and / or a system management unit communicatively coupled to the baseboard management controller.

[0013] In some examples, the system management unit is configured to access a second copy of the error report via an out-of-band register and provide the second copy of the error report to the baseboard management controller. In one example, the computing device also includes a first integrated circuit including an in-band processor, a machine check architecture, and a system management unit, and a second integrated circuit external to the first integrated circuit and including the baseboard management controller.

[0014] In some examples, the in-band processor and the out-of-band controller are configured to make error logging decisions independently of one another. Additionally or alternatively, the out-of-band controller is configured to instruct the machine check architecture to perform a particular action in response to a particular error detected in either circuit. For example, the particular action may include and / or represent triggering an interrupt that notifies the out-of-band controller of the particular error.

[0015] In some examples, a system includes a first integrated circuit including an out-of-band controller and a second integrated circuit communicatively coupled to the first integrated circuit. In such examples, the second integrated circuit includes an in-band processor and a machine check architecture including a pipeline and multiple error detectors. In one example, the error detector is configured to detect errors occurring in the multiple circuits and report the errors via the pipeline to the in-band processor and the out-of-band controller.

[0016] In some examples, the method includes generating an in-band processor and a machine check architecture. In such examples, the machine check architecture comprises a pipeline and a plurality of error detectors. In one example, the error detectors are configured to detect errors occurring in the plurality of circuits and report the errors via the pipeline to the in-band processor and the out-of-band controller. Additionally or alternatively, the method includes communicatively coupling the out-of-band controller to the machine check architecture.

[0017] The following provides a detailed description of example devices, systems and / or corresponding embodiments for out-of-band delivery of error reports with reference to Figures 1-5 and 7. A detailed description of an example method for out-of-band delivery of error reports is provided in connection with Figure 6.

[0018] 1 illustrates an example computing device 100 that facilitates and / or supports out-of-band delivery of error reports. As shown in FIG. 1, the example computing device 100 includes and / or represents a machine check architecture 102, an in-band processor 104, and / or an out-of-band controller 106. In some examples, the in-band processor 104 and / or the out-of-band controller 106 are electrically and / or communicatively coupled to the machine check architecture 102. In one example, the machine check architecture 102 includes and / or represents a pipeline 112 and / or a plurality of circuits 108(1)-(N). In this example, each of the circuits 108(1)-(N) includes and / or represents an error detector 110(1)-(N). In one particular embodiment, each of the error detectors 110(1)-(N) detects errors occurring in the circuits 108(1)-(N) and / or reports the errors to the in-band processor 104 and the out-of-band controller 106 via the pipeline 112.

[0019] In some examples, machine check architecture 102 may include and / or represent circuits, devices, and / or mechanisms that detect errors and / or report errors to other circuits, devices, and / or mechanisms. For example, a system on a chip (SoC) may include and / or implement machine check architecture 102 as well as various processors and / or central processing unit (CPU) cores. In this example, machine check architecture 102 is configured and / or programmed to monitor for hardware errors occurring in circuits 108(1)-(N), processors or CPU cores implemented on the SoC, and / or other functions or components of the SoC.

[0020] In some examples, circuits 108(1)-(N) include and / or represent hardware blocks and / or banks of machine check architecture 102. In one example, the hardware blocks and / or banks include and / or represent memory controllers and / or CPU cores. Additionally or alternatively, the hardware blocks and / or banks include and / or represent control registers and / or model-specific registers used to check, detect, and / or log various hardware and / or machine errors. Examples of such errors include, but are not limited to, memory or cache errors, buffer errors, translation errors, parity errors, system bus errors, error-correcting code (ECC) failures, error detection and correction (EDAC) failures, communication errors, input / output (I / O) errors, one or more portions thereof, combinations or variations of one or more thereof, and / or any other detectable error.

[0021] In some examples, machine check architecture 102 may be instantiated and / or implemented as multiple banks across one or more CPU sub-blocks. For example, as shown in FIG. 7, in-band processor 104 may include and / or represent CPU 702. In the example shown in FIG. 7, CPU 702 may include and / or represent at least CPU sub-blocks 704(1), 704(2), 704(3), and / or 704(4). In one example, each of CPU sub-blocks 704(1)-(4) may include and / or implement machine check architecture bank 706(1), 706(2), 706(3), and / or 706(4). Thus, machine check architecture 102 may be distributed across CPU sub-blocks 704(1)-(4), and / or machine check architecture bank 706(1)-(4) may log specific groups of errors per CPU sub-block. In one particular embodiment, each CPU may include and / or represent between 3 and 10 instantiations of the machine check architecture distributed across corresponding CPU sub-blocks.

[0022] In some examples, the in-band processor 104 may include and / or represent a hardware-implemented device and / or circuitry capable of executing firmware, an operating system, and / or user applications. For example, the in-band processor 104 may include and / or represent a graphics processing unit (GPU), a GPU core, a CPU, and / or a CPU core. In this example, the in-band processor 104 may include and / or represent any of several processors (e.g., several x86 processors) implemented and / or located on an SoC. Further examples of the in-band processor 104 include, but are not limited to, a parallel acceleration processor, a tensor core, a microprocessor, a microcontroller, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an integrated circuit, a chiplet, one or more portions thereof, one or more variations or combinations thereof, and / or any other suitable in-band processor.

[0023] The in-band processor 104 may implement and / or be configured with any of a variety of different architectures and / or microarchitectures. For example, the in-band processor 104 may be implemented and / or configured as a reduced instruction set computer (RISC) architecture. In another example, the in-band processor 104 may be implemented and / or configured as a complex instruction set computer (CISC) architecture. Additional examples of such architectures and / or microarchitectures include, but are not limited to, 16-bit computer architecture, 32-bit computer architecture, 64-bit computer architecture, x86 computer architecture, advanced RISC machine (ARM) architecture, microprocessor without interlocked pipelined stage (MIPS) architecture, scalable processor architecture (SPARC), load-store architecture, portions of one or more of these, combinations or variations of one or more of these, and / or any other suitable architecture or microarchitecture.

[0024] In some examples, the out-of-band controller 106 may include and / or represent hardware-implemented devices and / or circuits that can control and / or modify certain hardware functions and / or components on an integrated circuit (e.g., an SoC implementing various CPU cores). In one example, the out-of-band controller 106 may include and / or represent devices and / or circuits that are on-board (e.g., on-chip) and / or internal to an SoC implementing the in-band processor 104. For example, the out-of-band controller 106 may include and / or represent a system management unit implemented on-board and / or internal to an SoC. In another example, the out-of-band controller 106 may include and / or represent a baseboard management controller implemented outside (e.g., off-chip) and / or external to an SoC implementing the in-band processor 104. Further examples of the out-of-band controller 106 include, but are not limited to, a microprocessor, a microcontroller, an FPGA, an ASIC, an integrated circuit, a chiplet, one or more portions thereof, one or more variations or combinations thereof, and / or any other suitable out-of-band controller.

[0025] In some examples, the term “out-of-band” may refer to any components, circuits, and / or processes dedicated to and / or supporting the control plane (e.g., control data and / or firmware), management plane, and / or data related to the underlying device (e.g., SoC). In contrast, the term “in-band” may refer to any components, circuits, and / or processes dedicated to and / or supporting the user plane (e.g., user data and / or user applications) running on a processor (e.g., CPU cores of an SoC) and / or implemented by the processor. In one example, an in-band workload of an SoC may include and / or represent computing tasks performed for and / or in connection with user applications executed on the processor, and an out-of-band workload of an SoC may include and / or represent computing tasks performed for any other purpose other than being utilized and / or consumed by such user applications.

[0026] 2 illustrates an example embodiment of machine check architecture 102 that facilitates and / or supports out-of-band delivery of error reports. In some examples, machine check architecture 102 may include and / or represent certain components and / or functions that perform and / or provide similar and / or identical functions as those described above in connection with FIG. 1. In one example, pipeline 112 of machine check architecture 102 includes and / or represents unified lane 212, fork 214, single lane 222, and / or single lane 224. In this example, unified lane 212 conveys and / or forwards error report 220 toward both in-band processor 104 and out-of-band controller 106.

[0027] In some examples, the consolidated lane 212 is electrically and / or communicatively coupled to the fork 214. In such examples, the consolidated lane 212 supplies and / or distributes the error report 220 to the fork 214, and the fork 214 replicates and / or copies the error report 220. For example, the fork 214 bifurcates and / or splits the consolidated lane 212 into a single lane 222 and a single lane 224. In this example, the single lane 222 carries and / or forwards one copy of the error report 220 toward the in-band processor 104, and the single lane 224 carries and / or forwards another copy of the error report 220 toward the out-of-band controller 106.

[0028] In some examples, the machine check architecture 102 includes and / or represents one or more in-band registers 216 and / or out-of-band registers 218. In one example, a single lane 222 can electrically and / or communicatively couple the fork 214 to the in-band register 216. Additionally or alternatively, a single lane 224 can electrically and / or communicatively couple the fork 214 to the out-of-band register 218.

[0029] In some examples, each of the error detectors 110(1)-(N) monitors and / or detects a particular error within and / or via the circuits 108(1)-(N). In such examples, one or more of the error detectors 110(1)-(N) generates and / or issues an error report 220 in response to detecting such an error. In one example, the error detectors 110(1)-(N) can send and / or transmit the error report 220 via the pipeline 112 to both the in-band processor 104 and the out-of-band controller 106. For example, the error report 220 can traverse and / or propagate via the integration lane 212 from one or more of the circuits 108(1)-(N) to the fork 214. In this example, the fork 214 can copy the error report 220 for transmission to both the in-band register 216 and the out-of-band register 218. Thus, one copy of the error report 220 may traverse and / or propagate from the fork 214 to the in-band register 216 via a single lane 222, and another copy of the error report 220 may traverse and / or propagate from the fork 214 to the out-of-band register 218 via a single lane 224.

[0030] In some examples, the in-band register 216 receives one copy of the error report 220 and stores the copy of the error report 220 for access by the in-band processor 104. Additionally or alternatively, the out-of-band register 218 receives another copy of the error report 220 and stores the copy of the error report 220 for access by the out-of-band controller 106. By delivering the copy of the error report 220 to both the in-band register 216 and the out-of-band register 218 via the pipeline 112, the machine check architecture 102 allows the out-of-band controller 106 to access and / or obtain the copy of the error report 220 without having the in-band processor 104 forward the copy of the error report 220 to the out-of-band controller 106, thereby mitigating and / or reducing the out-of-band work performed by the in-band processor 104, improving its performance or efficiency, and / or avoiding race conditions between the in-band processor 104 and the out-of-band controller 106. Furthermore, by bypassing the in-band processor 104 when delivering a copy of the error report 220 to the out-of-band controller 106, the machine check architecture 102 can prevent and / or avoid the need to cause the in-band processor 104 to enter system management mode, thereby mitigating and / or reducing a corresponding security vulnerability.

[0031] FIG. 3 illustrates an exemplary embodiment of a computing device 100 that facilitates and / or supports out-of-band delivery of error reports. In some examples, computing device 100 may include and / or represent certain components and / or features that perform and / or provide similar and / or identical functions as those described above in connection with either of FIGS. 1 and 2. In one example, computing device 100 includes and / or represents integrated circuit 302 and / or integrated circuit 304 that are communicatively coupled to each other. In this example, integrated circuit 302 includes and / or represents machine check architecture 102 and / or in-band processor 104, and integrated circuit 304 includes and / or represents out-of-band controller 106. Thus, integrated circuit 304 is off-chip and / or external to integrated circuit 302. However, integrated circuits 302 and 304 may be located and / or applied to the same circuit board.

[0032] In some examples, the integrated circuit 302 includes and / or represents an SoC with multiple CPU cores and machine check architecture 102. In one example, the in-band processor 104 is on-chip and / or internal to the SoC, and the out-of-band controller 106 is off-chip and / or external to the SoC. In this example, the in-band processor 104 has access to copies of the error reports 220 stored in the in-band registers 216 but has limited access to copies of the error reports 220 stored in the out-of-band registers 218. For example, the in-band processor 104 may implement and / or execute an operating system 306 that acquires, receives, and / or retrieves copies of the error reports 220 from the in-band registers 216. Additionally or alternatively, the out-of-band controller 106 has access to copies of the error reports 220 stored in the out-of-band registers 218 but has limited access to copies of the error reports 220 stored in the in-band registers 216.

[0033] In some examples, the in-band processor 104 and the out-of-band controller 106 can make error logging decisions independently of one another. For example, the in-band processor 104 can clear certain flags (e.g., status flags) in the in-band registers 216 that remain set in the out-of-band registers 218. Alternatively, the out-of-band controller 106 can clear certain flags (e.g., status flags) in the out-of-band registers 218 that remain set in the in-band registers 216. In either case, such flag discrepancies across the in-band registers 216 and the out-of-band registers 218 can cause the in-band registers 216 and the out-of-band registers 218 to log and / or ignore different errors from the same error report. Thus, the in-band processor 104 and the out-of-band controller 106 can have independent control and / or programmability over their respective registers in the machine check architecture 102.

[0034] FIG. 4 illustrates another exemplary embodiment of a computing device 100 that facilitates and / or supports out-of-band delivery of error reports. In some examples, the computing device 100 may include and / or represent certain components and / or features that perform and / or provide similar and / or identical functions as those described above in connection with any of FIGS. 1-3. As shown in FIG. 4, the exemplary computing device 100 includes and / or represents an integrated circuit 302 and / or an integrated circuit 304 that are communicatively coupled to each other. In one example, the integrated circuit 302 includes and / or represents the machine check architecture 102, the in-band processor 104, and / or the out-of-band interface 404. In this example, the integrated circuit 304 includes and / or represents the out-of-band controller 106 that is communicatively coupled to the out-of-band interface 404 that facilitates access to a copy of the error report 220 stored in the out-of-band register 218 of the out-of-band controller 106.

[0035] In some examples, the out-of-band interface 404 may include and / or represent a system management unit that obtains, receives, and / or retrieves a copy of the error report 220 from the out-of-band register 218. Additionally or alternatively, the out-of-band controller 106 may include and / or represent a baseboard management controller that interfaces with and / or communicates with the system management unit. In one example, the baseboard management controller obtains, receives, and / or retrieves a copy of the error report 220 from the system management unit.

[0036] In some examples, the out-of-band controller 106 and / or the out-of-band interface 404 may command and / or instruct the machine check architecture 102 to perform one or more particular actions in response to a particular error identified and / or included in the error report 220. For example, the out-of-band controller 106 and / or the out-of-band interface 404 may program and / or configure the out-of-band registers 218 to initiate and / or trigger a particular action in response to a particular error. In one example, the particular action may include and / or represent triggering an interrupt that notifies the out-of-band controller 106 of the particular error. For example, the out-of-band interface 404 may be programmed and / or configured to generate an interrupt that notifies the out-of-band controller 106 of the particular error.

[0037] Figure 5 illustrates an example embodiment 500 involving a computing system 502. In some examples, computing system 502 may include and / or represent certain components and / or functionality that perform and / or provide similar and / or identical functionality as described above in connection with any of Figures 1-4. As shown in example embodiment 500 of Figure 5, computing system 502 includes and / or represents SoC 506 with machine check architecture 102 and / or system management unit 508.

[0038] In some examples, computing system 502 includes and / or represents a baseboard management controller 510 electrically and / or communicatively coupled to a system management unit 508. In one example, system management unit 508 obtains, receives, and / or retrieves a copy of the error report from an out-of-band register within machine check architecture 102. In this example, baseboard management controller 510 then obtains, receives, and / or retrieves a copy of the error report from system management unit 508 to facilitate processing and / or decision making.

[0039] 1-5 and 7 may include and / or represent one or more additional circuits, components, and / or functions not necessarily shown and / or labeled in FIGS. 1-5 and 7. For example, computing device 100 may include and / or represent additional analog and / or digital circuits, on-board logic, transistors, resistors, capacitors, diodes, inductors, switches, registers, flip-flops, connections, traces, buses, semiconductor (e.g., silicon) devices and / or structures, processing devices, storage devices, circuit boards, packages, substrates, housings, combinations or variations of one or more of these, and / or any other suitable components that facilitate and / or support out-of-band delivery of error reports. In particular embodiments, one or more of these additional circuits, components, devices, and / or functions may be inserted between and / or applied to any of the existing circuits, components, and / or devices shown in FIGS. 1-5 and 7 consistent with the purposes and / or goals provided herein. Thus, the electrical and / or communication couplings described with reference to Figures 1-5 and 7 may be direct connections without intermediate components, devices and / or nodes, or indirect connections involving one or more intermediate components, devices and / or nodes.

[0040] In some examples, the phrase "couple" and / or the term "coupling" as used herein may refer to a direct connection and / or an indirect connection. For example, a direct coupling between two components may constitute and / or represent a coupling in which the two components are directly connected to each other by a single node that provides electrical continuity from one of the two components to the other. In other words, a direct coupling may exclude and / or omit any additional components between the two components.

[0041] Additionally or alternatively, an indirect coupling between two components may constitute and / or represent a coupling in which the two components are indirectly connected to each other by multiple nodes that do not provide electrical continuity from one of the two components to the other. In other words, an indirect coupling may include and / or incorporate at least one additional component between the two components.

[0042]

[0023] Figure 6 is a flow diagram of an example method 600 for out-of-band delivery of error reports. In one example, the steps illustrated in Figure 6 may be implemented and / or performed during manufacturing and / or assembly of a computing device and / or system. Additionally or alternatively, the steps illustrated in Figure 6 may incorporate and / or involve various sub-steps and / or variations consistent with the description provided above in connection with Figures 1-5.

[0043] As shown in Figure 6, the exemplary method 600 includes and / or involves generating (610) an in-band processor. Step 610 may be performed in a variety of ways, including any of the ways described above in connection with Figures 1-5. For example, a computing device manufacturer and / or a subcontractor may generate, manufacture, and / or produce the in-band processor.

[0044] The example method 600 also includes generating (620) a machine check architecture that includes a pipeline and a plurality of error detectors configured to detect errors occurring in the plurality of circuits and report the errors via the pipeline to the in-band processor and the out-of-band controller. Step 620 may be performed in various manners, including any of the manners described above in connection with Figures 1-5. For example, a computing equipment manufacturer and / or subcontractor may generate, manufacture, and / or produce a machine check architecture that includes a pipeline and a plurality of error detectors configured to detect errors occurring in the plurality of circuits and report the errors via the pipeline to the in-band processor and the out-of-band controller.

[0045] The example method 600 further includes communicatively coupling 630 the out-of-band controller to the machine check architecture. Step 630 may be performed in a variety of ways, including any of the ways described above in connection with Figures 1-5. For example, the manufacturer and / or subcontractor of the computing equipment may communicatively couple and / or connect the out-of-band controller to the machine check architecture.

[0046] While the above disclosure describes various embodiments using specific block diagrams, flowcharts, and examples, each block diagram element, flowchart step, operation, and / or component described and / or illustrated herein may be individually and / or collectively implemented using a wide variety of hardware, software, or firmware (or any combination thereof) configurations. It should be noted that any disclosure of components contained within other components should be considered exemplary in nature, as many other architectures can be implemented to achieve the same functionality. Furthermore, the various steps, events, and / or functions performed by such components should be considered exemplary in nature, as many alternatives and / or variations can be implemented to achieve the same functionality within the scope of the disclosure.

[0047] The process parameters and order of steps described and / or illustrated herein are given by way of example only and can be changed as desired. For example, although the steps illustrated and / or described herein are shown or described in a particular order, these steps do not necessarily have to be performed in the order illustrated or described. The various exemplary methods described and / or illustrated herein may omit one or more of the steps described or illustrated herein or may include additional steps in addition to those disclosed.

[0048] The foregoing description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0049] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and claims should be interpreted as allowing both direct and indirect connections (i.e., via other elements or components). Additionally, the terms "a" or "an" as used in this specification and claims should be interpreted as meaning "at least one of." Finally, for ease of use, the terms "including" and "having" (and their derivatives) as used in this specification and claims are interchangeable with the term "comprising," and have the same meaning.

Claims

1. 1. A computing device comprising: an in-band processor; an out-of-band controller; a machine check architecture; The machine check architecture comprises: Pipeline and a plurality of error detectors; The plurality of error detectors Detecting errors occurring in multiple circuits; reporting the error to the in-band processor and the out-of-band controller via the pipeline; configured to: Computing devices.

2. The pipeline comprises: an integrated lane configured to convey error reports toward the in-band processor and the out-of-band controller; a fork; The fork connects the integrated lanes to a first lane for conveying a first copy of the error report toward the in-band processor; a second lane that conveys a second copy of the error report toward the out-of-band controller; configured to divide into The computing device of claim 1.

3. The machine check architecture comprises: at least one in-band register; at least one out-of-band register; The at least one in-band register comprises: receiving the first copy of the error report via the first lane; storing the first copy of the error report for access by the in-band processor; and The at least one out-of-band register receiving the second copy of the error report via the second lane; storing the second copy of the error report for access by the out-of-band controller; configured to: The computing device of claim 2.

4. The in-band processor configured to access the first copy of the error report via the in-band register; access to the second copy of the error report via the out-of-band register is restricted; The computing device of claim 3.

5. the in-band processor comprising an operating system configured to retrieve the first copy of the error report from the in-band register; The computing device of claim 4.

6. The out-of-band controller configured to access the second copy of the error report via the out-of-band register; access to the first copy of the error report via the in-band register is restricted; The computing device of claim 3.

7. The out-of-band controller a baseboard management controller, or a system management unit communicatively coupled to the baseboard management controller; At least one of The computing device of claim 3.

8. The system management unit accessing the second copy of the error report via the out-of-band register; providing the second copy of the error report to the baseboard management controller; configured to: The computing device of claim 7.

9. a first integrated circuit including the in-band processor, the machine check architecture, and the system management unit; a second integrated circuit external to the first integrated circuit and including the baseboard management controller; The computing device of claim 7.

10. the in-band processor and the out-of-band controller are configured to make error logging decisions independently of each other; The computing device of claim 1.

11. the out-of-band controller is configured to instruct the machine check architecture to perform a particular action in response to a particular error detected in any of the plurality of circuits. The computing device of claim 1.

12. the specific action includes triggering an interrupt that notifies the out-of-band controller of the specific error; The computing device of claim 11.

13. 1. A system comprising: a first integrated circuit including an out-of-band controller; a second integrated circuit communicatively coupled to the first integrated circuit; The second integrated circuit comprises: an in-band processor; a machine check architecture; The machine check architecture comprises: Pipeline and a plurality of error detectors; The plurality of error detectors Detecting errors occurring in multiple circuits; reporting the error to the in-band processor and the out-of-band controller via the pipeline; configured to: system.

14. The pipeline comprises: an integrated lane configured to convey error reports toward the in-band processor and the out-of-band controller; a fork; The fork connects the integrated lanes to a first lane for conveying a first copy of the error report toward the in-band processor; a second lane that conveys a second copy of the error report toward the out-of-band controller; configured to divide into The system of claim 13.

15. The machine check architecture comprises: at least one in-band register; at least one out-of-band register; The at least one in-band register comprises: receiving the first copy of the error report via the first lane; storing the first copy of the error report for access by the in-band processor; and The at least one out-of-band register receiving the first copy of the error report via the first lane; storing the second copy of the error report for access by the out-of-band controller; configured to:

15. The system of claim 14.

16. The in-band processor configured to access the first copy of the error report via the in-band register; access to the second copy of the error report via the out-of-band register is restricted; 15. The system of claim 14.

17. the in-band processor comprising an operating system configured to retrieve the first copy of the error report from the in-band register; 17. The system of claim 16.

18. The out-of-band controller configured to access the second copy of the error report via the out-of-band register; access to the first copy of the error report via the in-band register is restricted; 16. The system of claim 15.

19. The out-of-band controller a baseboard management controller, or a system management unit communicatively coupled to the baseboard management controller; At least one of 16. The system of claim 15.

20. generating an in-band processor; generating a machine check architecture, the machine check architecture comprising a pipeline and a plurality of error detectors configured to detect errors occurring in a plurality of circuits and report the errors via the pipeline to the in-band processor and the out-of-band controller; communicatively coupling the out-of-band controller to the machine check architecture; method.

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