Inductively coupled plasma source with parallel helical RF coils.

Abstract

A substrate processing system includes a processing chamber and an RF generator configured to generate RF power. A matching network is connected to the RF generator. N spiral coils are connected to the matching network and include M turns, where N and M are integers greater than 1. The N spiral coils are wound symmetrically around an outer surface of the processing chamber. The N spiral coils are connected in parallel to the matching network.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63 / 434,305, filed December 21, 2022. The entire disclosures of the above-referenced applications are incorporated herein by reference.

[0002] The present disclosure relates to substrate processing systems, and more particularly to an inductively coupled plasma source with parallel helical radio frequency (RF) coils. [Background technology]

[0003] The background art description provided herein is intended to generally present the context for the present disclosure. The work of the presently named inventors, to the extent that that work is described in this background art section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted expressly or impliedly as prior art to the present disclosure.

[0004] Substrate processing systems can be used to etch films on substrates, such as semiconductor wafers. Substrate processing systems generally include a processing chamber, a gas distribution device, and a substrate support. During processing, the substrate is placed on the substrate support. Different gas mixtures can be introduced into the processing chamber, and radio frequency (RF) plasma can be used to activate chemical reactions.

[0005] In some substrate processing systems, plasma is generated inside the processing chamber using an induction coil located outside the processing chamber. Current flowing through the induction coil generates a time-varying electromagnetic field inside the processing chamber. The time-varying electromagnetic field excites a process gas mixture in the processing chamber to generate the plasma. The plasma is used to process a substrate disposed on a substrate support. Variations in the plasma at different locations in the processing chamber can cause process non-uniformities. Summary of the Invention

[0006] A substrate processing system includes a processing chamber and an RF generator configured to generate RF power. A matching network is connected to the RF generator. N spiral coils are connected to the matching network and include M turns, where N and M are integers greater than 1. The N spiral coils are symmetrically interwound around an outer surface of the processing chamber. The N spiral coils are connected in parallel to the matching network.

[0007] In other features, N and M are equal to 2, N is equal to 3, or N is equal to 4. First ends of the N spiral coils are connected to a matching network. The first ends of the N spiral coils are connected adjacent a lower portion of the processing chamber. Second ends of the N spiral coils are connected to first terminals of a first capacitor.

[0008] In other features, second ends of the N spiral coils are connected adjacent to an upper portion of the processing chamber. A ground plane is disposed between the first capacitor and the N spiral coils. An enclosure surrounds the first capacitor, the enclosure being made of a conductive material and grounded. The N spiral coils are rotationally offset by 360 / N degrees.

[0009] In other features, N capacitors are connected between intermediate portions of the N spiral coils, where N is equal to 2, 3, or 4. An enclosure surrounds the first capacitor and the N capacitors. The enclosure is made of a conductive material and is grounded.

[0010] In other features, the processing chamber has one of a dome shape and a bell jar shape. The N helical coils are wound smoothly and gradually into a helical shape.

[0011] In other features, the N helical coils are wound in a helical shape with a plurality of levels and transitions between the plurality of levels, the plurality of levels being evenly spaced apart vertically, and a first vertical spacing between a first pair of the plurality of levels being different from a second vertical spacing between a second pair of the plurality of levels.

[0012] Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims, and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

[0013] The present disclosure will become more fully understood from the detailed description and accompanying drawings. [Brief explanation of the drawings]

[0014] [Figure 1A] FIG. 1 is a functional block diagram of an example substrate processing system according to the present disclosure.

[0015] [Figure 1B] FIG. 2 is a perspective view of an example of an asymmetric series RF source disposed around the exterior surface of a processing chamber.

[0016] [Figure 1C] FIG. 1C is an electrical schematic diagram of the asymmetric series RF source of FIG. 1B.

[0017] [Figure 2A] 1 is a simplified cross-sectional view of an example of symmetrical parallel RF sources arranged around the exterior surface of a processing chamber according to the present disclosure.

[0018] [Figure 2B] FIG. 2B is an electrical schematic diagram of the symmetrical parallel RF source in FIG. 2A.

[0019] [Figure 2C] FIG. 2 is a perspective view of an example of first and second interwound helical coils according to the present disclosure.

[0020] [Figure 2D] 2D is a side view of the first and second interwound helical coils of FIG. 2C. FIG.

[0021] [Figure 2E] FIG. 10 is a perspective view of another example of first and second interwound helical coils according to the present disclosure.

[0022] [Figure 2F] 2D is a side view of the first and second interwound helical coils of FIG. 2C. FIG.

[0023] [Figure 3A] 10 is a simplified cross-sectional view of another example of a symmetrical parallel RF source disposed around the outer surface of a processing chamber and including an intermediate capacitor on each spiral coil in accordance with the present disclosure.

[0024] [Figure 3B] FIG. 3B is an electrical schematic diagram of the symmetrical parallel RF source in FIG. 3A.

[0025] [Figure 4A] FIG. 1 is an electrical schematic diagram of an example of a symmetric parallel RF source including three helical coils. [Figure 4B] FIG. 1 is an electrical schematic diagram of an example of a symmetric parallel RF source including three helical coils.

[0026] [Figure 5A] FIG. 1 is an electrical schematic diagram of an example of a symmetric parallel RF source including four helical coils. [Figure 5B] FIG. 1 is an electrical schematic diagram of an example of a symmetric parallel RF source including four helical coils. DETAILED DESCRIPTION OF THE INVENTION

[0027] In the drawings, reference numbers may be reused to identify similar and / or equivalent elements.

[0028] A substrate processing system according to the present disclosure uses a symmetric parallel RF coil source to reduce plasma non-uniformity in the azimuthal direction.

[0029] When using an asymmetric series RF source, one end of a first or lower coil is connected to a first terminal of a first capacitor. The first coil is wrapped around the lower portion of the processing chamber and connected to a first terminal of the first capacitor (located adjacent to the middle of the processing chamber). The processing chamber may have a dome or bell jar shape. A second terminal of the first capacitor is connected to one end of a second or upper coil wrapped around the upper portion of the processing chamber. Another end of the second coil is connected to a second capacitor located above the processing chamber.

[0030] The asymmetric series configuration of the coils causes asymmetric RF coupling to the plasma in the azimuthal direction. Because the first capacitor is located near the processing chamber, the first capacitor causes localized low RF coupling to the plasma, resulting in cold spots, which increase plasma non-uniformity and overall processing non-uniformity.

[0031] The substrate processing system according to the present disclosure includes a symmetric parallel spiral RF coil source including two or more induction coils. For example, a first spiral coil and a second spiral coil are positioned 180 degrees apart, wound around a processing chamber, and connected in parallel. Because each parallel spiral coil has only two turns, it has lower inductance compared to the four-turn coil of a series spiral RF coil source. Therefore, the first capacitor (located adjacent to the outside of the processing chamber in the asymmetric series configuration) can be omitted without causing a high RF voltage on the parallel coil. Avoiding a high RF voltage on the RF coil prevents strong ion bombardment of the processing chamber, which can generate particles or cause chamber deposition problems. Therefore, the parallel spiral RF coil source eliminates the first capacitor close to the processing chamber and eliminates the cold spot non-uniformity problem created by the asymmetric series RF source described above. As a result, the symmetric parallel RF source improves RF coupling uniformity and wafer etching uniformity in the azimuthal direction.

[0032] In another example, when a high frequency, such as 27.12 MHz or higher, is used or when the RF voltage on the parallel RF coil needs to be further reduced, the first and second spiral coils are split at their midsections and connected to a first capacitor and a second capacitor, respectively. The first and second capacitors are connected to the split first and second spiral coils on either side of the processing chamber. All capacitors are insulated and shielded by a grounded enclosure to avoid possible effects on the electromagnetic field around the processing chamber and on the plasma inside the processing chamber.

[0033] Referring now to FIG. 1A, an example of a substrate processing system 100 is shown. While a particular processing chamber is shown, the present disclosure also relates to other types of systems that use inductively coupled plasma. The substrate processing system 100 includes a processing chamber 117 having a lower chamber 102 and an upper chamber 104. In some examples, the processing chamber 117 includes an inductively coupled plasma (ICP) source. In some examples, the upper chamber 104 has a bell-jar shape, although other shapes can be used. The lower chamber 102 is defined by a chamber sidewall surface 108, a chamber bottom surface 110, and a lower surface of a gas distribution device 114. In some examples, the gas distribution device 114 is omitted. The upper chamber 104 is defined by an upper surface of the gas distribution device 114 and an inner surface of an upper chamber wall 118 (e.g., a bell-jar-shaped chamber).

[0034] The substrate processing system 100 further includes a gas distribution device 121, such as a platen or plate. The gas distribution device 121 is used to filter ions generated by the plasma and block VUV or UV radiation. The gas distribution device 121 is disposed between the substrate support 122 and the upper chamber 104. Secondary gas injectors 134 inject a secondary gas at a location between the gas distribution device 121 and the substrate support 122. In some examples, the secondary gas injectors 134 are disposed at uniform intervals around the periphery of the processing chamber.

[0035] In some examples, the gas distribution device 121 includes a plurality of spaced-apart through-holes 123 for supplying process gas to the upper chamber 104, as described further below. The through-holes 123 may be uniformly spaced around the periphery of the upper chamber 104. In some examples, the process gas is supplied by the through-holes 123 in an upward direction.

[0036] A substrate support 122 is disposed in the lower chamber 102. In some examples, the substrate support 122 includes an electrostatic chuck (ESC), although other types of substrate supports may be used. A substrate 126 is disposed on an upper surface of the substrate support 122 during etching. In some examples, the temperature of the substrate 126 may be controlled. For example, the substrate support 122 may be temperature controlled (heated and / or cooled) using one or more temperature control elements (TCEs) 139, such as resistive heaters (e.g., heater plates 141), fluid channels 145, or other types of thermal control devices. The substrate support 122 may include a single temperature control zone or multiple individually controlled temperature control zones. In some examples, a temperature controller 143 and / or a coolant controller 147 may be used to control the heating and cooling of the substrate support 122. Heating may be performed by the heater plate 141, and cooling may be performed by a cooling plate in conjunction with the fluid channels 145. For example, temperature controller 143 may be in communication with one or more temperature sensors (not shown) that sense the temperature of substrate support 122 or substrate 126, and may communicate with coolant controller 147 to control coolant flow through channels 145. Controllers 143 and / or 147 may further include a fluid source, a pump, a control valve, and a temperature sensor (all not shown).

[0037] In some examples, the gas distribution device 114 includes a showerhead (e.g., a platen or plate 128 having a plurality of spaced apart holes 129) disposed between the gas distribution device 121 and the substrate support 122. The plurality of spaced apart holes 129 extend from an upper surface of the plate 128 to a lower surface of the plate 128. The gas distribution device 114 can be used to redirect active strip or etching species above the substrate 126.

[0038] An induction coil 140 is disposed around an outer portion of the upper chamber wall 118. When energized, the induction coil 140 creates an electromagnetic field inside the upper chamber wall 118. A gas injector 142 injects one or more gas mixtures from a gas supply system 150-1 into the upper chamber 104. In some examples, the gas injector 142 injects gases in one or more directions (such as central and side gas injection directions as shown in FIG. 1).

[0039] In some examples, the gas supply system 150-1 includes one or more gas sources 152-1, 152-2, 152-N (collectively, gas sources 152), one or more valves 154-1, 154-2, 154-N (collectively, valves 154), one or more mass flow controllers (MFCs) 156-1, 156-2, 156-N (collectively, mass flow controllers 156), and a mixing manifold 158, although other types of gas supply systems may be used. A gas splitter (not shown) may be used to vary the flow rate of the gas mixture. A separate gas supply system 150-2 may be used to provide a secondary gas (e.g., an etching gas, a conditioning gas, a purge gas, or other gas mixture) to the secondary gas injector 134. As can be appreciated, the gas supply systems 150-1, 150-2 may be simplified if the substrate processing system uses a single plasma gas and a single secondary gas.

[0040] In some examples, the gas injector 142 includes a central injection location that directs gas in a downward direction and one or more side injection locations that inject gas at an angle relative to the downward direction. In some examples, the gas supply system 150-1 supplies a first portion of the gas mixture at a first flow rate to the central injection location and a second portion of the gas mixture at a second flow rate to the side injection location(s) of the gas injector 142. In other examples, a different gas mixture is supplied by the gas injector 142. In some examples, the gas supply system 150-2 supplies a tuning gas to the secondary gas injector 134 and / or to other locations in the processing chamber.

[0041] A plasma generator 170 may be used to generate RF power that is output to the inductive coil 140. A plasma 190 is generated in the upper chamber 104. In some examples, the plasma generator 170 includes an RF generator 172 and a matching network 174. The matching network 174 matches the impedance of the RF generator 172 to the impedance of the inductive coil 140. In some examples, the gas distribution device 114 is connected to a reference potential, such as ground. A valve 178 and a pump 180 may be used to control the pressure within the lower chamber 102 and the upper chamber 104 and to evacuate reactants therefrom.

[0042] A system controller 176 communicates with gas supply systems 150-1 and 150-2, valves 178, pumps 180, and / or plasma generator 170 to control the flow of process gases, purge gases, conditioning gases, RF plasma, and chamber pressure. In some examples, the plasma is maintained within the upper chamber wall 118 by an inductive coil 140. One or more gas mixtures are introduced from the upper portion of the chamber using gas injectors 142 (and / or perforations 123), and the plasma is confined within the upper chamber wall 118 using gas distribution device 114.

[0043] Confining the plasma within the upper chamber wall 118 allows for volume recombination of plasma species and release of desired etchant species through the gas distribution device 114. In some instances, no RF bias is applied to the substrate 126. As a result, there is no active sheath above the substrate 126, and ions do not strike the substrate with finite energy. Some ions will diffuse from within the plasma region through the gas distribution device 114. However, the amount of plasma that diffuses is an order of magnitude smaller than plasma located within the upper chamber wall 118. A large portion of the ions in the plasma are lost due to volume recombination at high pressures. Surface recombination losses at the upper surface of the gas distribution device 114 also reduce the ion density below the gas distribution device 114.

[0044] 1B and 1C, an asymmetric series RF coil configuration includes a first coil 140-1, a second coil 140-2, a first capacitor 194, and a second capacitor 196 disposed around the outer surface of the upper chamber 104. The first coil 140-1 is disposed around a lower portion of the outer surface of the upper chamber 104. One end of the first coil 140-1 is connected to one terminal of the first capacitor 194. The first capacitor C1 is inserted between the first and second coils to reduce the RF voltage on the coils. The first capacitor C1 is disposed adjacent to a middle portion of the processing chamber. Another terminal of the first capacitor 194 is connected to one end of the second coil 140-2. The second coil 140-2 is disposed around an upper portion of the outer surface of the upper chamber 104. The opposite end of the second coil 140-2 is connected to a second capacitor 192 located above the processing chamber. The equivalent circuit is shown in Figure 1C.

[0045] As can be seen, the plasma density at a location near the first capacitor location is reduced by the distortion coil RF current at that location, resulting in locally reduced RF coupling to the plasma in the processing chamber, which causes a cold spot due to lower plasma density.

[0046] 2A-2D, a substrate processing system 200 according to the present disclosure includes helical coils positioned 180 degrees apart, wound together in a symmetrical configuration around the outer surface of the upper chamber 104, and connected in parallel. In FIGS. 2A and 2B, a first coil 210 and a second coil 214 have a helical shape and are wound together.

[0047] A first end of the first coil 210 and a first end of the second coil 214 are connected in parallel to the output of the matching network 174 and are located near the bottom of the processing chamber 104. A second end of the first coil 210 and a second end of the second coil 214 are located near the top of the processing chamber 104 and are connected in parallel to a first capacitor C1, which is located inside the grounded enclosure and spaced from the outer surface of the upper chamber 104. Although the first coil 210 and the second coil 214 are shown with two turns, additional turns can be used. An equivalent circuit is shown in FIG. 2B.

[0048] One terminal of the first capacitor C1 is grounded, and the first capacitor C1 is disposed in an enclosure 220. The enclosure 220 is made of a conductive material, such as aluminum, that is grounded to eliminate possible electromagnetic interference (EMI) to the plasma inside the processing chamber.

[0049] In this example, one of the first and second coils is rotated 180° relative to the other of the first and second coils. The first and second coils are connected in parallel in a side-by-side configuration. Each coil has two turns with low inductance and low RF voltage.

[0050] The first capacitor (from FIGS. 1B and 1C) is removed to eliminate the corresponding cold spot. Capacitor C1 in FIG. 2A is insulated and shielded by the ground plane and therefore has no effect on plasma uniformity. Connecting straps 226 and 228 are also insulated and shielded by the ground plane and have no effect on plasma uniformity. In some examples, connecting straps 226 and 228 are made from copper. RF input and output are connected to intermediate positions between straps 226 and 228 to provide two symmetrical and identical coils.

[0051] The symmetric parallel RF source improves azimuthal plasma uniformity. In some instances, the azimuthal uniformity of the symmetric parallel RF source is improved by more than 50% over the asymmetric serial RF source. The radial uniformity is the same or slightly improved, and across-wafer uniformity is also improved.

[0052] 2C and 2D, perspective and plan views, respectively, are shown of an example of a first coil 210 and a second coil 214. The first coil 210 is rotated 180° relative to the second coil 214. The first coil 210 and the second coil 214 are identical. The first coil 210 and the second coil 214 are wound smoothly and gradually into a helical shape.

[0053] 2E and 2F , perspective and plan views, respectively, of another example of a first coil 210 and a second coil 214 are shown. The first coil 210 is rotated 180° relative to the second coil 214. The first coil 210 and the second coil 214 are identical. The first coil 210 and the second coil 214 transition between multiple different levels 280-1, 280-2, 280-3, and 280-4 (collectively, level portions 280) (as best seen in FIG. 2F ). The first coil 210 and the second coil 214 are wound with multiple level portions and vertical transitions 282 between the level portions. The first coil 210 and the second coil 214 can have equal or unequal distances from one level to an adjacent level.

[0054] 3A-3B, a substrate processing system according to the present disclosure includes a first spiral coil and a second spiral coil, which are connected in parallel and wound around the outer surface of the upper chamber 104. In FIGS. 3A and 3B, when a higher frequency, such as 27.12 MHz, is applied or when further reduction in RF voltage on the coils is required, a capacitor can be inserted at an intermediate position of each coil to reduce the RF voltage. The one or more coils include a first coil 310-1, a second coil 310-2, a third coil 314-1, and a fourth coil 314-2. A second capacitor C2 is disposed between the first coil 310-1 and the second coil 310-2. A third capacitor C3 is disposed between the third coil 314-1 and the fourth coil 314-2.

[0055] The coil pairs (first coil 310-1 and second coil 310-2, and third coil 314-1 and fourth coil 314-2) have a helical shape and are wound together. A first end of the first coil 310-1 and a first end of the third coil 314-1 are connected in parallel to a matching network 174 located near the bottom of the upper chamber 104.

[0056] The second end of the second coil 310-2 and the second end of the fourth coil 314-2 are connected in parallel to a first capacitor C1 located near the top of the processing chamber and spaced apart from the outer surface of the upper chamber 104. Although the coil pairs (first coil 310-1 and second coil 310-2, and third coil 314-1 and fourth coil 314-2) are shown with two turns, additional turns can be used. The first capacitor C1, second capacitor C2, and third capacitor C3 are disposed inside the enclosure 220. While two turns are shown and described above, a symmetrical parallel RF source can include additional turns. An enhanced design can have three or more turns for each coil and operate at frequencies ranging from 300 kHz to 30 MHz.

[0057] 4A-5B, additional spiral coils can be wound and connected in parallel. For example, in FIGS. 4A and 4B, three coils L1, L2, and L3, or coil pairs L1A and L1B, L2A and L2B, and L3A and L3B (along with intermediate capacitors C2, C3, and C4) can be used. For example, the coils are rotated by 360 / N, where N is equal to the number of coils or coil pairs (when intermediate capacitors are used as in FIGS. 3A and 3B).

[0058] For example, in Figures 5A and 5B, four coils L1, L2, L3, and L4, or coil pairs L1A and L1B, L2A and L2B, L3A and L3B, and L4A and L4B (with intervening capacitors C2, C3, C4, and C5) may be used.

[0059] 4A-5B, three or four equivalent coils or coil pairs are wound together and connected in parallel. The coils are uniformly spaced in the azimuth direction (e.g., spaced 360° / N apart). These designs improve the uniformity of RF coupling to the plasma in the azimuth direction. Each coil contains two or more turns and can be used for frequencies ranging from 300 kHz to 30 MHz. Intermediate capacitors can be added to further reduce the RF voltage on the coils.

[0060] The above description is merely exemplary in nature and in no way limits the disclosure, its application, or uses. The broad teachings of the present disclosure may be implemented in a variety of forms. Thus, while the present disclosure includes certain examples, the true scope of the disclosure should not be so limited, as other modifications will become apparent upon review of the drawings, the specification, and the following claims. It should be understood that one or more steps within a method may be performed in a different order (or in parallel) without altering the principles of the present disclosure. Furthermore, while each of the embodiments has been described above as having several features, any one or more of the features described with respect to any embodiment of the present disclosure may be implemented in and / or combined with any feature of any of the other embodiments, even if the combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and substituting one or more embodiments for one another remains within the scope of the present disclosure.

[0061] Spatial and functional relationships between elements (e.g., between modules, circuit elements, semiconductor layers, etc.) are described using a variety of terms, including "connected," "engaged," "coupled," "adjacent," "next to," "on top of," "above," "below," and "disposed." Unless explicitly described as being "direct," when a relationship between a first element and a second element is described in the above disclosure, the relationship may be a direct relationship, where no other intervening elements exist between the first element and the second element, but may also be an indirect relationship, where one or more intervening elements exist (either spatially or functionally) between the first element and the second element. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical non-exclusive OR (A OR B OR C), and not to mean "at least one of A, at least one of B, and at least one of C."

[0062] In some implementations, the controller is part of a system, such as may be part of the examples described above. Such systems can include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms, and / or specific processing components (such as wafer pedestals, gas flow systems, etc.) for processing. These systems can be integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronics, sometimes referred to as a "controller," can control various components or subportions of one or more systems. Depending on the processing requirements and / or type of system, the controller can be programmed to control any of the processes disclosed herein, including process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer into and out of tools and other transfer tools and / or load locks connected to or interfaced with a particular system.

[0063] Generally, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits may include firmware that stores program instructions, chips defined as digital signal processors (DSPs), application-specific integrated circuits (ASICs), and / or chips in the form of one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0064] The controller, in some implementations, may be part of, coupled to, or a combination of a computer integrated with, coupled to, or otherwise networked to the system. For example, the controller may be in the “cloud” or in all or part of a fab host computer system that can enable remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a fabrication operation, examine the history of past fabrication operations, and examine trends or performance metrics from multiple fabrication operations in order to change parameters of a current process, set up processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network that may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by having one or more individual controllers networked together and working toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on the chamber in communication with one or more remotely located integrated circuits (such as at the platform level or as part of a remote computer) that combine to control the process on the chamber.

[0065] Without limitation, exemplary systems may include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0066] As described above, depending on the process step or steps to be performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transfers carrying containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

Claims

1. 1. A substrate processing system, comprising: a processing chamber; an RF generator configured to generate RF power; a matching network connected to the RF generator; N spiral coils connected to the matching network and each containing M turns, where N and M are integers greater than 1; Equipped with the N spiral coils are wound symmetrically around an outer surface of the processing chamber; The N spiral coils are connected in parallel to the matching network.

2. 2. The substrate processing system of claim 1, wherein N and M are equal to two.

3. 2. The substrate processing system of claim 1, wherein N is equal to three.

4. 2. The substrate processing system of claim 1, wherein N is equal to four.

5. 2. The substrate processing system of claim 1, wherein first ends of the N spiral coils are connected to the matching network.

6. 6. The substrate processing system of claim 5, wherein the first ends of the N spiral coils are connected adjacent to a lower portion of the processing chamber.

7. 2. The substrate processing system of claim 1, further comprising a first capacitor, wherein second ends of the N spiral coils are connected to a first terminal of the first capacitor.

8. 8. The substrate processing system of claim 7, wherein the second ends of the N spiral coils are connected adjacent to an upper portion of the processing chamber.

9. 8. The substrate processing system of claim 7, further comprising a ground plane disposed between the first capacitor and the N spiral coils.

10. 8. The substrate processing system of claim 7, further comprising an enclosure surrounding the first capacitor, the enclosure being made from a grounded conductive material.

11. 2. The substrate processing system of claim 1, wherein the N spiral coils are rotationally offset by 360 / N degrees.

12. The substrate processing system of claim 11 , further comprising N capacitors connected between intermediate portions of the N spiral coils.

13. 12. The substrate processing system of claim 11, wherein N is equal to two.

14. 12. The substrate processing system of claim 11, wherein N is equal to three.

15. 12. The substrate processing system of claim 11, wherein N is equal to four.

16. 13. The substrate processing system of claim 12, further comprising an enclosure surrounding the first capacitor and the N capacitors, the enclosure being made from a grounded conductive material.

17. 10. The substrate processing system of claim 1, wherein the processing chamber has one of a dome shape and a bell jar shape.

18. 2. The substrate processing system of claim 1, wherein the N spiral coils are wound smoothly and gradually into a spiral shape.

19. 2. The substrate processing system of claim 1, wherein the N spiral coils are wound in a spiral shape with a plurality of levels and transitions between the plurality of levels.

20. 20. The substrate processing system of claim 19, wherein the plurality of levels are evenly spaced vertically.

21. 20. The substrate processing system of claim 19, wherein a first vertical spacing between a first pair of the plurality of levels is different from a second vertical spacing between a second pair of the plurality of levels.

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