Level shift circuit for controlling power switches (version)

Abstract

The device 100 for level shifting used to control a power switch comprises a switch 140, a control pulse transmission channel 150, an interference transmission channel 130 and an interference suppression circuit 170. The device is proposed in two embodiments, one comprising a current source 120 and the other comprising a controllable current source 1120. High interference immunity is achieved together with low power consumption.

Description

[Technical Field]

[0001] The proposed invention is related to power electronics and can be used in secondary power supplies, inverters, HVAC systems, and other industrial and consumer devices. The proposed design is intended for use in transferring low-voltage pulse signals to high-voltage levels in power switches to control MOSFETs, Silicon Carbide (SiC) FETs, Gallium Nitride (GaN) FETs, and Insulated Gate Bipolar Transistors (IGBTs), which can constitute power switches. [Background technology]

[0002] In many modern power electronics applications, power switches are semiconductor devices that convert electrical power into pulses by opening and closing power circuits.

[0003] The power switches are controlled by low voltage pulses, while high voltage transistors are used to switch the power circuits.

[0004] Power switches with two high-voltage transistors, one of which (the high-side transistor) can be connected to a high-voltage power supply, are widely used. The low-voltage pulse signal for controlling the transistors is shifted to a high level by a level shift circuit (LSC), which can include an RS trigger.

[0005] During operation, power switches are known to experience high intensity pulse interference, either due to switching of the high-side transistors, failure of those transistors (in which case multiple pulses may be present), or for some other reason. The input of the RS trigger may be prone to these interferences, resulting in an erroneous response by the RS trigger and catastrophic failure of both the power switch and the device using it.

[0006] The degree of immunity of an LSC to switching and other interferences is measured by the acceptable interference rise rate dV / dt (V / ns) for a particular device. For most LSCs using RS triggers, this value is normalized by a value of dV / dt = 50 V / ns. However, in modern power electronics, high-speed SiC and GaN FETs are increasingly used, for which dV / dt of up to 200 V / ns should be guaranteed. Therefore, developing an LSC that does not include RS triggers and takes into account power switches with high interference rise rates dV / dt (V / ns) presents a challenge that also opens up opportunities for creating fault-free devices for power electronics.

[0007] For easy reference to further explanation, some terms used herein are explained below.

[0008] High-side transistor, high-side transistor - a high-voltage transistor of a power switch, connected by one of its electrodes to a high-voltage source, either directly or through a capacitor.

[0009] Low-side transistor, low-side transistor - The high-voltage transistor of the power switch that is connected by one of its electrodes to the common wire of the LSC.

[0010] Upper level stray high voltage - the power supply of the device, its level relative to the common wire of the LSC depends on the presence or absence of a control pulse.

[0011] Upper level floating bias voltage - the voltage at the point of connection between the upper and lower transistors, the level of which is associated with the common wire of the LSC, depending on the presence or absence of a control pulse.

[0012] Switch closed - The switch has little resistance.

[0013] Switch is open - The switch has high resistance.

[0014] The first electrode of a transistor - for a FET it is the drain, for a bipolar transistor it is the collector.

[0015] The second control electrode of the transistor - for a FET it is the gate, for a bipolar transistor it is the base.

[0016] The third electrode of the transistor - for a FET it is the source, for a bipolar transistor it is the emitter.

[0017] Controllable Current Source - A current source with a control input, the value of the current being a function of the presence of a pulse at the control input.

[0018] Many designs of LSCs are known in the art.

[0019] For example, designs including a two-output generator of short pulses, first and second switches, first and second resistors, a two-input pulse filter, an RS trigger, an output stage, and a first terminal for receiving a low-voltage supply are used in numerous ICs (see, for example, International Rectifier's "Current Limiting Single Channel Driver," IR2125(S)&(PbF) Data Sheet No. PD60017 Rev. Q, dated September 12, 2004, or "ON Semiconductor FAN7083-GF085 High Side Gate Driver with Reset," Rev. 2, dated September 2017, and many others).

[0020] In this design (analog device), the input of the short pulse generator is electrically connected to the second terminal of the analog device, the second control terminal of the first switch is connected to the first output of the short pulse generator, and the second control terminal of the second switch is connected to the second output of the short pulse generator. the first terminals of the first and second switches are connected to the third terminal of the analog device, and the third terminals of the first and second switches are connected to the first terminals of the first and second resistors, respectively; The second terminals of the first and second resistors are connected to the fourth terminal of the analog device, the junction of the switch and the resistor is connected to the input of a pulse filter, the output of which is connected to the input of the RS trigger, the output of which is connected to an output stage, the output of which is connected to the fifth terminal of the analog device, and the power supply terminals of the output stage are connected to the fourth and sixth terminals of the analog device.

[0021] The first proposed technical design shares a common feature with the analog device: a switch. At the same time, the second, control, terminal of the switch is connected to the control input of the device.

[0022] The second proposed technical design also shares a common feature with the analog device: a switch. At the same time, the second, control, terminal of the switch is connected to the control input of the device.

[0023] The drawback of the known device is its low immunity to high-intensity internal and external interferences (dV / dt values ​​not exceeding 50V / nsec). At the same time, having an RS trigger in the structure of the analog device sets the stage for catastrophic failure of the power switch and the entire device in which it is used.

[0024] Also known is the technical design of an analog device disclosed in "A noise immunity improved level shift structure for a 600 V HVIC" by Zhang Yunwu et al., Journal of Semiconductors, Vol. 34, No. 6, June 2013.

[0025] The device (see Figure 1 in the publication) a two-output generator of short pulses, first and second switches, first and second resistors, a two-input pulse filter, an RS trigger, first and second diodes connected in parallel with the first and second resistors, respectively, an interference suppression circuit, and a first terminal for receiving a low-voltage power supply; Includes:

[0026] In this device, the input of the short pulse generator is connected to the second terminal of the analog device, the second control terminal of the first switch is connected to the first output of the short pulse generator, and the second control terminal of the second switch is connected to the second output of the short pulse generator; the first terminals of the first and second switches are connected to the third terminal of the analog device; The third terminals of the first and second switches are respectively connected to the first terminals of the first and second resistors and to the input of the interference suppression circuit, the output of the interference suppression circuit is connected to the input of the pulse filter, the second terminals of the first and second resistors are connected to the fourth terminal of the analog device, the output of the pulse filter is connected to the input of the RS trigger, and the output of the RS trigger is connected to the fifth terminal of the analog device and is the output of the device.

[0027] The shared features of the first proposed technical design with the analog device are the switch and interference suppression circuit and the connection of the second control terminal of the switch to the control input of the device.

[0028] The shared features of the second proposed technical design with the analog device are the switch and interference suppression circuit and the connection of the second control terminal of the switch to the control input of the device.

[0029] However, analog devices do not provide sufficient immunity in the presence of high-intensity internal and external interference, because, according to the above reference, dV / dt does not exceed 65V / ns.

[0030] A known circuit is disclosed in US9564882, published on February 7, 2017, relating to a high-speed voltage level shifter. The analog circuit (see FIG. 3a in the publication) includes a current source, an inverter, first and second switches, first and second resistors, first and second capacitors, a current setting device (shown in FIG. 3b), and first and second diodes.

[0031] The output of the current setter is connected to the control input of a current source, the input of the current source is connected to first terminals of first and second switches, the output of the current source is connected to the common wire of the circuit, the second control terminal of the first switch is connected directly to the control input of the circuit, and the second control terminal of the second switch is connected to the control input of the circuit via an inverter.

[0032] The third terminals of the first and second switches are connected to the first terminals of the first and second resistors, respectively.

[0033] The second terminals of the first and second terminals are connected to the powered circuit terminal, the anodes of the diodes are connected to each other and to the output of the circuit, while the cathodes of the first and second diodes are connected to the first and second terminals of the first and second resistors, respectively.

[0034] The first and second capacitors are connected in parallel with the first and second resistors, respectively.

[0035] The shared features of the first proposed technical design and the analog circuit are a current source and a switch. The input of the current source is connected to the first terminal of the switch, the output of the current source is connected to the common wire of the circuit, and the second, control, terminal of the switch is connected to the control input of the circuit.

[0036] A shared feature between the second proposed technical design and the analog circuit is a switch, the second, control, terminal of which is connected to the control input of the circuit.

[0037] The disadvantage of an analog circuit is the increased energy consumption due to the presence of two resistors, through which alternately but constantly flows a current resulting from a voltage equal to the potential difference between the fourth and third terminals of the circuit, which may be several hundred volts.

[0038] Another drawback of analog circuits is the presence of current surges caused by the recharging of the parasitic capacitances of the transistors used for the first and second switches, which can cause one of the switches to crash or generate an erroneous output signal of the circuit.

[0039] The LSC disclosed in US9264022, issued February 16, 2016, is believed to be the closest analog (prototype). The known device shown in Figure 1 of that patent, which corresponds to Figure 1 of the present application, includes a current setter, a current source, first and second surge suppression circuits, first and second inverters, first and second switches, first and second resistors, an output stage, and a first terminal receiving a low-voltage power supply. The output of the current setter is connected to a control input of the current source, the first and second inputs of the current source are connected to first terminals of the first and second switches, respectively, and the output of the current source is connected to a third terminal of the prototype device.

[0040] First and second surge suppression circuits are connected to the first terminals of the first and second switches, respectively.

[0041] The second,control,terminal of the first switch is connected to the second terminal of the prototype device through a first inverter.,The second,control,terminal of the second switch is connected to the second terminal of the prototype device through,first and second inverters connected in series.

[0042] The third terminals of the first and second switches are connected to the first terminals of the first and second resistors, respectively, and the second terminals of the first and second resistors are connected to the fourth terminal of the prototype device. The junction of the switches and resistors is connected to the input of the output stage, the output of the output stage is connected to the fifth terminal of the prototype device, and the power input of the output stage is connected to the fourth and sixth terminals of the prototype device.

[0043] The features shared between the first proposed technical design and the prototype device are a current source and a switch.

[0044] Thereby, the input of the current source is connected to the first terminal of the switch, the output of the current source is connected to the third terminal of the device, and the second, control, terminal of the switch is connected to the second terminal of the device.

[0045] A feature shared between the second proposed technical design and the prototype device is a switch, whereby a second, control, terminal of the switch is connected to a second terminal of the device.

[0046] The disadvantage of this device is the increased energy consumption due to the current flowing alternately but constantly through the first and second resistors, which current results in a voltage close to the potential difference between the fourth and third terminals of the circuit, which can reach several hundred volts. Summary of the Invention

[0047] The object of the invention is to overcome the drawbacks of known devices and to provide an LSC with high immunity to interference and low power consumption (comparable to that of an LSC using an RS trigger).

[0048] The technical result that is achievable with the proposed circuit and that is believed to be unachievable with known circuits is both the suppression of high intensity pulse interference with a high rate of rise and moderate power consumption.

[0049] It is believed that prior art designs cannot achieve the above technical results because their objectives were either to function stably in the presence of high-intensity pulse interference with a high rate of rise (which entails increased power consumption) or to reduce power consumption (which entails reduced fail-safety), without addressing the issue of achieving both objectives simultaneously.

[0050] The above-mentioned technical results are achieved in a first embodiment of the proposed LSC (also "device") for controlling a power switch by further providing an interference transmission channel, a control pulse transmission channel, and an interference suppression circuit in the first device including a current setter, a current source, a surge suppression circuit, a switch, and an output stage.

[0051] The output of the current setter is connected to the control input of the current source, the input of the current source is connected to the first terminal of the switch, the output of the current source is connected to the third terminal of the first device, the second control terminal of the switch is connected to the second terminal of the first device, and the first terminal of the switch is connected to the surge suppression circuit. The first, second, and third terminals of the first device serve to receive a low-voltage power supply, a control pulse, and connect to the common wire of the first device, respectively, and the fourth, fifth, and sixth terminals of the first device serve to connect to a source of a non-fixed upper-level referenced voltage, a control electrode of the upper transistor of the power switch, and a source of a non-fixed upper-level referenced bias voltage, respectively.

[0052] The third terminal of the switch is connected to the input of the control pulse transmission channel, and the power supply input of the switch, the power supply input of the interference transmission channel, and the power supply input of the current setter are all connected to the first terminal of the first device. The control pulse transmission channel, the interference transmission channel, and the output stage are connected in parallel to the fourth and sixth terminals of the first device. The outputs of the control pulse transmission channel and the interference transmission channel are connected to the input of the interference suppression circuit, and the output of the interference suppression circuit is connected to the input of the output stage, the output of which is connected to the fifth terminal of the first device.

[0053] In addition, the first embodiment of the device contributes to achieving the above-mentioned technical result by the fact that, in the absence of interference pulses, a control pulse to the second terminal of the first device closes the switch, ensuring current flow through the current source and the control pulse transmission channel. The value of this current I0 is set by a current setting device and can be selected to be sufficiently small so that power consumption during the control pulse is small even when using a high-voltage power supply. At the output of the control pulse transmission channel connected to the first input of the interference suppression circuit, a positive pulse is generated relative to the potential at the sixth terminal of the first device. At this time, the potential at the sixth terminal of the first device is maintained at that at the output of the interference transmission channel connected to the second input of the interference suppression circuit.

[0054] In the interference suppression circuit, the output signals of the channels are subtracted, resulting in the formation of a positive pulse that is applied to the output stage, which supplies a potential at the fourth terminal of the first device, sufficient to control the upper transistor of the power switch, to the fifth terminal of the first device, which serves to connect the control electrode of the upper transistor of the power switch.

[0055] If there is no control pulse at the second terminal of the first device, no positive pulse appears at the output of the control pulse transmission channel, and therefore no pulse for controlling the upper transistor of the power switch appears at the fifth terminal of the first device.

[0056] If high-power pulse interference appears at the sixth terminal of the first device, it travels via the interference transmission channel to the second input of the interference suppression circuit. Via the control pulse transmission channel, this high-power pulse interference travels to the first input of the interference suppression circuit. The above input signals subtract from each other in the interference suppression circuit, resulting in the suppression of high-power pulse interference regardless of the presence of a control pulse.

[0057] Therefore, by including an interference transmission channel, a control pulse transmission channel, and an interference suppression circuit in a first embodiment of the device, both the suppression of high-intensity pulse interference with a high rate of rise and modest power consumption (approximately 2-3 watts) are achieved, which is believed to be non-obvious and meets the patent requirements.

[0058] The above-mentioned technical results are achieved in a second embodiment of the proposed LSC (also "second device") for controlling a power switch by further providing a controllable current source, an interference transmission channel, a control pulse transmission channel, and an interference suppression circuit in the second device including a current setter, a surge suppression circuit, a switch, and an output stage.

[0059] The output of the current setter is connected to the control input of the controllable current source, the input of the controllable current source is connected to the first terminal of the switch, the output of the controllable current source is connected to the third terminal of the second device, the second control terminal of the switch and the pulse input of the controllable current source are connected to the second terminal of the second device, and the surge suppression circuit is connected to the first terminal of the switch.

[0060] Furthermore, the third terminal of the switch is connected to the input of the control pulse transmission channel, and the power supply inputs of the switch, the interference transmission channel and the current setter are connected to the first terminal of the second device.

[0061] The control pulse transmission channel, the interference transmission channel, and the output stage are connected in parallel to the fourth and sixth terminals of the second device, and the outputs of the control pulse transmission channel and the interference transmission channel are connected to the inputs of the interference suppression circuit, the output of which is connected to the input of the output stage.

[0062] The output of the output stage is connected to the fifth terminal of the second device, the low voltage power supply and control pulses are applied to the first and second terminals of the second device, respectively, and the third terminal of the second device is connected to the common wire of the second device.

[0063] In addition, in the second embodiment of the device, a control pulse to the second terminal of the second device closes the switch, ensuring current flow through the controllable current source and the control pulse transmission channel, in the absence of pulse interference. The value of this current I0 is set by a current setting device and can be selected to be sufficiently small so that power consumption during the control pulse is low even when using a high-voltage power supply.

[0064] A control pulse is also sent to the controllable current source to temporarily increase the current I0 in order to rapidly charge the capacitor of the transistor forming part of the switch, thereby making the response of the second device faster compared to the first.

[0065] At the output of the control pulse transmission channel connected to the first input of the interference suppression circuit, a positive pulse is generated relative to the potential at the sixth terminal of the second device, while the potential at the sixth terminal of the second device is maintained at the output of the interference transmission channel connected to the second input of the interference suppression circuit.

[0066] In the interference suppression circuit, the output signals of the channels are subtracted, resulting in the formation of a positive pulse that is applied to the output stage, which supplies a potential at the fourth terminal of the second device, sufficient to control the upper transistor of the power switch, to the fifth terminal of the second device, which serves to connect the control electrode of the upper transistor of the power switch.

[0067] If there is no control pulse at the second terminal of the second device, no positive pulse appears at the output of the control pulse transmission channel, and therefore no pulse for controlling the upper transistor of the power switch appears at the fifth terminal of the second device.

[0068] If high-intensity pulse interference appears at the sixth terminal of the second device, it travels via the interference transmission channel to the second input of the interference suppression circuit. Via the control pulse transmission channel, this high-intensity pulse interference travels to the first input of the interference suppression circuit. The above input signals subtract from each other in the interference suppression circuit, resulting in the suppression of high-intensity pulse interference regardless of the presence of the control pulse. Therefore, by including an interference transmission channel, a control pulse transmission channel, an interference suppression circuit, and a controllable current source in the second embodiment of the device, suppression of high-intensity pulse interference with a high rate of rise, moderate power consumption (approximately 2-3 watts), and a faster operating speed are achieved.

[0069] This is not obvious and the second device is believed to comply with the patent requirements.

[0070] An analysis conducted of known designs in the prior art shows that none contain the aggregate of all the limitations of the proposed device or its individual features, which meets the criteria of novelty and inventive step.

[0071] The claimed invention will be further described with reference to the accompanying drawings, which illustrate several implementations of the proposed LSC for controlling a power switch, and which are included to provide a better understanding of the claimed invention, and which are incorporated into and constitute a part of this disclosure and, together with the specification, serve to explain the mode of operation of the invention. [Brief explanation of the drawings]

[0072] [Figure 1] Figure 1 shows the prototype (prior art). [Figure 2a] FIG. 2a shows a block diagram of one possible embodiment of the device, 100a. [Figure 2b] FIG. 2b shows a block diagram of another possible embodiment of the device, 100b. [Figure 3] FIG. 3 shows one possible embodiment of switch 140. [Figure 4] FIG. 4 illustrates one possible embodiment of a surge suppression circuit 160. [Figure 5a] FIG. 5a shows one possible embodiment of an interference suppression circuit, 170a. [Figure 5b] FIG. 5b shows another possible embodiment, 170b, of an interference suppression circuit. [Figure 6] FIG. 6 shows one possible embodiment of output stage 180. [Figure 7a] FIG. 7a shows one of the possible embodiments of the current source 120 according to the first embodiment of the device. [Figure 7b] FIG. 7b shows another possible embodiment of the controllable current source 1120 according to the second embodiment of the device. [Figure 8] FIG. 8 shows one possible embodiment of a control pulse transmission channel 150. [Figure 9] FIG. 9 shows one possible embodiment of an interference transmission channel 130 similar to that shown in FIG. 8, with only minor differences. [Figure 10a]FIG. 10a shows a block diagram of one possible embodiment of the device, 100a, in more detail compared to FIG. 2a, and discloses elements shown in FIGS. [Figure 10b] FIG. 10b shows a block diagram of another possible embodiment of the apparatus, 100b, which is more detailed compared to FIG. 2b and discloses elements shown in FIGS. DETAILED DESCRIPTION OF THE INVENTION

[0073] Details of the implementation of the claimed invention are provided below with reference to the drawings.

[0074] When applied to transistors rather than contacts or switches, the term "open" and its derivatives mean "to be in a conducting state" and the term "closed" and its derivatives mean "to be in a non-conducting state."

[0075] When the specification or claims refer to one element being "connected" to another element, this means either a direct connection or an electrical connection through a third element.

[0076] Additionally, the term "comprises" and its derivatives (including, including, including, including, including, including other similar terms) are to be understood to include those elements and not to exclude any other elements unless specifically stated.

[0077] A claimed LSC, or apparatus, for controlling a power switch according to a first embodiment is shown in Figure 2a, with the LSC generally designated 100a. The LSC includes a current setter 110, a current source 120, an interference transmission channel 130, a switch 140, a control pulse transmission channel 150, a surge suppression circuit 160, an interference suppression circuit 170, and an output stage 180.

[0078] Also shown in FIG. 2a are elements of the power switch that are not part of LSC 100a: low voltage power supply 5, high voltage power supply 6, upper power switch transistor 7a, lower power switch transistor 7b, and floating low voltage power supply 8, which may specifically include a diode and boost capacitor, not shown.

[0079] Input 101 Vcc of LSC 100a is connected to low-voltage power supply input 115 of current setter 110, low-voltage power supply input 135 of interference transmission channel 130, and low-voltage power supply input 143 of switch 140. Output 117 of current setter 110 is connected to control input 126 of current source 120. Control input 102 IN of LSC 100a is connected to second, control, terminal 145 of switch 140 and second, control, terminal 165 of surge suppression circuit 160. First terminal 127 of current source 120 and first terminal 165 of surge suppression circuit 160 are connected to each other and to terminal 103 GND of LSC 100a, which serves to connect the common wire of LSC 100a. The second terminal 129 of the current source 120 and the second terminal 169 of the surge suppression circuit 160 are connected to each other and to the first terminal 147 of the switch 140, and the third terminal 149 of the switch 140 is connected to the input 151 of the control pulse transmission channel 150.

[0080] An output 159 of the control pulse transmission channel 150 is connected to a first input 171 of an interference suppression circuit 170, to a second input 175 of which the output 139 of the interference transmission channel 130 is connected. An output 179 of the interference suppression circuit 170 is connected to an input 181 of an output stage 180, whose output 189 is connected to the fifth terminal 105 of the LSC 100a, which serves to connect to the control electrode of the upper transistor 7a of the power switch.

[0081] Terminal 104 of LSC 100a, which serves to connect to the upper level floating high voltage power supply Vb, is connected to power supply inputs 133, 153, 173, and 183 of interference transmission channel 130, control pulse transmission channel 150, interference suppression circuit 170, and output stage 180, respectively.

[0082] Upper level floating bias voltage V S Terminal 106 of LSC 100a, which serves to connect the above, is connected to terminals 137, 157, 177, and 187 of interference transmission channel 130, control pulse transmission channel 150, interference suppression circuit 170, and output stage 180, respectively.

[0083] A proposed LSC according to a second embodiment is shown in Figure 2b, where the LSC is generally designated as 100b. The elements of the LSC shown in Figure 2b and their interconnections are the same as those shown in Figure 2a, except that current source 120 is replaced by a controllable current source 1120, and the pulse input 1125 of the controllable current source 1120 is connected to the control terminal 102 of LSC 100b.

[0084] Figure 3 shows one possible embodiment of the switch 140 in a device, which can be part of any device implementing the proposed LSC. Shown in Figure 3 are the switch 140, a first p-type FET 340, a second n-type FET 350, and a resistor 360.

[0085] A first terminal 365 of resistor 360 is connected to the low voltage power supply input 143 of switch 140; The gate 345 of the first FET 340 is connected to the second, control, terminal 145 of the switch 140; The gate 355 of the second FET 350 is connected to the second terminal 367 of the resistor 360 and to the source 347 of the first FET 340; The drain 343 of the first FET 340 and the source 357 of the second FET 350 are connected to the first terminal 147 of the switch 140 , and the drain 353 of the second FET 350 is connected to the third terminal 149 of the switch 140 .

[0086] FIG. 4 shows one possible embodiment of a surge suppression circuit 160 in the proposed LSC. This circuit can be part of any device implementing the proposed LSC. The circuit shown in FIG. 4, generally designated 160, includes a transistor 460 and a Zener diode 430. A gate 465 of transistor 460 is connected to a second, control, input 165 of circuit 160. An anode 432 of Zener diode 430 is connected to a drain 463 of transistor 460, a cathode 435 of Zener diode 430 is connected to a second terminal 169 of surge suppression circuit 160, and a source 467 of transistor 460 is connected to a first terminal 167 of surge suppression circuit 160.

[0087] Figure 5a shows one possible embodiment of an interference suppression circuit 170 in a device. This can be part of any device implementing the proposed LSC. Figure 5a shows a p-type FET 570a and a resistor 510a. A first input 171 of the interference suppression circuit 170a is connected to a source 571a of the FET 570a, a second input 175 of the interference suppression circuit 170a is connected to a gate 575a of the FET 570a, a terminal 179 of the interference suppression circuit 170a is connected to a drain 577a of the FET 570a and a first terminal 511a of a resistor 510a, and a second terminal 513a of the resistor 510a is connected to a terminal 177 of the interference suppression circuit 170a.

[0088] Figure 5b shows another possible embodiment of an interference suppression circuit 170b in a device. This can be part of any device implementing the proposed LSC. Figure 5b shows first, second, and third p-type FETs 570b, 520, and 530, and a resistor 510b. A first input 171 of the interference suppression circuit 170b is connected to a source 571b of the first p-type FET 570b, and a second input 175 of the interference suppression circuit 170b is connected to a gate 575b of the first p-type FET 570b.

[0089] The drain 577b of the first p-type FET 570b is connected to the drain 527 of the second p-type FET 520 and to the junction of the gates 525 and 535 of the second and third p-type FETs 520 and 530. The source 521 of the second p-type FET 520 and the source 531 of the third p-type FET 530 are connected to each other and to the power supply input 173 of the interference suppression circuit 170. As a result, the pair of p-type FETs 520 and 530 and their connections form a current mirror.

[0090] The output 179 of the interference suppression circuit 170b is connected to the drain 537 of the third p-type FET 530 and to a first terminal 511b of a resistor 510b, the second terminal 513b of which is connected to a terminal 177 of the interference suppression circuit 170b.

[0091] Figure 6 shows one possible embodiment of the output stage 180, which can be part of any device implementing the proposed LSC.

[0092] In FIG. 6, output stage 180 and Schmitt trigger 650 are shown.

[0093] A first input 181 of output stage 180 is connected to an input 651 of Schmitt trigger 650. An output 655 of Schmitt trigger 650 is connected to terminal 189 of output stage 180. A power supply input 652 of Schmitt trigger 650 is connected to a power supply input 183 of output stage 180, and a terminal 654 of Schmitt trigger 650 for connection to the common wire of the LSC is connected to terminal 187 of output stage 180.

[0094] 7a shows one possible embodiment of a current source according to the first embodiment of the proposed LSC, which can be part of any device implementing the first embodiment of the LSC. In FIG. 7a, the entire current source 120, a first transistor 730, and a second transistor 740 are shown.

[0095] A drain 733 of the first transistor 730 and the junction of a gate 735 of the first transistor 730 and a gate 745 of the second transistor 740 are connected to a control input 126 of the current source 120. A drain 743 of the second transistor 740 is connected to a second terminal 129 of the current source 120. A source 737 of the first transistor 730 and a source 747 of the second transistor 740 are connected to each other and to a first terminal 127 of the current source 120.

[0096] Figure 7b shows one possible embodiment of a current source according to the second embodiment of the proposed LSC, which can be part of any device implementing the second embodiment of the LSC. Figure 7b shows the entire controllable current source 1120, the first transistor 730, the second transistor 740, the third transistor 720, the driving multivibrator 710, and the first, second, and third resistors 750, 770, and 760 with terminals 751 and 753, 771 and 773, and 761 and 763.

[0097] The drain 733 of the first transistor 730 and the junction of the gate 735 of the first transistor 730 and the gate 745 of the second transistor 740 are connected to the control input 126 of the controllable current source 1120 .

[0098] The drain 743 of the second transistor 740 is connected to the second terminal 129 of the controllable current source 1120 .

[0099] The source 737 of the first transistor 730 is connected to a first terminal 127 of the controllable current source 1120 via a first resistor 750, and the source 747 of the second transistor 740 is connected to the same terminal 127 via a second resistor 770.

[0100] A terminal 763 of the third resistor 760 is connected to the common point of the second resistor 770 and the source 747 of the second transistor 740 .

[0101] A terminal 761 of the third resistor 760 is connected to the drain 723 of the third transistor 720. In turn, a gate 725 of the third transistor 720 is connected to the output 719 of the drive multivibrator 710, a source 727 of the third transistor 720 is connected to the first terminal 127 of the controllable current source 1120, and an input 711 of the drive multivibrator 710 is connected to the pulse input 1125 of the controllable current source 1120.

[0102] Figure 8 shows one possible embodiment of the control pulse transmission channel 150 in the proposed LSC, which can be part of any device implementing an LSC. Shown in Figure 8 is the entire control pulse transmission channel 150, a first FET 870, a second FET 880, a third FET 890, a low-voltage power supply 8030, its positive terminal 8031, its negative terminal 8033, and first, second, third, and fourth resistors 801, 802, 803, and 804.

[0103] The gate 875 of the first FET 870 is connected to the positive terminal 8031 ​​of the low-voltage power supply 8030, and the source 877 of the first FET 870 is connected to the second terminal 812 of the first resistor 801, the first terminal 811 of which is connected to the input 151 of the control pulse transmission channel 150.

[0104] The drain 873 of the first FET 870 is connected to the drain 833 of the second FET 880 and to the junction of the gate 885 of the second FET 880 and the gate 895 of the third FET 890. The source 887 of the second FET 880 is connected to the first terminal 831 of the third resistor 803, the second terminal 832 of which is connected to the power supply input 153 of the control pulse transmission channel 150.

[0105] The drain 893 of the third FET 890 is connected to the second terminal 822 of the second resistor 802 and to the output 159 of the control pulse transmission channel 150, and the source 897 of the third FET 890 is connected to the first terminal 841 of the fourth resistor 804, the second terminal 842 of which is connected to the power supply input 153 of the control pulse transmission channel 150. The first terminal 821 of the second resistor 802 is connected to the negative terminal 8033 of the low-voltage power supply 8030 and to the terminal 157 of the control pulse transmission channel 150.

[0106] Figure 9 shows one possible embodiment of the interference transmission channel 130 in the claimed LSC. It can be part of any device that implements an LSC. Figure 9 shows the entire interference transmission channel 130, a first FET 970, a second FET 980, a third FET 990, and a fourth FET 9010. The low-voltage power supply is shown as 9030, with its positive terminal at 9031 and its negative terminal at 9033, and resistors numbered first 901, second 902, third 903, and fourth 904.

[0107] The gate 9015 and source 9017 of the fourth FET 9010 are connected to each other and to the low voltage power supply input 135 , and the drain 9013 of the fourth FET 9010 is connected to the first terminal 911 of the first resistor 901 .

[0108] A second terminal 932 of the third resistor 903 and a second terminal 942 of the fourth resistor 904 are connected to each other and to the power supply input 133 of the interfering transmission channel 130. A drain 993 of the third FET 990 is connected to the output 139 of the interfering transmission channel 130. A first terminal 921 of the second resistor 902 is connected to the terminal 137 of the interfering transmission channel 130.

[0109] Other connections between elements of the interference transmission channel 130 are similar to those of the control pulse transmission channel 150 .

[0110] FIG. 10a shows the elements included in the functional units shown in FIG. 2a and their connections for one of the possible implementations of the first embodiment of the proposed device (LSC).

[0111] The claimed LSC is shown at 100a and includes a current setter 110, a current source 120, an interference transmission channel 130, a switch 140, a control pulse transmission channel 150, a surge suppression circuit 160, an interference suppression circuit 170, and an output stage 180.

[0112] Also shown in FIG. 10a are elements of the power switch that are not part of LSC 100a: low voltage power supply 5, high voltage power supply 6, upper power switch transistor 7a, lower power switch transistor 7b, and floating low voltage power supply 8, which may specifically include a diode and boost capacitor, not shown.

[0113] Input 101 Vcc of LSC 100a is connected to low voltage power supply input 115 of current setter 110, low voltage power supply input 135 of interference transmission channel 130, and low voltage power supply input 143 of switch 140. Output 117 of current setter 110, which includes resistor 112, is connected to control input 126 of current source 120.

[0114] Current source 120 comprises a current mirror and includes two transistors 730 and 740, the gates of which are connected to each other and to the drain of transistor 730 and the control input 126 of current source 120. The sources of transistors 730 and 740 are connected to each other and to a first terminal 127 of current source 120.

[0115] The drain of transistor 740 is connected to second terminal 129 of current source 120, which in turn is connected to second terminal 169 of surge suppression circuit 160 and first terminal 147 of switch 140. Surge suppression circuit 160 includes transistor 460 and Zener diode 430, with the gate of transistor 460 connected to second, control, terminal 165 of surge suppression circuit 160, which in turn is connected to control input 102 of device 100a and second, control, terminal 145 of switch 140. The drain of transistor 460 is connected to the anode of Zener diode 430, which in turn is connected to second terminal 169 of surge suppression circuit 160. The source of transistor 460 is connected to a first terminal 167 of surge suppression circuit 160, which is connected to terminal 103 of device 100a, which serves to connect to the common wire of the LSC, and to a first terminal 127 of current source 120.

[0116] Switch 140 includes a p-type FET 340 and an n-type FET 350. The gate of p-type FET 340 is connected to a second, control, terminal 145 of switch 140, the source of this transistor is connected to a first terminal 147 of switch 140 and the source of n-type FET 350, and the drain of n-type FET 350 is connected to a third terminal 149 of switch 140. The drain of p-type FET 340 is connected to the gate of n-type FET 350 and to a low-voltage power supply input 143 of switch 140 through resistor 360. The control terminal 145 of switch 140 is connected to a control input 102IN of device 100a, and the third terminal 149 of the switch is connected to an input 151 of a control pulse transmission channel 150.

[0117] The control pulse transmission channel 150 includes a first FET 870, two transistors, a second FET 880 and a third FET 890, which together form a current mirror, a low-voltage power supply 8030, a first resistor 801, a second resistor 802, a third resistor 803, and a fourth resistor 804. Connected to the input 151 of the control pulse transmission channel 150 is the first resistor 801, in series with the first FET 870, the second FET 880, and the third resistor 803, which is connected to the power supply input 153 of the control pulse transmission channel 150. Connected to the terminal 157 of the control pulse transmission channel 150 is the second resistor 802, in series with the third FET 890 and the fourth resistor 803, which is connected to the power supply input 153 of the control pulse transmission channel 150.

[0118] Furthermore, the negative terminal of the low-voltage power supply source 8030 is connected to the terminal 157 of the control pulse transmission channel 150 , and the positive terminal of the low-voltage power supply source 8030 is connected to the gate of the first FET 870 .

[0119] The gates of the second FET 880 and the third FET 890 are connected to each other and to the drain of the first FET 870 and the source of the second FET 880. The junction of the drain of the third FET 890 and the second resistor 802 is connected to the output 159 of the control pulse transmission channel 150.

[0120] The interference transmission channel 130 includes a first FET 970, two transistors, a second FET 980 and a third FET 990, which together form a current mirror, a fourth FET 9010, a low-voltage power supply 9030, a first resistor 901, a second resistor 902, a third resistor 903, and a fourth resistor 904.

[0121] A fourth FET 9010 is connected to the low-voltage power supply input 135 of the interferer transmit channel 130, in series with a first resistor 901, a first FET 970, a second FET 980, and a third resistor 903 connected to the power supply input 133 of the interferer transmit channel 130. A second resistor 902 is connected to a terminal 137 of the interferer transmit channel 130, in series with a third FET 990 and a fourth resistor 904 connected to the power supply input 133 of the interferer transmit channel 130. A negative terminal of a low-voltage power supply 9030 is connected to terminal 137 of the interferer transmit channel 130, and a positive terminal of the low-voltage power supply 9030 is connected to the gate of the first FET 970. The gates of the second FET 980 and the third FET 990 are connected to each other and to the drain of the first FET 970 and the source of the second FET 980. The junction of the drain of the third FET 990 and the second resistor 902 is connected to the output 139 of the interfering transmission channel 130, and the gate and source of the fourth FET 9010 are connected together.

[0122] The interference suppression circuit 170 includes a p-channel FET 570a and a resistor 510a. The source of the p-channel FET 570a is connected to a first input 171 of the interference suppression circuit 170, and the gate of the p-channel FET 570a is connected to a second input 175 of the interference suppression circuit 170. The drain of the p-channel FET 570a is connected to an output 179 of the interference suppression circuit 170, and the resistor 510a is connected between this output 179 and a terminal 177 of the interference suppression circuit 170.

[0123] Output stage 180 includes a Schmitt trigger 650, the input of which is connected to input 181 of output stage 180, the output of which is connected to output 189 of output stage 180, and the power supply inputs of Schmitt trigger 650 are connected to power supply input 183 and terminal 187 of output stage 180, respectively.

[0124] The output 159 of the control pulse transmission channel 150 is connected to a first input 171 of an interference suppression circuit 170, the second input 175 of which is connected to the output 139 of the interference transmission channel 130. The output 179 of the interference suppression circuit 170 is connected to an input 181 of an output stage 180, the output 189 of which is connected to a terminal 105 of the device 100a, which serves to connect the control electrode of the upper transistor 7a of the power switch.

[0125] Terminal 104 of device 100a, which serves to connect to a floating upper-level power supply voltage Vb, is connected to power supply inputs 133, 153, 173, and 183 of interference transmission channel 130, control pulse transmission channel 150, interference suppression circuit 170, and output stage 180, respectively.

[0126] In this implementation, the power supply input 173 of the interference suppression circuit 170 is not used.

[0127] Terminal 106 of device 100a, which serves to connect to a floating upper level bias voltage Vs, is connected to power inputs 137, 157, 177, and 187 of interference transmission channel 130, control pulse transmission channel 150, interference suppression circuit 170, and output stage 180, respectively.

[0128] FIG. 10b shows the elements constituting the functional units shown in FIG. 2b and their connections for one of the possible realizations of the second embodiment of the proposed device (LSC).

[0129] The claimed LSC is shown at 100b. LSC 100b includes a current setter 110, a controllable current source 1120, an interference transmission channel 130, a switch 140, a control pulse transmission channel 150, a surge suppression circuit 160, an interference suppression circuit 170a, and an output stage 180.

[0130] Also shown in Figure 10b are elements of the power switch that are not part of LSC 100b: low voltage power source 5, high voltage power supply 6, upper power switch transistor 7a, lower power switch transistor 7b, and floating low voltage power supply 8, which may specifically include a diode and boost capacitor, not shown.

[0131] The input 101 Vcc of the device 100a is connected to the low voltage power supply input 115 of the current setter 110, the low voltage power supply input 135 of the interference transmission channel 130, and the low voltage power supply input 143 of the switch 140. The output 117 of the current setter 110, which includes the resistor 112, is connected to the control input 126 of the controllable current source 1120.

[0132] The controllable current source 1120 of FIG. 10b includes a first transistor 730, a second transistor 740, a third transistor 720, a drive multivibrator 710, and first, second, and third resistors 750, 770, and 760.

[0133] The gates of the first and second transistors 730 and 740 are connected to each other and to the drain of the first transistor 730 and the control input 126 of the controllable current source 1120 .

[0134] The drain of the second transistor 740 is connected to the second terminal 129 of the controllable current source 1120 .

[0135] The source of the first transistor 730 is connected to the first terminal 127 of the controllable current source 1120 via a first resistor 750, and the source of the second transistor 740 is connected to the same first terminal 127 of the controllable current source 1120 via a second resistor 770.

[0136] One terminal of the third resistor 760 of the controllable current source 1120 is connected to the common point between the source of the second transistor 740 and the second resistor 770, and the other terminal of the third resistor 760 is connected to the drain of the third transistor 720. In addition, the gate of the third transistor 720 is connected to the output of the drive multivibrator 710, the source of the third transistor 720 is connected to the first terminal 127 of the controllable current source 1120, and the input of the drive multivibrator 710 is connected to the pulse input 1125 of the controllable current source 1120, which is connected to the control input 102IN of the LSC 100b.

[0137] Switch 140 includes a p-type FET 340 and an n-type FET 350. The gate of p-type FET 340 is connected to a second, control, terminal 145 of switch 140, the source of this transistor is connected to a first terminal 147 of switch 140 and the source of n-type FET 350, and the drain of n-type FET 350 is connected to a third terminal 149 of switch 140. The drain of p-type FET 340 is connected to the gate of n-type FET 350 and to a low-voltage power supply input 143 of switch 140 through resistor 360. The control terminal 145 of switch 140 is connected to a control input 102IN of device 100a, and the third terminal 149 of the switch is connected to an input 151 of a control pulse transmission channel 150.

[0138] The control pulse transmission channel 150 includes a first FET 870, two transistors, a second FET 880 and a third FET 890, which together form a current mirror, a low-voltage power supply 8030, a first resistor 801, a second resistor 802, a third resistor 803, and a fourth resistor 804. Connected to the input 151 of the control pulse transmission channel 150 is the first resistor 801, in series with the first FET 870, the second FET 880, and the third resistor 803, which is connected to the power supply input 153 of the control pulse transmission channel 150. Connected to the terminal 157 of the control pulse transmission channel 150 is the second resistor 802, in series with the third FET 890 and the fourth resistor 803, which is connected to the power supply input 153 of the control pulse transmission channel 150.

[0139] Furthermore, the negative terminal of the low-voltage power supply source 8030 is connected to the terminal 157 of the control pulse transmission channel 150 , and the positive terminal of the low-voltage power supply source 8030 is connected to the gate of the first FET 870 .

[0140] The gates of the second FET 880 and the third FET 890 are connected to each other and to the drain of the first FET 870 and the source of the second FET 880. The junction of the drain of the third FET 890 and the second resistor 802 is connected to the output 159 of the control pulse transmission channel 150.

[0141] The interference transmission channel 130 includes a first FET 970, two transistors, a second FET 980 and a third FET 990, which together form a current mirror, a fourth FET 9010, a low-voltage power supply 9030, a first resistor 901, a second resistor 902, a third resistor 903, and a fourth resistor 904.

[0142] A fourth FET 9010 is connected to the low voltage power supply input 135 of the interference transmission channel 130, and in series with it are a first resistor 901, a first FET 970, a second FET 980, and a third resistor 903 connected to the power supply input 133 of the interference transmission channel 130.

[0143] Connected to terminal 137 of interferor transmit channel 130 is a second resistor 902 in series with a third FET 990 and a fourth resistor 904 connected to power supply input 133 of interferor transmit channel 130. Also connected to terminal 137 of interferor transmit channel 130 is the negative terminal of a low-voltage power supply 9030, the positive terminal of which is connected to the gate of first FET 970. The gates of second FET 980 and third FET 990 are connected to each other and to the drain of first FET 970 and the source of second FET 980. The junction of the drain of third FET 990 and second resistor 902 is connected to output 139 of interferor transmit channel 130, and the gate and source of fourth FET 9010 are connected to each other.

[0144] The interference suppression circuit 170 includes a p-channel FET 570a and a resistor 510a. The source of the p-channel FET 570a is connected to a first input 171 of the interference suppression circuit 170, and the gate of the p-channel FET 570a is connected to a second input 175 of the interference suppression circuit 170. The drain of the p-channel FET 570a is connected to an output 179 of the interference suppression circuit 170, and the resistor 510a is connected between this output 179 and a terminal 177 of the interference suppression circuit 170.

[0145] Output stage 180 includes a Schmitt trigger 650, the input of which is connected to input 181 of output stage 180, the output of which is connected to output 189 of output stage 180, and the power supply inputs of Schmitt trigger 650 are connected to power supply input 183 and terminal 187 of output stage 180, respectively.

[0146] The output 159 of the control pulse transmission channel 150 is connected to a first input 171 of an interference suppression circuit 170, the second input 175 of which is connected to the output 139 of the interference transmission channel 130. The output 179 of the interference suppression circuit 170 is connected to an input 181 of an output stage 180, the output 189 of which is connected to a terminal 105 of an LSC 100b serving to connect the control electrode of the upper transistor 7a of the power switch.

[0147] Terminal 104 of device 100b, which serves to connect to the floating upper level power supply voltage Vb, is connected to power supply inputs 133, 153, 173 and 183 of interference transmission channel 130, control pulse transmission channel 150, interference suppression circuit 170 and output stage 180, respectively.

[0148] In this implementation, the power supply input 173 of the interference suppression circuit 170 is not used.

[0149] Terminal 106 of device 100b, which serves to connect to a floating upper level bias voltage Vs, is connected to power inputs 137, 157, 177, and 187 of interference transmission channel 130, control pulse transmission channel 150, interference suppression circuit 170, and output stage 180, respectively.

[0150] Operation of the invention The LSC 100a in one of the possible implementations according to the first embodiment of the proposed device operates as follows (see FIG. 2a).

[0151] When the control pulse IN reaches the control input 102 and then the second, control, terminal 145 of the switch 140, the switch 140 closes and a current I0 starts to flow along the circuit: terminal 104 of the LSC 100a connecting the floating upper level power supply voltage - power supply input 153 of the control pulse transmission channel 150 - control pulse transmission channel 150 - switch 140 - current source 120 - first terminal 127 of the current source 120 - terminal 103 of the LSC 100a connecting the common wire of the LSC 100a.

[0152] This circuit is completed by connecting the common wire of LSC 100a to the source of transistor 7b, which is not part of LSC 100a, and to the negative terminal of high voltage power supply 6.

[0153] The value of current I0 is determined by current source 120, which is controlled from output 117 of current setter 110 via control input 126. Low voltage power supply input 115 of current setter 110 is then connected to input 101 of LSC 100a, where low voltage supply Vcc is applied from low voltage power supply 5, which is not part of LSC 100a.

[0154] The value of the low voltage supply Vcc can be in the range of 4.5-5.5V relative to the potential of the common wire of the LSC 100a.

[0155] The value of the power supply voltage Vb of the upper transistor of the power switch (floating power supply 8) is the potential V at terminal 106 of LSC 100a. S Relative to the high voltage power supply V, which can be in the range of 12-18V hh The value of (High Voltage Power Supply 6) can be within 500-600V, and can also be in other ranges depending on the operating environment of the power switch.

[0156] The aforementioned I0 flowing along the circuit "terminal 104-terminal 103 of LSC 100a" is maintained stable by current source 120 during the control pulse IN, and its value is set to a very low level (such as a few milliamps) by current setter 110 to keep power consumption low.

[0157] Most commonly, the current setter is a series connection of a constant voltage source and a constant resistor, as disclosed, for example, in the above-mentioned US Pat. No. 9,564,822 B2, although more complex circuits are possible.

[0158] In the absence of interference, during a control pulse IN, the voltage V at terminal 106 of LSC 100a is S A pulse of positive polarity relative to the potential V at the terminal 106 of the LSC 100a is generated and applied to the first input 171 of the interference suppression circuit 170. Under the conditions considered, the potential V S The output voltage from the output 139 of the interference transmission channel 130, which is equal to V, is applied to a second input 175 of the interference suppression circuit 170 by connecting terminal 106 to terminal 137 of the interference transmission channel 130. The positive polarity pulse formed at the output 179 of the interference suppression circuit 170 is input to an input 181 of the output stage 180. This means that the output stage 180 outputs from its output 189 to terminal 105 of the LSC 100a a pulse V for controlling the upper transistor of the power switch. h A positive polarity pulse is sent as follows.

[0159] After the control pulse IN is terminated, the switch 140 opens, the current flow in the circuit "terminal 104-terminal 103 of LSC 100a" stops, and a pulse at the output 159 of the control pulse transmission channel 150 and at the output 179 of the interference suppression circuit 170 and a pulse V at the output 105 of LSC 100a are generated. h And that ends it.

[0160] When a large pulse of interference occurs at terminal 106 of LSC 100a, typically caused by the switching of a power switch transistor and characterized by a high rate of rise dV / dt, the pulse arrives simultaneously at terminals 137 and 157 of interference transmission channel 130 and control pulse transmission channel 150, respectively.

[0161] Since channels 130 and 150 are highly identical (and taking into account switch 140), interference pulses arrive simultaneously and with equal amplitude at their outputs 139 and 159 and at inputs 171 and 175 of interference suppression circuit 170. Therefore, mutual compensation of these pulses is performed in interference suppression circuit 170, and large pulse interference is practically absent at output 179 of interference suppression circuit 170, output 189 of output stage 180, and output 105 of LSC 100a, and this mutual compensation of large pulse interference occurs with or without control pulse IN.

[0162] In this way, in normal operating mode, interference suppression of large pulses with high rise rates and moderate power consumption are simultaneously ensured, achieving the stated technical results.

[0163] The LSC 100b in one of the possible implementations according to the second embodiment of the proposed device operates as follows (see FIG. 2b).

[0164] When the control pulse IN reaches the control input 102 of LSC 100b and then the second, control, terminal 145 of switch 140, switch 140 closes and current I0 starts to flow along the following circuit: terminal 104 of LSC 100b connecting the floating upper level power supply voltage - power supply input 153 of control pulse transmission channel 150 - control pulse transmission channel 150 - switch 140 - controllable current source 1120 - first terminal 127 of controllable current source 1120 - terminal 103 of LSC 100b connecting the common wire of LSC 100b.

[0165] This circuit is completed by connecting the common wire of LSC 100b to the source of transistor 7b, which is not part of LSC 100b, and to the negative terminal of high voltage power supply 6.

[0166] The value of this current I0 is determined by a current source 120 that is controlled from the output 117 of the current setter 110 via a control input 126. The low voltage power supply input 115 of the current setter 110 is then connected to the input 101 of the LSC 100b, where the low voltage supply Vcc is applied from a low voltage power supply 5 that is not part of the LSC 100b.

[0167] The value of the low voltage supply Vcc can be in the range of 4.5-5.5V relative to the potential of the common wire of the LSC.

[0168] The value of the power supply voltage Vb of the upper transistor of the power switch (floating power supply 8) is the potential V at terminal 106 of LSC 100b. S Relative to the high voltage power supply V, which can be in the range of 12-18V hh The value of (High Voltage Power Supply 6) can be within 500-600V, and can also be in other ranges depending on the operating environment of the power switch.

[0169] The aforementioned I0 flowing along the circuit "terminal 104-terminal 103 of LSC100b" is maintained stable during the control pulse IN by a controllable current source 1120, and its value is set to a very low level (such as a few milliamps) by a current setter 110 to keep power consumption low.

[0170] Most commonly, the current setter is a series connection of a constant voltage source and a constant resistor, as disclosed, for example, in the above-mentioned US Pat. No. 9,564,822 B2, although more complex circuits are possible.

[0171] However, a control pulse I1 is also applied from the control input 102 of LSC 100b to the pulse input 1125 of the controllable current source 1120. For a short period of time, this causes a sudden rise in current along the circuit (terminal 104-terminal 103 of LSC 100b) to a value I1=5-15I0 at the start of the control pulse I1. The duration of the current rise is less than 1 percent of the duration of the control pulse I1. The current I1 charges the capacitance of switch 140, which contributes to the faster performance of LSC 100b according to the second embodiment of the proposed device. Because the duration of I1 is short, little, if any, power is consumed by the device.

[0172] In the absence of interference, during a control pulse IN, the voltage V at terminal 106 of LSC 100b is S A pulse of positive polarity relative to the potential V at the terminal 106 of the LSC 100b is generated and applied to the first input 171 of the interference suppression circuit 170. Under the conditions considered, the potential V S The output voltage from the output 139 of the interference transmission channel 130, which is equal to V, is applied to a second input 175 of the interference suppression circuit 170 by connecting terminal 106 to terminal 137 of the interference transmission channel 130. The positive polarity pulse produced at the output 179 of the interference suppression circuit 170 is input to an input 181 of the output stage 180. This means that the output stage 180 transmits from its output 189 to terminal 105 of the LSC 100b a pulse V for controlling the upper transistor of the power switch. h A positive polarity pulse is sent as follows.

[0173] After the control pulse IN is terminated, the switch 140 opens, the current flow in the circuit "terminal 104-terminal 103 of LSC 100a" stops, and a pulse at the output 159 of the control pulse transmission channel 150 and at the output 179 of the interference suppression circuit 170 and a pulse V at the output 105 of LSC 100b are generated. h And that ends it.

[0174] When a large pulse of interference occurs at terminal 106 of LSC 100b, typically caused by the switching of a power switch transistor and characterized by a high rate of rise dV / dt, the pulse arrives simultaneously at terminals 137 and 157 of interference transmission channel 130 and control pulse transmission channel 150, respectively.

[0175] Since channels 130 and 150 are highly identical (and taking into account switch 140), interference pulses arrive simultaneously and with equal amplitude at their outputs 139 and 159 and at inputs 171 and 175 of interference suppression circuit 170. Therefore, mutual compensation of these pulses is performed in interference suppression circuit 170, and large pulse interference is practically absent at output 179 of interference suppression circuit 170, output 189 of output stage 180, and output 105 of LSC 100b, and this mutual compensation of large pulse interference occurs with or without control pulse IN.

[0176] In this way, in normal operating mode, interference suppression of large pulses with high rise rates and moderate power consumption are simultaneously ensured, achieving the stated technical result. Furthermore, the short rise in current through the controllable current source 1120, the switch 140 and the control pulse transmission channel 150 at the start of the control pulse IN ensures an improved response time of the LSC.

[0177] The claimed components of an LSC can be implemented in a variety of ways.

[0178] In particular, Figure 3 shows one possible implementation of switch 140, which can be used in both embodiments of the proposed design, and which operates as follows (see also Figures 2a and 2b).

[0179] When a control pulse IN arrives at second, control, terminal 145, transistor 340 closes, causing a very high resistance between its first electrode 343 and third electrode 347. At the same time, transistor 350 is opened by the potential Vcc at low-voltage power supply input 143, which reaches second, control, electrode 355 of transistor 340 through resistor 360. Thus, current flows through switch 140 along the path: third terminal 149 of switch 140 - first terminal 353 of transistor 350 - third terminal 357 of transistor 350 - first terminal 147 of switch 140, which means that switch 140 is closed.

[0180] After control pulse IN ends, transistor 340 opens, the resistance between its first electrode 343 and third electrode 347 becomes low, and the potential difference between its second, control electrode 355 and third electrode 357 of transistor 350 becomes close to zero. This closes transistor 350, opening the circuit for current flow between terminal 149 and terminal 147 and opening switch 140.

[0181] Having transistor 340 in switch 140 speeds up the closing of the switch because the low resistance of open transistor 340 shorts out the high capacitance of transistor 350, thus increasing the overall speed of the claimed LSC.

[0182] 4 shows a possible implementation of surge suppression circuit 160 in the claimed LSC, which can be used with both of the proposed designs. In many prior art devices (analog, etc. (see US9564822b2)), at the leading edge of control pulse IN, the cross capacitance of transistor 350 of switch 140 causes a voltage surge to appear at drain 353 of transistor 350, which is transferred to third electrode 357 of transistor 350. This surge can cause an input barrier breakdown in transistor 350, potentially causing the entire claimed LSC to fail.

[0183] The prototype (US9246022) uses a surge suppression circuit connected in parallel with a current source. The surge suppression circuit 160 of the claimed LSC is also connected in parallel with the current source 120 (see FIG. 2a) or in parallel with the controllable current source 1120 (see FIG. 2b), but unlike the prototype, it includes a Zener diode 430 and a transistor 460 connected in series.

[0184] A surge suppression circuit 160 implemented according to FIG. 4 operates as follows (see also FIGS. 2a, 2b).

[0185] A control pulse IN is applied from the control input 102 of the asserted LSC to the second control input 165, which is connected to the gate 465 of transistor 460, causing the transistor to open. Because the cathode 435 of Zener diode 430 is connected to the third electrode 357 of transistor 350 of switch 140 through the second terminal 169 of surge suppression circuit 160 and the first terminal 147 of switch 140 (see FIG. 3), the potential at the third electrode 357 of transistor 350 now equals the voltage at the cathode 435 of Zener diode 430, which is the voltage across the open transistor 460 and the stabilizing voltage of Zener diode 430, which is only a few volts.

[0186] The voltage at the second (control) electrode 355 of transistor 350 is equal to the potential Vcc of the low-voltage power supply 5 at the low-voltage power supply input 143 of switch 140, and the potential difference between the second (control) electrode 355 of transistor 350 and the cathode 435 of Zener diode 430 is fairly small, so input barrier breakdown in transistor 350 is not possible in that circumstance.

[0187] When the control pulse IN ends, the transistor 460 opens, thus disconnecting the Zener diode 430 from the first terminal 167 of the surge suppression circuit 160 and preventing failure of the Zener diode 430 due to the potential Vcc of the low-voltage power supply 5 being applied from the low-voltage power supply input 143 of the switch 140 through the shorted transistor 340 to the cathode 435 of the Zener diode 430.

[0188] FIG. 8 shows a possible implementation of a control pulse transmission channel 150, which can be used in both implementations of the proposed design and operates as follows.

[0189] When a control pulse IN appears at the control input 102 of the claimed LSC (see Figures 2a, 2b) and is sent to the second (control) terminal 145 of the switch 140, it closes, completing a circuit that allows current to flow from the power supply input 153 of the control pulse transmission channel 150 to the first terminal 127 of the current source 120 (see Figure 2a) or to the first terminal 127 of the controllable current source 1120 (see Figure 2b).

[0190] Current flows through the control pulse transmission channel 150 along the following circuit (see FIG. 8): power supply input 153 of the control pulse transmission channel 150 - third resistor 803 - second transistor 880 - first transistor 870 - first resistor 801 - input 151.

[0191] When the control pulse IN is present, the voltage of the DC voltage source 8030 causes the first transistor 870 to be in a conducting state, acting as a buffer stage and contributing to a sufficiently fast response of the circuit being described.

[0192] The transistor pair of the second transistor 880 and the third transistor 890 forms a current mirror, so that when a current flows through the second transistor 880, a current also flows through the third transistor 890, and the value of this current is determined by the nominal ratio of the third resistor 803 to the fourth resistor 804. This current causes a voltage drop across the resistor 802, which is sent to the terminal 159 as an output pulse of the control pulse transmission channel 150, and the amplitude of this pulse is determined by the potential V S exceeds by a predetermined value.

[0193] If a high-intensity pulse interference appears at terminal 157 of control pulse transmission channel 150 while control pulse IN is present, a surge current appears along the circuit: power supply input 153 of control pulse transmission channel 150 - third resistor 803 - second transistor 880 - first transistor 870 - first resistor 801 - input 151. At the same time, due to the current mirror effect, the pulse interference current also flows through fourth resistor 804 and third transistor 890, causing an additional voltage drop across second resistor 802. This voltage drop is added to the voltage of the output pulse of control pulse transmission channel 150 and is sent to output 159 as an output signal containing the sum of the control pulse and the high-intensity pulse interference.

[0194] When there is no control pulse IN at the control input 102 of the claimed LSC and switch 140 is open (see Figures 2a and 2b), there is no current along the circuit between power supply input 153 and input 151 of control pulse transmission channel 150 (see Figure 8). Similarly, there is no current along the circuit between power supply input 153 and terminal 157 of control pulse transmission channel 150. Therefore, there is no output pulse of control pulse transmission channel 150.

[0195] However, if, during the absence of a control pulse, a high-intensity pulse interference appears at terminal 157 of control pulse transmission channel 150, a surge current will again appear along the power supply input 153 of control pulse transmission channel 150 - third resistor 803 - second transistor 880 - first transistor 870 - first resistor 801 - input 151. Due to the current mirror effect, the pulse interference current will also flow through fourth resistor 804 and third transistor 890, causing an additional voltage drop across second resistor 802. This voltage drop will be sent to output 159 as an output signal containing the pulse interference.

[0196] Therefore, during a control pulse IN, an output control pulse is always present at output 159 of control pulse transmission channel 150, and an interference pulse is added to it if a high-power pulse interference appears. If there is no control pulse IN, there is no output control pulse at output 159 of control pulse transmission channel 150, and if a high-power pulse interference appears, an interference pulse appears at output 159.

[0197] Figure 9 shows a possible implementation of the interference transmission channel 130, which can be used in both embodiments of the proposed design and operates similarly to the control pulse transmission channel 150, but with the following features:

[0198] 1) No control pulse is applied to the interference transmission channel 130, but it has a fourth transistor 9010 (always closed due to the connection between the second (control) electrode 9015 and the third electrode 9017) similar to the transistor 350 of the switch 140 (see FIG. 3). Therefore, the parameters of the circuit power supply input 133 - third resistor 903 - second transistor 980 - first transistor 970 - first resistor 901 - fourth transistor 9010 are similar to the corresponding circuit of the control pulse transmission channel 150 shown in FIG. 8 (also considering the switch 140 of FIG. 3), except that no current flows along this circuit both in the presence and absence of a control pulse. No current flows along the circuit power supply input 133 - fourth resistor 904 - third transistor 990 - second resistor 902 - terminal 137 of the interference transmission channel 130. Thus, no output pulses of the interfering transmission channel 130 appear at the output 139 during the presence or absence of the control pulse IN.

[0199] 2) If a high-power pulse interference appears at terminal 137 of the interference transmission channel 130, the channel 130 operates in the same way as the control pulse transmission channel 150, and when a high-power pulse interference arrives, an interference pulse is always present at output 139 of the interference transmission channel 130.

[0200] Therefore, the control pulse is always absent at the output 139 of the interference transmission channel 130 , and the interference pulse appears only if a high intensity pulse interference appears at the terminal 137 .

[0201] Since the control pulse transmission channel 150 and the interference transmission channel 130 are implemented similarly (taking into account the switch 140), a high degree of similarity in the interference pulses coming to the inputs 171 and 175 of the interference suppression circuit 170 is achieved.

[0202] Figure 5a shows a possible version of the interference suppression circuit 170a in the proposed LSC. In the absence of interference, the circuit operates as follows.

[0203] When a control pulse IN is applied to the control input 102 of the asserted LSC, the potential V at terminal 157 S A pulse with an amplitude exceeding the set value appears at the output 159 of the control pulse transmission channel 150 (see FIGS. 2a and 2b). This pulse is applied to the first input 171 of the interference suppression circuit 170a and is sent to the third electrode 571a of the transistor 570a. At the same time, a potential V at the terminal 106 of the asserted LSC is transmitted from the output 139 of the interference transmission channel 130 to the second input 175 of the circuit 170a. S is applied to the second, control, electrode 575a of transistor 570a.

[0204] The potential difference between inputs 171 and 175 causes a positive polarity difference pulse to be generated across resistor 510a of interference suppression circuit 170a and sent to output 179 of circuit 170a.

[0205] In the absence of a control pulse IN, the voltages at the source 571a and the second, control, electrode 575a of the transistor 570a are equal, and a zero difference signal is formed at the resistor 510a of the interference suppression circuit 170a, which is connected to the first electrode 577a of the transistor 570a, and this is sent to the output 179 of the interference suppression circuit 170a.

[0206] If both a control pulse and a high-intensity pulse interference are present at the output 159 of the control pulse transmission channel 150 and applied to the input 171 of the circuit 170a, a high-intensity pulse interference similar in amplitude and shape to that at the input 171 is also present at the output 139 of the interference transmission circuit 130 (and at the second input 175 of the interference suppression circuit 170a). In this case, a subtraction of the pulse interference at the input 171 and the input 175 occurs, and a difference signal is formed as a pulse of positive polarity and set amplitude at the resistor 510a connected to the first electrode 577a of the transistor 570a of the interference suppression circuit 170a, and this positive pulse is sent to the output 179 of the circuit 170a.

[0207] If high intensity pulse interference is present in the absence of a control pulse, the voltages at the third electrode 571a of transistor 570a and the second, control, electrode 575a are equal, and a zero difference signal is formed at resistor 510a, which is connected to the first electrode 577a of transistor 570a, and this is sent to the output 179 of the interference suppression circuit 170a.

[0208] Thus, when a control pulse is present at the input 171 of the interference suppression circuit 170a, a difference signal is formed at its output 179 as a positive pulse, regardless of whether high-intensity pulse interference is present or absent.

[0209] In the absence of a control pulse at the input 171 of the interference suppression circuit 170a, a zero difference signal is produced at its output 179, regardless of whether high intensity pulse interference is present or absent.

[0210] This is because no high intensity pulse interference is coming to the input 181 of the output stage 180 (see FIGS. 2a and 2b), and therefore the output V of the claimed LSC h This means that the signal is not coming in, which provides a high level of fail-safety in the event of high-intensity pulse interference with a high rate of rise.

[0211] The interference suppression circuit 170b shown in FIG. 5b can be used in both embodiments of the proposed LSC and operates as follows.

[0212] When a control pulse IN is applied to the control input 102 of the claimed LSC in the absence of high-intensity pulse interference, the potential V S A pulse with an amplitude exceeding the set value appears at the output 159 of the control pulse transmission channel 150 (see Figures 2a and 2b).

[0213] This pulse is applied to the first input 171 of the interference suppression circuit 170b and is sent to the third electrode 571b of the transistor 570b. At the same time, the potential V at the terminal 106 of the asserted LSC is transferred from the output 139 of the interference transmission channel 130 to the second input 175 of the circuit 170b. S is applied to the second, control, electrode 575b of transistor 570b. The potential difference between input 171 and input 175 causes transistor 570b to open, allowing current to flow through the path: power supply input 173 of interference suppression circuit 170 - transistor 520 - transistor 570b - first input 171. Since the pair of transistors 520 and 530 and their connections form a current mirror, the same current flows along the other path: power supply input 173 of interference suppression circuit 170b - transistor 530 - resistor 510b - terminal 177.

[0214] At this time, the difference signal is formed as a positive polarity pulse across resistor 510 b and goes to output 179 .

[0215] In the absence of a control pulse IN, the voltages at the third electrode 571b and the second, control electrode 575b of transistor 570b are equal to each other, forming a zero difference signal at resistor 510b, which passes to output 179.

[0216] When both a control pulse applied to input 171 of circuit 170b and high-intensity pulse interference are present at output 159 of control pulse transmission channel 150, there is present at output 139 of interference transmission channel 130 (and at second input 175 of interference suppression circuit 170b) high-intensity pulse interference similar in shape and amplitude to that at input 171. In this case, a subtraction of the pulse interference at input 171 and input 175 occurs, and a difference signal is formed at resistor 510b as a pulse of positive polarity and set amplitude, which is sent to output 179 of circuit 170b.

[0217] If high-intensity pulse interference is present in the absence of a control pulse, the voltages at the third electrode 571b and the second, control, electrode 575b of transistor 570b are equal and a zero-difference signal is formed at resistor 510b, which is sent to the output 179 of the interference suppression circuit 170b.

[0218] Thus, when a control pulse is present at the input 171 of the interference suppression circuit 170b, a difference signal is formed at its output 179 as a positive pulse, regardless of whether high-intensity pulse interference is present or absent.

[0219] In the absence of a control pulse at the input 171 of the interference suppression circuit 170b, a zero difference signal is produced at its output 179, regardless of whether high intensity pulse interference is present or absent.

[0220] This is because no high intensity pulse interference is coming to the input 181 of the output stage 180 (see FIGS. 2 and 2b), and therefore the output V of the claimed LSC h This means that the signal is not coming in, which provides a high level of fail-safety in the event of high-intensity pulse interference with a high rate of rise.

[0221] FIG. 6 shows a possible implementation of output stage 180, which can be used in both embodiments of the proposed LSC, and which operates as follows.

[0222] The control pulse, having been filtered out by the interference suppression circuit 170 (see FIGS. 2a and 2b), reaches the input 181 of the output stage 180 and then the input 651 of the Schmitt trigger 650, which converts the analog input signal into a digital output signal. From the output 655 of the Schmitt trigger 650, the control pulse goes to the output stage 189 of the output stage 180 (and further to the output 105 of the claimed LSC), which has a sufficiently sharp edge to turn on the upper transistor 7a of the power switch (shown in FIGS. 2a and 2b, but not part of the LSC).

[0223] FIG. 7a shows a possible implementation of a current source 120 made as a current mirror according to a first embodiment of the LSC.

[0224] In such a current source, the first transistor 730 and the second transistor 740 are the same.

[0225] Current source 120 operates as follows.

[0226] An input current I0 generated by the current setter 110 (see FIG. 2a) flows through the current source 120 along the path of the control input 126 of the current source 120, the first transistor 730, and the first terminal 127. The potential difference between the second (control) electrode 735 and the third electrode 737 of the first transistor 730 is equal to the potential difference between the second (control) electrode 745 and the third electrode 747 of the second transistor 740, and therefore a current I0 equal to that of the input flows through the second transistor 740. This current is also invariant and does not depend on the parameters of the load connected to the second terminal of the current source 120.

[0227] A possible implementation of the controllable current source 1120 according to the second embodiment of the LSC is shown in FIG. 7b and operates as follows.

[0228] The input current I0 generated by the current setter 110 (see FIG. 2b) flows through the controllable current source 1120 along the following path: control input 126 of the controllable current source 1120 - first transistor 730 - first resistor 750 - first terminal 127 of the controllable current source 1120. If the resistances of the first resistor 750 and the second resistor 770 are equal, a current I0 equal to the input current also flows through the transistor 740. This current is continuous and does not depend on the parameters of the load connected to the second terminal 129 of the controllable current source 1120.

[0229] When a control pulse IN arrives at the input 711 of the driving multivibrator 710 from the pulse input of the controllable current source 1120, a short pulse is generated at the multivibrator output 719, whose length is a fraction of a percent of the period of pulse IN. This pulse is applied to the second, control, electrode 725 of the third transistor 720, opening it. Because the third transistor 720 has low resistance when open, terminal 761 of the third resistor 760 is virtually instantly connected to the first terminal 127 of the controllable current source 1120 via the first electrode 723 and the third electrode 727 of the third transistor 720, and the third resistor 760 is connected in parallel with the second resistor 770 of the controllable current source 1120. Typically, the resistance of the third resistor 760 is chosen to be 5 to 15 times smaller than that of the second resistor 770, so that the current through the controllable current source 1120 increases at approximately the same rate, reaching a level I = 5 to 15I. When the short pulse at the output 719 of the driving multivibrator 710 is completed, the third transistor 720 closes, the resistance between its first electrode 723 and third electrode 727 becomes very high, and the third resistor 760 is disconnected from the first terminal 127 of the controllable current source 1120. Therefore, for the remaining duration of the control pulse IN, the current I flows through the controllable current source 1120.

[0230] An LSC 100a in one of its possible implementations is shown in Figure 10a, which shows the elements disclosed in Figures 3, 4, 5a, 6, 7a, 8, 9 according to a first embodiment of the proposed apparatus and operates as follows.

[0231] When a control pulse IN is applied to the control input 102 of LSC 100a and also appears at the second, control, terminal 145 of switch 140, transistor 340 closes and the resistance between its first and third electrodes becomes very high. At the same time, transistor 350 opens due to the potential Vcc being passed to the second (control) electrode of transistor 340 through resistor 360 at the low voltage power supply input 143 of switch 140. Thus, current flows through transistor 350 (and thus through switch 140) through terminal 104 of LSC 100a, which serves as the connection for the floating upper-level high-voltage power supply, power supply input 153 of control pulse transmission channel 150, third resistor 803, second transistor 880, first transistor 870, and first resistor 801 of control pulse transmission channel 150, transistor 350 of switch 140, transistor 740 of current source 120, first terminal 127 of current source 120, and terminal 103 of LSC 100a, which serves as the connection for the common wire of the LSC. The circuit is closed by the connection of the common wire of the LSC to the source of transistor 7b and the negative terminal of high-voltage power supply 6.

[0232] After the control pulse IN ends, transistor 340 of switch 140 opens, the resistance between first electrode 353 (drain) and third electrode 357 (source) becomes low, and the potential difference between second, control, electrode 355 (gate) and third electrode of transistor 350 of switch 140 becomes close to zero. Therefore, transistor 350 closes, switch 140 is now open, and the circuit through which the above-mentioned current flows is also opened.

[0233] The inclusion of transistor 340 in switch 140 speeds up the process of closing the switch because the low resistance of opening transistor 340 shunts the high input capacitance of transistor 350, improving the overall speed of LSC 100a.

[0234] The value of I0 that flows during the control pulse IN is determined by the current source 120.

[0235] I0=(V CC -V d ) / R 112

[0236] where V CC is a low voltage power supply applied to the first terminal 101 of the LSC 100a from a low voltage power supply 5 not included in the LSC 100a, and V d is the voltage between the second (control) and third electrodes of transistor 730 of current source 120, and R 112 is the resistance of the resistor 112 of the current setting device 110.

[0237] The value of the low voltage power supply Vcc can be within 4.5 to 5.5 V relative to the potential of the common wire of the LSC, and the value of I0 is set to a very low level (e.g., a few milliamps) using the current setter 110 to keep power consumption low.

[0238] Surge suppression circuit 160 is used to prevent breakdown of the input barrier of transistor 350 of switch 140, which could result in failure of both transistor 350 and the entire LSC 100a. Breakdown can occur at the leading edge of control pulse IN when a voltage surge occurs at the first electrode of transistor 350 of switch 140 and is passed to the third electrode of transistor 350 through the cross capacitance of this transistor.

[0239] Surge suppression circuit 160 operates as follows.

[0240] A control pulse IN is applied from the control input 102 of LSC 100a to the second (control) input 165, which is connected to the second electrode of transistor 460, opening transistor 460. Because the anode of Zener diode 430 is connected to the third electrode of transistor 350 of switch 140 through second terminal 169 of surge suppression circuit 160 and first terminal 147 of switch 140, the potential of the third electrode of transistor 350 is now equal to the voltage at the anode of Zener diode 430. This voltage, which includes the voltage at open transistor 460 and the voltage that stabilizes Zener diode 430, is several volts. The voltage at the second (control) electrode of transistor 350 is equal to the potential Vcc of the low-voltage power supply 5 at the low-voltage power supply input 143 of switch 140, and the potential difference between the second, control, electrode of transistor 350 and the anode of Zener diode 430 is small; therefore, from this point of view, breakdown of the input barrier of transistor 350 is not possible.

[0241] When control pulse IN terminates, transistor 460 closes, disconnecting Zener diode 460 from first terminal 167 of surge suppression circuit 160, thus preventing Zener diode 460 from breaking down due to the potential Vcc of low-voltage power supply 5 being applied to the anode of Zener diode 430 from low-voltage power supply input 143 of switch 140 through shorted transistor 340.

[0242] The control pulse transmission channel 150 (see FIG. 8) operates as follows.

[0243] During the control pulse IN, if there is no interference (situation 1), the voltage V at terminal 106 of LSC 100a is S A positive polarity pulse is generated relative to the first input 171 of the interference suppression circuit 170 .

[0244] The pulse is generated as follows: When a control pulse IN appears at the control input 102 of LSC 100a and is passed to the second, control, terminal 145 of switch 140, it closes, thus completing a circuit through which current flows from the power supply input 153 of control pulse transmission channel 150 to the first terminal 127 of current source 120.

[0245] This current flows through the control pulse transmission channel 150 along the path: power supply input 153 - third resistor 803 - second transistor 880 - first transistor 870 - first resistor 801 - input 151.

[0246] The first transistor 870 is opened by the voltage of the DC voltage source 8030 when the control pulse IN is present, and acts as a buffer stage to ensure sufficient operating speed of the circuit in question.

[0247] The pair of second and third transistors 880, 890 form a current mirror, so that when a current flows through the second transistor 880, it also flows through the third transistor 890. The value of this current is determined by the nominal ratio of the third resistor 803 to the fourth resistor 804. This current causes a voltage drop across resistor 802, which is sent to terminal 159 as an output pulse of the control pulse transmission channel 150. The amplitude of this pulse is determined by the potential V at terminal 157. S exceeds by a predetermined value.

[0248] If a high-intensity pulse interference appears at terminal 157 of control pulse transmission channel 150 while the control pulse IN is present (situation 2), a surge current appears along the power supply input 153 of control pulse transmission channel 150 - third resistor 803 - second transistor 880 - first transistor 870 - first resistor 801 - input 151. At the same time, due to the current mirror effect, the pulse interference current also flows through fourth resistor 804 and third transistor 890, causing an additional voltage drop across second resistor 802. This voltage drop is added to the voltage of the output pulse of control pulse transmission channel 150 and is sent to output 159 as an output signal containing the sum of the control pulse and the high-intensity pulse interference.

[0249] When there is no control pulse IN at the control input 102 of LSC 100a (situation 3), switch 140 disconnects the circuit for current flowing between power supply input 153 and input 151 of control pulse transmission channel 150. Similarly, no current flows through fourth resistor 804-third transistor 890-second resistor 802, and there is no output pulse of control pulse transmission channel 150.

[0250] If, during the absence of a control pulse, a high-intensity pulse interference appears at terminal 157 of control pulse transmission channel 150 (situation 4), a surge current appears along the power supply input 153 of control pulse transmission channel 150 - third resistor 803 - second transistor 880 - first transistor 870 - first resistor 801 - input 151. Due to the current mirror effect, the pulse interference current also flows through fourth resistor 804 and third transistor 890, causing an additional voltage drop across second resistor 802. This voltage drop is sent to output 159 as an output signal containing the pulse interference.

[0251] Thus, during a control pulse IN, an output control pulse is always present at output 159 of control pulse transmission channel 150 (situation 1), and if a high-power pulse interference appears, an interference pulse is added to it (situation 2). In the absence of a control pulse IN, there is no output control pulse at output 159 of control pulse transmission channel 150 (situation 3), and if a high-power pulse interference is present, an interference pulse appears at output 159 (situation 4).

[0252] The interference transmission channel 130 operates similarly to the control pulse transmission channel 150, but with the following special features.

[0253] 1) No control pulse is applied to the interfering transmission channel 130, but it has a fourth transistor 9010 similar to transistor 350 of switch 140 (which is always closed due to the connection between its second (control) electrode and its third electrode).

[0254] Thus, the parameters of the power supply input 133 - third resistor 903 - second transistor 980 - first transistor 970 - first resistor 901 - fourth transistor 9010 circuit in the interference transmission circuit 130 are similar to the corresponding circuit in the control pulse transmission channel 150 (also considering transistor 350), except that no current flows along this circuit both in the presence and absence of a control pulse. No current flows along the power supply input 133 - fourth resistor 904 - third transistor 990 - second resistor 902 - terminal 137 circuit in the interference transmission channel 130. Therefore, no output pulse of the interference transmission channel 130 appears at the output 139, either during the presence or absence of the control pulse IN.

[0255] 2) If a high-power pulse interference appears at terminal 137 of the interference transmission channel 130, the channel 130 operates in the same way as the control pulse transmission channel 150, and when a high-power pulse interference arrives, an interference pulse is always present at output 139 of the interference transmission channel 130.

[0256] Therefore, the control pulse is always absent at the output 139 of the interference transmission channel 130 , and the interference pulse appears only if a high intensity pulse interference appears at the terminal 137 .

[0257] Since the control pulse transmission channel 150 and the interference transmission channel 130 are implemented similarly (considering the transistor 350), a high degree of similarity is achieved in the interference pulses coming to the inputs 171 and 175 of the interference suppression circuit 170a.

[0258] From the output 159 of the control pulse transmission channel 150, the output control pulse in situation 1 or the output control pulse and interference pulse in situation 2 is sent to a first input 171 of an interference suppression circuit 170a, which is connected to the third electrode of transistor 570.

[0259] In situations 2 and 4, an interference pulse is sent from the output 139 of the interference transmission channel 130 to the second input 175 of the interference suppression circuit 170a.

[0260] When both the control pulse and the high-intensity pulse interference are simultaneously present at inputs 171 and 175 (at the third electrode and second (control) electrode of transistor 570), subtraction of the pulse interference occurs at those inputs and a positive difference signal of a set amplitude appears across resistor 510 of the interference suppression circuit 170a, which is connected to the first electrode 577 of transistor 570, and the difference signal is passed to the output 179 of the interference suppression circuit 170a.

[0261] If a high intensity pulse interference occurs in the absence of a control pulse, the voltages at the third electrode and the second, control, electrode of transistor 570 are equal, and a zero difference signal is formed across resistor 510 connected to the first electrode 577 of transistor 570, which is passed to the output 179 of the interference suppression circuit 170a.

[0262] Therefore, when a control pulse is present at the input 171 of the interference suppression circuit 170a (situation 1 or 2), a difference signal as a positive pulse is formed at its output 179, regardless of whether high-intensity pulse interference is present or not, and when there is no control pulse at the input 171 of the interference suppression circuit 170a (situation 3 or 4), a zero difference signal is formed at its output 179, regardless of whether high-intensity pulse interference is present or not.

[0263] The difference signal is sent from the output 179 of the interference suppression circuit 170a to the input 181 of an output stage 180 which includes a Schmitt trigger 650 which converts the analog input signal into a digital output signal. From the output 189 of the output stage 180, an output digital signal (representing a pulse which controls the upper transistor of the power switch) goes to the output 105 of the claimed LSC, which has a sufficiently sharp edge to turn on the upper transistor 7a of the power switch (shown in Figure 10b and which is not part of the LSC).

[0264] Thus, the claimed device according to the first embodiment simultaneously provides compensation of high intensity pulse interference with a high rate of rise (due to subtraction of the interference passing through the same transmission channels 150 and 130 as the control pulse and the interference) and moderate power consumption in normal operating mode (due to the ability to set the current flowing through the current source 120, the switch 140 and the control pulse transmission channel 150 to a very low level (e.g., a few milliamperes)), thereby achieving the declared technical result.

[0265] The claimed LSC in one of its possible implementations is shown in Figure 10b, which shows the elements disclosed in Figures 3, 4, 5a, 6, 7b, 8, and 9 according to a second embodiment of the proposed device, and operates as follows.

[0266] When a control pulse IN is applied to the control input 102 of LSC 100b and also appears at the second, control, terminal 145 of switch 140, transistor 340 closes and the resistance between its first and third electrodes becomes very high. At the same time, transistor 350 opens due to the potential Vcc being passed to the second (control) electrode of transistor 340 through resistor 360 at the low voltage power supply input 143 of switch 140. Thus, current flows through transistor 350 (and thus through switch 140) through terminal 104 of LSC 100b, which serves as the connection for the floating, upper-level high-voltage power supply, power supply input 153 of control pulse transmission channel 150, third resistor 803, second transistor 880, first transistor 870, and first resistor 801 of control pulse transmission channel 150, transistor 350 of switch 140, transistor 740 of controllable current source 1120, first terminal 127 of controllable current source 1120, and terminal 103 of LSC 100b, which serves as the connection for the common wire of the LSC. The circuit is closed by the connection of that common wire of the LSC to the source of transistor 7b and the negative terminal of high-voltage power supply 6, which is shown in FIG. 10b but is not part of LSC 100b.

[0267] After the control pulse IN ends, transistor 340 of switch 140 opens, the resistance between its first electrode (drain) and third electrode (source) becomes low, and the potential difference between its second, control, electrode (gate) and third electrode of transistor 350 of switch 140 becomes close to zero. Therefore, transistor 350 closes, switch 140 is now open, and the circuit through which the current flows is also opened.

[0268] The inclusion of transistor 340 in switch 140 speeds up the process of closing the switch because the low resistance of opening transistor 340 shunts the high input capacitance of transistor 350, improving the overall speed of LSC 100b.

[0269] The value of I0 flowing during the control pulse IN is determined by the controllable current source 1120.

[0270] I0=(V CC -V d ) / R 112

[0271] where V CC is a low voltage power supply applied to the first terminal 101 of the LSC 100b from a low voltage power supply 5 not included in the LSC 100b, and V d is the voltage between the second (control) and third electrodes of transistor 730 of controllable current source 1120, and R 112 is the resistance of the resistor 112 of the current setting device 110.

[0272] The value of the low voltage power supply Vcc can be within 4.5 to 5.5 V relative to the potential of the circuit common wire, and the value of I0 is set to a very low level (e.g., a few milliamps) using the current setter 110 to keep power consumption low.

[0273] When the control pulse IN arrives at the drive multivibrator 710 from the pulse input of the controllable current source 1120, a short pulse is generated at the multivibrator output, whose length is a fraction of a percent of the duration of the pulse IN. This pulse opens the third transistor 720, which connects the third resistor 760 of the controllable current source 1120 in parallel with the second resistor 770. Typically, the resistance of the third resistor 760 is selected to be 5 to 15 times smaller than that of the second resistor 770, so that the current through the controllable current source 1120 increases at approximately the same rate, reaching a level I1 = 5 to 15 I0. When the short pulse at the output of the drive multivibrator 710 is complete, the third transistor 720 closes, disconnecting the third resistor 760 from the first terminal 127 of the controllable current source 1120. Therefore, for the remaining duration of the control pulse IN, the current I0 flows through the controllable current source 1120.

[0274] Surge suppression circuit 160 is used to prevent breakdown of the input barrier of transistor 350 of switch 140, which could result in failure of both transistor 350 and the entire LSC 100b. Breakdown can occur at the leading edge of control pulse IN when a voltage surge occurs at the first electrode of transistor 350 of switch 140 and is passed to the third electrode of transistor 350 through the cross capacitance of this transistor.

[0275] Surge suppression circuit 160 operates as follows.

[0276] A control pulse IN is applied from the control input 102 of LSC 100b to a second (control) input 165 connected to the second electrode of transistor 460, opening transistor 460. Because the anode of Zener diode 430 is connected to the third electrode of transistor 350 of switch 140 through second terminal 169 of surge suppression circuit 160 and first terminal 147 of switch 140, the potential of the third electrode of transistor 350 is now equal to the voltage at the anode of Zener diode 430. This voltage, which includes the voltage at open transistor 460 and the voltage that stabilizes Zener diode 430, is several volts. The voltage at the second (control) electrode of transistor 350 is equal to the potential Vcc of the low-voltage power supply 5 at the low-voltage power supply input 143 of switch 140, and the potential difference between the second, control, electrode of transistor 350 and the anode of Zener diode 430 is small; therefore, from this point of view, breakdown of the input barrier of transistor 350 is not possible.

[0277] When control pulse IN terminates, transistor 460 closes, disconnecting Zener diode 460 from first terminal 167 of surge suppression circuit 160, thus preventing Zener diode 460 from breaking down due to the potential Vcc of low-voltage power supply 5 being applied to the anode of Zener diode 430 from low-voltage power supply input 143 of switch 140 through shorted transistor 340.

[0278] The control pulse transmission channel 150 (see FIG. 8) operates as follows. During the control pulse IN, if there is no interference (situation 1), the voltage V at terminal 106 of LSC 100b is S A positive polarity pulse is generated relative to the first input 171 of the interference suppression circuit 170 .

[0279] The pulse is generated as follows: When a control pulse IN appears at the control input 102 of LSC 100b and is passed to the second, control, terminal 145 of switch 140, it closes, thus completing a circuit through which current flows from the power supply input 153 of control pulse transmission channel 150 to the first terminal 127 of controllable current source 1120.

[0280] This current flows through the control pulse transmission channel 150 along the path: power supply input 153 - third resistor 803 - second transistor 880 - first transistor 870 - first resistor 801 - input 151.

[0281] The first transistor 870 is opened by the voltage of the DC voltage source 8030 when the control pulse IN is present, and acts as a buffer stage to ensure sufficient operating speed of the circuit in question.

[0282] The pair of second and third transistors 880, 890 form a current mirror, so that when a current flows through the second transistor 880, it also flows through the third transistor 890. The value of this current is determined by the nominal ratio of the third resistor 803 to the fourth resistor 804. This current causes a voltage drop across resistor 802, which is sent to terminal 159 as an output pulse of the control pulse transmission channel 150. The amplitude of this pulse is determined by the potential V at terminal 157. S exceeds by a predetermined value.

[0283] If a high-intensity pulse interference appears at terminal 157 of control pulse transmission channel 150 while the control pulse IN is present (situation 2), a surge current appears along the power supply input 153 of control pulse transmission channel 150 - third resistor 803 - second transistor 880 - first transistor 870 - first resistor 801 - input 151. At the same time, due to the current mirror effect, the pulse interference current also flows through fourth resistor 804 and third transistor 890, causing an additional voltage drop across second resistor 802. This voltage drop is added to the voltage of the output pulse of control pulse transmission channel 150 and is sent to output 159 as an output signal containing the sum of the control pulse and the high-intensity pulse interference.

[0284] When there is no control pulse IN at the control input 102 of LSC 100b (situation 3), switch 140 disconnects the circuit for current flowing between power supply input 153 and input 151 of control pulse transmission channel 150. Similarly, no current flows through fourth resistor 804-third transistor 890-second resistor 802, and there is no output pulse of control pulse transmission channel 150.

[0285] If, during the absence of a control pulse, a high-intensity pulse interference appears at terminal 157 of control pulse transmission channel 150 (situation 4), a surge current appears along the power supply input 153 of control pulse transmission channel 150 - third resistor 803 - second transistor 880 - first transistor 870 - first resistor 801 - input 151. Due to the current mirror effect, the pulse interference current also flows through fourth resistor 804 and third transistor 890, causing an additional voltage drop across second resistor 802. This voltage drop is sent to output 159 as an output signal containing the pulse interference.

[0286] Thus, during a control pulse IN, an output control pulse is always present at output 159 of control pulse transmission channel 150 (situation 1), and if a high-power pulse interference appears, an interference pulse is added to it (situation 2). In the absence of a control pulse IN, there is no output control pulse at output 159 of control pulse transmission channel 150 (situation 3), and if a high-power pulse interference is present, an interference pulse appears at output 159 (situation 4).

[0287] The interference transmission channel 130 operates similarly to the control pulse transmission channel 150, but with the following special features.

[0288] 1) No control pulse is applied to the interfering transmission channel 130, but it has a fourth transistor 9010 similar to transistor 350 of switch 140 (which is always closed due to the connection between its second (control) electrode and its third electrode).

[0289] Thus, the parameters of the power supply input 133 - third resistor 903 - second transistor 980 - first transistor 970 - first resistor 901 - fourth transistor 9010 circuit in the interference transmission circuit 130 are similar to the corresponding circuit in the control pulse transmission channel 150 (also considering transistor 350), except that no current flows along this circuit both in the presence and absence of a control pulse. No current flows along the power supply input 133 - fourth resistor 904 - third transistor 990 - second resistor 902 - terminal 137 circuit in the interference transmission channel 130. Therefore, no output pulse of the interference transmission channel 130 appears at the output 139, either during the presence or absence of the control pulse IN.

[0290] 2) If a high-power pulse interference appears at terminal 137 of the interference transmission channel 130, the channel 130 operates in the same way as the control pulse transmission channel 150, and when a high-power pulse interference arrives, an interference pulse is always present at output 139 of the interference transmission channel 130.

[0291] Therefore, the control pulse is always absent at the output 139 of the interference transmission channel 130 , and the interference pulse appears only if a high intensity pulse interference appears at the terminal 137 .

[0292] Since the control pulse transmission channel 150 and the interference transmission channel 130 are implemented similarly (considering the transistor 350), a high degree of similarity is achieved in the interference pulses coming to the inputs 171 and 175 of the interference suppression circuit 170a.

[0293] From the output 159 of the control pulse transmission channel 150, the output control pulse in situation 1 or the output control pulse and interference pulse in situation 2 is sent to a first input 171 of an interference suppression circuit 170a, which is connected to the third electrode of transistor 570.

[0294] In situations 2 and 4, an interference pulse is sent from the output 139 of the interference transmission channel 130 to the second input 175 of the interference suppression circuit 170a.

[0295] When both the control pulse and the high-intensity pulse interference are simultaneously present at inputs 171 and 175 (at the third electrode and second (control) electrode of transistor 570), subtraction of the pulse interference occurs at those inputs and a positive difference signal of a set amplitude appears across resistor 510 of the interference suppression circuit 170a, which is connected to the first electrode 577 of transistor 570, and the difference signal is passed to the output 179 of the interference suppression circuit 170a.

[0296] If a high intensity pulse interference occurs in the absence of a control pulse, the voltages at the third electrode and the second, control, electrode of transistor 570 are equal, and a zero difference signal is formed across resistor 510 connected to the first electrode 577 of transistor 570, which is passed to the output 179 of the interference suppression circuit 170a.

[0297] Therefore, when a control pulse is present at the input 171 of the interference suppression circuit 170a (situation 1 or 2), a difference signal as a positive pulse is formed at its output 179, regardless of whether high-intensity pulse interference is present or not, and when there is no control pulse at the input 171 of the interference suppression circuit 170a (situation 3 or 4), a zero difference signal is formed at its output 179, regardless of whether high-intensity pulse interference is present or not.

[0298] The difference signal is sent from the output 179 of the interference suppression circuit 170a to the input 181 of an output stage 180 which includes a Schmitt trigger 650 which converts the analog input signal into a digital output signal. From the output 189 of the output stage 180, an output digital signal (representing a pulse which controls the upper transistor of the power switch) goes to the output 105 of the claimed LSC, which has a sufficiently sharp edge to turn on the upper transistor 7a of the power switch (shown in Figure 10b and which is not part of the LSC).

[0299] Thus, the claimed device according to the second embodiment simultaneously provides compensation of high-intensity pulse interference with a high rise rate (due to the subtraction of the interference through the same transmission channels 150 and 130 as the control pulse and the interference) and moderate power consumption in normal operating mode (due to the ability to set the current flowing through the controllable current source 1120, the switch 140, and the control pulse transmission channel 150 to a very low level (e.g., a few milliamperes)), thereby achieving the declared technical result. Also, according to the second embodiment, the LSC is characterized by an increased operating speed due to a short rise in the current flowing through the controllable current source 1120, the switch 140, and the control pulse transmission channel 150 at the start of the control pulse IN.

[0300] It will be apparent to those skilled in the art that various implementations of the claimed elements of the LSC are possible.

[0301] For example, the DC voltage source 8030 (9030) of the channels 150 and 130 for transmitting control pulses and interference can be realized as a voltage divider connected to a floating low-voltage power supply 8 via terminal 104 of the device (see Figures 2a, 2b), or as a series connection of a resistor and a Zener diode, or in any other way that ensures the generation of the required voltage.

[0302] The current source 120 and the controllable current source 1120 can be realized not only in the form shown in Figures 7a and 7b but also in other known forms, such as the circuit described in U.S. Patent 3,320,439, issued May 16, 1967 to R.J. Widlar.

[0303] 2a and 2b can be implemented using standard electronic components such as diodes, transistors, and resistors, or integrated circuits (ICs), including custom-designed ICs. Thus, an n-channel FET, such as DMN26DOUT, with a maximum drain-source voltage of 20 V, a drain current of at least 20 mA, and a pulse current of at least 0.5 A can be used in current source 120.

[0304] Transistors 355 and 9010 (shown in FIGS. 3 and 9) should have a maximum drain-source voltage of at least 600 V and a drain-source capacitance of less than 5 pF at a voltage of 500 V. For transistors of this capacitance, BSS225 can be used.

[0305] Bipolar transistors may be used in place of the FETs disclosed herein and shown in the drawings, particularly with respect to transistor pairs 520-530, 730-740, and 880-890 used for the current mirrors of current sources 120 and 1120, control pulse transmission channel 150, and interference transmission channel 130.

[0306] A comparator such as an LT1719 can be used for the interference suppression circuit 170. The output stage 180 shown in Figure 6 can be implemented using a Microchip UCC27511DBV with a power supply voltage of 4.5 to 18V, an outgoing current of 4A, an input current of 8A, and an on / off delay of 13ns, or a Microchip SN74LVC1G1 with a power supply voltage of 1.65 to 5.5V, an outgoing / input current of 24mA, and an on / off delay of 1ns.

[0307] The nominal values ​​of resistors 803 (903) and 804 (904) of the control pulse transmission channel 150 (FIG. 8) and the interference transmission channel 130 (FIG. 9) may be within 100-200 ohms and 200-300 ohms, respectively.

[0308] The other elements of the LSC 100 may be realized in any manner known in the art that will achieve the declared technical results.

[0309] The claimed LSC can be made, for example, as a microchip, a microassembly, or a microboard, with the preferred form being a microchip, which allows for minimizing space and reducing manufacturing costs.

[0310] Also, the claimed LSCs may be part of other structures or other microchips, microassemblies, or microboards. Unless otherwise specified, portions of some elements described in this disclosure may differ from, partially coincide with, or completely coincide with portions of other elements. Furthermore, unless otherwise specified, portions of some elements may be located in various portions of other elements.

[0311] Experimental results To confirm the achievability of the declared technical results, scale modelling of a second embodiment of the LSC for the control of the power switch was carried out, with the following results:

[0312] The interference rise rate dV / dt is 100V / ns or more. Power consumption is less than 600mW at a control frequency of 100kHz and a duty cycle of 2. High voltage power supply is 500V or higher. On-off delay is 130 / 180ns respectively.

[0313] From the above description and the accompanying drawings, it follows that the technical result achieved by the claimed design is in fact by proposing an LSC with high interference immunity and low power consumption in the presence of a high voltage power supply for the upper transistor of the power switch.

[0314] The claimed invention, however, is not limited to what is disclosed above. It has been described based on what are currently considered to be practical implementations of various embodiments. It should be understood that the claimed invention is not limited to the disclosed embodiments, but is intended to be used in various modifications and equivalent implementations that correspond to the spirit and scope of the following claims.

[0315] Accordingly, the description and drawings are illustrative and do not limit the feasibility of implementing the invention.

[0316] The proposed technology is defined by the claims below.

Claims

1. A level shift circuit (100a) for controlling a power switch, comprising a current source (120) and a switch (140), wherein a second terminal (129) of the current source (120) is connected to a first terminal (147) of the switch (140), and a second control terminal (145) of the switch (140) is connected to an input (102) of the level shift circuit (100a), an interference transmission channel (130), a control pulse transmission channel (150), and an interference suppression circuit (170) for generating an output signal of the level shift circuit (100a) for controlling the power switch; The third terminal (149) of the switch (140) is connected to the input (151) of the control pulse transmission channel (150); a first input (171) of said interference suppression circuit (170) connected to the output (159) of said control pulse transmission channel (150); A second input (175) of the interference suppression circuit (170) is connected to the output (139) of the interference transmission channel (130).

1. A level shift circuit comprising:

2. 2. A level shift circuit (100a) according to claim 1, comprising: The control pulse transmission channel (150) includes a first transistor (870), a second transistor (880) forming a current mirror with a third transistor (890), a low voltage power supply (8030), a first resistor (801), a second resistor (802), a third resistor (803), and a fourth resistor (804); the input (151) of the control pulse transmission channel (150) is connected to the first resistor (801), which is connected in series with the first transistor (870), the second transistor (880), and the third resistor (803), which is connected to the power supply input (153) of the control pulse transmission channel (150); a second resistor (802) connected to a terminal (157) of the control pulse transmission channel (150), the second resistor being connected in series with the third transistor (890) and the fourth resistor (804) connected to a power supply input (153) of the control pulse transmission channel (150); the negative terminal of the low-voltage power supply (8030) is connected to the terminal (157) of the control pulse transmission channel (150), and the positive terminal of the low-voltage power supply is connected to the second control electrode of the first transistor (870); second control electrodes of the second transistor (880) and the third transistor (890) are connected to each other and to the first electrode of the first transistor (870) and to the third electrode of the second transistor (880); The junction between the first electrode of the third transistor (890) and the second resistor (802) is connected to the output (159) of the control pulse transmission channel (150).

1. A level shift circuit comprising:

3. 2. A level shift circuit (100a) according to claim 1, comprising: The interference transmission channel (130) includes a first transistor (970), a second transistor (980) forming a current mirror with a third transistor (990), a fourth transistor (9010), a low voltage power supply (9030), a first resistor (901), a second resistor (902), a third resistor (903), and a fourth resistor (904); a low voltage power supply input (135) of the interference transmission channel (130) is connected to the series connection of the fourth transistor (9010), the first resistor (901), the first transistor (970), the second transistor (980), and the third resistor (903) connected to a high voltage power supply input (133) of the interference transmission channel (130); a terminal (137) of the interference transmission channel (130) is connected to a series connection of the second resistor (902), the third transistor (990), and the fourth resistor (904), the fourth resistor also being connected to the high voltage power supply input (133) of the interference transmission channel (130); The terminal (137) of the interference transmission channel (130) is also connected to the negative terminal of the low-voltage power supply (9030), the positive terminal of which is connected to the second control electrode of the first transistor (970); second control electrodes of the second transistor (980) and the third transistor (990) are connected to each other and to the first electrode of the first transistor (970) and to the third electrode of the second transistor (980); a junction between the first electrode of the third transistor (990) and the second resistor (902) is connected to an output (139) of the interference transmission channel (130); The second control electrode of the fourth transistor (9010) is connected to the third electrode of the fourth transistor.

1. A level shift circuit comprising:

4. 2. A level shift circuit (100a) according to claim 1, comprising: The interference suppression circuit (170) includes a transistor (570) and a resistor (510); a third electrode (571) of the transistor (570) is connected to a first input (171) of the interference suppression circuit (170); a second control electrode (575) of the transistor (570) is connected to a second input (175) of the interference suppression circuit (170); a first electrode (577) of the transistor (570) connected to the output (179) of the interference suppression circuit (170); The resistor (510) is connected between the output (179) and terminal (177) of the interference suppression circuit (170).

1. A level shift circuit comprising:

5. 2. A level shift circuit (100a) according to claim 1, comprising: The interference suppression circuit (170) includes a first transistor (570), a second transistor (520), a third transistor (530), and a resistor (510); a first input (171) of the interference suppression circuit (170) is connected to a third electrode (571) of the first transistor (570); a second input (175) of the interference suppression circuit (170) is connected to a second control electrode (575) of the first transistor (570); a first electrode (577) of the first transistor (570) is connected to a first electrode (527) of the second transistor (520) and to a junction point between a second control electrode (525) of the second transistor (520) and a second control electrode (535) of the third transistor (530); a third electrode (521) of the second transistor (520) and a third electrode (531) of the third transistor (530) are connected to each other and to a power supply input (173) of the interference suppression circuit (170); The output (179) of the interference suppression circuit (170) is connected to the first electrode (537) of the third transistor (530) and to the first terminal (511) of the resistor (510), the second terminal (513) of which is connected to the terminal (177) of the interference suppression circuit (170).

1. A level shift circuit comprising:

6. 2. A level shift circuit (100a) according to claim 1, comprising an output stage (180), the input (181) of which is connected to the output (179) of the interference suppression circuit (170), and the output (189) of which is the output of the level shift circuit (100a).

7. 7. A level shift circuit (100a) according to claim 6, comprising: the output stage (180) includes a Schmitt trigger (650); The input (181) of the output stage is connected to the input (651) of the Schmitt trigger (650); the output (655) of said Schmitt trigger (650) is connected to the output (189) of said output stage (180); a power supply input (652) of said Schmitt trigger (650) is connected to a power supply input (183) of said output stage (180); The terminal (654) of the Schmitt trigger (650) serves as a connection to a common wire and is connected to the terminal (187) of the output stage (180).

1. A level shift circuit comprising:

8. 2. A level shift circuit (100a) according to claim 1, comprising: The current source (120) includes a first transistor (730) and a second transistor (740); a first electrode (733) of the first transistor (730) and a connection point between a second control electrode (735) of the first transistor (730) and a second control electrode (745) of the second transistor (740) are connected to a control input (126) of the current source (120); a first electrode (743) of the second transistor (740) is connected to a second terminal (129) of the current source (120); The third electrode (737) of the first transistor (730) and the third electrode (747) of the second transistor (740) are connected to each other and to the first terminal (127) of the current source (120).

1. A level shift circuit comprising:

9. 2. A level shift circuit (100a) according to claim 1, comprising: The switch (140) includes a first transistor (340), a second transistor (350), and a resistor (360); a first terminal (365) of the resistor (360) connected to the low voltage power supply input (143) of the switch (140); A second control electrode (345) of the first transistor (340) is connected to a second control terminal (145) of the switch (140); a second control electrode (355) of the second transistor (350) is connected to a second terminal (367) of the resistor (360) and to a third electrode (347) of the first transistor (340); a first electrode (343) of the first transistor (340) and a third electrode (357) of the second transistor (350) are connected to a first terminal (147) of the switch (140); The first electrode (353) of the second transistor (350) is connected to the third terminal (149) of the switch (140).

1. A level shift circuit comprising:

10. 2. A level shift circuit (100a) according to claim 1, comprising: a surge suppression circuit (160) connected in parallel with the current source (120) and including a transistor (460) and a Zener diode (430); a second control electrode (465) of the transistor (460) is connected to a second control input (165) of the surge suppression circuit (160); an anode (432) of the Zener diode (430) connected to a first electrode (463) of the transistor (460), and a cathode (435) of the Zener diode (430) connected to a first terminal (169) of the surge suppression circuit (160); The third electrode (467) of the transistor (460) is connected to the second terminal (167) of the surge suppression circuit (160).

1. A level shift circuit comprising:

11. A level shift circuit (100b) for controlling a power switch, comprising a switch (140), a second control terminal of which is connected to an input (102) of the level shift circuit (100b), a controllable current source (1120), a control pulse transmission channel (150), an interference transmission channel (130), and an interference suppression circuit (170) for generating an output signal of the level shift circuit (100b) for controlling the power switch; a second terminal (129) of the controllable current source (1120) is connected to a first terminal (147) of the switch (140); The third terminal (149) of the switch (140) is connected to the input (151) of the control pulse transmission channel (150); a first input (171) of said interference suppression circuit (170) connected to the output (159) of said control pulse transmission channel (150); a second input (175) of said interference suppression circuit (170) connected to the output (139) of the interference transmission channel (130); The pulse input (1125) of the controllable current source (1120) is connected to the input (102) of the level shift circuit (100b).

1. A level shift circuit comprising:

12. 12. A level shift circuit (100b) according to claim 11, comprising: The control pulse transmission channel (150) includes a first transistor (870), a second transistor (880) forming a current mirror with a third transistor (890), a low voltage power supply (8030), a first resistor (801), a second resistor (802), a third resistor (803), and a fourth resistor (804); the input (151) of the control pulse transmission channel (150) is connected to the first resistor (801), which is connected in series with the first transistor (870), the second transistor (880), and the third resistor (803), which is connected to the power supply input (153) of the control pulse transmission channel (150); a second resistor (802) connected to a terminal (157) of the control pulse transmission channel (150), the second resistor being connected in series with the third transistor (890) and the fourth resistor (804) connected to a power supply input (153) of the control pulse transmission channel (150); the negative terminal of the low-voltage power supply (8030) is connected to the terminal (157) of the control pulse transmission channel (150), and the positive terminal of the low-voltage power supply is connected to the second control electrode of the first transistor (870); second control electrodes of the second transistor (880) and the third transistor (890) are connected to each other and to the first electrode of the first transistor (870) and to the third electrode of the second transistor (880); The junction between the first electrode of the third transistor (890) and the second resistor (802) is connected to the output (159) of the control pulse transmission channel (150).

1. A level shift circuit comprising:

13. 12. A level shift circuit (100b) according to claim 11, comprising: The interference transmission channel (130) includes a first transistor (970), a second transistor (980) forming a current mirror with a third transistor (990), a fourth transistor (9010), a low voltage power supply (9030), a first resistor (901), a second resistor (902), a third resistor (903), and a fourth resistor (904); a low voltage power supply input (135) of the interference transmission channel (130) is connected to the series connection of the fourth transistor (9010), the first resistor (901), the first transistor (970), the second transistor (980), and the third resistor (903) connected to a high voltage power supply input (133) of the interference transmission channel (130); a terminal (137) of the interference transmission channel (130) is connected to a series connection of the second resistor (902), the third transistor (990), and the fourth resistor (904), the fourth resistor also being connected to the high voltage power supply input (133) of the interference transmission channel (130); The terminal (137) of the interference transmission channel (130) is also connected to the negative terminal of the low-voltage power supply (9030), the positive terminal of which is connected to the second control electrode of the first transistor (970); second control electrodes of the second transistor (980) and the third transistor (990) are connected to each other and to the first electrode of the first transistor (970) and to the third electrode of the second transistor (980); a junction between the first electrode of the third transistor (990) and the second resistor (902) is connected to an output (139) of the interference transmission channel (130); The second control electrode of the fourth transistor (9010) is connected to the third electrode of the fourth transistor.

1. A level shift circuit comprising:

14. 12. A level shift circuit (100b) according to claim 11, comprising: The interference suppression circuit (170) includes a transistor (570) and a resistor (510); a third electrode (571) of the transistor (570) is connected to a first input (171) of the interference suppression circuit (170); a second control electrode (575) of the transistor (570) is connected to a second input (175) of the interference suppression circuit (170); a first electrode (577) of the transistor (570) connected to the output (179) of the interference suppression circuit (170); The resistor (510) is connected between the output (179) and terminal (177) of the interference suppression circuit (170).

1. A level shift circuit comprising:

15. 12. A level shift circuit (100b) according to claim 11, comprising: The interference suppression circuit (170) includes a first transistor (570), a second transistor (520), a third transistor (530), and a resistor (510); a first input (171) of the interference suppression circuit (170) is connected to a third electrode (571) of the first transistor (570); a second input (175) of the interference suppression circuit (170) is connected to a second control electrode (575) of the first transistor (570); a first electrode (577) of the first transistor (570) is connected to a first electrode (527) of the second transistor (520) and to a junction point between a second control electrode (525) of the second transistor (520) and a second control electrode (535) of the third transistor (530); a third electrode (521) of the second transistor (520) and a third electrode (531) of the third transistor (530) are connected to each other and to a power supply input (173) of the interference suppression circuit (170); The output (179) of the interference suppression circuit (170) is connected to the first electrode (537) of the third transistor (530) and to the first terminal (511) of the resistor (510), the second terminal (513) of which is connected to the terminal (177) of the interference suppression circuit (170).

1. A level shift circuit comprising:

16. 12. A level shift circuit (100b) according to claim 11, comprising an output stage (180), the input (181) of which is connected to the output (179) of the interference suppression circuit (170), and the output (189) of which is the output of the level shift circuit (100a).

17. 17. A level shift circuit (100b) according to claim 16, comprising: the output stage (180) includes a Schmitt trigger (650); The input (181) of the output stage is connected to the input (651) of the Schmitt trigger (650); the output (655) of said Schmitt trigger (650) is connected to the output (189) of said output stage (180); a power supply input (652) of said Schmitt trigger (650) is connected to a power supply input (183) of said output stage (180); The terminal (654) of the Schmitt trigger (650) serves as a connection to a common wire and is connected to the terminal (187) of the output stage (180).

1. A level shift circuit comprising:

18. 12. A level shift circuit (100b) according to claim 11, comprising: The controllable current source (1120) includes a first transistor (730), a second transistor (740), a third transistor (720), a driving multivibrator (710), a first resistor (750), a second resistor (770), and a third resistor (760); a first electrode (733) of the first transistor (730) and a junction point between a second control electrode (735) of the first transistor (730) and a second control electrode (745) of the second transistor (740) are connected to a control input (126) of the controllable current source (1120); a first electrode (743) of the second transistor (740) is connected to a second terminal (129) of the controllable current source (1120); a third electrode (737) of the first transistor (730) is connected to a first terminal (127) of the controllable current source (1120) via the first resistor (750); a third electrode (747) of the second transistor (740) is connected to the first terminal (127) through the second resistor (770); a terminal (763) of the third resistor (760) is connected to a common point between the third electrode of the second transistor (740) and the second resistor (770); a terminal (761) of the third resistor (760) is connected to a first electrode (723) of the third transistor (720); a second control electrode (725) of the third transistor (720) is connected to the output (719) of the driving multivibrator (710); a third electrode (727) of the third transistor (720) is connected to the first terminal (127) of the controllable current source (1120); The input (711) of the driving multivibrator (710) is connected to the pulse input (1125) of the controllable current source (1120).

1. A level shift circuit comprising:

19. 12. A level shift circuit (100b) according to claim 11, comprising: The switch (140) includes a first transistor (340), a second transistor (350), and a resistor (360); a first terminal (365) of the resistor (360) connected to the low voltage power supply input (143) of the switch (140); A second control electrode (345) of the first transistor (340) is connected to a second control terminal (145) of the switch (140); a second control electrode (355) of the second transistor (350) is connected to a second terminal (367) of the resistor (360) and to a third electrode (347) of the first transistor (340); a first electrode (343) of the first transistor (340) and a third electrode (357) of the second transistor (350) are connected to a first terminal (147) of the switch (140); The first electrode (353) of the second transistor (350) is connected to the third terminal (149) of the switch (140).

1. A level shift circuit comprising:

20. 12. A level shift circuit (100b) according to claim 11, comprising: a surge suppression circuit (160) connected in parallel with the controllable current source (1120) and including a transistor (460) and a Zener diode (430); a second control electrode (465) of the transistor (460) is connected to a second control input (165) of the surge suppression circuit (160); an anode (432) of the Zener diode (430) connected to a first electrode (463) of the transistor (460), and a cathode (435) of the Zener diode (430) connected to a first terminal (169) of the surge suppression circuit (160); The third electrode (467) of the transistor (460) is connected to the second terminal (167) of the surge suppression circuit (160).

1. A level shift circuit comprising:

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