Method for manufacturing a wafer with two regions having a wettability contrast greater than 90° and wafers manufactured in this way

Abstract

The present invention relates primarily to the field of 3D interconnection technologies for microelectronics, but also to any application requiring high wettability contrast on the micrometer scale. The proposed method makes it possible to manufacture a wafer (1) having a main surface (10) with solid regions (101) and micro- or nanostructured regions (102) having a wettability contrast between them of greater than 90°, preferably greater than 120°, each structured region (102) extending around the solid region (101), the wafer comprising a substrate (11) having a first level (111) mainly made of a semiconductor material and a second level (112) mainly made of a dielectric material, the solid regions and each structured region being formed on the second level of the substrate, each structured region having a plurality of protrusions (131) mainly made of said dielectric material, the wafer being such that the protrusions have faceted edges.

Description

[Technical Field]

[0001] The invention relates mainly to the field of 3D interconnection technology for microelectronics, but can concern any kind of application that requires having a high wettability contrast on a micrometer scale.

[0002] The present invention more particularly relates to die-to-wafer (DTW) hybrid bonding die self-assembly technology.

[0003] The invention is particularly advantageously applied to the self-assembly of microelectronic components for their 3D integration, in which case the invention can relate to the self-assembly of other types of dies than microelectronic dies, in particular the self-assembly of microsystems, biological dies, fluidic devices, optical devices, etc. [Background technology]

[0004] 3D interconnection technologies have been developed to increase the number of functionalities per surface unit. Die-to-Wafer (DTW) transfer techniques are of particular interest for heterogeneous 3D integration, offering the advantage of assembling different technologies onto one and the same receiving circuit, or equivalently, onto one and the same functionalized receiving wafer.

[0005] Current DTW methods fall into two categories: a. Pick-and-place transfer method: The dies are picked up by a robot and aligned one by one on the receiving wafer (hereinafter also referred to as the "target wafer"). However, in these methods, the alignment accuracy is inversely proportional to the transfer speed; and b. Self-assembly transfer method: The die is transferred to the receiving wafer by a pick-and-place machine and roughly pre-aligned, with final alignment achieved by the capillary force of the liquid at the interface between the die and the transfer area of ​​the die on the receiving wafer.

[0006] More specifically, self-assembly consists of depositing a water droplet on the transfer area of ​​the die, which is hydrophilic, and then approaching the die so that it self-aligns due to the capillary forces between the two surfaces in the presence of both sides of the droplet. This technique can increase both the alignment accuracy and the transfer speed. The transfer of the dies can also be performed individually or in bulk.

[0007] Self-assembly therefore requires adaptation of conventional die-to-wafer (DTW) bonding integration, in particular with the definition of hydrophilic and hydrophobic regions on the target wafer, preferably with a high surface energy contrast between both.

[0008] It is noted that in this case the hydrophilic, hydrophobic and superhydrophobic properties of the surfaces are characterized by their drop angle values, which are less than 90°, between 90 and 120°, and greater than 120°, respectively.

[0009] With reference to FIG. 1, one way to create a wettability contrast (the difference between the drop angle α in the transfer area 101 of the die and the drop angle β in the area 102 surrounding the transfer area 101) is to: a. forming mesas 15, typically a few micrometers thick, on the surface 10 of the receiving wafer 1, with the upper surface of the mesas 15 constituting the receiving area 101 for the die; and / or b. forming a mesa, typically a few micrometers thick, on the surface of each die to be transferred; and / or c. using a hydrophilic layer 1000 on the top surface of each mesa to provide chemical contrast between each receiving area 101 on the surface of the receiving wafer 1 and the inter-die areas 102 surrounding each receiving area 101, and even between the receiving areas 101 on the surface of the receiving wafer 1 and the rest of the surface of the receiving wafer 1; and / or d. Creating a chemical contrast between the receiving area 101 and the inter-die area 102 on the surface of the receiving wafer 1 using a hydrophobic layer 1001 covering at least the inter-die area 102 and, if necessary, the periphery of each mesa 15.

[0010] In this way, a wettability contrast of approximately 90° can be obtained.

[0011] To create a wettability contrast between the receiving areas of the dies to be transferred and the areas surrounding these receiving areas, it is also possible to create a micro- or nano-structured surface, i.e., a surface with micro- or nano-roughness, on the surface of the receiving wafer, at least in the areas surrounding the receiving areas, which creates the conditions for observing the lotus effect. In particular, if such surface structuring is combined with the presence of a chemical hydrophobic coating, it is possible to reach a wettability contrast of more than 120°. In this way, superhydrophobicity is achieved, allowing for better alignment accuracy.

[0012] Thus, a method for producing hydrophilic receptor sites surrounded by a superhydrophobic surface using dry etching of Si obtained by deep reactive ion etching, which makes it possible to obtain black silicon, i.e. a very rough silicon surface made up of small needle shapes, is known from the article entitled "Surface-Tension-Driven Self-Alignment of Microchips on Black-Silicon-Based Hybrid Template in Ambient Air" by Ali Shah et al., published in JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, Volume 22, Issue 3, June 2013, page 739.

[0013] However, obtaining such a superhydrophobic surface by deep reactive ion etching is not easy to reproducibly. In addition, black silicon can generate a significant amount of silicon debris that breaks off from the surface in the form of particles, due to the highly irregular and weakly positioned microneedles produced. This is therefore a significant disadvantage for hybrid bonding techniques, which require surfaces that are as clean and particle-free as possible.

[0014] Additionally, the methods described in the above-mentioned articles require accessing the silicon of the substrate in the inter-die regions, which may require having to remove all of the material deposited on the target wafer during circuit fabrication, which may prove difficult and expensive depending on the complexity of the material stack, especially in the upper levels of the receiving wafer that are typically functionalized to be used as interconnect levels between the target wafer and the dies. [Prior art documents] [Non-patent literature]

[0015] [Non-Patent Document 1] Ali Shah et al., "Surface-Tension-Driven Self-Alignment of Microchips on Black-Silicon-Based Hybrid Template in Ambient Air," in JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, Volume 22, Issue 3, June 2013, pp. 739-740. Summary of the Invention [Problem to be solved by the invention]

[0016] The object of the present invention is therefore to propose a method for manufacturing wafers comprising a main surface having at least one solid region and one micro- or nanostructured region with a wettability contrast between them of greater than 90°, preferably greater than 120°, each micro- or nanostructured region extending around the solid region, which method makes it possible to overcome at least one of the disadvantages of the prior art.

[0017] The object of the present invention is more particularly to propose such a method leading to the production of wafers suitable for die self-assembly by die-to-wafer hybrid bonding.

[0018] Other objects, features and advantages of the present invention will become apparent upon consideration of the following description and accompanying drawings, and it will be understood that other advantages may be incorporated. [Means for solving the problem]

[0019] To this end, according to one embodiment, there is provided a method for manufacturing a wafer comprising a main surface having at least one solid region and one micro- or nanostructured region with a wettability contrast between them of greater than 90°, preferably greater than 120°, each micro- or nanostructured region extending around the solid region, the method comprising the following steps: a. providing a substrate comprising a first level primarily comprised of a semiconductor material and a second level primarily comprised of a dielectric material, the second level extending over the first level; b. forming on the exposed surface of the second level of the provided substrate a layer based on a sacrificial material, such as a resin, having at least one first area in which a solid layer based on said sacrificial material extends, and a second area having a surface structured by a plurality of micrometric or nanometric protrusions based on said sacrificial material, each first area being surrounded by a second area and each first area extending over a surface that is at least one order of magnitude larger than the micrometric or nanometric surface of each protrusion based on said sacrificial material; and then c. removing a portion of the previously formed sacrificial-based layer and a portion of the second level of the substrate; and etching at a second level of the substrate to form the at least one solid region in each first region and micro- or nanostructured regions in each second region, each micro- or nanostructured region having a plurality of protrusions based on the dielectric material corresponding to a plurality of protrusions based on the sacrificial material.

[0020] Among the advantages resulting from the manufacturing method as presented above, the following may be mentioned: a. The shape, size and density of the protrusions made from the dielectric material are fully controlled and adjustable, since they are determined by the pattern imposed by the sacrificial-based layer. Similarly, the distance between the solid regions and the micro- or nanostructured regions is fully controlled and adjustable, since it is determined by the pattern imposed by the sacrificial-based layer; and / or b. In this way, it is avoided to create solid regions or mesas with very high thickness on the surface of the wafer, which mesas are nevertheless obtained in a way that contributes to achieving a high wettability contrast between the solid regions (or mesas) and the micro- or nanostructured regions.

[0021] Optionally, the first aspect of the present invention may further comprise at least one of the following features, which may be selected separately or in combination:

[0022] According to one example, etching can be continued with over-etching until lift-off of the sacrificial material-based protrusions is achieved. The dimensional difference (of one order of magnitude) between the sacrificial material-based solid layers and the sacrificial material-based protrusions explains why the sacrificial material constituting the sacrificial material-based protrusions is consumed more rapidly by etching than the sacrificial material constituting the first regions, due to the "faceting" phenomenon consisting of lateral consumption of the sacrificial material added to its consumption from above. Therefore, dielectric material-based protrusions are thus obtained with faceted edges, e.g., needle-like. While this angle is substantially equal to 130° compared to the drop angle obtained with a flat protrusion head, the faceted head of the protrusion obtained after over-etching advantageously allows achieving a drop angle substantially equal to 160°. A better hydrophobic effect is thus obtained.

[0023] According to another example, the formation of the layer based on the sacrificial material can include a photolithography step. It is therefore clear that applying one single photolithography level to the provided substrate is sufficient to obtain a wafer having at least two regions with a wettability contrast between them of greater than 90°, preferably greater than 120°. Furthermore, the etching step that allows the generation of microroughness therefore corresponds to standard fully controlled microelectronic techniques and does not generate defects or particles. It is very easy to integrate into a method for producing a receiving wafer intended for the transfer of dies by hybrid die bonding, implementing the same type of equipment as the technique for producing the provided substrate.

[0024] According to another example, etching can be stopped before obtaining lift-off of the sacrificial material-based layer on the surface of each first region, the sacrificial material-based layer remaining on the surface of each first region, preferably having a thickness between 100 nm and 5 μm. Preferably, etching comprises exposure to an etching plasma or to ion etching.

[0025] According to another example, the manufacturing method according to the first aspect of the present invention can further comprise, following etching, the deposition of a layer based on a hydrophobic material, preferably conformal, hereinafter referred to as the "hydrophobic layer." For example, the hydrophobic material of which the hydrophobic layer is composed is preferably based on at least one polymer, for example, 0.1 wt. % fluorosilane polymer in a hydrofluoroether carrier solvent. For example, the deposition of the hydrophobic layer can comprise a spin-coating step or a plasma deposition step.

[0026] According to another example, the manufacturing method according to the first aspect of the present invention may further comprise the step of removing a portion of the layer mainly composed of the sacrificial material that remains on the surface of the first regions after etching, so as to expose a second level surface of the substrate located on the surface of each first region.

[0027] According to one example related to the two previous examples, deposition of a hydrophobic layer can be implemented before lifting off the part of the sacrificial material-based layer that remains on the surface of the first region after etching. Lifting off the part of the sacrificial material-based layer that remains on the surface of the first region thus results in removal of the hydrophobic material-based layer on the surface of the solid region. Subsequently, since the material from which the second level of the substrate is composed is hydrophilic, the wettability contrast between the solid region (or mesa) and the micro- or nanostructured region is advantageously significantly increased.

[0028] According to another example, the wafer may constitute a receiving wafer intended for the transfer of microelectronic components, such as microelectronic dies, by hybrid bonding, each solid area intended to receive a microelectronic component and each micro- or nanostructured area intended to constitute at least one part of the area between the microelectronic components.

[0029] According to the previous example, the second level of the substrate comprises at least one electrical interconnection level extending at least over the surface of each solid region and, if necessary, extending from the solid region into an adjacent micro- or nanostructured region, and etching can be stopped before reaching said at least one electrical interconnection level. The method thus makes it possible to preserve the integrity of insulating and metallic materials, which can be very numerous in the inter-die regions and, given their variety, difficult to remove by etching.

[0030] A second aspect of the present invention relates to a wafer having a major surface with at least one solid region and one micro- or nanostructured region having a wettability contrast therebetween of greater than 90°, preferably greater than 120°, each micro- or nanostructured region extending around the solid region, the wafer comprising a substrate having a first level mainly made of semiconductor material and a second level mainly made of dielectric material, the second level extending over the first level, the at least one solid region and each micro- or nanostructured region being formed in the second level of the substrate, each micro- or nanostructured region having a plurality of protrusions mainly made of said dielectric material, the wafer being such that the protrusions mainly made of said dielectric material have faceted edges.

[0031] The wafer according to the second aspect of the invention makes it possible to obtain a further increased wettability contrast with respect to that offered by a wafer supporting protrusions each in the form of a pillar, the cross section of which remains substantially constant from base to apex.

[0032] A third aspect of the present invention relates to a method for self-assembling microelectronic components onto a wafer according to the second aspect of the present invention, wherein a plurality of microelectronic components, such as microelectronic dies, are self-assembled onto the wafer by die-to-wafer hybrid bonding.

[0033] A fourth aspect of the invention relates to an assembly comprising a wafer according to the second aspect of the invention and a plurality of microelectronic components, such as microelectronic dies, attached to the wafer by hybrid bonding.

[0034] The objects, goals, as well as features and advantages of the present invention will be best apparent from the following detailed description of one embodiment of the present invention, illustrated by the accompanying drawings. [Brief explanation of the drawings]

[0035] [Figure 1] 1A and 1B are schematic cross-sectional views of a portion of one embodiment of a receiving wafer according to the prior art; [Figure 2] 1A and 1B are schematic cross-sectional views of a portion of one embodiment of a receiving wafer according to the present invention and a microelectronic die positioned toward a surface of the receiving wafer, the microelectronic die intended to be attached to the receiving wafer by hybrid bonding. [Figure 3A] 3A-3C illustrate schematically various steps of an embodiment of a method for manufacturing an incoming wafer as illustrated in FIG. 2. [Figure 3B] 3A-3C illustrate schematically various steps of an embodiment of a method for manufacturing an incoming wafer as illustrated in FIG. 2. [Figure 3C] 3A-3C illustrate schematically various steps of an embodiment of a method for manufacturing an incoming wafer as illustrated in FIG. 2. [Figure 3D] 3A-3C illustrate schematically various steps of an embodiment of a method for manufacturing an incoming wafer as illustrated in FIG. 2. [Figure 3E] 3A-3C illustrate schematically various steps of an embodiment of a method for manufacturing an incoming wafer as illustrated in FIG. 2. [Figure 4A] 1A and 1B schematically illustrate a top view of one embodiment of a receiving wafer according to the present invention. [Figure 4B] 4B illustrates an enlarged view of four protrusions made from a dielectric material of an embodiment of a receiving wafer according to the present invention illustrated in FIG. 4A. [Figure 5A] 3 shows a perspective photograph of a protrusion made from a dielectric material obtained by mounting without overetching in one embodiment of the manufacturing method according to the first aspect of the present invention. [Figure 5B] 3 shows a perspective photograph of a protrusion made from a dielectric material obtained by mounting with overetching in one embodiment of the manufacturing method according to the first aspect of the present invention. [Figure 6A]1 represents a perspective photograph of a portion of a receiving wafer according to the present invention, comprising protrusions made of a dielectric material and covered with a layer made of a hydrophobic material, obtained by implementing an embodiment of a manufacturing method according to the first aspect of the present invention; [Figure 6B] 1 shows a perspective photograph of a portion of a receiving wafer according to the present invention, comprising a receiving mesa obtained by implementing one embodiment of a manufacturing method according to the first aspect of the present invention, in which a hydrophobic layer covers the side surfaces of the mesa and the bottom of the main surface of the substrate, but does not cover the top surface of the mesa. [Figure 7] 1 is a schematic representation of a cross-sectional view of a portion of one embodiment of a receiving wafer according to the present invention and a microelectronic die positioned toward a surface of the receiving wafer, the microelectronic die intended to be assembled to the receiving wafer by hybrid bonding, substantially corresponding to FIG. 2 except further illustrating electrical interconnection levels of the receiving wafer and of the microelectronic die. DETAILED DESCRIPTION OF THE INVENTION

[0036] The drawings are given as examples and are not intended to limit the invention. They constitute a schematic representation of principles intended to facilitate understanding of the invention and are not necessarily to scale for practical application. In particular, the thicknesses of the different layers illustrated in the drawings do not represent reality.

[0037] Before commencing a detailed discussion of embodiments of the present invention, optional features, which can optionally be used in conjunction with or instead of each other, are described below.

[0038] According to one example, the dielectric material of which the second level of the provided substrate is made is primarily an oxide of the material of which the first level of the substrate is made.

[0039] Alternatively or complementary to the previous example, the main material of which the first level of the substrate and / or the second level of the substrate are made is selected from the group consisting of silicon, germanium, sapphire, and the like.

[0040] According to one example of the first aspect of the present invention, the photolithography step comprises the following sub-steps: a. depositing a solid layer of the sacrificial material, e.g., a photosensitive resin, on the exposed second level surface of the provided substrate; b. exposing said layer based on sacrificial material to optical radiation through a structured photolithography mask so as to define a negative or positive microstructuring of said layer based on sacrificial material, and then c. Chemically etching said layer based on sacrificial material so as to obtain a microstructuring of said layer based on sacrificial material.

[0041] Alternatively to the previous example, the formation of the sacrificial material-based layer comprises a screen printing step or an electron beam photolithography step.

[0042] According to another example of the first aspect of the present invention, the deposition of the hydrophobic layer can be configured so that the hydrophobic layer covers each protrusion made mainly of the dielectric material and each space between one and a plurality of the same protrusions made mainly of the dielectric material, and if necessary also covers the side edges of each solid region.

[0043] According to another example of the first aspect of the present invention, the layer based on sacrificial material may be formed to have a substantially constant thickness between 200 nm and 5 μm, preferably between 500 nm and 1.5 μm, and more preferably substantially equal to 800 nm.

[0044] According to another example of the first aspect of the present invention, the sacrificial material-based layer may be formed such that each solid region has at least one lateral dimension between 100 μm and 20,000 μm, preferably between 500 μm and 5,000 μm, more preferably substantially equal to 2,000 μm.

[0045] According to another example of the first aspect of the present invention, the layer based on sacrificial material can be formed such that two adjacent protrusions of one and the same plurality are spaced apart from each other by a distance between 100 nm and 1 μm, preferably between 200 nm and 800 nm, more preferably substantially equal to 500 nm.

[0046] According to another example of the first aspect of the invention, the etching is configured so that each protrusion based on said dielectric material has a height between 100 nm and 5 μm, preferably between 400 nm and 2.5 μm, more preferably substantially equal to 1 μm.

[0047] According to one example, each of the plurality of protrusions based on said dielectric material may be distributed in a matrix manner over the micro- or nanostructured area in question and / or may have an octagonal cross section with a characteristic size substantially equal to 500 nm and / or may be spaced apart from one another by a minimum distance substantially between 300 nm and 1 μm.

[0048] According to one example of the second aspect of the present invention, the wafer may further comprise a hydrophobic layer that covers each protrusion made primarily of the dielectric material and each space between one of the same plurality of protrusions made primarily of the dielectric material, and if necessary also covers the side edges of each solid region, but does not cover the at least one solid region.

[0049] According to another example of the second aspect of the present invention: a. each protrusion based on said dielectric material may have a height between 100 nm and 5 μm, preferably between 400 nm and 2.5 μm, more preferably substantially equal to 1 μm; and / or b. each protrusion based on said dielectric material may have at least one lateral dimension between 100 nm and 2 μm, preferably between 200 nm and 1 μm, more preferably substantially equal to 500 nm; and / or c. Two adjacent protrusions of one and the same plurality based on the dielectric material may be spaced apart from each other by a distance between 100 nm and 1 μm, preferably between 200 nm and 800 nm, more preferably substantially equal to 500 nm.

[0050] According to another example of the second aspect of the invention, the wafer may constitute a receiving wafer intended for the transfer of microelectronic components, such as microelectronic dies, by hybrid bonding, wherein each solid area is intended to receive a microelectronic component and each micro- or nanostructured area is intended to constitute at least one part of the area between the microelectronic components.

[0051] According to another example of the second aspect of the present invention, the second level of the substrate may comprise at least one electrical interconnection level extending at least over the surface of each solid region and, if necessary, from the solid region to an adjacent micro- or nanostructured region, the electrical interconnections being at the same height from the exposed surface of each solid region to the second level of the substrate and extending from each solid region to at least an adjacent micro- or nanostructured region, and more particularly extending under a plurality of protrusions made primarily of the dielectric material of said adjacent micro- or nanostructured region by being encapsulated in the dielectric material of which the second level of the substrate is composed.

[0052] By "hybrid bonding" it is meant bonding obtained between hybrid surfaces, i.e., between surfaces composed of several materials. In the case of 3D interconnects, these materials can be Cu (for electrical contact) and SiO2 (to insulate the contacts from each other). Hybrid bonding can be performed in wafer-to-wafer mode or in die-to-wafer mode.

[0053] By "protrusion having a faceted end" is meant a protrusion that appears in cross section to decrease from its base or from a non-zero distance to its end opposite its base. For example, the protrusion can have an ogive-shaped or pinhead-shaped end.

[0054] By "micro- or nanostructured region" is meant a region having elements that are microstructured, i.e. that are distinguished by their characteristic micro- or nanometer size. It is primarily a matter of regions having a micro- or nanostructured surface in this case.

[0055] By "solid region" is meant in this sense a region defined in opposition to a micro- or nanostructured region, such as a region having a smooth (or flat) surface whose roughness is much smaller, for example by at least an order of magnitude, than the roughness associated with the microstructuring of the surface of the micro- or nanostructured region. For example, a solid region has a surface roughness of less than 0.3 nm.

[0056] By "membrane based on material A" this means a membrane comprising this material A and optionally other materials.

[0057] By a parameter "substantially equal to / greater than / less than" this means that this parameter is equal to / greater than / less than the given value, plus or minus 20% or even 10% of this value. By a parameter "substantially between (two given values)" this means that this parameter is minimum equal to the lowest given value, plus or minus 20% or even 10% of this value, and maximum equal to the maximum given value, plus or minus 20% or even 10% of this value.

[0058] 2, a first aspect of the present invention relates to a method for manufacturing a wafer 1 comprising a main surface 10 having at least one solid region 101 and one micro- or nano-structured region 102, hereinafter referred to as "structured region 102", which have a wettability contrast between them, defined as the difference between the drop angle α associated with the solid region 101 and the drop angle β associated with the structured region 102, that is greater than 90°, preferably greater than 120°. Moreover, each structured region 102 extends around the solid region 101.

[0059] This adoption makes it possible to define not only wafers and their manufacturing methods intended to receive by transfer microelectronic components 2, such as microelectronic dies, for hybrid bonding to these wafers, but also any other type of application, in particular any type of application that requires high wettability contrast on the micrometer scale.

[0060] Therefore, although the present invention will be described hereinafter in the scope of its main application, namely for the self-assembly of microelectronic components 2 on a wafer 1 by die-to-wafer hybrid bonding, the present invention is nevertheless not limited to this application.

[0061] One embodiment of a manufacturing method according to the first aspect of the present invention is described below with reference to Figures 3A-3E.

[0062] The first step of the method consists of providing a substrate 11 comprising a first level 111 based on a semiconductor material and a second level 112 based on a dielectric material, the second level 112 extending over the first level 111 so that the second level 112 has an exposed surface 1121. In the illustrated example, the semiconductor material based on which the first level 111 is made is silicon, and the dielectric material based on which the second level 112 is made is silicon oxide. However, the dielectric material based on which the second level of the substrate is made is not necessarily an oxide of the material based on which the first level of the substrate is made. Furthermore, semiconductor materials other than silicon are conceivable, for example, which can be structured by photolithography and dry etching techniques potentially involved in the implementation of the method according to the first aspect of the invention, as is typically the case for germanium, sapphire, etc. It is noted that in this case the second level 112 of the substrate 11 has a thickness e of less than 10 μm, which thickness e will still be greater than the height of the protrusions 131 based on dielectric material that can be produced on the surface of the substrate 11 by the method, which will also be greater than the height of the protrusions 131, if necessary, and of the electrical interconnect level 110 (see FIG. 7) that will be embedded in the dielectric material of the second level 112. The dielectric protrusions 131 can in fact be intended to be formed on top of the second level 112 of the substrate 11, which does not have any electrical interconnects, so that their formation makes it possible to preserve the integrity of said electrical interconnects, if present.

[0063] With reference to FIG. 3B, the method according to the first embodiment of the present invention further comprises forming a layer 12 based on a sacrificial material, hereinafter referred to as "sacrificial layer 12," on the exposed surface 1121 of the second level 112 of the substrate 11. The sacrificial material can be a resin, more particularly a photosensitive, thermosetting, or electrosensitive resin (in the case of electron photolithography). The sacrificial layer 12 is formed to have a first region 1201 spanning a solid layer 121 based on the sacrificial material, and a second region 1202 spanning a plurality of micrometer or nanometer protrusions 122 based on the sacrificial material, hereinafter referred to as "sacrificial protrusions 122." While the second regions 1202 are shown on either side of the first region 1201 in FIG. 3B, FIG. 3B illustrates a cross-sectional view, and each first region 1201 is actually surrounded by a second region 1202.

[0064] 4A provides a top view of one embodiment of a wafer 1 according to the second aspect of the invention, in which it is clear that each solid area 101 is in fact surrounded by a structured area 102, presenting a corresponding distribution of each first area 1201 and of the surrounding second areas 1202. It is noted in this case that FIG. 4A also makes it possible to illustrate that the receiving surface of the microelectronic components 2 is not necessarily circular or square, but can accommodate shape variations, although it is understood that perhaps the greater the shape ratio of this receiving surface, the greater the risk of obtaining an inaccurate alignment of the microelectronic components 2 on the receiving surface.

[0065] Furthermore, each first region 1201 extends over a surface larger than the micrometer or nanometer surface over which each sacrificial protrusion 122 extends. Preferably, the surface of each first region 1201 is at least one order of magnitude larger than the surface over which each sacrificial protrusion 122 extends. In this case, it is noted that in the example provided by FIG. 3B, all sacrificial protrusions 122 have the same dimensions and are regularly spaced apart, but any variation of this matrix arrangement is conceivable as long as it allows the production of a wafer 1 according to the second embodiment of the present invention. In particular, it is conceivable for the sacrificial layer 12 to follow a design that will ultimately allow a density gradient of dielectric protrusions 131 on the surface of the structured region 102 and a wettability gradient between the bonding surfaces.

[0066] As will be seen below, the surface extending over each first region 1201 is intended to form the receiving surface of a microelectronic component 2, the dimensions of which are therefore mainly limited by the dimensions of said microelectronic component 2 or by those of the mesas formed on the surface of said microelectronic component 2 which define the transfer surface of said component on the wafer 1. In this sense, the sacrificial layer 12 can be formed such that each solid region 101 has at least one lateral dimension between 100 μm and 20,000 μm, preferably between 500 μm and 5,000 μm, and even more preferably substantially equal to 2,000 μm.

[0067] The dimensions of the sacrificial protrusions 122 are themselves limited by the desired objective to be reached in terms of wettability contrast between the solid areas 101 and the structured areas 102 of the main surface 10 of the wafer 1. The sacrificial protrusions 122 in fact have dimensions that predetermine the dimensions of the protrusions 131 made from a dielectric material, hereinafter referred to as "dielectric protrusions 131", which will be described below, and the dimensions of the spaces separating these dielectric protrusions 131 from one another, which dimensions define the drop angle β on the microstructured surface that the dielectric protrusions 131 cause and therefore influence the wettability contrast that the manufactured wafer 1 will have.

[0068] The dimensions of the dielectric protrusions 131 and the spaces separating them from each other are preferably: a. each sacrificial protrusion 122 has at least one lateral dimension between 100 nm and 2 μm, preferably between 200 nm and 1 μm, more preferably substantially equal to 500 nm; and / or b. one and the same plurality of sacrificial protrusions 122, each adjacent to the other, are spaced apart from each other by a distance between 100 nm and 1 μm, preferably between 200 nm and 800 nm, more preferably substantially equal to 500 nm.

[0069] Furthermore, the sacrificial layer 12 is preferably formed to have a substantially constant thickness between 200 nm and 5 μm, preferably between 500 nm and 1.5 μm, and more preferably substantially equal to 800 nm. As will be seen below, the thickness of the sacrificial layer 12, together with its nature and the etching method implemented, determines the height of the dielectric protrusions 131 and therefore influences the wettability contrast that will be obtained.

[0070] The manufacturing method according to the first aspect of the present invention is not, however, limited to the case where it is preferred that the sacrificial layer 12 has a substantially constant thickness between different solid 101 or structured 102 regions. For example, the sacrificial layer 12 can be formed such that the thickness of the sacrificial layer 12 in each solid region 101 is greater than the height of the sacrificial protrusions 122, for example, so that the over-etching described below can be further carried out without consuming all of the sacrificial material present in each solid region 101 before the over-etching.

[0071] According to a preferred embodiment of the manufacturing method according to the first aspect of the present invention, the formation of the sacrificial layer 12 comprises a controlled and widely adjustable photolithography step, i.e. a standard microelectronic step. Nevertheless, it is specified that such a photolithography step may comprise the following sub-steps: a. depositing a solid layer based on said sacrificial material on the exposed surface 1121 of the second level 112 of the provided substrate 11; b. exposing said sacrificial material-based layer to optical radiation through a photolithography mask structured to define a negative or positive of the desired microstructuring of said sacrificial material-based layer; and c. Chemical etching of said layer based on sacrificial material to obtain the desired microstructuring.

[0072] Alternatively, forming the sacrificial material-based layer comprises at least one screen printing step.

[0073] 3C, the method according to the first embodiment of the present invention further comprises etching a portion of the previously formed sacrificial layer 12 and a portion of the second level 112 of the substrate 11. The etching is more particularly such that a solid region 101 in each first region 1201 and a structured region 102 in each second region 1202 are formed in the second level 112 of the substrate 11, each structured region 102 having a plurality of dielectric protrusions 131 corresponding to the plurality of sacrificial protrusions 122 as described above, each dielectric protrusion 131 having a cross-section whose dimensions and shape correspond to those of the sacrificial protrusions 122. For example, with reference to FIGS. 4A and 4B, if the sacrificial protrusions 122 have an octagonal cross-section with a characteristic size A equal to 500 nm between two opposing edges and are spaced apart by a minimum distance B between 300 nm and 1 μm, the corresponding dielectric protrusions 131 will have the same octagonal cross-section and will be spaced apart by the same minimum distance. Other shapes are of course possible (circular, square, etc.).

[0074] The plurality of dielectric protrusions 131 extending from each structured region 102 imparts its superhydrophobicity to the exposed surface of the structured region 102 by creating the conditions for observing the lotus effect. However, the superhydrophobicity that the plurality of dielectric protrusions imparts to the exposed surface of each structured region 102 may be more or less apparent depending on how the etching is performed.

[0075] In the field of microelectronics, a standard implementation of such etching involves exposure to an etching plasma or to ion etching, aiming at the formation of pillars as illustrated in FIG. 5A. These pillars each have a substantially constant cross section from their base to their apex, as can be seen in the dielectric protrusions 131. However, to increase the wettability contrast between the solid region 101 and the surrounding structured region 102, it is preferable for the dielectric protrusions 131 to have a cross section that evolves by decreasing from their base or from a non-zero distance thereto to their apex. For example, it is preferable for each dielectric protrusion 131 to have an ogive-shaped or pinhead-shaped end, as illustrated in FIG. 5B. To achieve this advantageous shape of the dielectric protrusions 131, the etching can simply be continued beyond that performed in the standard manner until lift-off of the sacrificial protrusions 122 is obtained, which can therefore be referred to as over-etching, as already mentioned above. In this way, an etching step that is sufficiently advanced, more particularly advanced beyond the standard (which only provides partial consumption of the sacrificial material) so that the sacrificial material constituting the sacrificial protrusions 122 is completely consumed by mere etching, makes it possible to obtain sharp-headed dielectric protrusions 131 as illustrated in FIG. 5B, which is advantageously increased relative to what would give flat-headed dielectric protrusions in the structured regions 102, with a drop angle substantially equal to 160°, as illustrated in FIG. 5A.

[0076] A difference of at least one order of magnitude between the lateral dimensions of the solid layer 121 and those of each sacrificial protrusion 122 allows this to occur. Indeed, it is observed that the sacrificial material is consumed more rapidly during etching in the narrower patterns constituted by the sacrificial protrusions 122, and not in the largest patterns constituted by the solid layer 121. Consequently, over-etching leaves a solid layer 121' with a smaller thickness than the solid layer 121 on top of the solid region 101, as illustrated in FIG. 3C. This observation can be explained by the faceting phenomenon. This phenomenon conveys the fact that during etching, the lateral consumption of these materials is added to the consumption from above of the sacrificial material and of the main dielectric material of which the second level 112 of the substrate 11 is composed; furthermore, the lateral consumption is increased in smaller patterns relative to larger patterns when the same etching is applied to them. It should be noted that in FIG. 3C, the effect of the faceting phenomenon on the shape of the formed dielectric protrusions 131 is diagrammatically illustrated by illustrating each protrusion in the form of a conical cross-section.

[0077] However, extension of etching beyond the standard is preferably exceptionally limited and for at least the two reasons given below.

[0078] The first of these two reasons is that it is actually advantageous for the etching to be stopped before obtaining a lift-off of the sacrificial material on the surface of each first region 1201. In this way, at the end of the etching, and more particularly at the end of the over-etching, a thickness of sacrificial material remains on the surface of each first region 1201, this thickness being preferably between 100 nm and 5 μm.

[0079] The second of the two reasons for not extending the etching beyond obtaining lift-off of the sacrificial material 12 on the surface of each second region 1202 is that the dimensions of the dielectric protrusions 131, in particular their height, are reduced; furthermore, it is preferred that the etching be configured so that each dielectric protrusion 131 has a height between 100 nm and 5 μm, preferably between 400 nm and 2.5 μm, and more preferably substantially equal to 1 μm.

[0080] With reference to FIG. 3D, the method according to the first embodiment of the present invention can further include, following etching, the deposition of a layer 14 based on a hydrophobic material, preferably a conformal layer, hereinafter referred to as "hydrophobic layer 14." For example, the hydrophobic material of which hydrophobic layer 14 is composed is preferably based on at least one polymer. It can consist, for example, of 0.1% by weight of a fluorosilane polymer in a hydrofluoroether carrier solvent. For example, this can be a coating known under the trade name 3M™ Novec™ 1720 Electronic Grade Ultra Fine. Any material known for its hydrophobic properties can be considered in the context of the present invention, and the examples listed above are not limiting. For example, the deposition of the hydrophobic layer can include a spin-coating step or a plasma deposition step. Naturally, hydrophobic layer 14 can advantageously contribute to increasing the wettability contrast between solid regions 101 and structured regions 102.

[0081] 6A and 6B, the deposition of the hydrophobic layer 14 is preferably configured so that it covers each dielectric protrusion 131 and each space 132 between the dielectric protrusions 131 or between the dielectric protrusions and the mesas 15 formed by the solid regions, and, if necessary, also covers the side edges 1011 of said mesas 15. It is noted that in this case, if it is interesting to push the etching until all the sacrificial material on the surface of the second regions 1202 is consumed in order to obtain faceted dielectric protrusions 131, such over-etching also appears interesting in that it allows the deposition of the hydrophobic layer 14 on and between the dielectric protrusions 131 without requiring a step of removing the sacrificial material that would otherwise remain on the surface of the second regions 1202. Furthermore, although it is preferred that the etching not involve all of the sacrificial material formed on the surface of the first region 1201, the deposition of the hydrophobic layer 14 will in this case also result in covering the sacrificial material remaining on the surface of the first region 1201, at least on its top surface and potentially on its sides, a situation which is illustrated in Figure 3D.

[0082] 3E, the method according to the first aspect of the invention can further comprise, preferably following the deposition of the hydrophobic layer 14, a step of removing the sacrificial layer 12, more particularly, the portions of the sacrificial layer 12 that remained on the surface of the first regions 1201 after etching, from the possible remainder. This removal makes it possible to expose the surface 1000 of the second level 112 of the substrate 11 located on the surface of each first region 1201. It is noted in this case that this surface 1000 is also illustrated in FIGS. 2 and 7. Therefore, in view of FIGS. 3D and 3E, it can be seen that proceeding with the deposition of the hydrophobic layer 14 before the removal of the remainder of the sacrificial layer 12 after etching simultaneously makes it possible to remove the hydrophobic layer 14 covering the remainder of the sacrificial layer 12 after etching, in particular in the solid regions 101. Subsequently, insofar as the main material of which the second level 112 of the substrate 11 is composed is hydrophilic, in particular in the case of silicon oxide, the wettability contrast between the solid regions 101 and the structured regions 102 is advantageously significantly increased. It is noted that the droplet angle α of water on such silicon oxide-based hydrophilic surfaces is typically less than 10°.

[0083] It will be noted that the wafer as illustrated in Figure 3E corresponds to the wafer as illustrated in Figure 2. In other words, from the method steps depicted in Figure 3E, a wafer 1 has been produced, suitable for the self-assembly of microelectronic components 2 on the wafer 1 by die-to-wafer hybrid bonding.

[0084] FIG. 7 illustrates a more specific case, not excluded from the above considerations, in which the second level 112 of the substrate 11 comprises at least one electrical interconnection level 110 extending from the solid region 101 to the structured region 102. More specifically, the electrical interconnections are embedded or equivalently encapsulated in the dielectric material of which the second level 112 of the substrate 11 is composed. The electrical interconnections are flush with the second level 112 of the substrate 11 from the exposed surface 1000 of each solid region 101 to allow electrical reconnection with the microelectronic components 2 on the solid region 101 that are intended to be removed. Conversely, the electrical interconnections are embedded or equivalently encapsulated in the dielectric material of which the second level 112 of the substrate 11 is composed, in each structured region 102. The depth to which these interconnections are embedded determines the thickness of the second level 112 of the substrate 11 that can be dedicated to the formation of dielectric protrusions 131, if etching is required not to alter the integrity of the embedded interconnections. The manufacturing method according to the first aspect of the invention is thus shown to be compatible with self-organizing processes leading to the transfer of microelectronic components electrically connected to one another via the receiving wafer 1, with the electrical interconnection level extending from the solid area 101 to the adjacent structured area 102 and beyond. Preserving the integrity of the electrical interconnection actually presupposes that the electrical interconnection is stopped before it is reached by etching. Thus, during the manufacture of the substrate 11 as provided, it is possible to provide that the electrical interconnection level, at the level intended to form the structured area 102, is covered by a sufficiently thick layer of dielectric material, so that dielectric protrusions 131 of the desired geometry can be etched into this layer, without the need to etch the electrical interconnections. Furthermore, it will be noted that the height of the dielectric protrusions 131 obtained by implementing the method according to the first aspect of the invention is substantially equal to the height of the mesas 15 obtained by this same implementation.With respect to the incoming wafer known from the prior art, for example with respect to the wafer according to the example given in FIG. 1, the mesas 15 obtained by implementing the method according to the first aspect of the invention are advantageously reduced, even if this reduction does not increase the wettability contrast between the solid area 101 and the structured area 102 surrounding it. a. it facilitates industrial integration of the method according to the first aspect of the invention; b. The micro-roughness imparted to the structured area 102 by the micro-structuring obtained by implementing the method according to the first aspect of the present invention makes it possible to largely compensate for any possible performance degradation in terms of self-alignment that would result from this.

[0085] The manufacturing method according to the first aspect of the invention therefore enables the production of a wafer 1 according to the second aspect of the invention, more particularly a receiving wafer 1 intended for the transfer of microelectronic components 2 by hybrid bonding, each solid area 101 intended to receive a microelectronic component 2 and each structured area 102 intended to constitute at least one part of the area between the microelectronic components 2.

[0086] More specifically, such a wafer 1 comprises a main surface 10 having at least one solid region 101 and one structured region 102 having a wettability contrast between them of greater than 90°, preferably greater than 120°, each micro- or nano-structured region 102 extending around the solid region 101; the wafer comprises a substrate 11 having a first level 111 mainly made of a semiconductor material and a second level 112 mainly made of a dielectric material, the second level 112 extending over the first level 111; the at least one solid region 101 and each structured region 102 are formed on the second level 112 of the substrate 11; and each micro- or nano-structured region 102 has a plurality of protrusions 131 mainly made of the dielectric material.

[0087] And if the etching is an over-etch that consumes all the sacrificial material formed on the surface of each second region 1202, the dielectric protrusion 131 of the wafer 1 has a facet edge 1311, for example, as illustrated in FIG. 5B, so as to obtain a wettability contrast that is further increased and easily brought to values ​​greater than 120°, or even greater than 140°.

[0088] More specifically, the wafer 1 according to the second aspect of the present invention is a. each dielectric protrusion 131 has a height between 100 nm and 5 μm, preferably between 400 nm and 2.5 μm, more preferably substantially equal to 1 μm; and / or b. each dielectric protrusion 131 has at least one lateral dimension between 100 nm and 2 μm, preferably between 200 nm and 1 μm, more preferably substantially equal to 500 nm; and / or c. two adjacent dielectric protrusions 131 of one and the same plurality are spaced apart by a distance between 100 nm and 1 μm, preferably between 200 nm and 800 nm, more preferably substantially equal to 500 nm; The dielectric protrusions 131 may be such that the spaces 132 between these protrusions are also covered or not covered by the hydrophobic coating 14 so as to impart superhydrophobicity to the surface of the structured area 102 .

[0089] According to a third aspect, the present invention also relates to a self-assembly method for implementing a receiving wafer 1 according to the second aspect of the invention, and to an assembly 0 obtained by implementing the self-assembly method according to the third aspect of the invention.

[0090] According to the present invention, a. It may be sufficient to add one single photolithography level to the substrate 11 as provided to make it most suitable for self-assembly, and / or b. The etching step that allows to create micro-roughness is a standard, fully controlled microelectronic step, does not generate defects or particles, is very easy to integrate into the method for producing dies, uses the same type of equipment as the previous steps of said production method, and / or c. The shape, size and density of the dielectric protrusions 131 produced are fully controllable, since they correspond to the pattern written in the additional photolithography level. Similarly, the distance between the receiving area (hydrophilic area) and the inter-die area (superhydrophobic area) of the die 2 is adjustable, since it is also determined by the design of the sacrificial layer 12, which is not the case with black silicon, which made it possible to obtain the scientific paper mentioned in the introduction, and / or d. It is not necessary to remove all of the insulating and metallic material that makes up the electrical interconnects 110, which can be quite abundant in the inter-die area and, given their variety, difficult to remove by etching; and / or e. It will be appreciated that the creation of very large mesas 15 on the surface of the die and of the receiving wafer 1 is avoided, which mesas are nevertheless obtained in a manner that contributes to achieving a high wettability contrast between the solid regions 101 and the structured regions 102.

[0091] The invention is not limited to the embodiments described above, but extends to all embodiments encompassed by the claims. [Explanation of symbols]

[0092] 0 Assembly 1 wafer 2. Microelectronic Components 10 Main Surface 11 Circuit Board 12 Sacrificial Layer 14 Hydrophobic layer 15 Mesa 101 Solid Region 102 Structured area 110 Electrical Interconnect Level 111 First Level 112 Second Level 121 Solid Layer 121' solid layer 122 Sacrificial protrusion 131 Dielectric protrusion 132 Space 1000 exposed surface 1011 Side edge 1121 Exposed surface 1201 First Area 1202 Second Area 1311 Facet Edge

Claims

1. 1. A method for manufacturing a wafer (1) comprising a main surface (10) having at least one solid region (101) and one micro- or nanostructured region (102) with a wettability contrast between them of greater than 90°, preferably greater than 120°, each micro- or nanostructured region (102) extending around the solid region (101), said method comprising the following steps: providing a substrate (11) comprising a first level (111) mainly composed of a semiconductor material and a second level (112) mainly composed of a dielectric material, said second level (112) extending over said first level (111); forming, on the exposed surface (1121) of the second level (112) of the provided substrate (11), a layer (12) based on a sacrificial material, such as a resin, having at least one first area (1201) over which a solid layer (121) based on the sacrificial material extends, and a second area (1202) over which a plurality of micrometer or nanometer protrusions (122) based on the sacrificial material extend, each first area (1201) being surrounded by a second area (1202) and each first area (1201) extending over a surface that is at least one order of magnitude larger than the micrometer or nanometer surface over which each protrusion (122) based on the sacrificial material extends; a portion of the previously formed layer (12) based on sacrificial material and a portion of the second level (112) of the substrate (11); forming, in the second level (112) of the substrate (11), the at least one solid region (101) in each first region (1201) and a respective micro- or nanostructured region (102) in each second region (1202), each micro- or nanostructured region (102) having a plurality of protrusions (131) based on the dielectric material corresponding to the plurality of protrusions (122) based on the sacrificial material; Etching; A method comprising:

2. 2. The method of claim 1, wherein the etching comprises over-etching the protrusions (122) leading to lift-off of the protrusions (122) based on the sacrificial material.

3. The method of claim 1, wherein forming the layer (12) based on the sacrificial material comprises a photolithography step.

4. 2. The method of claim 1, wherein the etching is stopped before obtaining lift-off of the layer (12) based on the sacrificial material on the surface of each first region (1201), and the layer (12) based on the sacrificial material remains on the surface of each first region (1201), preferably with a thickness between 100 nm and 5 μm.

5. 2. The method of claim 1, further comprising, following said etching, depositing a layer (14) based on a hydrophobic material, preferably Conform.

6. 6. The method according to claim 5, wherein the deposition of the hydrophobic layer (14) is configured so that the hydrophobic layer (14) covers each protrusion (131) made mainly of the dielectric material and each space (132) between the same plurality of protrusions (131) made mainly of the dielectric material, and also covers the side edges (1011) of each solid region (101) if necessary.

7. 2. The method of claim 1, further comprising removing a portion of the layer (12) mainly composed of the sacrificial material that remains on the surface of the first regions (1201) after the etching, so as to expose a surface (1000) of the second level (112) of the substrate (11) located on the surface of each first region (1201).

8. The method according to claim 5 or 6 and claim 7, wherein the deposition of the hydrophobic layer (14) is implemented before lift-off of the portion of the layer (12) based on the sacrificial material that remains on the surface of the first region (1201) after the etching.

9. 2. The method according to claim 1, wherein the wafer (1) constitutes a receiving wafer intended for the transfer of microelectronic components (2), such as microelectronic dies, by hybrid bonding, each solid area (101) being intended to receive a microelectronic component (2) and each micro- or nanostructured area (102) being intended to constitute at least one part of the area between the microelectronic components (2).

10. 2. The method of claim 1, wherein the layer (12) based on the sacrificial material is formed such that the protrusions (122, 131) have at least one lateral dimension between 100 nm and 2 μm, preferably between 200 nm and 1 μm, more preferably substantially equal to 500 nm.

11. 2. The method according to claim 1, wherein the layer (12) based on the sacrificial material is formed such that two adjacent protrusions (122, 131) of one and the same plurality are spaced apart from each other by a distance between 100 nm and 1 μm, preferably between 200 nm and 800 nm, more preferably substantially equal to 500 nm.

12. 2. The method of claim 1, wherein the etching is configured so that each protrusion (131) based on the dielectric material has a height between 100 nm and 5 μm, preferably between 400 nm and 2.5 μm, and more preferably substantially equal to 1 μm.

13. A wafer (1) comprising a main surface (10) with at least one solid region (101) and one micro- or nanostructured region (102) having a wettability contrast between them of greater than 90°, preferably greater than 120°, each micro- or nanostructured region (102) extending around the solid region (101), said wafer comprising a substrate (11) comprising a first level (111) mainly composed of a semiconductor material and a second level (112) mainly composed of a dielectric material, 1. A wafer (1), characterized in that the second level (112) extends over the first level (111), the at least one solid region (101) and each micro- or nanostructured region (102) are formed in the second level (112) of the substrate (11), each micro- or nanostructured region (102) having a plurality of protrusions (131) mainly composed of the dielectric material, and the wafer is characterized in that the protrusions (131) mainly composed of the dielectric material have faceted ends (1311).

14. 14. The wafer (1) according to claim 13, further comprising a hydrophobic layer (14) that covers each protrusion (131) made primarily of the dielectric material and each space (132) between the protrusions (131) made primarily of one of the same plurality of dielectric material, and also covers the side edges (1011) of each solid region (101) if necessary, but does not cover the at least one solid region (101).

15. each protrusion (131) based on said dielectric material has a height between 100 nm and 5 μm, preferably between 400 nm and 2.5 μm, more preferably substantially equal to 1 μm; and / or each protrusion (131) based on said dielectric material has at least one lateral dimension between 100 nm and 2 μm, preferably between 200 nm and 1 μm, more preferably substantially equal to 500 nm; and / or 14. The wafer (1) according to claim 13, wherein two of the same adjacent protrusions (131) made mainly of the dielectric material are spaced apart from each other by a distance between 100 nm and 1 μm, preferably between 200 nm and 800 nm, more preferably substantially equal to 500 nm.

16. 14. The wafer (1) according to claim 13, constituting a receiving wafer intended for the transfer of microelectronic components (2), such as microelectronic dies, by hybrid bonding, wherein each solid area (101) is intended to receive a microelectronic component (2) and each micro- or nanostructured area (102) is intended to constitute at least one part of the area between the microelectronic components (2).

17. 17. The wafer (1) of claim 16, wherein the second level (112) of the substrate (11) comprises at least one electrical interconnection level (110) extending at least over the surface of each solid region (101) and, if necessary, from a solid region (101) to an adjacent micro- or nanostructured region (102), wherein the electrical interconnections (100) are flush with the exposed surface (1000) of each solid region (101) and extend from each solid region (101) to at least the adjacent micro- or nanostructured region (102), and more particularly extend under the plurality of protrusions (131) mainly composed of the dielectric material of the adjacent micro- or nanostructured region (102) by being encapsulated in the dielectric material of which the second level (112) of the substrate (11) is mainly composed.

18. A method for the self-assembly of microelectronic components mounting a wafer (1) according to any one of claims 13 to 17.

19. 20. The self-assembly method of claim 18, wherein a plurality of microelectronic components (2), such as microelectronic dies, are self-assembled onto the wafer (1) by die-to-wafer hybrid bonding.

20. 18. An assembly (0) comprising a wafer (1) according to any one of claims 13 to 17 and a plurality of microelectronic components (2), such as microelectronic dies, assembled to the wafer (1) by hybrid bonding.

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