Package Structure

Abstract

A package structure is provided that includes an illuminant epitaxial structure, a light-receiving structure, a first conductive structure, a second conductive structure, and a third conductive structure. The illuminant epitaxial structure includes an upper distributed Bragg reflector, an active structure, and a lower distributed Bragg reflector, which are stacked in order. The light-receiving structure is located below the active structure and in contact with the illuminant epitaxial structure. The first conductive structure contacts the upper distributed Bragg reflector and extends to cover the lower surface of the light-receiving structure, the second conductive structure contacts the light-receiving structure at its lower surface, and the third conductive structure contacts the upper surface of the lower distributed Bragg reflector and extends to cover the lower surface opposite the upper surface. The first conductive structure is insulated from the second conductive structure, and the first conductive structure is insulated from the third conductive structure, and the second conductive structure is insulated from the third conductive structure.

Description

[Technical Field]

[0001] The present application relates to a packaging structure, and more particularly to a packaging structure for an optoelectronic device. [Background technology]

[0002] Vertical-cavity surface-emitting lasers (VCSELs) are a type of semiconductor laser device. Due to the structural advantage of emitting light from the epitaxial surface, and the emergence of various application needs and market demand in IoT products, smart electronics products, and smart sensing products, VCSEL devices are gradually expanding from the network communication market to various smart products, such as optical communication light source modules, proximity sensors in smart tablet phones and smart headphones, depth / distance / 3D sensors, lidar sensors for advanced driver assistance systems, light sources or panels for microprojection displays, eye trackers for interactive devices, and photonic integrated circuits.

[0003] In most of the current application products mentioned above, due to various requirements in product development and product use (e.g., low cost, light weight and portability, miniaturization, high integration and compatibility with other elements, reliability in harsh environments in automotive applications, long product life, low power consumption and long usage time, high-frequency electrical drive operation, etc.), more and more VCSEL devices are adopting flip-chip packaging technology to meet the above requirements. Summary of the Invention

[0004] In view of the above, the present application provides various embodiments of package structures.

[0005] In some embodiments, a package structure is provided that includes an illuminant epitaxial structure, a light-receiving structure, a first conductive structure, a second conductive structure, and a third conductive structure. The illuminant epitaxial structure includes an upper distributed Bragg reflector (DBR), an active structure, and a lower DBR, which are stacked in this order. The light-receiving structure is located below the active structure and in contact with the illuminant epitaxial structure. The first conductive structure contacts the upper DBR and extends to cover a lower surface of the light-receiving structure. The second conductive structure contacts the light-receiving structure at its lower surface. The third conductive structure contacts an upper surface of the lower DBR and extends to cover a lower surface opposite the upper surface. The first conductive structure is insulated from the second conductive structure, and the first conductive structure is insulated from the third conductive structure, and the second conductive structure is insulated from the third conductive structure.

[0006] In some embodiments, the upper DBR comprises a P-type semiconductor structure and the lower DBR comprises an N-type semiconductor structure.

[0007] In some embodiments, the first conductive structure is a P electrode of an illuminant epitaxial structure.

[0008] In some embodiments, the second conductive structure is an N-electrode of a light-receiving structure.

[0009] In some embodiments, the third conductive structure is a common electrode for the light-emitting epitaxial structure and the light-receiving structure.

[0010] In some embodiments, the light receiving structure is integrally formed as part of the lower DBR.

[0011] In some embodiments, the package structure further includes a transparent base layer that is bonded to the luminescent epitaxial structure via a first adhesive layer, and the transparent base layer and the first adhesive layer are transparent to light emitted from the self-luminescent epitaxial structure.

[0012] In some embodiments, the light-receiving structure is adhered to the lower DBR via a second adhesive layer.

[0013] In some embodiments, the second adhesive layer is electrically conductive.

[0014] In some embodiments, the packaging structure further includes another DBR located below the light-receiving structure.

[0015] In some embodiments, a method for singularizing an epitaxial wafer is provided. The epitaxial wafer includes a semiconductor laminate layer and a base layer, the semiconductor laminate layer being located on an upper surface of the base layer, and the base layer can be made of sapphire, glass, or a III-V compound. The method includes a processing step, a dicing step, and a cleaving step. Processing step: using a stealth dicing technique to process a portion of an internal region of the base layer from the upper surface of the epitaxial wafer to form a processing area in the portion of the internal region of the base layer, wherein the processing area includes at least one row of break points, the extension direction of the at least one row of break points is substantially parallel to the extension direction of the lower surface of the epitaxial wafer, and the distance between the processing area and the upper surface of the epitaxial wafer is 60 μm or less. Dicing step: using a laser lift-off technique or a wheel dicing technique to dice another portion of the base layer from the underside of the epitaxial wafer and form streets in the other portion of the base layer, where the streets have a dicing width and a dicing depth, the dicing width is less than 20 μm and the dicing depth is 30 μm. Cleavage step: applying a cleaving technique to the streets to cleave the epitaxial wafer into a plurality of semiconductor lasers.

[0016] In some embodiments, a method for singulating an epitaxial wafer is provided. The epitaxial wafer includes a semiconductor laminate layer and a base layer, the semiconductor laminate layer being located on an upper surface of the base layer, and the base layer can be made of sapphire, glass, or a III-V compound. The method includes a dicing step and a cleaving step. The dicing step: dicing a portion of the base layer from the lower surface of the epitaxial wafer using a laser lift-off technique or a wheel dicing technique to form streets in the portion of the base layer, the streets having a dicing width and a dicing depth, the dicing width being less than 10 μm, and the dicing depth being 90 μm or less. The cleaving step: cleaving the epitaxial wafer along the streets to cleave the epitaxial wafer into a plurality of semiconductor laser diodes.

[0017] In some embodiments, the stealth dicing technique is accomplished using a laser having a wavelength of 1064 nm.

[0018] In some embodiments, the III-V compound is GaAs, InP, or GaSb.

[0019] In some embodiments, a semiconductor laser is provided that includes a base layer, an epitaxial structure located on the base layer, an insulating layer, a first electrode, and a second electrode. The epitaxial structure includes an upper reflector, a lower reflector, and an active region located between the upper reflector and the lower reflector. The upper reflector, the active region, and the lower reflector are stacked on the base layer. The second electrode is located on the epitaxial structure and electrically connected to a semiconductor layer of the reflector. The first electrode is located on the base layer and electrically connected to a semiconductor layer of the upper reflector. The second electrode includes at least one metal layer and a P-type contact layer connected to a P-type semiconductor layer of the upper reflector, and the first electrode includes at least one metal layer connected to the base layer and electrically connected to an N-type semiconductor layer of the lower reflector. The insulating layer is located between the epitaxial structure and the second electrode and extends to a side of the epitaxial structure to prevent the second electrode from directly contacting the active region and the lower reflector. The sides of the base layer have at least one row of break points.

[0020] In some embodiments, the semiconductor laser may be a vertical-cavity surface-emitting laser with a vertical chip structure or a flip-chip vertical-cavity surface-emitting laser.

[0021] In some embodiments, a VCSEL chip is provided that includes a base layer, an epitaxial structure located on the base layer, an insulating layer, a first electrode, and a second electrode. The epitaxial structure includes an upper reflector, a lower reflector, and an active region located between the upper reflector and the lower reflector. The upper reflector, the active region, and the lower reflector are stacked on the base layer. The second electrode is located on the epitaxial structure and electrically connected to a semiconductor layer of the reflector. The first electrode is located on the base layer and electrically connected to a semiconductor layer of the upper reflector. The second electrode includes at least one metal layer and a P-type contact layer connected to a P-type semiconductor layer of the upper reflector, and the first electrode includes at least one metal layer connected to the base layer and electrically connected to an N-type semiconductor layer of the lower reflector. The insulating layer is located between the epitaxial structure and the second electrode and extends to the side of the epitaxial structure to prevent the second electrode from directly contacting the active region and the lower reflector.

[0022] In some embodiments, at least one region of the second electrode has at least one group of patterns to indicate a relative position of the VCSEL chip on the epitaxial wafer, and in some embodiments, the at least one region is at least one side or at least one corner of the second electrode.

[0023] In some other embodiments, at least one region of the insulating layer has at least one group of patterns to indicate the relative positions of the VCSEL chips in the epitaxial wafer, and in some embodiments, the at least one region is at least one side or at least one corner of the insulating layer.

[0024] Furthermore, in some embodiments, at least two of the insulating layer region and the second electrode region of the epitaxial structure each have at least 11 groups of patterns to indicate the relative positions of the VCSEL chips in the horizontal and vertical directions of the epitaxial wafer.

[0025] In some embodiments, a semiconductor laser chip is provided that includes a base layer and a semiconductor laminate layer formed on the base layer, the base layer having a step structure on an opposite side to the semiconductor laminate layer.

[0026] In some embodiments, the package structure of the photovoltaic unit further includes an upper electrode and a lower electrode, the upper electrode being formed on the semiconductor laminate layer of the VCSEL chip, the lower electrode being formed on the bottom surface of the semiconductor laminate layer of the VCSEL chip, the upper electrode being electrically connected to the first-type semiconductor layer of the semiconductor laminate layer, and the lower electrode being electrically connected to the second-type semiconductor layer of the semiconductor laminate layer via the base layer.

[0027] In some embodiments, a VSCEL chip is provided that includes a base layer, a semiconductor stack, a first electrode structure, a second electrode structure, and an insulating layer. The semiconductor stack is located on the base layer and has a first surface, a second surface, and a side surface. The second surface is located opposite the first surface, and the side surface is located between the first surface and the second surface. The semiconductor stack includes a first-type semiconductor layer, a second-type semiconductor layer, and an active layer. The active layer is located between the first-type semiconductor layer and the second-type semiconductor layer. The base layer is located on the opposite side of the second-type semiconductor layer from the first-type semiconductor layer. The base layer may be a growth substrate for the semiconductor stack, i.e., the semiconductor stack is grown directly on the base layer. The base layer is conductive and has a bottom and a boss portion extending from the bottom, the boss portion having a boss surface (connected to the second surface) and a boss side surface, and the boss side surface is connected to the boss surface. The bottom has a bottom first surface, a bottom second surface, and a bottom side surface. The bottom first surface is connected to the boss side surface, and the bottom second surface is located opposite the bottom first surface, with the bottom side surface being located between the bottom first surface and the bottom second surface. The insulating layer is located on the first surface and extends through the side surface, the boss surface, and the boss side surface to the bottom first surface. The insulating layer has an opening, the opening is located on the first surface, and the first electrode structure is located within the opening and contacts the first-type semiconductor layer. The first electrode structure is also located on the first surface and extends through the side surface, the boss surface, and the boss side surface to the bottom first surface. The insulating layer further extends through the bottom first surface to the bottom side surface. The second-type semiconductor layer in the semiconductor laminate layer further includes a platform portion extending laterally and distributed on the boss surface, with the insulating layer and the first electrode structure being located on the surface of the platform portion. The second electrode structure is located on the bottom second surface. Therefore, when the VSCEL chip is subsequently electrically bonded to the electrode pads on the carrier board, the first electrode structure extends to the side surface of the boss, so that the bonding area between the electrode structure on one side of the VSCEL chip and the bonding structure (e.g., solder paste) bonded between the electrode structure on one side of the VSCEL chip and the carrier board can be enlarged without increasing the size of the VSCEL chip. In this way, when the VSCEL chip is packaged, the chip size can be reduced while maintaining the gap between the electrode pads on the carrier board.

[0028] In some embodiments, an electro-optic module is provided that includes a driver chip, a light-emitting device, and a light-receiving device, wherein the driver chip is electrically connected to the light-emitting device and the light-receiving device.

[0029] In one or more embodiments, the light emitting device includes at least one semiconductor light source, such as a semiconductor laser, such as a VCSEL structure.

[0030] In one or more embodiments, the light receiving device includes at least one semiconductor sensor, such as a single-photon avalanche diode (SPAD).

[0031] In some embodiments, the photovoltaic module further includes a lens group mounted in the area of ​​the light receiving device.

[0032] In some embodiments, the photovoltaic module may be electrically connected to the circuit board by a ball grid array (BGA) structure. Specifically, in one embodiment, the photovoltaic module further includes a ball grid array structure located on the back surface of the driver chip (the side facing the light emitting device and the light receiving device) for electrically connecting to the circuit board.

[0033] In some embodiments, an electro-optic module is provided that includes a driver chip, a light-emitting device, and a passive component. The light-emitting device may be directly mounted to the driver chip, or the light-emitting device may be mounted on a carrier board, which may then be mounted to the driver chip. The driver chip provides an electrical signal, voltage, or current to drive the light-emitting device as a light source and is electrically connected to a printed circuit board via a ball grid array structure.

[0034] In some embodiments, an emission module is provided that integrates a light-emitting device, a passive element, a driver chip, and a carrier board. The light-emitting device, the passive element, and the driver chip are mounted on the carrier board. The light-emitting device, the passive element, and the driver chip may be mounted on the same side or different sides of the carrier board. The carrier board distributes power between these components (including the driver chip, the light-emitting device, and the passive element) through multiple through-holes and multiple metal layers and is electrically connected to a printed circuit board via a ball grid array structure. The driver chip provides an electrical signal, voltage, or current to drive the light-emitting device as a light source.

[0035] In some embodiments, a bottom fill adhesive may be included between the driver chip and the carrier board, the bottom fill adhesive covering the ball grid array structure.

[0036] In some embodiments, the photovoltaic module further includes a molding material and a metal line, the driver chip is electrically connected to the carrier board through the metal line, and the molding material covers the driver chip and the metal line.

[0037] In some embodiments, a light-emitting device is provided that includes a semiconductor layer, a transparent base layer, a spacer layer, a first pattern layer, and a covering layer, wherein the first pattern layer is formed on an upper surface of the spacer layer, and then the covering layer is formed on the first pattern layer.

[0038] In some embodiments, a light-emitting device is provided that includes a semiconductor layer, a transparent base layer, a spacer layer, a first pattern layer, a second pattern layer, and a cover layer. The first pattern layer is formed on the spacer layer. The second pattern layer is formed between the transparent base layer and the spacer layer.

[0039] In some embodiments, a light-emitting device is provided that includes a semiconductor layer, a transparent base layer, a spacer layer, a first pattern layer, a second pattern layer, a third pattern layer, and a cover layer. The first pattern layer is formed on the spacer layer. The second pattern layer is formed between the transparent base layer and the spacer layer. The third pattern layer is formed between the transparent base layer and the semiconductor layer.

[0040] In some embodiments, a light-emitting device is provided that includes a semiconductor layer, a first transparent base layer, a first pattern layer, and a covering layer, wherein the first transparent base layer is located on the semiconductor layer, the first pattern layer is formed on an upper surface of the first transparent base layer, and the covering layer is located on the first pattern layer.

[0041] In some embodiments, a light-emitting device is provided that includes a semiconductor layer, a first transparent base layer, a first pattern layer, a second pattern layer, and a covering layer, wherein the first transparent base layer is located on the semiconductor layer, the second pattern layer is formed between the first transparent base layer and the semiconductor layer, the first pattern layer is formed on an upper surface of the first transparent base layer, and the covering layer is located on the first pattern layer.

[0042] In some embodiments, a light-emitting device is provided, including a semiconductor layer, a first transparent base layer, a second transparent base layer, and a first pattern layer, wherein the first transparent base layer is located on the semiconductor layer, the first pattern layer is formed between two transparent base layers (the first transparent base layer and the second transparent base layer), and an adhesive layer may further be located on one side of the first pattern layer.

[0043] In some embodiments, the first pattern layer may be formed on the first transparent base layer or the second transparent base layer, and a separate adhesive layer may be further positioned between the first transparent base layer and the second transparent base layer.

[0044] In some embodiments, a light-emitting device is provided that includes a semiconductor layer, a first transparent base layer, an adhesive layer, a second transparent base layer, and a pattern layer, where the first transparent base layer is located on the semiconductor layer, the second transparent base layer is adhered onto the first transparent base layer using the adhesive layer, and the pattern layer is formed on the second transparent base layer.

[0045] In some embodiments, a light-emitting device is provided, including a semiconductor layer, a first transparent base layer, an adhesive layer, a second transparent base layer, a pattern layer, and a third transparent base layer, wherein the first transparent base layer is located on the semiconductor layer, the second transparent base layer is adhered onto the first transparent base layer using the adhesive layer, and the pattern layer is formed on the second transparent base layer, and the third transparent base layer covers the pattern layer. [Brief explanation of the drawings]

[0046] [Figure 1A] 1 is a cross-sectional view illustrating a package structure of an optoelectronic unit according to an embodiment; [Figure 1B] 1 is a cross-sectional view illustrating a package structure of an optoelectronic unit according to an embodiment; [Figure 1C] 1 is a cross-sectional view illustrating a package structure of a light-emitting sensing package according to an embodiment. [Figure 1D] 1 is a cross-sectional view illustrating a package structure of a light-emitting sensing package according to an embodiment. [Figure 2A] 1 is a cross-sectional view illustrating a package structure of an optoelectronic unit according to an embodiment; [Figure 2B] 1 is a cross-sectional view illustrating a package structure of a light-emitting sensing package according to an embodiment. [Figure 3A] 1 is a cross-sectional view illustrating a package structure of an optoelectronic device according to an embodiment; [Figure 3B] 1 is a cross-sectional view illustrating a package structure of an optoelectronic device according to an embodiment; [Figure 3C] 1 is a cross-sectional view illustrating a package structure of an optoelectronic device according to an embodiment; [Figure 4]4A-4D are top views illustrating packaging structures of optoelectronic devices according to some embodiments. [Figure 5] 1 is a cross-sectional view illustrating a package structure of an optoelectronic device according to an embodiment; [Figure 6] 1 is a schematic diagram illustrating an application of a packaging structure for an optoelectronic device according to an embodiment; [Figure 7] 7A to 7K are schematic cross-sectional views illustrating steps in a manufacturing process of an optoelectronic device packaging structure according to an embodiment. [Figure 8A] FIG. 1 is a top view of a portion of a VCSEL wafer imaged with an optical microscope. [Figure 8B] FIG. 1 is a top view of a portion of a VCSEL wafer imaged with an optical microscope. [Figure 9] 9A-9B are schematic diagrams illustrating the process of singulating the VCSEL dies from the front side of a thin VCSEL wafer using an ablation laser or a dicing machine. [Figure 10] 10A-10C are schematic diagrams illustrating dicing of multiple dies by a process method for singulating a thin VCSEL wafer, according to one embodiment. [Figure 11] 11A to 11D are schematic perspective views showing processing steps of an epitaxial wafer singulation method according to some embodiments. [Figure 12] 12A-12B are schematic diagrams illustrating dicing of multiple dies by a process method for singulating a thin VCSEL wafer according to one embodiment. [Figure 13A] 1 is a cross-sectional view of a VCSEL chip according to an embodiment of the present invention; [Figure 13B] This is a cross-sectional image of a VCSEL chip taken with an optical microscope. [Figure 13C] This is a cross-sectional image of a VCSEL chip taken with an optical microscope. [Figure 14A] FIG. 1 is a top view of a VCSEL chip according to an embodiment. [Figure 14B] FIG. 14B is a schematic cross-sectional view showing a cross section taken along line 14B-14B' in FIG. 14A. [Figure 15] 15A-15B are different schematic diagrams illustrating a VCSEL chip according to one or more embodiments. [Figure 15C] FIG. 1 is a top view of a VCSEL chip according to one or more embodiments. [Figure 15D] FIG. 1 is a top view of a VCSEL chip according to one or more embodiments. [Figure 16] FIG. 1 is a top view of a VCSEL chip according to an embodiment. [Figure 17] 17A-17F are cross-sectional schematic views illustrating steps in a manufacturing process for the VCSEL chip shown in FIG. 15B according to one embodiment. [Figure 18] 18A-18G are cross-sectional views illustrating steps in a manufacturing process for a VCSEL chip taken along line 16Z-16Z' of FIG. 16 according to one embodiment. [Figure 19A] 1 is a schematic diagram showing the bottom / backside of an epitaxial wafer for an optoelectronic device according to one embodiment. [Figure 19B] FIG. 19B is a schematic cross-sectional view showing a cross section taken along line 19X-19X′ in FIG. 19A. [Figure 19C] 19B is a cross-sectional schematic diagram of a semiconductor laser chip cut from the epitaxial wafer of the optoelectronic device shown in FIG. 19A according to one embodiment. [Figure 19D] FIG. 19D is a cross-sectional view showing the semiconductor laser chip of FIG. 19C welded to a carrier board. [Figure 20] FIG. 1 is a cross-sectional view showing a VCSEL chip mounted on a carrier board and welded to electrode pads of the carrier board. [Figure 21] 1 is a cross-sectional view illustrating a photoelectric module applicable as a Time of Flight (ToF) ranging module according to an embodiment; [Figure 22] 1 is a schematic cross-sectional view illustrating a radiation module according to an embodiment. [Figure 23A] 1 is a schematic cross-sectional view illustrating a radiation module according to an embodiment. [Figure 23B]1 is a schematic cross-sectional view illustrating a radiation module according to an embodiment. [Figure 24A] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment; [Figure 24B] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment; [Figure 24C] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment; [Figure 25A] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment; [Figure 25B] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment; [Figure 25C] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment; [Figure 25D] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment; [Figure 25E] 1 is a cross-sectional view illustrating a light emitting device according to an embodiment; [Figure 26] 1 is a cross-sectional view illustrating a laser element according to an embodiment. [Figure 27A] 1 is a cross-sectional view schematically illustrating a semiconductor light-emitting device according to an embodiment. [Figure 27B] FIG. 27B is a bottom view showing the laser device shown in FIG. 27A. [Figure 27C] FIG. 27B is a top view showing the laser device shown in FIG. 27A. [Figure 28] 1 is a cross-sectional view schematically illustrating a semiconductor light-emitting device according to an embodiment. [Figure 29] 1 is a cross-sectional view schematically illustrating a semiconductor light-emitting device according to an embodiment. [Figure 30] Figures 30A to 30E are respectively a top perspective schematic view, a bottom perspective schematic view, and a cross-sectional schematic view of a different cross section of a semiconductor light-emitting element to explain the configuration of the light-emitting area and common electrode structure of a semiconductor light-emitting element in one embodiment. [Figure 31] 1 is a cross-sectional view schematically illustrating a semiconductor light-emitting device according to an embodiment. [Figure 32]FIG. 32A is a schematic top see-through view of a semiconductor light emitting device according to one embodiment, and FIGS. 32B and 32C are schematic cross-sectional views taken along lines 32B-32B' and 32C-32C' in FIG. 32A, respectively. [Figure 33] 1 is a cross-sectional view schematically illustrating a semiconductor light-emitting device according to an embodiment. [Figure 34] 1 is a cross-sectional view illustrating a semiconductor laser device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0047] The concept of the present application will be described below with reference to the drawings and exemplary embodiments. In the drawings and the specification, similar or identical parts are designated by the same element symbols. Furthermore, the drawings are drawn for ease of understanding, and the thickness and shape of each layer in the drawings do not represent the actual dimensions or proportional relationships of the elements. It should be particularly noted that elements not shown in the drawings or described in the specification may have forms known to those skilled in the art.

[0048] In the following, various embodiments of the present application will be described in conjunction with the drawings to facilitate understanding of the present invention, which should be regarded as exemplary descriptions. In this specification, phrases such as "in one embodiment" are not intended to be limited to a specific embodiment or the same embodiment, and those skilled in the art will recognize that various modifications, combinations, or adjustments can be made to the embodiments of the present invention without departing from the scope and spirit of the present invention.

[0049] Terms such as "first," "second," and "third" used in this specification are intended to indicate and explain the characteristics of the corresponding embodiments, and do not necessarily have any significance in terms of order, hierarchy, or precedence (e.g., spatial position, temporal order, order of steps, etc.).

[0050] As used herein, the terms "upper," "lower," "left," "right," "front," "rear," "relatively lower," "relatively higher," "top," or "bottom" are intended to describe the relative spatial distribution of one element to another element (or one structure to another) in each drawing. If the structures shown in the drawings were turned upside down, it would be understood that elements described as being on the "lower," "below," or "relatively lower" side would become elements on the "upper," "above," or "relatively higher" side.

[0051] FIG. 1A is a cross-sectional view illustrating a packaging structure of an optoelectronic unit 2 according to an embodiment, which may function as a self-mixing interferometry (SMI) sensing unit.

[0052] FIG. 1B is a schematic cross-sectional view illustrating a packaging structure of the photovoltaic unit 2 according to an embodiment, in which the photovoltaic unit 2 shown in FIG. 1A is adhered to a transparent base layer 1100. As shown in FIG.

[0053] FIG. 1C is a cross-sectional schematic diagram showing the package structure of a light-emitting sensing package 2C according to one embodiment, which includes a plurality of photoelectric units 2 as shown in FIG. 1A adhered to a transparent base layer 1100, and the light-emitting sensing package 2C may function as a self-mixing interference sensing device.

[0054] FIG. 1D is a cross-sectional schematic diagram showing the package structure of a light-emitting sensing package 2D according to one embodiment, which includes a plurality of photoelectric units 2 as shown in FIG. 1A attached to a transparent base layer 1100, and the light-emitting sensing package 2D may function as a self-mixing interference sensing device.

[0055] 1A, the photovoltaic unit 2 includes a light-emitting structure and a light-receiving structure, and is a laminated structure 2000 including a semiconductor epitaxial structure, a conductive structure, and an insulating structure. The laminated structure 2000 has an upper surface 2000T and a lower surface 2000B opposite to the upper surface 2000T. In the embodiment shown in FIG. 1A, the laminated structure 2000 of the photovoltaic unit 2 may be formed by epitaxial growth.

[0056] 1A, the stacked structure 2000 includes a light-emitting epitaxial structure 2100 corresponding to the light-emitting structure of the optoelectronic unit 2. In this embodiment, the light-emitting epitaxial structure 2100 may be a vertical-cavity surface-emitting laser (VCSEL), which may be a stacked epitaxial structure including an upper distributed Bragg reflector (hereinafter referred to as DBR) 2100U, a lower DBR 2100L, and an active structure 2100A located between the upper DBR 2100U and the lower DBR 2100L.

[0057] 1A, the conductive structure 2100P contacts the upper DBR 2100U at the upper surface 2100UT of the upper DBR 2100U, and then the conductive structure 2100P continues to extend to cover a portion of the lower surface 2000B through a through-hole structure 2100V formed inside the laminate structure 2000. In this embodiment, the insulating structure 2100VI is formed between the conductive structure 2100P and the laminate structure 2000, and the insulating structure 2100VI is used to electrically isolate the conductive structure 2100P from the upper DBR 2100U and the active structure 2100A from the lower DBR 2100L.

[0058] 1A, the upper DBR 2100U includes a P-type semiconductor structure, and the lower DBR 2100L includes an N-type semiconductor layer structure. In this embodiment, the conductive structure 2100P functions as a P-electrode of the illuminant epitaxial structure 2100.

[0059] 1A, the light-receiving structure 2200 is integrally formed as part of the lower DBR 2100L of the light-emitting epitaxial structure 2100 (e.g., a VCSEL). In other words, in this embodiment, the lower DBR 2100L is formed by sequentially stacking a DBR structure 2100L1, a light-receiving structure 2200, and a DBR structure 2100L2.

[0060] 1A, the conductive structure 2200N contacts the light-receiving structure 2200 at a bottom surface 2200B of the light-receiving structure 2200. In one embodiment, the light-receiving structure 2200 may be a photodiode, such as an avalanche photodiode (APD) or a PIN photodiode. In the embodiment shown in FIG. 1A, the conductive structure 2200N functions as the N-electrode of the light-receiving structure 2200.

[0061] 1A , the conductive structure 2400 contacts the DBR structure 2100L1 at the upper surface 2100LT of the lower DBR 2100L, and then the conductive structure 2400 continues to extend through a through-hole structure 2000V formed inside the stack structure 2000 to cover a portion of the lower surface 2000B. In the embodiment shown in FIG. 1A , the insulating structure 2000VI is located within the through-hole structure 2000V and extends to cover a portion of the lower surface 2000B, and the insulating structure is used to electrically insulate the conductive structure 2400 from the lower DBR 2100L. In the embodiment shown in FIG. 1A , the conductive structure 2400 contacts the N-type semiconductor DBR structure 2100L1, and the N-type semiconductor lower DBR 2100L is connected to the upper part of the light-receiving structure 2200. Therefore, the conductive structure 2400 is a common electrode for the light-emitting epitaxial structure 2100 and the light-receiving structure 2200. In this embodiment, the conductive structure 2400 is both the N-electrode of the light-emitting epitaxial structure 2100 and the P-electrode of the light-receiving structure 2200 .

[0062] 1A , in one embodiment, the epitaxial light-emitting structure 2100 may further include a current-limiting layer 2125 located between the upper DBR 2100U and the active structure 2100A, and the current-limiting layer 2125 includes a current-limiting area 2125B and a current-conducting area 2125A, where the current-conducting area 2125A is surrounded and defined by the current-limiting area 2125B. The active structure 2100A may be a single-layer structure or a multi-layer structure, for example, the active structure 2100A includes at least one quantum well layer. Furthermore, the active structure 2100A may include at least one current-limiting layer and / or at least one tunnel junction structure.

[0063] 1A and 1B, in one embodiment, the transparent base layer 1100 may be adhered to the upper surface 2000T via the adhesive layer 1200, and the transparent base layer 1100 and the adhesive layer 1200 are transparent to light emitted from the active structure 2100A of the illuminant epitaxial structure 2100. In this embodiment, electrode pads 2400e, 2200e, and 2100e are respectively formed on the lower surface 2000B, with the electrode pad 2400e contacting the conductive structure 2400 and bonded to the second corresponding pad 1320 of the carrier board 1300 (see FIG. 1B), the electrode pad 2200e contacting the conductive structure 2200N and bonded to the first corresponding pad 1310 of the carrier board 1300, and the electrode pad 2100e contacting the conductive structure 2100P and bonded to the third corresponding pad 1330 of the carrier board 1300. In the embodiment shown in FIG. 1A, the photoelectric unit 2 is driven to emit coherent light Lo to a first object, and then the reflected light Lr from the first object can be detected by the light-receiving structure 2200 of the photoelectric unit 2.

[0064] 1B as an example, the optoelectronic unit 2 may be coupled to the controller via a carrier board 1300. The light-emitting structure of the optoelectronic unit 2 and the light-receiving structure of the optoelectronic unit 2 may then be respectively operable by the controller via the conductive structure 2100P or the conductive structure 2200N corresponding to the respective structure (light-emitting structure or light-receiving structure). Alternatively, the light-emitting structure of the optoelectronic unit 2 and the light-receiving structure of the optoelectronic unit 2 may be jointly operable by the controller via a common electrode (conductive structure 2400) of the emitting device and the light-receiving device.

[0065] 1C shows a package structure of a light emitting sensing package 2C according to one embodiment, which includes a plurality of photoelectric units 2 (photoelectric unit 2-1 and photoelectric unit 2-2) as shown in FIG. 1A attached to a transparent base layer 1100, and the light emitting sensing package 2C may function as a self-mixing interferometric sensing device. In one or more embodiments, the plurality of photoelectric units 2 of the light emitting sensing package 2C may be arranged in an array.

[0066] In the embodiment shown in FIG. 1C, the stacked structures of the photoelectric units 2-1 and 2-2 have the same or similar structures as the photoelectric unit 2. In the embodiment shown in FIG. 1C, the conductive structure 2100P1 of the photoelectric unit 2-1 may be connected to the conductive structure 2100P2 of the photoelectric unit 2-2 through an interconnection structure (not shown in FIG. 1C). In other words, in this embodiment, the conductive structures 2100P1 and 2100P2 may be connected to form a common electrode (conductive structure 2100P), which may function as the common electrode of the photoelectric units 2-1 and 2-2. For example, in the embodiment shown in FIG. 1C, the common electrode (conductive structure 2100P) is the common P electrode of the photoelectric units of the light-emitting sensing package 2C.

[0067] In the embodiment shown in FIG. 1C, the electrode pad 2200e1 of the conductive structure 2200N1 may be connected to the electrode pad 2200e2 of the conductive structure 2200N2 through a common pad (first corresponding pad 1310) of the carrier board 1300 (not shown in FIG. 1C). In other words, in this embodiment, the common pad (first corresponding pad 1310) of the carrier board 1300 may function as a common N electrode electrically connected to the light-receiving structure of the light-emitting sensing package 2C. In the embodiment shown in FIG. 1C, the electrode pad 2200e3 of the conductive structure 2200N3 may further be connected to the electrode pads 2200e1 and 2200e2 through the common pad (first corresponding pad 1310) of the carrier board 1300.

[0068] In the embodiment shown in FIG. 1C , the conductive structure 2401 of the photoelectric unit 2-1 is separated from the conductive structure 2402 of the photoelectric unit 2-2. In other words, in this embodiment, the conductive structure 2401 and the conductive structure 2402 are substantially electrically isolated from each other. Therefore, each photoelectric unit 2-1, 2-2 can be individually driven and controlled. In the embodiment shown in FIG. 1C , the photoelectric unit 2-1 is driven to emit coherent light Lo1 toward a first object, and then the reflected light Lr1 from the first object can be detected by the light-receiving structure of the photoelectric unit 2-1. The photoelectric unit 2-2 is driven to emit coherent light Lo2 toward a second object, and then the reflected light Lr2 from the second object can be detected by the light-receiving structure of the photoelectric unit 2-2.

[0069] Specifically, in some embodiments, the laser light is reflected from the object and contains information about the state of the object (e.g., distance to the photoelectric unit, rotation speed, movement speed, acceleration, etc.), and the aforementioned information can be obtained by comparing the phase changes of the light from different lasers and performing conversion calculations.

[0070] 1D shows a package structure of a light-emitting sensing package 2D according to an embodiment, which includes a plurality of optoelectronic units 2 (e.g., optoelectronic units 2-1 and 2-2) as shown in FIG. 1A adhered to a transparent base layer 1100, and the light-emitting sensing package 2D may function as a self-mixing interferometric sensing device. Each stack structure of the optoelectronic units 2 in the embodiment shown in FIG. 1D has the same or similar structure as the stack structure of the optoelectronic units 2 in the embodiment shown in FIG. 1A.

[0071] 1D and 1C, the structure of the light-emitting sensing package 2D is similar to that of the light-emitting sensing package 2C, in which the conductive structures 2100P1 and 2100P2 are connected to form a common electrode (conductive structure 2100P), which can function as a common electrode (e.g., a common P electrode) of the photoelectric units, and the conductive structures 2401 and 2402 are substantially electrically isolated from each other. Therefore, each photoelectric unit shown in FIG. 1D can be driven and controlled individually.

[0072] Specifically, in the embodiment shown in Figure 1D, the conductive structure 2200N1 and the conductive structure 2200N2 are each covered by an insulating structure, and the conductive structure 2200N1 and the conductive structure 2200N2 are connected to the conductive structure 2200N3 via an interconnection structure (not shown in Figure 1D). Therefore, the conductive structure 2200N3 serves as a common electrode to electrically connect each light-receiving structure 2200. Electrode 1D, the electrode pad 2200e3 may function as a common N-electrode electrically connected to the light-receiving structure 2200 of the light-emitting sensing package body 2D.

[0073] 1D as an example, in one or more embodiments, the transparent base layer 1100 may have an integrated optical element 1101. In one or more embodiments, the integrated optical element 1101 may include multiple optical elements (e.g., microlenses 1101A and 1101B), where the microlens 1101A corresponds to the optoelectronic unit 2-1 below the microlens 1101A and the microlens 1101B corresponds to the optoelectronic unit 2-2 below the microlens 1101B. In one or more embodiments, the center position (or optical axis) of the microlens 1101A is offset from the center position of the current conducting area in the optoelectronic unit 2-1 located thereunder, and / or the center position (or optical axis) of the microlens 1101B is offset from the center position of the current conducting area in the optoelectronic unit 2-2 located thereunder, although the present application is not limited thereto.

[0074] In some embodiments, by alternating the optical elements with the current conducting areas of each semiconductor laser (i.e., the light exit ports corresponding to the semiconductor lasers), the light emitted by the semiconductor lasers can be offset, thereby varying the field of illumination (FOI) of the optoelectronic device.

[0075] 2A is a schematic cross-sectional view illustrating a packaging structure of an optoelectronic unit 2' according to an embodiment, which can be used as a self-mixing interferometric (SMI) sensing unit.

[0076] Referring to Figures 2A and 1A, the photovoltaic unit 2' has a structure similar to that of the photovoltaic unit 2, and in the embodiment shown in Figure 2A, the photovoltaic unit 2' includes a light-emitting epitaxial structure 2100' and a light-receiving structure 2200', and the light-receiving structure 2200' is located below the light-emitting epitaxial structure 2100'.

[0077] Specifically, unlike the embodiment shown in FIG. 1A (in which the light-receiving structure 2200 is integrally formed as part of the lower DBR 2100L of the light-emitting epitaxial structure 2100), in the embodiment shown in FIG. 2A, the photovoltaic unit 2′ further includes an adhesive layer 2500 located between the light-emitting epitaxial structure 2100′ and the light-receiving structure 2200′, and the upper surface of the light-receiving structure 2200′ is substantially adhered to the lower surface of the light-emitting epitaxial structure 2100′ via the adhesive layer 2500, and the adhesive layer 2500 is transparent to the coherent light Lo′ emitted from the active structure 2100A′ of the light-emitting epitaxial structure 2100′.

[0078] In the embodiment shown in Figure 2A, the illuminant epitaxial structure 2100' may be a VCSEL, which may be a layered epitaxial structure including an upper DBR 2100U', a lower DBR 2100L', and an active structure 2100A' located between the upper DBR 2100U' and the lower DBR 2100L'. In the embodiment shown in Figure 2A, the upper DBR 2100U' includes a P-type semiconductor structure, and the lower DBR 2100L' includes an N-type semiconductor layer structure, and the conductive structure 2100P (see Figure 2A) functions as a P-electrode of the illuminant epitaxial structure 2100'.

[0079] In the embodiment shown in Figure 2A, the adhesive layer 2500 is electrically conductive, so that the conductive structure (see Figure 2A) may be electrically connected to the lower DBR 2100L' of the illuminant epitaxial structure 2100' and the light-receiving structure 2200'. Therefore, the conductive structure 2400 is a common electrode for the illuminant epitaxial structure 2100' and the light-receiving structure 2200'. In the embodiment shown in Figure 2A, the conductive structure 2400 is both the N-electrode of the illuminant epitaxial structure 2100' and the P-electrode of the light-receiving structure 2200'.

[0080] In the embodiment shown in FIG. 2A , the light-receiving structure 2200′ further includes a DBR structure 2210′ and a conductive structure 2200N (see FIG. 2A ) that contacts the light-receiving structure 2200′ on a lower surface of the light-receiving structure 2200′. In one embodiment, the light-receiving structure 2200′ may be a photodiode such as an avalanche photodiode or a PIN photodiode. In the embodiment shown in FIG. 2A , the conductive structure 2200N functions as an N-electrode of the light-receiving structure 2200′. In the embodiment shown in FIG. 2A , the light-receiving structure 2200′ may be formed by a wafer fusion process.

[0081] 2B is a cross-sectional schematic diagram showing a package structure of a light-emitting sensing package 2D' according to one embodiment, the light-emitting sensing package 2D' includes a plurality of photoelectric units 2' (photoelectric unit 2-1' and photoelectric unit 2-2') shown in FIG. 2A attached to a transparent base layer 1100, and the light-emitting sensing package 2D' may function as a self-mixing interferometric sensing device. In one or more embodiments, the plurality of photoelectric units 2' of the light-emitting sensing package 2D' may be arranged in an array.

[0082] In the embodiment shown in Figure 2B, the conductive structure 2100P1 of the photoelectric unit 2-1' may be connected to the conductive structure 2100P2 of the photoelectric unit 2-2' through an interconnection structure (not shown in Figure 2B). In other words, in this embodiment, the conductive structures 2100P1 and 2100P2 are connected to form a common electrode (conductive structure 2100P) (see Figure 2B), which may function as the common electrode of the photoelectric units 2-1' and 2-2'. For example, in the embodiment shown in Figure 2B, the common electrode is the common P electrode of the photoelectric units of the light-emitting sensing package body 2D'.

[0083] 2B, the conductive structure 2401 of the photoelectric unit 2-1′ and the conductive structure 2402 of the photoelectric unit 2-2′ are separated, in other words, in this embodiment, the conductive structure 2401 and the conductive structure 2402 are substantially electrically separated from each other, so that each photoelectric unit 2-1′, 2-2′ can be driven and controlled separately.

[0084] In the embodiment shown in Figure 2B, conductive structure 2200N1 and conductive structure 2200N2 may be connected to conductive structure 2200N3 via an internal interconnect structure (not shown in Figure 2B). Thus, conductive structure 2200N3 serves as a common electrode. each The light receiving structure 2200' is electrically connected Electrode 2B, the electrode pad 2200e3 may function as a common N-electrode electrically connected to the light-receiving structure 2200′ of the light-emitting sensing package body 2D′.

[0085] 3A is a cross-sectional schematic diagram illustrating a package structure of an optoelectronic device 3A according to one embodiment. Referring to FIG. 3A as an example, in one or more embodiments, the optoelectronic device 3A further includes a housing 1400 that covers the light-emitting sensing package 2D'. Note that the light-emitting sensing package 2D' can be replaced with any of the light-emitting sensing packages described above, but the present application is not limited thereto.

[0086] In one or more embodiments, taking the embodiment shown in FIG. 3A as an example, the housing 1400 may include multiple optical elements 1401A, 1401B. In one or more embodiments, taking the embodiment shown in FIG. 3A as an example, the optical elements 1401A, 1401B may have the same or different optical functions. In one embodiment, the optical elements 1401A, 1401B may be used to project light. In another embodiment, the optical elements 1401A, 1401B may be used to focus light. In other embodiments, the optical element 1401A may be used to project light, while the optical element 1401B may be used to focus light. In one embodiment, the optical elements 1401A, 1401B may be used to project light in different directions or to focus light, or alternatively, the optical elements 1401A, 1401B may be used to project light at different angles, thereby expanding the field of view of the photovoltaic device 3A.

[0087] In some embodiments, there may be a containment space between the housing 1400 and the transparent base layer 1100, which may be filled with normal air, an inert gas, nitrogen, or maintained in a vacuum, thereby providing a medium environment with different refractive indices. In other embodiments, an optical element having a concave lens structure may be formed in the transparent base layer 1100 and then covered with the housing 1400, which may also provide the focusing and / or collimating functions of the optical element.

[0088] In some embodiments, taking the embodiments shown in Figure 1D or 3A-3C as examples, the optical element may include, for example, a diffractive optical element (DOE) structure, a microlens array structure, a metasurface structure, a metalens structure, or a combination of the various optical element structures described above. Among these, the metasurface structure is a nanostructure having a plurality of periodic arrangements.

[0089] In one or more embodiments, taking the embodiment shown in FIG. 3A as an example, the carrier board 1300 may be a ceramic substrate, a printed circuit board, or the like.

[0090] FIG. 3B is a cross-sectional view illustrating a package structure of an optoelectronic device 3B according to an embodiment, and the optoelectronic device 3B may be used as a self-mixing interferometric sensing device with a baseline signal or a reference signal.

[0091] In the embodiment shown in FIG. 3B, the conductive structure 2100P1 completely covers the top surface of the left epitaxial light-emitting structure 2100-1, while the conductive structure 2100P2 does not completely cover the top surface of the right epitaxial light-emitting structure 2100-2. The right epitaxial light-emitting structure 2100-2 can emit light normally. Therefore, light emitted from the active structure of the left light-emitting epitaxial structure 2100-1 is blocked and reflected downward by the conductive structure 2100P1. Therefore, the signal output from the left light-receiving structure 2200-1 can be used as a baseline signal / reference signal for the signal output from the right light-receiving structure 2200-2 for self-mixing interferometric sensing.

[0092] 3C is a cross-sectional view illustrating a package structure of an optoelectronic device 3C according to an embodiment, and the optoelectronic device 3C may be used as a self-mixing interferometric sensing device. According to the embodiment shown in FIG. 3C, the optoelectronic device 3C includes a plurality of optoelectronic units arranged in an array, and the light emission structure of one or more of the optoelectronic units may be different from the light emission structure of the other optoelectronic units.

[0093] In one or more embodiments, the photoelectric device can provide a two-dimensionally distributed laser beam by arranging multiple photoelectric units in an array. When the two-dimensionally distributed laser beam is irradiated onto an object, the laser light emitted from each photoelectric unit is reflected by the object, and the reflected beam contains information about the distance between the object and the photoelectric device, information about the object's motion, and the like, as described above. Furthermore, because the photoelectric device irradiates the object with two-dimensionally distributed laser beams, each laser light can irradiate a different position on the object, which can improve the accuracy of distance information and motion information obtained by calculation, and can also provide three-dimensional contour information about the object.

[0094] 3C and 3B, the right illuminant epitaxial structure 2100-2′ shown in FIG. 3C has the same or a similar structure as the right illuminant epitaxial structure 2100-2 shown in FIG. 3B. In the embodiment shown in FIG. 3C, the right illuminant epitaxial structure 2100-2′ includes a VCSEL structure.

[0095] 3C, the illuminant epitaxial structure 2100-1' on the left side may be different from the illuminant epitaxial structure 2100-2' on the right side. In other words, in this embodiment, the illuminant epitaxial structure 2100' on the left side may include an LED structure or a resonant cavity light emitting diode (RCLED) structure.

[0096] In one or more embodiments, the electrode structure of the light-emitting structure and / or the electrode structure of the light-receiving structure of the aforementioned photoelectric device (e.g., self-mixing interferometric sensing device) may be jointly constructed as one or more common electrodes for jointly driving / controlling (e.g., jointly driven / controlled mode). When the photoelectric device (e.g., self-mixing interferometric sensing device) is enabled in the joint driving / control mode, activation signals for enabling different units of the photoelectric device may be ignored.

[0097] 4A to 4D, which are top views illustrating packaging structures of optoelectronic devices according to some embodiments.

[0098] 4A, in some embodiments, the photovoltaic device 4A includes 32 SMI sensing units 4-1 forming an array, the light emitting structure of each SMI sensing unit 4-1 being, for example, a VCSEL semiconductor laser, the gap between the SMI sensing units 4-1 being 133 μm, the emission wavelength of the VCSEL semiconductor laser being, for example, 940 nm, and the aperture diameter of the light exit port of the VCSEL semiconductor laser being 8 to 10 μm.

[0099] As shown in FIG. 4B, in some embodiments, the photoelectric device 4B includes 32 SMI sensing units 4-2 forming an array, and the gap between the SMI sensing units 4-2 is 166 μm.

[0100] As shown in FIG. 4C, in some embodiments, the photoelectric device 4C includes 32 SMI sensing units 4-3 forming an array, and the gap between the SMI sensing units 4-3 is 186 μm.

[0101] As shown in FIG. 4D, in some embodiments, the photoelectric device 4D includes 32 SMI sensing units 4-4 forming an array, and the gap between the SMI sensing units 4-4 is 300 μm.

[0102] 4A-4D, in some embodiments, the photovoltaic devices 4A, 4B, 4C, and 4D include a plurality of SMI sensing units 4-1, 4-2, 4-3, and 4-4 forming an array, each having a light-emitting structure (e.g., a VCSEL semiconductor laser), where the upper electrode (e.g., VCSEL-) of each VCSEL semiconductor laser of each SMI sensing unit 4-1, 4-2, 4-3, and 4-4 extends to a respective external electrode (shown as a square) via conductive wiring, and the lower electrode (e.g., VCSEL+) of each VCSEL semiconductor laser is commonly connected, thereby allowing each SMI sensing unit of the photovoltaic devices 4A, 4B, 4C, and 4D to be addressable or separately controllable by the respective external electrodes.

[0103] 5 is a cross-sectional view illustrating a package structure of an optoelectronic device according to an embodiment. Referring to FIG. 5, in this embodiment, the optoelectronic unit 5 is an SMI sensing chip with a vertical chip structure.

[0104] The photovoltaic unit 5 includes a light-emitting structure, a light-receiving structure 5200 and a conductive base layer 5500, and the photovoltaic unit 5 is a stacked structure 5000 including a semiconductor epitaxial structure and a conductive structure.

[0105] In this embodiment, an illuminant epitaxial structure 5100 (corresponding to the light-emitting structure of the optoelectronic unit 5) is provided on the conductive base layer 5500. The stacked structure includes the illuminant epitaxial structure 5100 corresponding to the light-emitting structure of the optoelectronic unit 5. In this embodiment, the illuminant epitaxial structure 5100 is a vertical cavity surface-emitting laser, and may be a stacked epitaxial structure including an upper DBR 5100U, a lower DBR 5100L, and an active structure 5100A located between the upper DBR 5100U and the lower DBR 5100L.

[0106] In the embodiment shown in FIG. 5, the conductive structure 5100P contacts the upper DBR 5100U at the upper surface 5100UT of the upper DBR 5100U.

[0107] 5, the light-receiving structure 5200 is integrally formed as part of the lower DBR 5100L of the light-emitting epitaxial structure 5100 (e.g., a VCSEL). In other words, in this embodiment, the lower DBR 5100L is formed by sequentially stacking a DBR structure 5100L1, a light-receiving structure 5200, and a DBR structure 5100L2.

[0108] 5, the upper DBR 5100U includes a P-type semiconductor structure, and the lower DBR 5100L includes an N-type semiconductor layer structure. In this embodiment, the conductive structure 5100P functions as a P-electrode of the illuminant epitaxial structure 5100.

[0109] 5, the conductive structure 5200N is located on the opposite side of the conductive base layer 5500 from the light-receiving structure 5200 and is electrically connected to the light-receiving structure 5200 via the conductive base layer 5500. In one embodiment, the light-receiving structure 5200 may be a photodiode such as an avalanche photodiode or a PIN photodiode. In the embodiment shown in FIG. 5, the conductive structure 5200N functions as the N-electrode of the light-receiving structure 5200.

[0110] 5, the conductive structure 5400 is connected to the top of the light-receiving structure 5200 and is electrically connected to the lower DBR 5100L by the light-receiving structure 5200. Therefore, the conductive structure 5400 is a common electrode for the illuminating epitaxial structure 5100 and the light-receiving structure 5200. In this embodiment, the conductive structure 5400 is both the N-electrode of the illuminating epitaxial structure 5100 and the P-electrode of the light-receiving structure 5200.

[0111] 5, in one embodiment, the epitaxial light-emitting structure 5100 further includes a current-limiting layer 5125 located between the upper DBR 5100U and the active structure 5100A, and the current-limiting layer 5125 includes a current-limiting area 5125B and a current-conducting area 5125A, where the current-conducting area 5125A is surrounded and defined by the current-limiting area 5125B. The active structure 5100A may be a single-layer structure or a multi-layer structure, for example, the active structure 5100A includes at least one quantum well layer. Furthermore, the active structure 5100A may include at least one current-limiting layer and / or at least one tunnel junction structure.

[0112] In one embodiment, referring to FIG. 6 , FIG. 6 is a schematic diagram illustrating the application of a packaging structure of an optoelectronic device according to one embodiment. In this embodiment, the structure of optoelectronic device 6 is similar to that of optoelectronic device 5, with the main difference being that in this embodiment, conductive structure 6400 is located on one side of illuminant epitaxial structure 6100 in a cross-sectional view, whereas in the embodiment shown in FIG. 5 , conductive structure 5400 is located on both sides of illuminant epitaxial structure 5100 in a cross-sectional view. In some embodiments, conductive structure 5400 is ring-shaped. Also, in the embodiment shown in FIG. 6 , illuminant epitaxial structure 6100 (corresponding to the light-emitting structure of optoelectronic unit 6) and light-receiving structure 6200 are sequentially disposed on conductive base layer 6500. In this embodiment, illuminant epitaxial structure 6100 (corresponding to the light-emitting structure of optoelectronic unit 6) and light-receiving structure 6200 are sequentially disposed on conductive base layer 6500. In this embodiment, the illuminant epitaxial structure 6100 is a vertical cavity surface emitting laser and may be a layered epitaxial structure including an upper DBR 6100U, a lower DBR 6100L, and an active structure 6100A located between the upper DBR 6100U and the lower DBR 6100L. In the embodiment shown in Figure 6, the conductive structure 6100P is on the upper surface 6100UT of the upper DBR 6100U and is electrically connected to the upper DBR 6100U. In the embodiment shown in Figure 6, the upper DBR 6100U includes a P-type semiconductor structure, and the lower DBR 6100L includes an N-type semiconductor layer structure. In this embodiment, the conductive structure 6100P functions as a P-electrode of the illuminant epitaxial structure 6100. In the embodiment shown in FIG. 6 , the conductive structure 6200N is located on the opposite side of the conductive base layer 6500 from the light-receiving structure 6200 and is electrically connected to the light-receiving structure 6200 via the conductive base layer 6500. In one embodiment, the light-receiving structure 6200 may be a photodiode such as an avalanche photodiode or a PIN photodiode. In the embodiment shown in FIG. 6 , the conductive structure 6200N functions as the N-electrode of the light-receiving structure 6200. In the embodiment shown in FIG. 6 , the conductive structure 6400 is connected to the top of the light-receiving structure 6200 and is electrically connected to the lower DBR 6100L via the light-receiving structure 6200.Therefore, the conductive structure 6400 is a common electrode for the illuminant epitaxial structure 6100 and the light-receiving structure 6200. In this embodiment, the conductive structure 6400 is the N-electrode of the illuminant epitaxial structure 6100 and the P-electrode of the light-receiving structure 6200 at the same time.

[0113] FIG. 6 is an exemplary schematic diagram of a package structure of a photoelectric device for eye tracking according to some embodiments. The photoelectric device 6 is an SMI sensing device including at least one SMI sensing unit, and can be mounted, for example, on a head-mounted display. The photoelectric device 6 can be used in combination with a micro-optical device (e.g., a microlens) for eye tracking. Coherent light L emitted from an optical emission device (e.g., a VCSEL) of the SMI sensing unit is collected and projected by a microlens to become collected light Lf. The collected light Lf is then projected onto the eyeball and reflected by the eyeball. The reflected light Lr reflected by the eyeball returns to the resonant cavity in the VCSEL of the SMI sensing unit, generating interference light Lg. A receiving device (e.g., an APD or PIN) of the SMI sensing unit detects changes in the interference light Lg and outputs a calculation output to obtain the rotational (movement) offset or velocity of the measured eyeball.

[0114] According to one embodiment, an SMI sensing device for gaze tracking includes a plurality of SMI sensing units distributed in an array, and the associated micro-optical device may be a microlens array, and each microlens calibrates the light exit aperture of the VCSEL of each SMI sensing unit respectively to generate projected sensing light with a wide field of view (FOV), for example, a FOV of 60x45, but the present application is not limited thereto.

[0115] According to one embodiment, the optical transmission distance of the SMI sensing device for eye tracking is typically 25-30 mm, and the spot size of the projected sensing light is typically 200 μm or less, although the present application is not limited thereto.

[0116] It should be noted that the SMI sensing device shown in one or more embodiments of the present application can also be used to detect information such as rotational (motion) offset or velocity of other types of measurement objects (e.g., body motion, vehicle motion, etc.).

[0117] 7A to 7K are schematic cross-sectional views illustrating steps in a manufacturing process of a packaging structure for an optoelectronic device according to an embodiment of the present application.

[0118] 7A, an epitaxial chip is provided. The epitaxial chip includes a light-receiving layer 7200 and a light-emitting layer (light-emitting epitaxial layer 7100) formed on a conductive base layer 7700, with the light-emitting epitaxial layer 7100 located on the light-receiving layer 7200. The light-emitting epitaxial layer 7100 includes a first-type semiconductor layer 7100U, a second-type semiconductor layer 7100L, and an active layer 7100A located between the first-type semiconductor layer 7100U and the second-type semiconductor layer 7100L.

[0119] The first-type semiconductor layer 7100U and / or the second-type semiconductor layer 7100L may have a multi-layer structure. In this embodiment, the first-type semiconductor layer 7100U is a P-type semiconductor layer, and the second-type semiconductor layer 7100L is an N-type semiconductor layer. The light-receiving structure 7200 and the light-emitting structure (light-emitting epitaxial structure 7100) can be grown on the conductive base layer 7700 by an epitaxial method, including, but not limited to, metal-organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, and liquid phase epitaxy. The light-receiving structure 7200 may be an avalanche photodiode or a PIN photodiode. The conductive base layer 7700 includes, but is not limited to, a III-V material, and its lattice constant is matched to that of the semiconductor laminate 10. In this embodiment, the material of the conductive base layer 7700 is gallium arsenide (GaAs). In other embodiments, the material of the conductive base layer 7700 may be indium phosphide (InP), sapphire, gallium nitride (GaN), silicon carbide (SiC), or the like.

[0120] 7A, a ring-shaped electrode structure 7100R is formed on the first-type semiconductor layer 7100U of the epitaxial chip, and the ring-shaped electrode structure 7100R is electrically connected to the first-type semiconductor layer 7100U. The material of the ring-shaped electrode structure 7100R may be a conductive metal.

[0121] Next, referring to FIG. 7B, a protective layer PL is formed to cover the first-type semiconductor layer 7100U of the epitaxial chip, and the material of the protective layer PL may be an insulating material, including but not limited to silicon nitride.

[0122] Next, referring to FIG. 7C, an etching procedure is performed on the semiconductor stack of the aforementioned epitaxial chip, and using a mask having a specific pattern, a portion of the first-type semiconductor layer 7100U, a portion of the active layer 7100A, and a portion of the second-type semiconductor layer 7100L are etched away to expose the second-type semiconductor layer 7100L, thereby forming a boss structure 7100M1.

[0123] 7C , a current limiting layer 7125 is formed in the epitaxial light emitting layer 7100. In this embodiment, the current limiting layer 7125 may be formed by oxidizing the material of the region where the current limiting area 7125B is to be formed through an oxidation process. For example, the aluminum content of at least one layer of the first-type semiconductor layer 7100U is higher than 97% (defined as the layer where the current limiting layer 7125 is to be formed), which is higher than the aluminum content of the active layer 7100A and the second-type semiconductor layer 7100L. Therefore, during the oxidation process, the layer region with a higher aluminum content (defined as the layer where the current limiting layer 7125 is to be formed) of the light emitting epitaxial layer 7100 is internally oxidized at a faster rate than the other regions, forming the current limiting area 7125B of the current limiting layer 7125 with lower conductivity. Alternatively, the current-restricting area 7125B with low conductivity can be formed in the illuminant epitaxial layer 7100 by an ion implant process, and the current-conducting area 7125A can be defined through a mask. The ion implantation implants hydrogen ions (H + ), helium ions (He + ), or argon ions (Ar + ) or the like, such that the ion concentration in the current-restricting area 7125B is much higher than the ion concentration in the current-conducting area 7125A, causing the current-restricting area 7125B to have a relatively low conductivity.

[0124] Next, referring to FIG. 7D, the light-emitting epitaxial layer 7100 of the aforementioned epitaxial chip is subjected to an etching procedure again, and a mask having a specific pattern is used to etch away a portion of the second-type semiconductor layer 7100L, exposing the light-receiving layer 7200, thereby forming a boss structure 7100M2.

[0125] 7E, an electrode structure 7409 is formed on the light-receiving layer 7200 of the epitaxial chip, and the electrode structure 7409 is electrically connected to the light-receiving layer 7200, and the electrode structure 7409 is electrically connected to the second-type semiconductor layer 7100L through the light-receiving layer 7200. The material of the electrode structure 7409 may be a conductive metal.

[0126] Next, as shown in FIG. 7F, an etching procedure is performed on the light-receiving layer 7200 of the epitaxial chip, and a mask having a specific pattern is used to etch away a portion of the light-receiving layer 7200, exposing the conductive base layer 7700, thereby forming a boss structure 7200M.

[0127] 7G, an insulating layer 7901 is formed to cover the light-emitting epitaxial layer 7100, the light-receiving layer 7200, and the conductive base layer 7700. Furthermore, an opening 7901A is formed in the insulating layer 7901 to expose a portion of the electrode structure 7409.

[0128] Next, referring to FIG. 7H, an extension electrode 7409E is formed in the opening 7901A and extends to the light-receiving layer 7200 and the conductive base layer 7700 of the epitaxial chip, whereby the electrode structure 7409 is electrically connected to the light-receiving layer 7200, and the extension electrode 7409E is electrically connected to the second-type semiconductor layer 7100L through the light-receiving layer 7200, thereby expanding the distribution range of the extension electrode 7409E.

[0129] 7I , an insulating layer 7902 is further formed to cover the luminescent epitaxial layer 7100, the light-receiving layer 7200, and the conductive base layer 7700. Furthermore, an opening 7902A is formed in the insulating layer 7902 to expose a portion of the ring-shaped electrode structure 7100R located in the first-type semiconductor layer 7100U of the luminescent epitaxial layer 7100 and the extension electrode 7409E located in the conductive base layer 7700.

[0130] Next, as shown in FIG. 7J , a conductive structure 7100P is formed, electrically connected to the ring-shaped electrode structure 7100R of the first-type semiconductor layer 7100U of the light-emitting epitaxial layer 7100 and extending to the insulating layer 7902 located in the light-receiving layer 7200 and the conductive base layer 7700. Furthermore, an opening 7902A of the conductive structure 7400 is formed in the conductive base layer 7700. In this embodiment, the conductive structure 7400 is electrically connected to the light-receiving structure 7200 via the electrode structure 7409 and the extension electrode 7409E, and is also electrically connected to the second-type semiconductor layer 7100L via the light-receiving structure 7200. Therefore, the conductive structure 7400 is a common electrode for the light-emitting epitaxial structure 7100 and the light-receiving structure 7200. In this embodiment, the conductive structure 7400 is both the N-electrode of the light-emitting epitaxial structure 7100 and the P-electrode of the light-receiving structure 7200.

[0131] 7K, a conductive structure 7200N is formed on the surface of the conductive base layer 7700 opposite the light-emitting epitaxial layer 7100. The conductive structure 7200N is electrically connected to the light-receiving layer 7200 via the conductive base layer 7700, which is capable of conducting electricity.

[0132] Typically, a single epitaxial wafer (epi-wafer) is subjected to a singulation process to produce multiple vertical cavity surface emitting laser chips (VCSEL chips).

[0133] Figure 8A is a top view of a portion of a VCSEL wafer imaged with an optical microscope. Figure 8B is a top view of a portion of a VCSEL wafer imaged with an optical microscope. The magnification of the optical microscope image in Figure 8B is greater than the magnification of Figure 8A. Referring to Figure 8A, the VCSEL wafer includes 48 VCSEL units formed in an array on a GaAs wafer.

[0134] 9A and 9B are schematic diagrams illustrating the process of singulating VCSEL dies from the front side 9000F of a thin VCSEL wafer 9000 using an ablation laser or dicing machine 9900. This singulation process requires that streets approximately 30 μm to 40 μm wide be maintained in the VCSEL wafer 9000. Note that by reducing the size of the streets, the number of chips (dies) cut from the VCSEL wafer 9000 can be increased, reducing overall production costs.

[0135] The VCSEL wafer 9000 includes a bottom metal layer 9300 , a thinned wafer layer 9200 on the bottom metal layer 9300 , and an epitaxial layer 9100 on the thinned wafer layer 9200 .

[0136] 10A-10C are schematic diagrams illustrating dicing of multiple dies by a process method for singulating a thinned VCSEL wafer according to one embodiment. The method illustrated in FIGS. 10A-10C can reduce street widths to 20 μm or less. In this embodiment, a method is provided for performing a singulation process on an epitaxial wafer 10000, the epitaxial wafer 10000 including a semiconductor stack 10020 (e.g., a VCSEL stack), a base layer 10010, and a metal layer 10030. The base layer 10010 may be a growth wafer layer of the semiconductor stack 10020 (e.g., a growth wafer of a VCSEL stack). Generally speaking, the base layer 10010 may be a thinned growth wafer layer to facilitate an effective singulation process. The base layer 10010 may also be made of glass (e.g., silicon-based glass or sapphire glass) or a III-V compound. In some embodiments, the III-V compound is GaAs, InP, or GaSb.

[0137] In this embodiment, the singulation process method includes a processing step, a dicing step, and a cleaving step, and each step is described below.

[0138] 10A , a stealth dicing technique is used to process a portion of the internal region of the base layer 10010 from the upper surface 10000T of the epitaxial wafer 10000 (e.g., a VCSEL epitaxial wafer) to form a processing area 10011 in the portion of the internal region of the base layer 10010. The processing area 10011 includes at least one row of break points 10012, the extension direction of which is substantially parallel to the extension direction of the lower surface 10000B of the epitaxial wafer 10000, and the distance between the processing area 10011 and the upper surface 10000T of the epitaxial wafer 10000 is typically 60 μm or less. In other words, in this embodiment, the region from the top surface 10000T of the epitaxial wafer 10000 to a depth of 60 μm is processed using stealth dicing technology, which changes the crystalline phase of the processed area 10011 in the base layer 10010 and creates a breaking point 10012 (or structural weakening point). In some embodiments, the stealth dicing technology is achieved using a laser having a wavelength of 1064 nm. In some embodiments, the top surface 10000T of the epitaxial wafer 10000 is flat. Note that the location of the breaking point 10012 needs to avoid the semiconductor stack layer 10020 of the epitaxial wafer so as not to affect the performance of the semiconductor laser.

[0139] 10B, using a laser lift-off technique or a wheel dicing technique (e.g., an ablation laser or a dicing machine 10900), the metal layer 10030 and another portion of the base layer 10010 are diced from the underside 10000B of the epitaxial wafer 10000, to form streets 10013 (dicing grooves) in the other portions of the metal layer 10030 and the base layer 10010. The streets 10013 have a dicing width W10 and a dicing depth D10, where the dicing width W10 is less than 20 μm and the dicing depth D10 is 30 μm, although the present application is not limited thereto.

[0140] 10C, a cleaving technique is applied to the streets 10013 to cleave the epitaxial wafer into multiple dies (chips). In this embodiment, a cleaving force (e.g., using a cleaving jig as shown by the arrows in the figure) is applied to each groove (street 10013) to form cracks G010 extending from the groove tip to the top surface 10000T of the epitaxial wafer 10000, thereby dividing the epitaxial wafer 10000 into multiple VCSEL dies (chips). In this embodiment, a jig may be fixed to a specific position on the epitaxial wafer 10000, and an external force may be applied to cleave the epitaxial wafer 10000 into multiple semiconductor lasers.

[0141] According to the singulation method of this embodiment, for an epitaxial wafer 10000 of the same size, the width of the street 10013 can be narrowed, allowing more semiconductor lasers to be diced, thereby reducing overall production costs.

[0142] In some embodiments, in the above step of forming processing areas 10011, a plurality of first processing areas are formed in the base layer 10010 along the length direction of the epitaxial wafer 10000 as viewed from above, and a plurality of second processing areas are formed along the width direction of the epitaxial wafer 10000 as viewed from above. Each first processing area includes at least one row of first break points, and each second processing area includes at least one row of second break points. Furthermore, the extension direction of the at least one row of first break points is substantially parallel to the length direction of the epitaxial wafer 10000 as viewed from above, and the extension direction of the at least one row of second break points is substantially parallel to the width direction of the epitaxial wafer 10000 as viewed from above. In other words, in this embodiment, a stealth dicing technique can be used to process a plurality of portions of the epitaxial wafer 10000 (simultaneously or batchwise) to form a plurality of processing areas 10011 in each of the length direction and the width direction. Each processing area 10011 includes at least one row of break points 10012. Furthermore, multiple rows of break points 10012 can be formed within the same processing area depending on the thickness of the base layer 10010. For example, as the thickness of the base layer 10010 increases, the number of rows of break points 10012 can be further increased, and the extension direction of the cracks G010 can be more effectively controlled.

[0143] 11A to 11D are schematic perspective views showing processing steps of an epitaxial wafer singulation method according to some embodiments.

[0144] As shown in Figure 11A, in this embodiment, each first processing area 11011A of the epitaxial wafer 11000A includes a row of first break points 11012A, and each second processing area 11011A' includes a row of second break points 11012A', the extension direction of the first break points 11012A of the row is substantially parallel to the length direction LD of the epitaxial wafer 11000A when viewed from above, and the extension direction of the second break points 11012A' of the row is substantially parallel to the width direction WD of the epitaxial wafer 11000A when viewed from above.

[0145] As shown in Figure 11B, in this embodiment, each first processing area 11011B of the epitaxial wafer 11000B includes two rows of first break points 11012B, and each second processing area 11011B' includes two rows of second break points 11012B', the extension direction of the first break points 11012B of each row is substantially parallel to the length direction LD of the epitaxial wafer 11000B when viewed from above, and the extension direction of the second break points 11012B' of each row is substantially parallel to the width direction WD of the epitaxial wafer 11000B when viewed from above.

[0146] 11C , in this embodiment, each first processing area 11011C of the epitaxial wafer 11000C includes two rows of first break points 11012C, and each second processing area 11011C′ includes one row of second break points 11012C′, the extension direction of the first break points 11012C in each row being substantially parallel to the length direction LD of the epitaxial wafer 11000C in a top view, and the extension direction of the second break points 11012C′ in each row being substantially parallel to the width direction LD of the epitaxial wafer 11000C in a top view. In some embodiments, the number of rows of the first break points 11012C and the number of rows of the second break points 11012C′ may differ.

[0147] As shown in Figure 11D, in this embodiment, each first processing area 11011D of the epitaxial wafer 11000D includes three rows of first break points 11012D, and each second processing area 11011D' includes two rows of second break points 11012D', the extension direction of the first break points 11012D of each row is substantially parallel to the length direction LD of the epitaxial wafer 11000D when viewed from above, and the extension direction of the second break points 11012D' of each row is substantially parallel to the width direction WD of the epitaxial wafer 11000D when viewed from above.

[0148] As shown in Figures 11C and 11D, in some embodiments, these first row of break points 11012C, 11012D and these second row of break points 11012C', 11012D' are arranged in a staggered pattern.

[0149] 12A-12B are schematic diagrams illustrating dicing of multiple dies by a process method for singulating a thin VCSEL wafer according to one embodiment. The method illustrated in Figures 12A-12B can reduce the width of the streets 12013 to 10 μm or less.

[0150] In this embodiment, a process method for singulating an epitaxial wafer is provided, wherein the epitaxial wafer 12000 includes a semiconductor laminate layer 12020 (e.g., a VCSEL laminate layer), a base layer 12010, and a metal layer 12030, wherein the base layer 12010 is located between the semiconductor laminate layer 12020 and the metal layer 12030, and the base layer 12010 may be a growth wafer layer of the semiconductor laminate layer 12010 (e.g., a growth wafer of a VCSEL laminate layer).

[0151] The singulation method of this embodiment includes a dicing step and a cleaving step, each of which will be described below.

[0152] Dicing step: Using laser lift-off technology or wheel dicing technology (e.g., an ablation laser or a dicing machine 12900), a portion of the metal layer 12030 and the base layer 12010 is diced from the underside of the epitaxial wafer 12000, and streets 12013 are formed in the portion of the metal layer 12030 and the base layer 12010, and the streets 12013 have a dicing width W12 and a dicing depth D12, where the dicing width W12 is less than 10 μm and the dicing depth D12 is typically 90 μm or less.

[0153] Cleavage step: The epitaxial wafer 12000 is cleaved into a plurality of semiconductor lasers by applying a cleavage technique (for example, a cleavage jig as indicated by the arrows in the figure) to the streets 12030.

[0154] Referring to FIG. 12A, in this embodiment, a dicing process is performed from the back side of the thinned epitaxial wafer 12000 (e.g., using an ablation laser or dicing machine 12900) to form grooves (streets 12013) in the thinned epitaxial wafer 12000.

[0155] Referring to FIG. 12B, in this embodiment, a cleaving force is applied to form cracks G012 that extend from the apex of each groove to the front side of the epitaxial wafer 12000, separating the epitaxial wafer 12000 into multiple VCSEL dies (chips).

[0156] According to the method for singulating the epitaxial wafer 12000 according to some embodiments of the present invention, the dicing width D12 can be reduced to less than 10 μm.

[0157] According to the singulation method of this embodiment, for an epitaxial wafer of the same size, the street width can be made narrower and more semiconductor lasers can be diced, thereby reducing the overall production cost.

[0158] 13A to 13C, Fig. 13A is a schematic cross-sectional view showing a VCSEL chip 13000 according to an embodiment of the present application. Fig. 13B and Fig. 13C are cross-sectional images of the VCSEL chip taken with an optical microscope, and the VCSEL chip was cut out from a VCSEL wafer.

[0159] As shown in FIGS. 13A to 13C, in this embodiment, the semiconductor laser includes a base layer 13010, an epitaxial structure 13020 located on the base layer 13010, an insulating layer 13030, a first electrode 13040, and a second electrode 13050. The epitaxial structure 13020 includes an upper reflecting mirror 13020U, a lower reflecting mirror 13020L, and an active region 13020A located between the upper reflecting mirror 13020U and the lower reflecting mirror 13020L. The upper reflecting mirror 13020U, the active region 13020A, and the lower reflecting mirror 13020L are stacked on the base layer 13010. The second electrode 13050 is located on the epitaxial structure 13020 and is electrically connected to the semiconductor layer of the upper reflecting mirror 13020U. The first electrode 13040 is on the base layer 13010 and is electrically connected to the semiconductor layer of the bottom reflector 13020L. The second electrode 13050 includes at least one metal layer and a P-type contact layer connected to the P-type semiconductor layer of the top reflector 13020U, and the first electrode 13040 includes at least one metal layer connected to the base layer 13010 and electrically connected to the N-type semiconductor layer of the bottom reflector 13020L. The insulating layer 13030 is located between the epitaxial structure 13020 and the second electrode 13050 and extends to the side surface E13 of the epitaxial structure 13020 to prevent the second electrode 13050 from directly contacting the active region 13020A and the bottom reflector 13020L. The side surface of the base layer 13010 has at least one row of breaks 13011. As shown in Figures 13A and 13B, in this embodiment, the side of the base layer 13010 has two rows of rupture points 13011, and the rupture points 13011 are generated by adopting the singulation process of the previous embodiment.

[0160] In one or more embodiments, as shown in FIG. 13A, the upper reflector 13020U is a multilayer structure, the lower reflector 13020L is a multilayer structure, and at least one or both of the upper reflector 13020U and the lower reflector 13020L include a distributed Bragg reflector (DBR) structure.

[0161] In some embodiments, the semiconductor laser may be a vertical chip structure VCSEL or a flip chip VCSEL.

[0162] 13B, in this embodiment, the semiconductor laser is a VCSEL with a vertical chip structure. In the case of a VCSEL with a vertical chip structure, the base layer is a growth substrate. In other words, in this embodiment, the semiconductor laminated layers are formed directly on the base layer by a semiconductor epitaxial process. In this embodiment, a break point is formed in the base layer, which is the growth substrate.

[0163] 13C, in this embodiment, the semiconductor laser is a flip-chip type VCSEL. In the case of a flip-chip type VCSEL, the base layer is a bonding substrate. In other words, in this embodiment, the semiconductor laminate layer is first formed on a growth substrate by an epitaxial semiconductor process and then transferred to the base layer via an adhesive layer. In this embodiment, a break point is formed in the base layer, which is a bonding substrate.

[0164] Typically, multiple VCSEL chips are individually manufactured by subjecting the same VCSEL epitaxial wafer (epi-wafer) to a singulation process, and the optical and electrical properties of all chips are tested in the epitaxial wafer state before the singulation process. Then, the optical and electrical properties of each VCSEL chip manufactured by subjecting the epitaxial wafer to the singulation process are tested. After the singulation process, all singulated chips have similar appearances and structures, making it difficult to track the position of each chip in the epitaxial wafer state. Therefore, it is difficult to understand the optical and electrical properties of each chip in the epitaxial wafer state before the singulation process, and it is also difficult to trace the test results of any singulated chip to the test results of the same chip in the epitaxial wafer state before the singulation process.

[0165] The present application provides a manufacturing method for forming multiple pattern structures with different shapes on each chip before performing a singulation process, and each chip has a corresponding group of pattern structures, so that after the singulation process, the position of each chip in the epitaxial wafer state can be tracked through the group of pattern structures that each chip has.

[0166] 14A and 14B are different schematic diagrams showing a VCSEL chip 14000 according to one embodiment. FIG. 14A is a top view of the VCSEL chip 14000 according to one embodiment. FIG. 14B is a schematic cross-sectional view taken along line 14B-14B' in FIG. 14A. The VCSEL chip 14000 has a layered structure including a base layer 14010, an epitaxial structure 14020 located on the base layer 14010, an insulating layer 14040, an electrode 14050, and an electrode 14030.

[0167] 14B, the epitaxial structure 14020 includes an upper reflector 14020U, a lower reflector 14020L, and an active region 14020A located between the upper reflector 14020U and the lower reflector 14020L. The upper reflector 14020U, the active region 14020A, and the lower reflector 14020L are stacked on a base layer 14010. In this embodiment, the base layer 14010 is a growth substrate for growing the epitaxial structure 14020, e.g., the lower reflector 14020L, the active region 14020A, and the upper reflector 14020U may be epitaxially grown on the base layer 14010.

[0168] In this embodiment, as shown in FIG. 14B, the base layer 14010 includes a semiconductor layer such as a GaAs layer, an InP layer and / or the like.

[0169] In one or more embodiments, the base layer 14010 may include a support substrate adhered to the VCSEL stack / epitaxial structure.

[0170] In one or more embodiments, as shown in FIG. 14B, the upper reflector 14020U is a multilayer structure, the lower reflector 14020L is a multilayer structure, and at least one or both of the upper reflector 14020U and the lower reflector 14020L include a distributed Bragg reflector (DBR) structure.

[0171] In one or more embodiments, the top reflector 14020U and the bottom reflector 14020L include semiconductor layers, as shown in Figure 14B. In this embodiment, the top reflector 14020U includes a P-type semiconductor layer, and the bottom reflector 14020L includes an N-type semiconductor layer, as shown in Figure 14B, but the present application is not limited thereto. In some embodiments, the top reflector 14020U includes an N-type semiconductor layer, and the bottom reflector 14020L includes a P-type semiconductor layer.

[0172] In this embodiment, as shown in FIG. 14B , the upper reflector 14020U includes a P-doped reflector, for example, a P-doped distributed Bragg reflector (PDBR: P-doped DBR). For example, the upper reflector 14020U includes a group of alternating P-doped GaAs (P-GaAs) layers and P-doped AlGaAs (P-AlGaAs) layers, or a group of alternating P-doped AlGaAs with a low aluminum content (low Al P-AlGaAs) and P-doped AlGaAs with a high aluminum content (high AlP-AlGaAs).

[0173] In this embodiment, as shown in FIG. 14B , the bottom reflector 14020L includes an N-doped reflector, for example, an N-doped distributed Bragg reflector (N-doped DBR, NDBR). For example, the bottom reflector 14020L includes a group of alternating N-doped GaAs (N-GaAs) layers and N-doped AlGaAs (N-AlGaAs) layers, or a group of alternating N-doped AlGaAs with a low aluminum content (low AlN-AlGaAs) layers and N-doped AlGaAs with a high aluminum content (high AlN-AlGaAs) layers.

[0174] In this embodiment, the N-doped semiconductor layer may be doped with Te, Se or other N-type dopants, and the P-doped semiconductor layer may be doped with C or other P-type dopants.

[0175] In one or more embodiments, the DBR structure is formed by multiple films of alternating materials with different refractive indices, each film having an optical thickness substantially equal to m*1 / 4 of the radiation wavelength, where m is an odd integer. The DBR structure includes at least one pair of optical films (a DBR pair), one of which has a higher refractive index than the other.

[0176] In one or more embodiments, the active region 14010A includes a multiple quantum well (MQW) structure.

[0177] 14B , the epitaxial structure 14020 further includes a current limiting layer 14104 selectively located between the active region 14020A and the top reflector 14020U or between the active region 14020A and the bottom reflector 14020L. The current limiting layer 14104 includes a current limiting area 14104B and a current conducting area 14104A surrounded by the current limiting area 14104B. The current conducting area 14104A has a higher conductivity than the current limiting area 14104B, allowing current to be concentrated in the current conducting area 14104A. In one or more embodiments, the current limiting layer 14104 includes aluminum oxide in the current limiting area 14104B.

[0178] 14A and 14B, the electrode 14050 is on the epitaxial structure 14020 and is electrically connected to the semiconductor layer of the top reflector 14020U. The electrode 14050 has a light exit opening O14 (see FIG. 14A) corresponding to the current conducting area 14104A of the current limiting layer 14104. The electrode 14030 is on the base layer 14010 and is electrically connected to the semiconductor layer of the bottom reflector 14020L. For example, in the embodiment shown in FIG. 14B, the electrode 14050 includes at least one metal layer and a P-type contact layer connected to the P-type semiconductor layer of the top reflector 14020U, and the electrode 14030 includes at least one metal layer connected to the base layer 14010 and electrically connected to the N-type semiconductor layer of the bottom reflector 14020L.

[0179] In one or more embodiments, as shown in FIG. 14B , the insulating layer 14040 is located between the epitaxial structure 14020 and the electrode 14050 and extends to the side surface E14 of the epitaxial structure 14020 to prevent the electrode 14050 from directly contacting the active region 14020A and the bottom reflector 14020L. The insulating layer 14040 is electrically insulating and comprises an inorganic or organic insulating material. In this embodiment, as shown in FIG. 14B , the insulating layer 14040 comprises a silicon oxide layer, although the application is not limited to this embodiment.

[0180] [Table 1A]

[0181] [Table 1B] Tables 1A and 1B are tables of ternary codes using decimal numbers and pattern codes. In one or more embodiments, as shown in Tables 1A and 1B, pattern codes of different shapes are provided to represent decimal numbers. For example, as shown in Tables 1A and 1B, the pattern codes of Group A include pattern codes of three shapes: a square, a parallelogram, and a triangle. In this embodiment, as shown in Tables 1A and 1B, the pattern codes of the three shapes of Group A represent three digits in a ternary system. For example, the pattern code for the square represents the digit "0," the pattern code for the parallelogram represents the digit "1," and the pattern code for the triangle represents the digit "2." Therefore, with reference to Tables 1A and 1B, the decimal number "998" can be converted to the ternary number "1100222," and the ternary number "1100222" is a pattern code of Group A.

number

[0182] 15A is a top view of a VCSEL chip 15000 having a pattern code according to an example embodiment. Referring to Table 1A, Table 1B, and FIG. 15A, in one or more embodiments, as shown in FIG. 15A, the electrode 15050 exposes at least one group of patterns 510, 511, 512 of the epitaxial structure 15020, and the patterns of the group are coded with the patterns of group A to provide identification of the VCSEL chip 15000. For example, the identification may be the location of the VCSEL chip 15000 in the epitaxial wafer, the serial number or manufacturing date of the VCSEL chip 15000, or other specific information of the VCSEL chip 15000.

[0183] Referring to Table 1A, Table 1B, Figures 15A and 15B, in this embodiment, as shown in Figures 15A and 15B, patterns 512, 511, and 510 are arranged in order from right to left along the horizontal direction, and the shape of pattern 510 is a square pattern code, the shape of pattern 511 is a parallelogram pattern code, and the shape of pattern 512 is a triangle pattern code. Therefore, in this embodiment, as shown in Figure 15, patterns 512, 511, and 510 of the group are arranged and are the pattern code of group A.

number

[0184] 15A-15B are different schematic diagrams illustrating a VCSEL chip according to one or more embodiments. FIG. 15B is a cross-sectional schematic diagram taken along line 15B-15B' in FIG. 15A. FIG. 15C-15D are top views of a VCSEL chip according to one or more embodiments.

[0185] In one or more embodiments, as shown in Figures 15A and 15C-15D, the electrodes have one or more groups of patterns in the epitaxial structure 15020. For example, in one embodiment, as shown in Figure 15A, the electrodes 15050 have two groups of patterns in the epitaxial structure 15020: a first group of patterns 510, 511, 512 and a second group of patterns 520, 521, 522. In this embodiment, as shown in Figure 15A, the patterns 520, 521, 522 are arranged along a direction different from the direction of the patterns 510, 511, 512 (in this embodiment, the vertical direction).

[0186] 15A and 15B, the pattern of the electrode 15050 may be an aperture structure of the electrode 15050. For example, as shown in FIG. 15B, patterns 520, 521, and 522 are aperture structures at different positions of the electrode 15050. These aperture structures 520, 521, 522 of different shapes may be fabricated during the manufacturing process of the VCSEL chip 15000 (i.e., fabricated in the epitaxial wafer state before the singulation process).

[0187] In one or more embodiments, as shown in FIG. 15C, the electrodes 15050 have two groups of patterns, and each group includes one or more patterns (eg, seven patterns).

[0188] In one or more embodiments, the electrode 15050 may have at least one group of patterns, and each group of patterns may be located in a corner region of the electrode 15050, as shown in FIG. 15D.

[0189] Figure 16 is a top view illustrating a VCSEL chip according to one embodiment. In one or more embodiments, as shown in Figure 16, the stacked structure of the VCSEL chip 16000 may further include an insulating layer 16060 covering the electrode 16050, and the insulating layer 16060 on the electrode 16050 may form at least one opening having a group of pattern structures 620-627, as shown in Figure 16. Thus, a group of patterns 520-526 corresponding to the pattern structures 620-627 of the opening in the insulating layer 16060 may appear on the electrode 16050.

[0190] 17A-17F are cross-sectional schematic views illustrating steps in a manufacturing process for the VCSEL chip 15000 shown in FIG. 15B according to one embodiment.

[0191] 17A, a stacked layer structure 1500 including a second-type semiconductor layer 15020L, an active layer 15020A, and a first-type semiconductor layer 15020U is epitaxially grown on a growth substrate 15100. The stacked layer structure 1500 may be formed on the growth substrate 15100 by an epitaxial process, including, but not limited to, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), etc. In this embodiment, the material of the growth substrate 15100 is GaAs, as shown in FIG. In other embodiments, the material of the growth substrate 15100 may be InP, a sapphire substrate, GaN, SiC, etc.

[0192] 17B, ​​a protective layer PL is formed on the stacked structure 1500, and then an etching process is performed to remove a part of the first-type semiconductor layer 15020U and a part of the active structure 15020A to expose a part of the surface of the second-type semiconductor layer 15020L, thereby forming the epitaxial structure 15020. In this embodiment, the protective layer PL is electrically insulating.

[0193] 17C , a current limiting layer 15104 is formed in the epitaxial structure 15020. In this embodiment, the current limiting area of ​​the current limiting layer 15104 is formed by an oxidation process. For example, the first-type semiconductor layer 15020U may include multiple AlGaAs layers, one or more of which have a higher aluminum content than the other layers, and then the current limiting layer 15104 may be formed on the layer or layers with the higher aluminum content by an oxidation process.

[0194] Next, as shown in FIG. 17D, an insulating layer 15040 is provided to cover the epitaxial structure 15020, and the insulating layer 15040 has an opening (not shown) that exposes a portion of the top surface of the epitaxial structure 15020.

[0195] Next, as shown in FIG. 17E, a metal layer having pattern structures 520, 521, 522 is formed on the insulating layer 15040 (for example, using an etching and masking process) to fill the openings in the insulating layer 15040, electrically connect the first-type semiconductor layer 15020U, and form an electrode 15050 having a group of pattern structures 520, 521, 522.

[0196] Next, as shown in Figure 17F, the growth substrate 15100 is thinned and a metal layer is formed on the thinned growth substrate 15100 to form the electrode 15030, forming a VCSEL chip as shown in Figures 15A and 15B.

[0197] 18A-18G are cross-sectional schematic diagrams illustrating steps in a manufacturing process for a VCSEL chip according to one embodiment, taken along line 18-18' in FIG. 16. FIG.

[0198] 18A , a stacked layer structure 1600 including a second-type semiconductor layer 16020L, an active layer 16020A, and a first-type semiconductor layer 16020U is epitaxially grown on a growth substrate 16100. The stacked layer structure 1600 may be formed on the growth substrate 16100 by an epitaxial process, including, but not limited to, metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, etc. In this embodiment, as shown in FIG. 18A , the material of the growth substrate 16100 is GaAs. In other embodiments, the material of the growth substrate 16100 may be InP, a sapphire substrate, GaN, SiC, etc.

[0199] Next, as shown in FIG. 18B, a protective layer PL is formed on the stacked structure 1600, and an etching process is performed to remove a portion of the first-type semiconductor layer 16020U and a portion of the active structure 16020A to expose a portion of the surface of the second-type semiconductor layer 16020L, thereby forming an epitaxial structure 16020.

[0200] 18C , a current limiting layer 16104 is formed in the epitaxial structure 16020. In this embodiment, the current limiting area of ​​the current limiting layer 16104 is formed by an oxidation process. For example, the first-type semiconductor layer 16020U may include multiple AlGaAs layers, one or more of which have a higher aluminum content than the other layers, and then the current limiting layer 16104 may be formed on the layer or layers with the higher aluminum content by an oxidation process.

[0201] For example, the aluminum content of at least one layer of the first-type semiconductor layer 16020U is higher than 97% (defined as the layer where the current limiting layer 16104 is to be formed) and higher than the aluminum content of the active layer 16020A and the second-type semiconductor layer 16020L. Therefore, during the oxidation process, the layer region of the epitaxial structure 16020 with a higher aluminum content (defined as the layer where the current limiting layer 16104 is to be formed) is oxidized faster from the side toward the inside at a faster rate than other regions, thereby forming a current limiting area with low conductivity in the current limiting layer 16104. Alternatively, the current limiting area with low conductivity can be formed in the epitaxial structure 16020 by an ion implantation process, and the current conducting area can be defined through a mask. The ion implantation is performed by implanting hydrogen ions (H + ), helium ions (He + ), or argon ions (Ar + ), the ion concentration in the current-restricting area is much higher than the ion concentration in the current-conducting area, causing the current-restricting area to have a relatively low conductivity.

[0202] Next, as shown in FIG. 18D, an insulating layer 16040 is provided to cover the epitaxial structure 16020, and the insulating layer 16040 has an opening (not shown) that exposes a portion of the top surface of the epitaxial structure 16020.

[0203] Next, as shown in FIG. 18E, a metal layer is formed on the insulating layer 16040, filling the opening to electrically connect the first-type semiconductor layer 16020U, and an electrode 16050 is formed.

[0204] Next, as shown in Figure 18F, an insulating layer 16060 having an opening (in which a group of pattern structures 620-627 is provided) is provided so as to cover the electrode 16050. As shown in Figures 18F and 16, the opening having the pattern structures 620-627 is formed on the electrode 16050. Therefore, a group of patterns 520-526 corresponding to the pattern structures 620-627 in the opening of the insulating layer 16060 may appear on the electrode 16050.

[0205] Next, as shown in FIG. 18G, the growth substrate 16100 is thinned, and a metal layer is formed on the thinned growth substrate 16100 to form the electrode 16030, thereby forming the VCSEL chip as shown in FIG.

[0206] In one or more embodiments, the pattern code may be formed on the side surface E14 of the epitaxial structure 14020 (see FIG. 14B), although the application is not limited to this embodiment.

[0207] Therefore, according to some embodiments, if a defect occurs later after a semiconductor having a pattern structure is laser-packaged and shipped from a factory, its position in the epitaxial wafer state, the manufacturing date, or the manufacturing batch number can be determined through the specific arrangement and combination of the pattern structure on the semiconductor laser chip, thereby achieving a traceability effect.

[0208] FIG. 19A is a schematic diagram showing the bottom / backside of an optoelectronic device epitaxial wafer 19001 (e.g., a VCSEL wafer) according to one embodiment. FIG. 19B is a schematic cross-sectional view taken along line 19B-19B' of FIG. 19A. FIG. 19C is a schematic cross-sectional view of a semiconductor laser chip 19000 (e.g., a VCSEL chip) cut from the optoelectronic device epitaxial wafer 19001 shown in FIG. 19A according to one embodiment. FIG. 19D is a cross-sectional view showing the semiconductor laser chip 19000 (e.g., a VCSEL chip) of FIG. 19C welded to a carrier board 19900.

[0209] 19A and 19B, a plurality of strip-shaped grooves G019 are formed by etching on the back surface of the epitaxial wafer 19001 (e.g., a VCSEL wafer) of the optoelectronic device. In some embodiments, after etching a portion of the base layer 19100 of the epitaxial wafer 19001 on the back surface 19001B (i.e., the base layer 19100 side of the epitaxial wafer 19001) of the epitaxial wafer 19001 of the optoelectronic device, the above-described singulation process method for the epitaxial wafer 19001 may be used to obtain semiconductor laser chips 19000 (e.g., VCSEL chips) having a plurality of base layers 19100 including step structures 19000S.

[0210] 19B and 19C, a strip-shaped groove G019 is etched into the back surface 19001B of an epitaxial wafer 19001 (e.g., a VCSEL wafer) of an optoelectronic device, so that a step structure 19000S having an etched pattern is held at the bottom of the VCSEL chip produced by the singulation process. Specifically, in one embodiment, the semiconductor laser chip 19000 includes a base layer 19100 and a semiconductor laminate layer 19020 formed on the base layer 19100. The base layer 19100 has a step structure 19000S on a side facing the semiconductor laminate layer 19020. An upper electrode 19030 and a lower electrode 19040 are further formed on the semiconductor laser chip 19000 (e.g., a VCSEL chip). The upper electrode 19030 is formed on the semiconductor laminate 19020 of the semiconductor laser chip 19000, and the lower electrode 19040 is formed on the bottom surface 19000B of the semiconductor laser chip 19000. The upper electrode 19030 is electrically connected to the first-type semiconductor layer of the semiconductor laminate 19020, and the lower electrode 19040 is electrically connected to the second-type semiconductor layer of the semiconductor laminate 19020 via the base layer 19100.

[0211] 19C and 19D, in the embodiment shown in FIG. 19D, a step structure having an etching pattern is provided on the bottom of the semiconductor laser chip 19000 (e.g., a VCSEL chip), so that the semiconductor laser chip 19000 (e.g., a VCSEL chip) can be welded at an angle to the carrier board 19900, thereby changing the light emission direction. That is, when the semiconductor laser chip 19000 is mounted on the carrier board 19900 (e.g., a circuit board) by soldering, the emission direction of the laser light emitted from the semiconductor laser chip 19000 is not parallel to the normal direction of the carrier board 19900 (the angle between the emission direction of the laser light and the normal direction of the carrier board 19900 is θ, i.e., the laser light is tilted by the angle θ). That is, the emission direction can be changed not only by attaching an optical element inside the light emission sensing package as in the above-described embodiment, but also by using the step structure formed on the bottom of the semiconductor laser chip 19000.

[0212] 19B and 19C, the etching pattern of the semiconductor laser chip 19000 (e.g., VCSEL chip) maintains a groove width L019 and a depth D019 that are substantially the same as or similar to those of the type of the epitaxial wafer 19001. Therefore, when the epitaxial wafer of the photoelectric device is pre-etched, the change angle of the light output direction of the semiconductor laser package body can be pre-set, and the width L019 and the depth D019 of the groove etching pattern are simultaneously formed on the bottom surface of the base layer 19100.

[0213] In some embodiments, the depth D019 is between 10 μm and 300 μm, depending on the size of the semiconductor laser and the desired change in the light output direction of the semiconductor laser.

[0214] 20 is a schematic cross-sectional view showing a VCSEL chip 20000 mounted on a carrier board 20900 and welded to an electrode pad 20900e of the carrier board 20900. Referring to Fig. 20, the upper electrode layer (first electrode structure 20020) of the VCSEL chip 20000 extends to the sidewall of the VCSEL chip 20000 and / or the sidewall of the base layer 20040, thereby increasing the electrode area of ​​the VCSEL chip 20000 and enabling it to be stably welded to the carrier board 20900. Furthermore, the planar size A of the VCSEL chip 20000 can be reduced, further improving the utilization rate of the VCSEL wafer.

[0215] FIG. 20 is a schematic cross-sectional view showing a VCSEL chip 20000 mounted on a carrier board 20900 and welded to an electrode pad 20900 e of the carrier board 20900 .

[0216] 20 , in this embodiment, the upper electrode layer (first electrode structure 20020) of the VCSEL chip 20000 extends to the sidewalls of the VCSEL chip 20000 and / or the sidewalls of the base layer 20040, thereby increasing the electrode area of ​​the VCSEL chip 20000 and enabling it to be stably welded to the carrier board 20900. Furthermore, the planar size A of the VCSEL chip 20000 can be reduced, further improving the utilization rate of the VCSEL wafer. In one or more embodiments, the carrier board 20900 may be a circuit board, a ceramic substrate, or the like.

[0217] In one or more embodiments, the VSCEL chip 20000 may include a single VCSEL structure, multiple VCSEL structures arranged in an array, or multiple of the aforementioned self-mixing interferometric sensing units arranged in an array.

[0218] In this embodiment, the VSCEL chip 20000 includes a base layer 20040 , a semiconductor stack 20010 , a first electrode structure 20020 , a second electrode structure 20050 , and an insulating layer 20030 .

[0219] The semiconductor laminate layer 20010 is located on the base layer 20040, and has a first surface 20011, a second surface 20012, and a side surface 20013. The second surface 20012 is located opposite the first surface 20011, and the side surface 20013 is located between the first surface 20011 and the second surface 20012. The semiconductor laminate layer 20010 includes a first-type semiconductor layer 20010U, a second-type semiconductor layer 20010L, and an active layer 20010A. The active layer 20010A is located between the first-type semiconductor layer 20010U and the second-type semiconductor layer 20010L.

[0220] The base layer 20040 is located on the opposite side of the first-type semiconductor layer 20010U from the second-type semiconductor layer 20010L. The base layer 20040 may be a growth substrate for the semiconductor laminate 20010, i.e., the semiconductor laminate 20010 is grown directly on the base layer 20040. The base layer 20040 is conductive and has a bottom 20041 and a boss 20042 extending from the bottom 20041. The boss 20042 has a boss surface 20042A (connected to the second surface 20012) and a boss side surface 20042B, which is connected to the boss surface 20042A. The bottom 20041 has a bottom first surface 20041A, a bottom second surface 20041B, and a bottom side surface 20041C. The first bottom surface 20041A is connected to the boss side surface 20042B, the second bottom surface 20041B is located opposite the first bottom surface 20041A, and the side bottom surface 20041C is located between the first bottom surface 20041A and the second bottom surface 20041B.

[0221] The insulating layer 20030 is located on the first surface 20011 and extends through the side surface 20013, the boss surface 20042A, and the boss side surface 20042B to the bottom first surface 20041A. The insulating layer 20030 has an opening 20031, the opening 20031 is located on the first surface 20011, and the first electrode structure 20020 is located within the opening 20031 and contacts the first-type semiconductor layer 20010U. The first electrode structure 20020 is further located on the first surface 20011 and extends through the side surface 20013, the boss surface 20042A, and the boss side surface 20042B to the bottom first surface 20041A. The insulating layer 20030 further extends through the bottom first surface 20041A to the bottom side surface 20041C.

[0222] The second-type semiconductor layer 20010L in the semiconductor laminate 20010 extends laterally and further includes platform portions 20012A and 20012B distributed on the boss surface 20042A, and the insulating layer 20030 and the first electrode structure 20020 are further located on the surfaces of the platform portions 20012A and 20012B. The second electrode structure 20050 is located on the bottom second surface 20041B.

[0223] Therefore, when the VSCEL chip 20000 is subsequently electrically bonded to the electrode pads 20900e on the carrier board 20900, the first electrode structure 20020 extends to the boss side surface 20042B, so that the bonding area between the electrode structure 20020 on one side of the VSCEL chip 20000 and the bonding structure CS (e.g., solder paste) bonded between the carrier board 20900 can be enlarged without increasing the size of the VSCEL chip 20000. In this way, when the VSCEL chip 2000 is packaged, the chip size can be reduced while maintaining the gaps between the electrode pads 20900e of the carrier board 20900.

[0224] In some embodiments, the height of the boss portion 20042 is 70 to 90 μm.

[0225] In some embodiments, the boss side surface 20042B of the boss portion 20042 has an included angle θ′ with respect to the boss surface 20042A, and the angle distribution range of the included angle θ′ is between 90 degrees and 120 degrees.

[0226] In one or more embodiments, the photoelectric module includes a light-emitting device, a light-receiving device, and a driver chip electrically connected to the light-emitting device and / or the light-receiving device.

[0227] In one or more embodiments, the light emitting device includes at least one semiconductor light source, such as a semiconductor laser, such as a VCSEL structure.

[0228] In one or more embodiments, the light receiving device includes at least one semiconductor sensor, such as a single-photon avalanche diode (SPAD).

[0229] FIG. 21 is a cross-sectional schematic diagram showing an optoelectronic module 21000 applicable as a time-of-flight ranging module according to one embodiment, in which the optoelectronic module 21000 includes an optical emission device 21020 mounted on a driver chip 21010, and the driver chip 21010 includes one or more SPADs 21030.

[0230] Referring to this embodiment, as shown in Fig. 21, the photoelectric module 21000 further includes a lens group 21011 mounted in the area of ​​the SPAD 21030. In this embodiment, as shown in Fig. 21, when the photoelectric module 21000 is applied as a time-of-flight ranging module, the driver chip 21010 provides an electrical signal, voltage or current to drive the light emitting device 21020 to irradiate light onto an object, and drive the SPAD 21030 to receive light reflected from the object. Furthermore, the light emitted by the light emitting device 21020 may be a patterned light source, and the pattern may be a point pattern, a line pattern, a plane pattern, or a mixture of two or more of the above patterns irradiated within a field of illumination (FOI).

[0231] Referring again to this embodiment, as shown in FIG. 21, a ball grid array (BGA) structure 21040 is disposed on the back surface 21010B of the driver chip 21010 (opposite the light emitting device 21020 and SPAD 21030), which can be electrically connected to a circuit board such as a printed circuit board (PCB).

[0232] FIG. 22 is a cross-sectional schematic diagram illustrating an embodiment of an emission module 22000, which integrates a flip-chip light-emitting device 22020, passive elements 22030, and a driver chip 22010. The light-emitting device 22020 may be directly mounted on the driver chip 22010, or the light-emitting device 22020 may be mounted on a carrier board, which may then be mounted on the driver chip 22010. The driver chip 22010 provides an electrical signal, voltage, or current to drive the light-emitting device 22020 as a light source and is electrically connected to a printed circuit board via a BGA structure 22040. The light source may be a point light source, a line light source, an area light source, or a patterned light source that combines two or more of the above light sources. One or more passive elements 22030 are used together with the driver chip 22010 to condition the electrical signal.

[0233] 23A is a schematic cross-sectional view of an emission module according to one embodiment. FIG. 23B is a schematic cross-sectional view of an emission module according to one embodiment. In one or more embodiments, as shown in FIGS. 23A and 23B , an emission module 23000 is provided, which integrates a light-emitting device 23020, a passive element 23030, a driver chip 23010, and a carrier board 23900. The light-emitting device 23020, the passive element 23030, and the driver chip 23010 are mounted on the carrier board 23900. The light-emitting device 23020, the passive element 23030, and the driver chip 23010 may be mounted on the same side of the carrier board 23900 or on different sides. The carrier board 23900 distributes power through multiple through-holes and multiple metal layers between the components (including the driver chip 23010, the light-emitting device 23020, and the passive elements 23030) and is electrically connected to the printed circuit board via a BGA structure 23040. The driver chip 23900 provides an electrical signal, voltage, or current to drive the light-emitting device 23020 as a light source. The light source may be a point light source, a line light source, an area light source, or a patterned light source that combines two or more of the above light sources, having an illumination area. In this embodiment, as shown in FIG. 23A , the driver chip 23010 is electrically connected to the carrier board 23900 via the BGA structure 23040. In one or more embodiments, as shown in FIG. 23B, the driver chip 23010 is electrically connected to the carrier board 23900 via wire-bonding, and a molding material 23060 covering the driver chip 23010 and the metal wires 23050 is required to protect the metal wires 23050.

[0234] In some embodiments, a bottom fill adhesive may be included between the driver chip 23010 and the carrier board 23900, where the bottom fill adhesive covers the BGA structure 23040.

[0235] In one or more embodiments, a light-emitting device includes a semiconductor, a spacer layer, a pattern layer, and a cover layer, as shown in Figures 24A-24C. Figure 24A is a schematic cross-sectional view of a light-emitting device according to one embodiment. Figure 24B is a schematic cross-sectional view of a light-emitting device according to one embodiment. Figure 24C is a schematic cross-sectional view of a light-emitting device according to one embodiment. The spacer layer surrounds the VCSEL chip and resembles a chip-scale package (CSP). The pattern layer includes one or more optical elements, such as a metasurface, a photonic crystal, a microlens array, or a diffractive optical element (DOE). In one embodiment, as shown in Figure 24A, light-emitting device 24000A includes a semiconductor layer 24010, a transparent base layer 24015, a spacer layer 24020, a first pattern layer 24031, and a cover layer 24040. A first pattern layer 24031 is formed on the top surface 24020T of the spacer layer 24020, and then a cover layer 24040 is formed on the first pattern layer 24031. The cover layer 24040 is used to prevent the first pattern layer 24031 from being damaged by scratches, moisture, solvents, etc. In one or more embodiments, the light-emitting device is integrated with a meta-interface optical element to shorten the optical focal length, thereby reducing the overall package height.

[0236] In one or more embodiments, the pattern layer may be a single layer or multiple layers and is formed between different interfaces, as shown in Figures 24A-24C. In one embodiment, as shown in Figure 24B, light-emitting device 24000B includes semiconductor layer 24010, transparent base layer 24015, spacer layer 24020, first pattern layer 24031, second pattern layer 24032, and cover layer 24040. In one embodiment, as shown in Figure 24C, light-emitting device 24000C includes semiconductor layer 24010, transparent base layer 24015, spacer layer 24020, first pattern layer 24031, second pattern layer 24032, third pattern layer 24033, and cover layer 24040. First pattern layer 24031 is formed on spacer layer 24020. Second pattern layer 24032 is formed between transparent base layer 24015 and spacer layer 24020. The third pattern layer 24033 is formed between the transparent base layer 24015 and the semiconductor layer 24010. It should be noted that since the transparent base layer 24015 is optically transparent to the light of the light-emitting device 24000, the object under the transparent base layer 24015 does not need to be clearly visible to the naked eye, and may be ultraviolet light, visible light, infrared light, etc., but the present application is not limited thereto.

[0237] In one or more embodiments, a light emitting device may integrate one or more patterned layers and be formed at different interfaces, as shown in Figures 25A-25E. Figure 25A is a schematic cross-sectional view of a light emitting device according to one embodiment. Figure 25B is a schematic cross-sectional view of a light emitting device according to one embodiment. Figure 25C is a schematic cross-sectional view of a light emitting device according to one embodiment. Figure 25D is a schematic cross-sectional view of a light emitting device according to one embodiment. Figure 25E is a schematic cross-sectional view of a light emitting device according to one embodiment.

[0238] 25A , light emitting device 25000A includes a semiconductor layer 25010, a first transparent base layer 25021, a first pattern layer 25031, and a covering layer 25040. First transparent base layer 25021 is located on semiconductor layer 25010, first pattern layer 25031 is formed on an upper surface 25021T of first transparent base layer 25021, and covering layer 25040 is located on first pattern layer 25031.

[0239] 25B , light emitting device 25000B includes semiconductor layer 25010, first transparent base layer 25021, first pattern layer 25031, second pattern layer 25032, and covering layer 25040. First transparent base layer 25021 is located on semiconductor layer 25010, second pattern layer 25032 is formed between first transparent base layer 25021 and semiconductor layer 25010, first pattern layer 25031 is formed on an upper surface 25021T of first transparent base layer 25021, and covering layer 25040 is located on first pattern layer 25031.

[0240] 25C, light-emitting device 25000C includes semiconductor layer 25010, first transparent base layer 25021, second transparent base layer 25022, and first pattern layer 25031. First transparent base layer 25021 is located on semiconductor layer 25010, first pattern layer 25031 is formed between two transparent base layers (first transparent base layer 25021 and second transparent base layer 25022), and an adhesive layer may further be located on one side of first pattern layer 25031.

[0241] In one or more embodiments, as shown in Figures 25C-25E, the light-emitting device may include stacked transparent base layers, and an adhesive layer may be interposed between the stacked transparent base layers.

[0242] 25C , light-emitting device 25000C includes semiconductor layer 25010, first transparent base layer 25021, first pattern layer 25031, and second transparent base layer 25022. Light-emitting device 25000C has second transparent base layer 25022 laminated to first pattern layer 25031. In some embodiments, first pattern layer 25031 may be formed on first transparent base layer 25021 or second transparent base layer 25022. Another adhesive layer may further be located between first transparent base layer 25021 and second transparent base layer 25022.

[0243] 25D , light-emitting device 25000D includes semiconductor layer 25010, first transparent base layer 25021, adhesive layer 25050, second transparent base layer 25022, and pattern layer 25030. First transparent base layer 25021 is located on semiconductor layer 25010, second transparent base layer 25022 is adhered to first transparent base layer 25021 using adhesive layer 25050, and pattern layer 25030 is formed on second transparent base layer 25022.

[0244] 25E, light-emitting device 25000E includes semiconductor layer 25010, first transparent base layer 25021, follower layer 25050, second transparent base layer 25022, pattern layer 25030, and third transparent base layer 25023. First transparent base layer 25021 is located on semiconductor layer 25010, second transparent base layer 25022 is adhered to first transparent base layer 25021 using adhesive layer 25050, and pattern layer 25030 is formed on second transparent base layer 25022, and third transparent base layer 25023 covers pattern layer 25030 to prevent scratches, moisture, or solvents, thereby preventing the optical function of pattern layer 25030 from being impaired.

[0245] FIG. 26 is a cross-sectional schematic diagram illustrating a laser element according to one embodiment. In one or more embodiments, the light-emitting device may be a laser element, as shown in FIG. 26. Referring to this embodiment, as shown in FIG. 26, the laser element 26000 includes a transparent base layer 26001, an adhesive layer 26002, a laser unit 26003, and a plurality of first channels 26034. The transparent base layer 26001 includes a conductive layer 26010. As an example, the transparent base layer 26001 includes sapphire, glass, or silicon carbide (SiC). In some embodiments, the transparent base layer 26001 is an optical element and can be patterned to generate specific optical effects. For example, the optical element allows the light-emitting device to generate a patterned light source, such as a point light source, a surface light source, or a multi-pattern light source, including a predetermined field of illumination (FOI). The conductive layer 26010 includes a transparent conductive oxide or metal. The transparent conductive film may be indium tin oxide (ITO), indium zinc oxide (IZO), etc. In this embodiment, the conductive layer 26010 is provided between the transparent base layer 26001 and the adhesive layer 26002.

[0246] One side of the adhesive layer 26002 is connected to the conductive layer 26010 of the transparent base layer 26001, and the other side is connected to the light-emitting side 26003S of the laser unit 26003. As an example, the adhesive layer 26002 may be benzocyclobutene (BCB), silicon dioxide, or a transparent conductive film.

[0247] The laser unit 26003 includes a front conductive structure 26030, a first-type semiconductor layer 26031, an active layer 26033, a second-type semiconductor layer 26035, an insulating layer 26036, and a back conductive structure 26032. The back conductive structure 26032 includes conductive electrodes 26032C and 26032D separated from each other. Here, the first type and second type refer to semiconductor structures with different electrical properties. If a semiconductor structure has holes as majority carriers, it is a p-type semiconductor. If a semiconductor structure has electrons as majority carriers, it is an n-type semiconductor. As an example, the first-type semiconductor layer 26031 is an n-type semiconductor and the second-type semiconductor layer 26035 is a p-type semiconductor, or vice versa. The active layer 26033 is located between the first-type semiconductor layer 26031 and the second-type semiconductor layer 26035 and includes a p-n junction that creates a depletion area where electrons and holes recombine to emit light. In some embodiments, the active layer 26033 is composed of multiple quantum wells, thereby having better light-emitting efficiency than a p-n junction, but is not limited to this. In one embodiment, the materials of the first-type semiconductor layer 26031, the second-type semiconductor layer 26035, and the active layer 26033 include III-V compound semiconductors such as GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, or AlGaAsP. In the embodiments of the present application, unless otherwise specified, the above chemical formulas include "stoichiometric compounds" and "non-stoichiometric compounds." A "stoichiometric compound" is, for example, a compound in which the total elemental content of group III elements is the same as the total elemental content of group V elements, while a "non-stoichiometric compound" is, for example, a compound in which the total elemental content of group III elements is different from the total elemental content of group V elements. As an example, the chemical formula AlGaAs means containing aluminum (Al) and / or gallium (Ga) of group III elements and arsenic (As) of group V, and the total elemental content of group III elements (aluminum and / or gallium) may be the same as or different from the total elemental content of group V element (arsenic). Furthermore, when each compound represented by the above chemical formula is a stoichiometric compound, AlGaAs is a compound in which Alx1 Ga (1-x1) As, where 0≦x1≦1, and AlInP represents Al x2 In (1-x2) P, where 0≦x2≦1, and AlGaInP is (Al y1 Ga (1-y1) ) 1-x3 In x3 P, where 0≦x3≦1, 0≦y1≦1, and AlGaN is Al x4 Ga (1-x4) N, where 0≦x4≦1, and AlAsSb is AlAs x5 Sb (1-x5) where 0≦x5≦1, and InGaP is In x6 Ga 1-x6 P, where 0≦x6≦1, and InGaAsP is In x6 Ga 1-x6 As 1-y2 P y2 where 0≦x6≦1, 0≦y2≦1, and InGaAsN is In x8 Ga 1-x8 As 1-y3 N y3 where 0≦x8≦1, 0≦y3≦1, and AlGaAsP is Al x9 Ga 1-x9 As 1-y4 P y4 where 0≦x9≦1, 0≦y4≦1, and InGaAs is In x10 Ga 1-x10represents As, where 0≦x10≦1. Depending on the material of the active layer 26033, if the material of the semiconductor layers 26031 and 26035 is AlGaAs-based, the active layer 26033 can emit infrared light with a peak wavelength of 700 nm to 1700 nm. If the material of the semiconductor layers 26031 and 26035 is AlGaInP-based, the active layer 26033 can emit red light with a peak wavelength of 610 nm to 700 nm or yellow light with a peak wavelength of 530 nm to 570 nm. If the material of the semiconductor layers 26031 and 26035 is InGaN-based, the active layer 26033 can emit blue or deep blue light with a peak wavelength of 400 nm to 490 nm or green light with a peak wavelength of 490 nm to 550 nm. When the semiconductor layers 26031 and 26035 are made of AlGaN-based material, the active layer 26033 can emit ultraviolet light with a peak wavelength of 250 nm to 400 nm.

[0248] In this embodiment, the first-type semiconductor layer 26031 and the second-type semiconductor layer 26035 include a DBR structure, so that the light emitted from the active layer 26033 is reflected back and forth between the two DBR structures to form coherent light, and then the coherent light is emitted from the direction of the first-type semiconductor layer 26031 to form laser light L26.

[0249] In this embodiment, the insulating layer 26036 is located between the backside conductive structure 26032 and the second-type semiconductor layer 26035, as shown in Figure 26. In one embodiment, the material of the protective layer 26036 includes silicon oxide.

[0250] In this embodiment, the contact resistance between the back conductive structure 26032 and the second-type semiconductor layer 26035 is 10 -4 Ωcm 2The metal content of the second conductive electrode 26032D of the back conductive structure 26032 is lower than that of the second-type semiconductor layer 26035, and an ohmic contact is formed between the back conductive structure 26032 and the second-type semiconductor layer 26035. The mechanism for forming an ohmic contact is that the work function of the metal must be smaller than that of the semiconductor, so that electrons can easily jump this energy level from the semiconductor to the metal and vice versa, allowing current to be conducted in both directions. As an example, the metal component of the second conductive electrode 26032D of the back conductive structure 26032 is mainly a titanium-aluminum alloy. This is because titanium can form titanium nitride with the III-V compound (e.g., aluminum gallium nitride) of the second-type semiconductor layer 26035, and the surface where nitrogen atoms exist becomes an n-type doped surface, which can form a good ohmic contact by high-temperature annealing, but is not limited to this.

[0251] In this embodiment, as shown in FIG. 26, the first-type semiconductor layer 26031 is Front conductive structure Connected to 26030, Front conductive structure 26030 is connected to conductive electrode 26032C through second channel 26320, conductive electrode 26032D and conductive electrode 26032C are isolated from each other to avoid short circuiting, and second-type semiconductor layer 26035 is connected to second conductive electrode 260324. To prevent the conductive medium filled in second channel 26320 from contacting second-type semiconductor layer 26035 of laser unit 26003 and forming a short circuit, laser unit 26003 further includes insulating layer 26340 located on the inner wall of second channel 26320. Through the above conductive structure, laser unit 26003 receives external driving voltage / current and generates laser light L26. Front conductive structure26030 is located on the light output side 26003S of the laser unit 26003 and is connected to the adhesive layer 26002. Therefore, the laser light L26 emitted from the laser unit 26003 passes through the adhesive layer 26002 and the transparent base layer 26001 and is output to the outside. Note that since the transparent base layer 26001 is optically transparent to the light L26 of the laser unit 26003, the object below the transparent base layer 26001 does not need to be clearly visible to the naked eye, and may be ultraviolet light, visible light, infrared light, etc., although the present application is not limited thereto.

[0252] In one or more embodiments, when a time-of-flight ranging module having the laser element 26000 is applied to a living body part (e.g., a human face or a human eye), the coherent light emitted from the laser element 26000 has higher energy, so a corresponding optical element (e.g., a transparent base layer) is required to process the coherent light and output laser light L26 with an appropriate intensity. To effectively monitor whether the laser element 26000 is damaged and prevent laser light L26 that has not been optically processed by the transparent base layer 26001 from leaking and directly irradiating human eyes, the laser element 26000 of this embodiment includes an eye safety monitoring circuit that can instantly monitor for abnormal damage to the light output side 26003S of the laser unit 26003. The following examples describe the operation principles of the laser element 26000 of some embodiments.

[0253] 26 , in addition to the aforementioned semiconductor structures necessary for emitting laser light, the laser unit 26003 further includes a back conductive structure 26032. The back conductive structure 26032 includes a plurality of detection electrodes 26032A, 26032B, and the back conductive structure 26032 and the front conductive structure 26030 are disposed opposite each other on both sides of the laser unit 26003. A plurality of first channels 26034 extend from the back conductive structure 26032, penetrate the front conductive structure 26030 and the adhesive layer 26002, and are connected to the conductive layer 26010. In other words, in this embodiment, both ends of the first channel 26034 are connected to the plurality of detection electrodes 26032A, 26032B and the conductive layer 26010, respectively. In some embodiments, the multiple, mutually separated detection electrodes 26032A, 26032B are connected across the conductive layer 26010 via the first channel 26034. Therefore, by connecting the multiple detection electrodes 26032A, 26032B to an external control circuit, changes in the resistance of the conductive layer 26010 can be monitored in real time. If the laser element 26000 is damaged by external impact, particularly if the light-emitting side 26003S is damaged, the conductive layer 26010 may also be damaged, causing an increase in resistance or even a circuit break due to the damage. Therefore, the control circuit determines whether to cut off the power supply to the laser unit 26003 via the monitoring circuit in response to changes in the resistance of the conductive layer 26010. This prevents the laser light L26 emitted from the laser unit 26003 from leaking through damaged gaps in the transparent base layer 26001 and directly irradiating the human eye, thereby achieving the effect of monitoring abnormal conditions in real time.

[0254] In this embodiment, as shown in FIG. 26, the conductive medium filled in the first channel 26034 is Front conductive structure To avoid contact with 26030, the first-type semiconductor layer 26031, or the second-type semiconductor layer 26035 and forming a short circuit, the laser unit 26003 further includes an insulating layer 26340 located between the inner wall of the laser unit 26003 and the first channel 26034.

[0255] In some embodiments, the backside conductive structure 26032 is 26 26 includes a plurality of detection electrodes 26032A, 26032B and a plurality of conduction electrodes 26032C, 26032D that are separated from each other and coplanar. This makes the laser device suitable for flip-chip connection to a carrier board, such as the driver chip shown in FIG. 26 , without the need for a wire bonding process, thereby saving package volume. In one or more embodiments, the back conductive structure 26032 includes a plurality of detection electrodes 26032A, 26032B, and the plurality of detection electrodes 26032A, 26032B extend from the back conductive structure 26032 through the front conductive structure 26030 and the adhesive layer 26002 to connect to the conductive layer 26010.

[0256] In one or more embodiments, the light emitting device may be a laser element, as shown in Figures 27A-27C. Figure 27B is a top view of laser element 27000 shown in Figure 27A (as viewed from the direction of arrow C in Figure 27A, i.e., from the direction of first pad structure 27902 and second pad structure 27904), and Figure 27A is a schematic cross-sectional view taken along line AA' in Figure 27B. Figure 27C is a top view of laser element 27000 shown in Figure 27A, i.e., as viewed from the direction of transparent base layer 27010 (as shown by arrow D in Figure 27A), and Figure 27A is a schematic cross-sectional view taken along line B-B' in Figure 27C.

[0257] 27A is a cross-sectional view illustrating a semiconductor light-emitting device according to one embodiment. In this embodiment, the semiconductor light-emitting device is a laser device 27000 and includes a transparent base layer 27010 and an epitaxial structure 27020 located on one side of the transparent base layer 27010. The epitaxial structure 27020 includes at least one pillar structure P27. In this embodiment, the epitaxial structure 27020 includes a plurality of pillar structures P27. Each pillar structure P27 includes a first semiconductor structure 27202, a current limiting layer 27205, and an active structure 27204, which are sequentially arranged on the transparent base layer 27010.

[0258] The plurality of pillar structures P27 may be arranged in a regular or random array in the second semiconductor structure 27206. The so-called regular array means that the plurality of pillar structures P27 have a specific spatial relationship and are arranged in a fixed, repetitive manner. For example, among the regularly arranged pillar structures P27, the gaps between adjacent pillar structures P27 may be substantially the same, while in other cases, the plurality of pillar structures P27 may be arranged along a specific direction. Each pillar structure P27 includes a top surface P271 facing the transparent base layer 27010 and a side surface P272 connecting the top surface P271 and the second semiconductor structure 27206. Furthermore, the epitaxial structure 27020 further includes a bottom surface 27206B away from the transparent base layer 27010, which is the surface of the second semiconductor structure 27206. In this embodiment, the conductivity type of the first semiconductor structure 27202 is P-type, and the conductivity type of the second semiconductor structure 27206 is N-type. For ease of explanation, only five pillar structures P27 are shown in Fig. 27A as an example. However, in an actual VCSEL product, the number of pillar structures P27 can be adjusted according to the current and power requirements during use, and may be, for example, but not limited to, 100 to 1000.

[0259] 27A-27C, current limiting layer 27205 may be selectively located between active structure 27204 and first semiconductor structure 27202 or between active structure 27204 and second semiconductor structure 27206. Current limiting layer 27205 includes current limiting area 27205B and current conducting area 27205A surrounded by current limiting area 27205B. Because the conductivity of current conducting area 27205A is higher than the conductivity of current limiting area 27205B, current is concentrated in current conducting area 27205A.

[0260] In this embodiment, as shown in FIGS. 27A to 27C, the first semiconductor structure 27202 and the active structure 27204 partially cover the second semiconductor structure 27206, exposing an end surface 27206A of the second semiconductor structure 27206. The laser device 27000 further includes a first insulating layer 27032 and a first metal connecting layer 27034. The first insulating layer 27032 covers the side surface P272 of the pillar-shaped structure P27, the end surface 27206A of the second semiconductor structure 27206, and a portion of the top surface P271 of the pillar-shaped structure P27. The first insulating layer 27032 has a plurality of first openings 27322, exposing a portion of the top surface P271 from the first insulating layer 27032. The first metal contact layer 27034 is located on the first insulating layer 27032 and is electrically connected to the first semiconductor structure 27202 through the first opening 27322. The first metal contact layer 27034 has a plurality of second openings 27342, through which light emitted by the active structure 27204 is emitted toward the transparent base layer 27010 and out of the laser element 27100. Furthermore, the second semiconductor structure 27206 has a first side edge 27342. S271 , and a second side S2712 opposite the first side S271. The first metal connection layer 27034 has a first protrusion 27341a extending beyond the first side S271 and a second protrusion 27341b extending beyond the second side S272. The first protrusion 27341a and the second protrusion 27341b are used for subsequent electrical connection. The detailed structure and electrical connection method will be described later.

[0261] In this embodiment, as shown in FIGS. 27A to 27C, the laser element 27000 further includes an adhesive layer 27040, and the epitaxial structure 27020 is connected to the transparent base layer 27010 via the adhesive layer 27040. A second metal connection layer 27050 is provided in the second semiconductor structure 270206 at a position away from the transparent base layer 27010, and the second metal connection layer 27050 is electrically connected to the second semiconductor structure 27206. The laser element 27000 of the present application also includes a second insulating layer 27060, and the second insulating layer 27060 covers the second metal connection layer 27050. The second insulating layer 27060 has two sides 27060A. Four openings (first opening 27602a, second opening 27602b, third opening 27602c, and fourth opening 27602d) further penetrate the second insulating layer 27060. Side 27060A covers a first side edge S271 and a second side edge S2712 of second semiconductor structure 27206. First opening 27602a further penetrates the first insulating layer 27032 to expose a first protrusion 27341a of first metal connecting layer 27034, and second opening 27602b further penetrates the first insulating layer 27032 to expose a second protrusion 27341b of first metal connecting layer 27034. Second insulating layer 27060 further has a fifth opening 27603 exposing second metal connecting layer 27050. The laser element 27000 of the present application includes a first electrode 27702 and a second electrode 27704, which are located on the same side of the transparent base layer 27010 and are physically separated from each other.

[0262] In this embodiment, as shown in FIGS. 27A to 27C, the laser element 27000 is a flip-chip type laser element, which can then be bonded to an external carrier board (e.g., a printed circuit board or a driver chip 21010 as shown in FIG. 21) using solder through a flip-chip bonding process. The first electrode 27702 is connected to the first metal connection layer 27034 through the first opening 27602a to the fourth opening 27602d, respectively, and is electrically connected to the first semiconductor structure 27202 through the first protrusion 27341a and the second protrusion 27341b of the first metal connection layer 27034. Furthermore, the first electrode 27702 covers the side portion 27060A of the second insulating layer 27060 and extends to cover the second metal connection structure 27050. The second insulating layer 27060 is located between the first electrode 27702 and the second metal connection structure 27050 to prevent the formation of a short-circuit path. The second electrode 27704 is connected to the second metal contact layer 27050 through the fifth opening 27603 , thereby electrically connecting the second electrode 27704 to the second semiconductor structure 27206 .

[0263] 27A to 27C , the laser element 27000 of the present application may further include a first pad structure 27902 and a second pad structure 27904 located on the first electrode 27702 and the second electrode 27704, respectively. The laser element 27000 of the present application further includes a third insulating layer 27080 covering the first electrode 27702 and the second electrode 27704. The third insulating layer 27080 has a first hole 27802 exposing the first electrode 27702 and a second hole 27804 exposing the second electrode 27704. The first pad structure 27902 is electrically connected to the first electrode 27702 via the first hole 27802, and the second pad structure 27904 is electrically connected to the second electrode 27904 via the second hole 27804. Furthermore, there is a gap G27 of 10 μm to 200 μm between the first pad structure 27902 and the second pad structure 27904. In this embodiment, from the bottom view of the laser element 27000, the shape of the first pad structure 27902 is different from the shape of the second pad structure 27904 for electrical identification.

[0264] 27A to 27C, the laser element 27000 of the present application may optionally include an antireflection structure 27101 located on the transparent base layer 27010 and spaced apart from the first electrode 27702 and the second electrode 27704. The antireflection structure 27101 is used to reduce reflection of light emitted from the laser element 27000 at the interface between the transparent base layer 27010 and air, thereby avoiding a decrease in the light-emitting efficiency of the laser element 27000 and the occurrence of unexpected light patterns.

[0265] 27A to 27C , first semiconductor structure 27202 and second semiconductor structure 27206 are formed by periodically stacking multiple layers with different refractive indices (e.g., by periodically stacking AlGaAs layers with a high aluminum content and AlGaAs layers with a low aluminum content) to form a DBR structure, and light emitted from active structure 27204 can be reflected between the two DBR structures to form coherent light. The reflectivity of first semiconductor structure 27202 is lower than the reflectivity of second semiconductor structure 27206, which causes the coherent light to be emitted toward transparent base layer 27010. Materials of first semiconductor structure 27202, second semiconductor structure 27206, and active structure 27204 include III-V compound semiconductors, such as AlGaInAs-based, AlGaInP-based, AlInGaN-based, AlAsSb-based, InGaAsP-based, InGaAsN-based, and AlGaAsP-based compounds, such as AlGaInP, GaAs, InGaAs, AlGaAs, GaAsP, GaP, InGaP, AlInP, GaN, InGaN, or AlGaN. In the present application, unless otherwise specified, the above chemical formulas include "stoichiometric compounds" and "non-stoichiometric compounds." A "stoichiometric compound" is, for example, a compound in which the total elemental content of group III elements is the same as the total elemental content of group V elements, while a "non-stoichiometric compound" is, for example, a compound in which the total elemental content of group III elements is different from the total elemental content of group V elements. As an example, the chemical formula of the AlGaInAs system means that it contains aluminum (Al) and / or gallium (Ga) and / or indium (In) of group III elements and arsenic (As) of group V element, and the total element content of the group III elements (aluminum and / or gallium and / or indium) may be the same as or different from the total element content of the group V element (arsenic). Also, when each compound represented by the above chemical formula is a stoichiometric compound, the AlGaInAs system is represented by (Al y1 Ga (1-y1) ) 1-x1 In x1 As, where 0≦x1≦1 and 0≦y1≦1; AlGaInP system is (Al y2 Ga (1-y2)) 1-x2 In x2 P, where 0≦x2≦1, 0≦y2≦1, and the AlInGaN system is (Al y3 Ga (1-y3) ) 1-x3 In x3 N, where 0≦x3≦1, 0≦y3≦1, and the AlAsSb system is AlAs x4 Sb (1-x4) where 0≦x4≦1. InGaAsP system is In x5 Ga 1-x5 As 1-y4 P y4 where 0≦x5≦1, 0≦y4≦1, and the InGaAsN system is In x6 Ga 1-x6 As 1-y5 N y5 where 0≦x6≦1, 0≦y5≦1, and the AlGaAsP system is Al x7 Ga 1-x7 As 1-y6 P y6 where 0≦x7≦1 and 0≦y6≦1.

[0266] Depending on the material, active structure 27204 can emit infrared light with a peak wavelength of 700 nm to 1700 nm, red light with a peak wavelength of 610 nm to 700 nm, yellow light with a peak wavelength of 530 nm to 570 nm, green light with a peak wavelength of 490 nm to 550 nm, blue or deep blue light with a peak wavelength of 400 nm to 490 nm, or ultraviolet light with a peak wavelength of 250 nm to 400 nm. In this embodiment, the peak wavelength of active structure 27204 is infrared light with a peak wavelength of 750 nm to 1200 nm.

[0267] The material of current limiting layer 27205 may be the aforementioned III-V semiconductor material. In this embodiment, as shown in FIGS. 27A to 27C , the material of current limiting layer 27205 is AlGaAs, and active structure 27204, first semiconductor structure 27202, and second semiconductor structure 27206 are made of a material containing aluminum. The aluminum content of current limiting layer 27205 is greater than the aluminum content of active structure 27204, first semiconductor structure 27202, and second semiconductor structure 27206. As an example, the aluminum content of current limiting layer 27205 is greater than 97%. In this embodiment, the oxygen content of current limiting area 27205B of current limiting layer 27205 is greater than the oxygen content of current conducting area 27205A, so that the conductivity of current limiting area 27205B is lower than that of current conducting area 27205A. The adhesive layer 27040 is made of a material having a high optical transmittance to the light emitted from the active structure 27204, for example, an optical transmittance of greater than 80%, and the material of the adhesive layer 27040 is an insulating material such as benzocyclobutene resin (BCB), epoxy resin, polyimide, spin-on glass (SOG), silicone, or perfluorocyclobutane (PFCB).

[0268] In this embodiment, as shown in FIGS. 27A to 27C, the first insulating layer 27032, the second insulating layer 27060, and the third insulating layer 27080 are made of non-conductive materials. The non-conductive materials include organic materials and inorganic materials. The organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin copolymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic materials include silicone, glass, aluminum oxide (Al2O3), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), magnesium fluoride (MgF x In one embodiment, the first insulating layer 27032, the second insulating layer 27060, and / or the third insulating layer 27080 may include one or more layers (e.g., SiO x Sublayer and TiO x The DBR structure is formed by alternately stacking two sublayers, such as a single sublayer.

[0269] In this embodiment, as shown in FIGS. 27A to 27C, the material of the first metal connection layer 27034 and the second metal connection layer 27050 may include metals such as aluminum (Al), silver (Ag), chromium (Cr), platinum (Pt), nickel (Ni), germanium (Ge), beryllium (Be), gold (Au), titanium (Ti), tungsten (W), and zinc (Zn). The material of the first electrode 27702 and the second electrode 27704 may be metal materials such as gold (Au), tin (Sn), and titanium (Ti), or alloys thereof. In this embodiment, the first electrode 27702 may have a multilayer electrode structure and may include, for example, a titanium (Ti) layer and a gold (Au) layer in a direction away from the transparent base layer 27010. The second electrode 27704 includes the same material and structural configuration as the first electrode 27702. The material of the first pad structure 27902 and the second pad structure 27904 is a metal material such as gold (Au), tin (Sn), titanium (Ti), copper (Cu), nickel (Ni), platinum (Pt), or an alloy thereof. The material of the first electrode 27702 is different from the material of the first pad structure 27902, and the material of the second electrode 27704 is different from the material of the second pad structure 27904. As an example, the first pad structure 27902 and the second pad structure 27904 contain one element, and the first electrode 27702 and the second electrode 27704 do not contain the element, thereby preventing external (tin-containing) solder from damaging the first electrode 27702 and the second electrode 27704 and causing electrical failure during solid-state crystal or high-current operation, thereby further improving the reliability of the laser device 27000 of the present invention. The above elements can be used to prevent the solder from diffusing into the first electrode 27702 and the second electrode 27704. The elements are, for example, nickel (Ni) and / or platinum (Pt). Specifically, the first pad structure 27902 and the second pad structure 27904 may each be a multi-layer structure including, in a direction away from the transparent base layer 27010, an intermediate layer 27902A, an intermediate layer 27904A, a bonding layer 27902B, and a bonding layer 27904B.The material of intermediate layers 27902A, 27904A is different from that of first electrode 27702 and second electrode 27704, thereby preventing the solder (e.g., tin or gold-tin alloy (AuSn)) from diffusing into first electrode 27702 and second electrode 27704. Therefore, the material of intermediate layers 27902A, 27904A preferably includes a metal element other than gold (Au), tin (Sn), and copper (Cu), such as nickel (Ni) and / or platinum (Pt). Materials for bonding layers 27902B, 27904B include highly ductile metal materials such as gold (Au). In this embodiment, the materials of the intermediate layers 27902A and 27904A are platinum (Pt) and nickel (Ni), which are stacked in this order in a direction away from the transparent base layer 27010, and the material of the bonding layers 27902B and 27904B is gold (Au). In other words, in a direction away from the transparent base layer 27010, the first pad structure 27902 and the second pad structure 27904 include a nickel layer, a platinum layer, and a gold layer.

[0270] 27A and 27B, the transparent base layer 27010 has a middle area and a peripheral area surrounding the middle area. The second insulating layer 27060 has a plurality of openings (e.g., a first opening 27602a, a second opening 27602b, a third opening 27602c, and a fourth opening 27602d) distributed throughout the peripheral area of ​​the transparent base layer 27010. Furthermore, four spacers G271 to G274 are present between the four openings. More specifically, in this embodiment, the first opening 27602a and the fourth opening 27602d are separated by a first gap G271, the first opening 2760a2 and the second opening 27602b are separated by a second gap G272, the second opening 27602b and the third opening 27602c are separated by a third gap G273, and the third opening 27602c and the fourth opening 27602d are separated by a fourth gap G274.

[0271] Furthermore, as shown in FIG. 27C , in this embodiment, a plurality of marking structures 27344A-27344D are formed on the first metal connection layer 27034, which is convenient for machine identification and facilitates subsequent packaging processes. The marking structures 27344B and 27344D are connected to each other to define a connecting line L1, and the marking structures 27344A and 27344C are connected to each other to define a connecting line L2. The connecting lines L1 and L2 intersect at a center position O27. Referring to FIGS. 27B and 27C , the marking structure 27344A corresponds to the first gap G271, the marking structure 27344B corresponds to the second gap G272, the marking structure 27344C corresponds to the third gap G273, and the marking structure 27344D corresponds to the fourth gap G274. Note that the dotted lines in Figures 27B and 27C indicate that the structure cannot be directly observed from the bottom / top views, and only the dotted outlines are visible.

[0272] In this embodiment, the second-type semiconductor structure 27206 may be located in the central area of ​​the transparent base layer 27010. In one embodiment, the distances from any side of the second-type semiconductor structure 27206 to the boundary of the adjacent transparent base layer 27010 are approximately equal, so that the first pad structure 27902 and the second pad structure 27904 (or the first electrode 27702 and the second electrode 27704) can be symmetrical about the connecting line L1, which is advantageous for the structural design of the subsequent packaging process and increases the effective area. As shown in FIG. 27B , when viewed from the direction from the second semiconductor structure 27206 toward the active structure 27204 of the laser element 27000, the transparent base layer 27010 has a first boundary C271 adjacent to the first side S271 and a second boundary C272 located opposite the first boundary C271 and adjacent to the second side S272. The first boundary C271 and the second boundary C272 correspond to each other and are located on the sides of the transparent base layer 27010. The difference between the first distance D271 between the first side S271 and the first boundary C271 and the second distance D272 between the second side S272 and the second boundary C272 is less than 30% of the first distance D271. That is, the difference between the first distance D271 and the second distance D272 is 0≦(D271−D272) / D271<30%, and in another embodiment, 0≦(D271−D272) / D271<20%, preferably 0≦(D271−D272) / D271<15%. In another embodiment, 1%<(D271−D272) / D271<10%. In this embodiment, the first distance D271 is equal to the second distance D272.

[0273] In one or more embodiments, the light emitting device may be a semiconductor light emitting device 28000, as shown in FIG.

[0274] 28 is a schematic cross-sectional view of a semiconductor light emitting device 28000 according to one embodiment. The semiconductor light emitting device 28000 of this embodiment is a laser diode and includes a base 28110, an epitaxial stacked layer 28120 formed on the base 28110, and a first electrode structure 28132 and a second electrode structure 28134 located on the epitaxial stacked layer 28120. The base 28110 is a highly transmittance gallium arsenide (GaAs) substrate and has a first surface 28110A and a second surface 28110B. The light emitting surface of the semiconductor light emitting device 28100 (the direction indicated by the arrow in FIG. 28) is defined as the first surface 28110A. The epitaxial stack 28120 is located on the second surface 28110B of the base 28110 and includes, in order, a first semiconductor structure 28121, a second semiconductor structure 28122, an intermediate layer 28123, a third semiconductor structure 28124, an active structure 28126, and a fourth semiconductor structure 28127.

[0275] In this embodiment, as shown in FIG. 28 , the base 28110 contains a dopant to have p-type or n-type conductivity. Alternatively, in another embodiment, the base 28110 does not contain a dopant, or the base 28110 is an undoped base layer. The first semiconductor structure 28121 is made of a semiconductor material that does not contain a dopant, which reduces the problem of light absorption by dopants. The second semiconductor structure 28122, the intermediate layer 28123, the third semiconductor structure 28124, and the fourth semiconductor structure 28127 are made of semiconductor materials that contain a dopant. The second semiconductor structure 28122, the intermediate layer 28123, and the third semiconductor structure 28124 have the same conductivity type, and the third semiconductor structure 28124 (or the second semiconductor structure 28122 or the intermediate layer 28123) and the fourth semiconductor structure 28127 have different conductivity types. In this embodiment, the conductivity type of second semiconductor structure 28122, intermediate layer 28123, and third semiconductor structure 28124 is p-type, and the conductivity type of fourth semiconductor structure 28127 is n-type. In another embodiment, the conductivity type of second semiconductor structure 28122, intermediate layer 28123, and third semiconductor structure 28124 is n-type, and the conductivity type of fourth semiconductor structure 28127 is p-type. First electrode structure 28132 and second electrode structure 28134 are located on fourth semiconductor structure 28127. Dopants may include beryllium, magnesium, zinc, carbon, silicon, antimony, or the like.

[0276] 28 , optionally, the third semiconductor structure 28124 or the fourth semiconductor structure 28127 includes a current limiting layer 28125. Alternatively, in this embodiment, the current limiting layer 28125 is formed in the third semiconductor structure 28124 or the fourth semiconductor structure 28127. The current limiting layer 28125 includes a current limiting area 28125B and a current conducting area 28125A that is defined by and surrounded by the current limiting area 28125B.

[0277] 28 , the semiconductor light emitting device 28000 further includes a recessed structure 28140 and a protective layer 28150. The recessed structure 28140 is formed in the epitaxial stacked layer 28120. Specifically, in this embodiment, the recessed structure 28140 is formed in the fourth semiconductor structure 28127, the active structure 28126, and the third semiconductor structure 28124. In other words, in this embodiment, the recessed structure 28140 penetrates the fourth semiconductor structure 28127, the active structure 28126, and the third semiconductor structure 28124 to expose the intermediate layer 28123. The protective layer 28150 fills the recessed structure 28140 and is located between the first electrode structure 28132 and the fourth semiconductor structure 28127. The first electrode structure 28132 has a first portion 28132A and a second portion 28132B. The first portion 28132A fills the recess structure 28140 and contacts and is electrically connected to the intermediate layer 28123. The second portion 28132B extends from the first portion 28132A and is located on the protective layer 28150. The second electrode structure 28134 is provided on and electrically connected to the fourth semiconductor structure 28127.

[0278] 28 , the semiconductor light emitting element 28000 further includes an optical element 28160 that covers the first surface 28110A of the base 28110. As an example, the optical element 28160 may be an anti-reflection element that further reduces reflection of light emitted from the semiconductor light emitting element 28000 at the interface between the base 28110 and air to avoid a decrease in the light emitting efficiency of the semiconductor light emitting element 28000 or to prevent interference between light reflected at the interface and light emitted from the semiconductor device 28000.

[0279] 28 , the first semiconductor structure 28121, the second semiconductor structure 28122, the third semiconductor structure 28124, and the fourth semiconductor structure 28127 each include a plurality of film layers with different refractive indices (e.g., AlGaAs layers with a high aluminum content and AlGaAs layers with a low aluminum content) that are periodically stacked alternately to form a distributed Bragg reflector (DBR), so that light emitted from the active structure 28126 can be reflected by the Bragg reflector to form coherent light. The reflectivities of the first semiconductor structure 28121, the second semiconductor structure 28122, and the third semiconductor structure 28124 are lower than the reflectivity of the fourth semiconductor structure 28127, so that the coherent light is emitted toward the base 28110. Materials of the first semiconductor structure 28121, the second semiconductor structure 28122, the third semiconductor structure 28124, the fourth semiconductor structure 28127, and the active structure 28126 include III-V compound semiconductors, such as AlGaInAs-based, AlGaInP-based, AlInGaN-based, AlAsSb-based, InGaAsP-based, InGaAsN-based, and AlGaAsP-based compounds, such as AlGaInP, GaAs, InGaAs, AlGaAs, GaAsP, GaP, InGaP, AlInP, GaN, InGaN, and AlGaN. In the present embodiment, unless otherwise specified, the above chemical formulas include both "stoichiometric compounds" and "non-stoichiometric compounds." A "stoichiometric compound" is, for example, a compound in which the total elemental content of group III elements is the same as the total elemental content of group V elements, while a "non-stoichiometric compound" is, for example, a compound in which the total elemental content of group III elements is different from the total elemental content of group V elements. As an example, the chemical formula of the AlGaInAs system means that it contains aluminum (Al) and / or gallium (Ga) and / or indium (In) of group III elements and arsenic (As) of group V element, and the total element content of the group III elements (aluminum and / or gallium and / or indium) may be the same as or different from the total element content of the group V element (arsenic). Also, when each compound represented by the above chemical formula is a stoichiometric compound, the AlGaInAs system is represented by (Al y1 Ga (1-y1) ) 1-x1In x1 As, where 0≦x1≦1, 0≦y1≦1, and the AlGaInP system is (Al y2 Ga (1-y2) ) 1-x2 In x2 P, where 0≦x2≦1, 0≦y2≦1, and the AlInGaN system is (Al y3 Ga (1-y3) ) 1-x3 In x3 N, where 0≦x3≦1, 0≦y3≦1, and the AlAsSb system is AlAs x4 Sb (1-x4) where 0≦x4≦1, and the InGaAsP system is In x5 Ga 1-x5 As 1-y4 P y4 where 0≦x5≦1, 0≦y4≦1, and the InGaAsN system is In x6 Ga 1-x6 As 1-y5 N y5 where 0≦x6≦1, 0≦y5≦1, and the AlGaAsP system is Al x7 Ga 1-x7 As 1-y6 P y6 where 0≦x7≦1 and 0≦y6≦1.

[0280] Depending on the material, active structure 28126 can emit infrared light with a peak wavelength between 700 nm and 1700 nm, red light with a peak wavelength between 610 nm and 700 nm, yellow light with a peak wavelength between 530 nm and 570 nm, green light with a peak wavelength between 490 nm and 550 nm, blue or deep blue light with a peak wavelength between 400 nm and 490 nm, or ultraviolet light with a peak wavelength between 250 nm and 400 nm. In this embodiment, the peak wavelength of active structure 28126 is infrared light with a peak wavelength between 750 nm and 2000 nm.

[0281] The current limiting layer 28125 can be formed by an oxidation process or an ion implantation process. In this embodiment, when the above-mentioned first semiconductor structure 28121, the second semiconductor structure 28122, the third semiconductor structure 28124, the active structure 28126, and the fourth semiconductor structure 28127 include multiple film layers and all include aluminum, the aluminum content of one or more layers in the third semiconductor structure 28124 can be designed to be greater than 97% (defined as the current limiting layer 28125) and greater than the aluminum content of the active structure 28126, other film layers of the third semiconductor structure 28124, the second semiconductor structure 28122, the first semiconductor structure 28121, and the fourth semiconductor structure 28127. Therefore, after the oxidation process, the layer or parts of these layers with an aluminum content greater than 97% are oxidized to form the current limiting area 28125B (e.g., aluminum oxide), and the unoxidized parts become the current conducting area 28125A. During the oxidation process, oxygen forms a concave structure. and passes through the epitaxial stack layer 28120, causing an oxidation reaction.

[0282] The material of the first electrode structure 28132 and the second electrode structure 28134 includes a metal material such as gold (Au), tin (Sn), titanium (Ti), copper (Cu), silver (Ag), germanium (Ge), platinum (Pt), palladium (Pd), nickel (Ni), or an alloy thereof.

[0283] In this embodiment, as shown in FIG. 28 , the material of the intermediate layer 28123 is different from the materials of the first semiconductor structure 28121, the second semiconductor structure 28122, and the third semiconductor structure 28124. The intermediate layer 28123 may be a single layer or a multilayer and functions as an etch stop layer that controls the depth of the recess structure 28140. The intermediate layer 28123 includes a semiconductor material such as GaAs or InGaP, and has a thickness that is an odd multiple of ¼n of the peak wavelength of the light emitted by the active structure 28126, where n is the refractive index. In one embodiment, the material of the intermediate layer 28123 is different from the materials of the first semiconductor structure 28121, the second semiconductor structure 28122, and the third semiconductor structure 28124, and is used to affect the optical properties (e.g., reflectivity, threshold current (I th )), the thickness of the intermediate layer 28123 is designed to be 0.05 μm to 0.5 μm. In one embodiment, the intermediate layer 28123 can reduce lateral current diffusion. Therefore, the second-type semiconductor layer 28122 can be used not only for optical properties but also as a current diffusion layer. When the intermediate layer 28123 has a multi-layer structure (for example, a two-layer structure in which the first layer is InGaP and the second layer is GaAs), the total thickness of these layers is between 0.05 μm and 0.5 μm.

[0284] 28 , when the first semiconductor structure 28121, the second semiconductor structure 28122, and the third semiconductor structure 28124 are all distributed Bragg reflectors (DBRs), the number of pairs of periodically alternating film layers in the first semiconductor structure 28121 may be greater than, equal to, or smaller than the number of pairs of periodically alternating film layers in the second semiconductor structure 28122. And / or the number of pairs of periodically alternating film layers in the first semiconductor structure 28121 may be greater than, equal to, or smaller than the number of pairs of periodically alternating film layers in the third semiconductor structure 28124. In one embodiment, the number of pairs of film layers in the second semiconductor structure 28122 may be less than the number of pairs of film layers in the third semiconductor structure 28124. In one embodiment, the number of pairs of film layers in the first semiconductor structure 28121 may be 5 to 15 pairs, the number of pairs of film layers in the second semiconductor structure 28122 may be 2 to 5 pairs, and the number of pairs of film layers in the third semiconductor structure 28124 may be 5 to 15 pairs.

[0285] 28 , depending on the requirements of optical properties, the total number of pairs of film layers of the first semiconductor structure 28121, the second semiconductor structure 28122, and the third semiconductor structure 28124 is less than the number of pairs of film layers of the fourth semiconductor layer 28127. For example, the total number of pairs of film layers of the first semiconductor structure 28121, the second semiconductor structure 28122, and the third semiconductor structure 28124 is 15 to 25 pairs, and the number of pairs of film layers of the fourth semiconductor layer 28127 is 30 to 60 pairs.

[0286] In one embodiment, as shown in FIG. 28, due to the manufacturing process, the doping concentration of the P-type semiconductor layer is lower than the doping concentration of the N-type semiconductor layer, and due to design, the sum of the number of pairs of film layers of the second semiconductor structure 28122 and the third semiconductor structure 28124 is less than the number of pairs of film layers of the fourth semiconductor layer 28127, and therefore, the first semiconductor structure 28121 The conductivity type of the third semiconductor structure 28124 may be designed to be P-type, and the conductivity type of the fourth semiconductor structure 28127 may be designed to be N-type, thereby reducing the series resistance of the entire semiconductor light emitting device 28000 and improving the light emitting efficiency.

[0287] 29 is a schematic cross-sectional view showing a semiconductor light emitting device 29000 according to one embodiment. The semiconductor light emitting device 29000 of this embodiment includes a substrate 29010, an epitaxial structure 29020 located on one side of the substrate 29010, and an epitaxial structure 29030. The epitaxial structures 29020 and 29030 are spaced apart by a predetermined distance and are not in contact with each other, although the present invention is not limited thereto. The semiconductor light emitting device 29000 further includes a metal connection layer 29040 located between the epitaxial structure 29020 and the substrate 29010 and between the epitaxial structure 29030 and the substrate 29010. The semiconductor light emitting device 29000 further includes an electrode structure 29050, an electrode structure 29060, an electrode structure 29070, and an electrode structure 29080, wherein the electrode structure 29050 and the electrode structure 29060 are located on a surface 29020A of the epitaxial structure 29020 remote from the substrate 29010, the electrode structure 29070 and the electrode structure 29080 are located on a surface 29030A of the epitaxial structure 29030 remote from the substrate 29010, and the electrode structure 29050 and the electrode structure 29070 are connected to semiconductor layers having the same conductivity, and the electrode structure 29060 and electrode structure 29080 are each connected to a semiconductor layer having the same conductivity.

[0288] The epitaxial structure 29020 includes a plurality (two in the embodiment shown in FIG. 29, but the present invention is not limited to this) of epitaxial columnar structures P291, P292 and a platform structure 29226, and the epitaxial structure 29030 includes a plurality (two in the embodiment shown in FIG. 29, but the present invention is not limited to this) of epitaxial columnar structures P293, P294 and a platform structure 29326, and the epitaxial columnar structures P291, P292 and the epitaxial columnar structures P293, P294 have identical or substantially identical structures. In this embodiment, each epitaxial columnar structure P291 (P292) includes a semiconductor structure 29222, a current limiting layer 29225, and an active region 29224 arranged sequentially on the substrate 29010, and the multiple epitaxial columnar structures P291, P292 are located between the platform structure 29226 and the substrate 29010 and are arranged regularly or irregularly. Similarly, the epitaxial columnar structure P293 (P294) of the epitaxial structure 29030 includes a semiconductor structure 29322, a current limiting layer 29325, and an active region 29324 arranged sequentially on the substrate 29010, and the multiple epitaxial columnar structures P293, P294 are located on the platform structure 29326 and are arranged regularly or irregularly. As used herein, the term "regularly arranged" means that multiple epitaxial columnar structures have a specific spatial relationship and are arranged in a fixed, repeating manner. In some regularly arranged epitaxial columnar structures, the gaps between adjacent epitaxial columnar structures are substantially the same, while in other regularly arranged epitaxial columnar structures, multiple epitaxial columnar structures are arranged along a specific direction. In the present application, the current limiting layer 29225 or the current limiting layer 29325 may be selectively provided between the active structure 29224 and the semiconductor structure 29222, and between the active structure 29324 and the semiconductor structure 29322, respectively, i.e., the embodiment shown in FIG. 29 . Alternatively, the current limiting layer 29225 or 29325 may be selectively provided between the active structure 29224 and the platform structure 29226, and between the active structure 29324 and the platform structure 29326, respectively.In one embodiment, current limiting layer 29225, 29325 may be provided between active structure 29224 and semiconductor structure 29222, between active structure 29324 and semiconductor structure 29322, between active structure 29224 and platform structure 29226, and between active structure 29324 and platform structure 29326, i.e., multiple current limiting layers may be provided in epitaxial structure 29020 and / or epitaxial structure 29020. Platform structure 29226 and platform structure 29326 have semiconductor structures, and the semiconductor structures of platform structure 29226 and platform structure 29326 have substantially the same configuration. In this embodiment, semiconductor structures 29222 and 29322 have the same conductivity type (e.g., P-type), semiconductor structures of platform structure 29226 and 29326 have the same conductivity type (e.g., N-type), semiconductor structures 29222 and 29226 have opposite conductivity types, and semiconductor structures 29322 and 29326 have opposite conductivity types. In this embodiment, platform structure 29226 has a width W291, and platform structure 29326 has a width W292 that is the same as width W291. In other embodiments, width W291 may be greater or less than width W292.

[0289] 29 , in this embodiment, the epitaxial columnar structures P291, P292 and the epitaxial columnar structures P293, P294 have corresponding contact structures 29220 and 29320 on their surfaces close to the substrate 29010. The contact structures 29220 and 29320 are, for example, multilayer metal structures. The contact structure 29220 or the contact structure 29320 as a multilayer metal structure contacting the P-type semiconductor structure may be Ti / Pt / Au, and the contact structure 29220 or the contact structure 29320 as a multilayer metal structure contacting the N-type semiconductor structure may be Au / GeAu / Au, but the present invention is not limited thereto. The contact structures 29220 and 29320 are connected to the semiconductor structures 29222 and 29322, respectively. In a top view, the contact structures 29220 and 29320 are ring-shaped.

[0290] 29 , the semiconductor light-emitting device 29000 of this embodiment further includes an insulating layer 29090 covering part of the side and top surfaces of each epitaxial columnar structure P291, P292 and part of the side and top surfaces of each epitaxial columnar structure P293, P294. The insulating layer 29090 is optically transparent to light emitted from each epitaxial columnar structure. Specifically, the insulating layer 29090 has multiple insulating layer openings 29090A, which expose the contact structure 29220 on the epitaxial structure 29020 and the contact structure 29320 on the epitaxial structure 29030. In this embodiment, the insulating layer openings 29090A are ring-shaped in top view. A metal connection layer 29040 covers the insulating layer 29090. In this embodiment, the metal connection layer 29040 is located between the epitaxial structure 29020 and the epitaxial structure 29030, and is electrically connected to the contact structure 29220 and the contact structure 29320 through the insulating layer openings 29090A. The metal connection layer 29040 has a plurality of connection layer openings 29040A located in the epitaxial columnar structures P291, P292, P293, and P294, so that light emitted by the active structures 29224 and 29324 can be emitted toward the substrate 29010 through the connection layer openings 29040A. Referring to FIG. 29 , the semiconductor light emitting device 29000 of this embodiment further includes a spacer 29040B located between the epitaxial columnar structure P292 and the epitaxial columnar structure P293, separating the connection layer 29040 therebetween, and the spacer 29040B is a spacer that separates the light emitting area 29010 from the light emitting area 29020. 29000A and the connecting layer 29040 located in the light emitting area 29000B. It is a long groove structureThe semiconductor light emitting device 29000 of this embodiment further includes an adhesive layer 29901, and the epitaxial structures 29020 and 29030 are connected to the substrate 29010 via the adhesive layer 29901. The substrate 29010 and the adhesive layer 29901 are optically transparent to light emitted from each epitaxial columnar structure. The insulating layer 29090 further includes a plurality of insulating layer openings 29090B, which are, for example, circular in top view, and the metal connecting layer 29040 fills the openings therebetween to form electrical continuity with the underlying structure. This will be described in more detail below.

[0291] 29, the semiconductor light emitting device 29000 of this embodiment has an electrode connection layer 29420 and an electrode connection layer 29520 on the side of the platform structure 29226 and the platform structure 29326 that is away from the substrate 29010. The electrode connection layer 29420 and the electrode connection layer 29520 are respectively formed on the semiconductor structure 29226 and semiconductor structures 29326The semiconductor light emitting element 29000 includes an insulating layer 29082 covering parts of the sides and surfaces of the electrode connecting layer 29420 and the electrode connecting layer 29520, and covering parts of the sides and surfaces of the platform structure 29226 and the platform structure 29326. Specifically, the insulating layer 29082 has a side 29821, an upper part 29822 and a plurality of openings 29082A, and the electrode connecting layer 29420 and the electrode connecting layer 29520 are exposed through the openings 29082A and are electrically connected to the electrode structure 29050 and the electrode structure 29070 through the openings 29082A. Epitaxial structure 29020 has a via 29201 penetrating platform structure 29226, epitaxial structure 29030 has a via 29301 penetrating platform structure 29326, insulating layer 29082 is filled in via 29201 and via 29301, insulating layer 29082 further includes a plurality of openings 29082B located respectively in via 29201 and via 29301, conductive layer 29421 is filled in opening 29082B of via 29201, conductive layer 29422 is filled in opening 29082B of via 29301, and conductive layer 29421 and conductive layer 29422 are electrically connected to metal connection layer 29040 via insulating layer opening 29090B and opening 29082B. In this embodiment, electrode structure 29060 is connected to conductive layer 29421 and electrically connected to metal connection layer 29040 on epitaxial structure 29020, and electrode structure 29080 is connected to conductive layer 29422 and electrically connected to metal connection layer 29040 on epitaxial structure 29030.

[0292] Referring to Figure 29, the semiconductor light-emitting element 29000 of this embodiment further includes an insulating layer 29084, which covers part of the side 29821 and the top 29822 of the insulating layer 29082, and has a plurality of openings 29084A, a plurality of openings 29082B corresponding respectively to the plurality of openings 29082A, and a plurality of openings 29084B, wherein the electrode structure 29050 and the electrode structure 29070 are electrically connected to the electrode connection layer 29420 and the electrode connection layer 29520, respectively, via the opening 29084A, and the electrode structure 29060 and the electrode structure 29080 are electrically connected to the metal connection layer 29040 via the opening 29084B.

[0293] 29 , in this embodiment, the conductivity type of semiconductor structure 29222 and semiconductor structure 29322 is P-type, and the conductivity type of semiconductor structure (platform 29226) and semiconductor structure (platform 29326) is N-type. Electrode structure 29060 and electrode structure 29080 are electrically connected to metal connection layer 29040, which is electrically connected to semiconductor structure 29222 and semiconductor structure 29322, and therefore electrode structure 29060 and electrode structure 29080 are P-electrodes, and electrode structure 29050 and electrode structure 29070 are electrically connected to their corresponding semiconductor structures, and therefore electrode structure 29050 and electrode structure 29070 are both N-electrodes. The electrical characteristics of epitaxial structure 29020 are controlled by electrode structure 29050 and electrode structure 29060, and the electrical characteristics of epitaxial structure 29030 are jointly controlled by electrode structure 29070 and electrode structure 29080. Because electrode structures 29050, 29060, 29070, and 29080 are isolated from each other, epitaxial structure 29020 and epitaxial structure 29030 can be independently controlled, for example, epitaxial structure 29020 or epitaxial structure 29030 can be individually lit.

[0294] In Figure 29, for the sake of simplicity, there are shown two epitaxial structures (epitaxial structure 29020 and epitaxial structure 29030), and each epitaxial structure includes two epitaxial columnar structures (epitaxial structure 29020 has two epitaxial columnar structures P291 and P292, and epitaxial structure 29030 has two epitaxial columnar structures P293 and P294). However, in actual product applications, the number of epitaxial structures and epitaxial columnar structures (for example, 10 to 1000, but not limited to these) can be adjusted depending on the current and power requirements when using a semiconductor light-emitting device (e.g., a VCSEL). Current limiting layer 29225 includes current limiting area 29225B and current conducting area 29225A, current limiting area 29225B surrounds current conducting area 29225A, and current conducting area 29225A has a higher conductivity than current limiting area 29225B, so that current is concentrated in current conducting area 29225A. Similarly, current limiting layer 29325 includes current limiting area 29325B and current conducting area 29325A, current limiting area 29325B surrounds current conducting area 29325A, and current conducting area 29325A has a higher conductivity than current limiting area 29325B.

[0295] 29, the semiconductor light emitting device 29000 in this embodiment is a flip-chip type vertical cavity surface emitting laser (VCSEL) device, which can then be bonded to an external circuit board (e.g., a printed circuit board) using solder.

[0296] 29 , in this embodiment, electrode structure 29050 may be a multi-layer structure, and in a direction away from substrate 29010, electrode structure 29050 includes, for example, a titanium (Ti) layer and a gold (Au) layer, or a titanium (Ti) layer, a platinum (Pt) layer and a gold (Au) layer, or a titanium tungsten (TiW) layer and a gold (Au) layer. Electrode structure 29050 includes an intermediate layer 29502 and a bonding layer 29504, electrode structure 29060 includes an intermediate layer 29602 and a bonding layer 29604, electrode structure 29070 includes an intermediate layer 29702 and a bonding layer 29704, and electrode structure 29080 also includes an intermediate layer 29802 and a bonding layer 29804. Electrode structure 29050, electrode structure 29060, electrode structure 29070, and electrode structure 29080 may contain at least one element, and electrode connection layer 29420, electrode connection layer 29520, and conductive layer 29421, conductive layer 29422 do not contain the element, thereby preventing external (tin-containing) solder from damaging electrode connection layer 29420, electrode connection layer 29520, and conductive layer 29421, conductive layer 29422 and causing electrical failure during solid-state crystal or high-current operation, thereby further improving the reliability of semiconductor light-emitting device 29000 of the present application. The above element can be used to prevent solder from diffusing into electrode connection layer 29420, electrode connection layer 29520, conductive layer 29421, and conductive layer 29422. The element includes, for example, nickel (Ni) and / or platinum (Pt). Specifically, electrode structure 29050, electrode structure 29060, electrode structure 29070, and electrode structure 29080 may each include multiple layers. As an example, the materials of intermediate layer 29502, intermediate layer 29602, intermediate layer 29702, and intermediate layer 29802 are different from the materials of electrode connection layer 29420, electrode connection layer 29520, conductive layer 29421, and conductive layer 29422, thereby preventing solder (e.g., tin or gold-tin alloy (AuSn)) from diffusing into electrode connection layer 29420, electrode connection layer 29520, conductive layer 29421, and conductive layer 29422.Therefore, the material of intermediate layer 29502, intermediate layer 29602, intermediate layer 29702, and intermediate layer 29802 preferably includes a metal element other than gold (Au), tin (Sn), and copper (Cu), such as nickel (Ni) and / or platinum (Pt). Bonding layer 29504, bonding layer 29604, bonding layer 29704, and bonding layer 29804 include a highly ductile metal material, preferably gold (Au). In other words, referring to FIG. 29 , in a direction away from substrate 29010, electrode structure 29050, electrode structure 29060, electrode structure 29070, and electrode structure 29080 may include a nickel layer, a platinum layer, and a gold layer, respectively, in that order. In another embodiment, electrode structure 29050, electrode structure 29060, electrode structure 29070, and electrode structure 29080 may include only bonding layer 29504, bonding layer 29604, bonding layer 29704, and bonding layer 29804, respectively.

[0297] In one or more embodiments, the light-emitting device may be a semiconductor light-emitting device 30000, as shown in FIGS. 30A to 30E. Referring to FIGS. 30C to 30E, cross-sectional views of different sections of the semiconductor light-emitting device 30000 of the present application are shown. FIG. 30C schematically illustrates the cross-sectional structure taken along line 30C-30C' in FIG. 30A, FIG. 30D schematically illustrates the cross-sectional structure taken along line 30D-30D' in FIG. 30A, and FIG. 30E schematically illustrates the cross-sectional structure taken along line 30E-30E' in FIG. 30A. The semiconductor light-emitting device 30000 of this embodiment has a similar configuration to the semiconductor light-emitting device 29000 shown in FIG. 29.

[0298] 30A to 30E, which respectively show a bottom perspective view, a top perspective view, and cross-sectional views of different cross sections of a semiconductor light emitting device 30000 according to one embodiment. In this embodiment, as shown in FIG. 30C, the semiconductor light emitting device 30000 includes a base layer 30010, an adhesive layer 30901, a plurality of epitaxial columnar structures P30 (P3011 to P3014), and a platform structure 30226. The epitaxial columnar structures P30 are formed on the platform structure 30226 and are bonded to the base layer 30010 via the adhesive layer 30901. The semiconductor light-emitting element 30000 further includes a metal connecting layer 30040 located between the epitaxial columnar structure P30 and the base layer 30010, and the metal connecting layer 30040 is electrically connected to the first semiconductor structure 30222 of each epitaxial columnar structure P30 (P3011 to P3014), and an insulating layer 30090 is located between the metal connecting layer 30040 and the columnar structure P30.

[0299] 30B to 30E, semiconductor light emitting element 30000 further includes electrode structures 30050A, 30050B, 30060A, 30060B, 30070A, 30070B, 30080A, and 30080B. In this embodiment, as shown in FIG. 30B, electrode structures 30050A, 30050B, 30060A, 30060B, 30070A, 30070B, 30080A, and 30080B of semiconductor light emitting element 30000 are located outside light emitting areas 30000A, 30000B, 30000C, and 30000D, and the electrode structures do not overlap with the light emitting areas. Specifically, in this embodiment, the structure of the semiconductor light emitting element is composed of a light emitting area structure and a non-light emitting area structure. The structure of the light-emitting region of semiconductor light-emitting element 30000 includes four light-emitting areas 30000A, 30000B, 30000C, and 30000D, and the structure of the non-light-emitting region of semiconductor light-emitting element 30000 includes electrode structures 30050A, 30050B, 30060A, 30060B, 30070A, 30070B, 30080A, and 30080B, but the number of light-emitting areas and the number of electrode structures of the present invention are not limited to this. 30B, electrode structure 30050A and electrode structure 30060A located outside light emitting area 30000A are used to control light emitting area 30000A, electrode structure 30070A and electrode structure 30080A located outside light emitting area 30000B are used to control light emitting area 30000B, and electrode structure 30070B and electrode structure 30080B located outside light emitting area 30000C are used to control light emitting area 30000C. Electrode structure 30050B and electrode structure 30060B located in the outer region of light emitting area 30000D are used to control light emitting area 30000D. In this embodiment, as shown in FIG. 30B, a plurality of electrode structures 30050A, 30060A, 30070A, 30080A, 30050B, 30060B, 30070B, and 30080B are separated from one another.

[0300] In this embodiment, the semiconductor light emitting device 30000 may optionally further include a thermal conduction structure TP30 located behind the plurality of light emitting areas 30000A, 30000B, 30000C, and 30000D, for conducting thermal energy generated in each light emitting area to the outside and enhancing the heat dissipation effect of the semiconductor light emitting device 30000. The material of the thermal conduction structure TP30 may be, for example, a metal thermal conduction structure, and the distribution area of ​​the thermal conduction structure TP30 may cover the corresponding area where all of the epitaxial columnar structures P30 are arranged for the purpose of heat conduction and heat dissipation of each light emitting area, but the present invention is not limited thereto. In one embodiment, for example, the electrode structure 30060A and the electrode structure 30080A may have an electrically conductive internal connection structure, so that the electrode structure 30060A and the electrode structure 30080A form a common electrode structure architecture. In another embodiment, for example, diagonally positioned electrode structure 30060A and electrode structure 30080B, or diagonally positioned electrode structure 30060B and electrode structure 30080A may have an internal connection structure that is conductive to each other, thereby forming two electrode structures with different electrical properties, which can further improve current distribution, but the present invention is not limited thereto.

[0301] 30C , four epitaxial pillar structures (i.e., corresponding to light-emitting holes) P301, P302, P303, and P304 of the light-emitting area 30000A are located above the same platform structure 30226, and an electrical control signal controls the light-emitting state of the light-emitting area 30000A through an electrode structure 30050A and an electrode structure 30060A located outside the platform structure 30226. In this embodiment, the electrode structure 30050A is electrically connected to the semiconductor structure (i.e., corresponding to the platform structure 30226) through an electrode connection layer 30420, and the electrode structure 30060A is connected to a conductive layer 30421, thereby electrically connected to the metal connection layer 30040 of the semiconductor light-emitting device 30000. In this embodiment, the semiconductor light-emitting device 30400 further includes a heat-conducting structure TP30 covering the insulating layer 30084 for heat conduction and dissipation.

[0302] 30D shows epitaxial columnar structures P3015, P3016, P3021, and P3022 located in different light emitting areas 30000A and 30000B, where epitaxial columnar structures P3015 and P3016 are located on platform structure 30226, and epitaxial columnar structures P3021 and P3022 are located on platform structure 30326. As shown in FIG. 30D, electrode structure 30050A and electrode structure 30070A are electrically connected to platform structure 30226 and platform structure 30326, respectively, and electrode structure 30050A and electrode structure 30070A are not electrically connected to each other (i.e., electrode structure 30050A and electrode structure 30070A are separated by insulating layer 30084). Thus, the electrical control signal can control the light emitting states of the light emitting areas 30000A and 30000B through the electrode structures 30050A and 30070A outside the light emitting areas 30000A and 30000B, respectively. Similarly, the heat conducting structure TP30 is disposed on the insulating layer 30084, and its area range covers the area where all the epitaxial columnar structures P30 are arranged, and performs heat conduction and heat dissipation in each light emitting area.

[0303] 30E, epitaxial columnar structures P3023 and P3024 in light emitting area 30000B and epitaxial columnar structures P3031 and P3032 in light emitting area 30000C are located on the same platform structure 30326. As shown in the figure, electrode structure 30080A and electrode structure 30080B located outside light emitting area 30000B and light emitting area 30000C, respectively, are not electrically connected to each other, allowing the light emitting states of light emitting area 30000B and light emitting area 30000C to be controlled individually. Similarly, heat conduction structure TP30 is covered with insulating layer 30084 and performs heat conduction and heat dissipation in the light emitting area. As shown in FIG. 30E, spacers 30040B are also formed on the metal connection layer 30040 on the platform structure 30226, separating the metal connection layer 30040 into portions 30040a and 30040b that are separated from each other, i.e., forming a groove-like structure between the portions 30040a and 30040b, and exposing a portion of the surface of the insulating layer 30090.

[0304] Referring again to Figures 30A-30E, in this embodiment, electrode structures 30050A, 30060A, 30070A, 30080A, and 30080B may each include an intermediate layer (e.g., intermediate layer 30502A, 30702A) and a bonding layer (e.g., bonding layer 30504A, 30704A).

[0305] In this embodiment, as shown in Figures 30A-30E, the semiconductor light emitting device 30000 is a flip-chip type laser device that can then be bonded to an external carrier board (e.g., a printed circuit board or a driver chip 21010 as shown in Figure 21) using solder via a flip-chip bonding process. In one or more embodiments, the light emitting device may be a semiconductor light emitting device 31000, as shown in Figure 31.

[0306] According to the present application, the selection of insulating layer materials and structural design can be further utilized to reduce the overall capacitance value of the semiconductor light emitting device, thereby improving the operating performance of the semiconductor light emitting device. Referring to Figure 31, a cross-sectional schematic diagram of a semiconductor light emitting device 31000 according to one embodiment.

[0307] 31 , the semiconductor light emitting device 31000 of this embodiment further includes a metal connection layer 31040 located between the epitaxial structure 31720 and the substrate 31010, and between the epitaxial structure 31730 and the substrate 31010. As shown in FIG. 31 , the semiconductor light emitting device 31000 of this embodiment further includes an adhesive layer 31901, and the above-mentioned epitaxial structure 31720 and epitaxial structure 31730 are connected to the substrate 31010 via the adhesive layer 31901. 31 , the semiconductor light emitting device 31000 of this embodiment further includes an insulating layer 31090 covering the side surfaces and portions of the top surfaces of the epitaxial columnar structures P311 and P312, and an insulating layer 31090 covering the side surfaces and portions of the top surfaces of the epitaxial columnar structures P313 and P314, where the insulating layer 31090 is optically transparent to light emitted from each epitaxial columnar structure. As shown in FIG. 31 , the semiconductor light emitting device 31000 of this embodiment further includes an insulating layer 31084 covering the side surfaces and portions of the surfaces of the electrode structures 31770 and 31780, and covering the side surfaces and portions of the surfaces of the platform structures 31226 and 31326. As shown in Figure 31, the semiconductor light-emitting element 31000 of this embodiment has a platform structure 31226, and an electrode connection layer 31242 and an electrode connection layer 31342 located on the side of the platform structure 31326 away from the substrate 31010, respectively, and the electrode connection layer 31242 and the electrode connection layer 31342 are electrically connected to the epitaxial structure 31720 and the epitaxial structure 31730, respectively.

[0308] 31 , electrode structure 31770 and electrode structure 31780 in semiconductor light emitting device 31000 are located outside epitaxial structure 31720 and epitaxial structure 31730. That is, in this embodiment, electrode structure 31770 is located on the side of epitaxial structure 31720 closer to side edge 31010A of substrate 31010, and electrode structure 31780 is located on the side of epitaxial structure 31730 closer to side edge 31010B of substrate 31010. In this embodiment, as shown in FIG. 31 , electrode structure 31770 and electrode structure 31780 are located outside electrode structure 31750 and electrode structure 31760, respectively. Furthermore, each electrode structure 31750, 31760 includes an intermediate layer and an adhesive layer. In this embodiment, as shown in FIG. 31, the semiconductor light-emitting element 31000 is a flip-chip type laser element, which can then be bonded to an external carrier board (e.g., a printed circuit board or a driver chip 21010 as shown in FIG. 21) using solder through a flip-chip bonding process.

[0309] 31 , the epitaxial columnar structures P311, P312 have a width W311, and the platform structures 31726, 31736 have a width W312. In some embodiments, the width W311 is smaller than the width W312. In other words, in some embodiments, the platform structures 31726, 31736 are formed as bosses whose outer sides protrude outward from the epitaxial columnar structures P311, P312, and form a two-tiered boss structure together with the epitaxial columnar structures P311, P312.

[0310] 31 , the width W312 of the platform structure 31726 and the platform structure 31736 of the semiconductor light emitting device 31000 is equal to or close to the width W311 of the epitaxial columnar structures P311 and P312, i.e., the width w312 is equal to the width w311. In other words, in this embodiment, the platform structure 31726 and the platform structure 31736 form bosses at the same level as the epitaxial columnar structures P311 and P312, and therefore the epitaxial structure 31720 and the epitaxial structure 31730 do not have a two-step boss structure.

[0311] 31 , epitaxial structure 31720 and epitaxial structure 31730 each form a boss structure, and their electrode structure 31770 and electrode structure 31780 are provided outside epitaxial structure 31720 and epitaxial structure 31730, respectively, so that the depth and width of the gap between epitaxial structure 31720 and epitaxial structure 31730 are greater than those of a typical semiconductor light-emitting element. Therefore, in the present application, a low-dielectric constant (low-k) paste (e.g., spin-on glass (SOG) paste) is used as the insulating material for insulating layer 31782 in semiconductor light-emitting element 31000.

[0312] Therefore, the adhesive layer not only can easily fill the spacer region between the epitaxial structures 31720 and 31730, but also allows the epitaxial structures 31720, 31730 and the insulating layer 31782 therebetween to form a co-planarized surface 31720B, thereby planarizing the entire device surface, facilitating the distribution of the metal layer, and reducing resistance. Furthermore, the adhesive layer also functions as a buffer layer to protect the chip in the subsequent die attach process. Furthermore, applying the adhesive layer can increase the thickness of the semiconductor light-emitting device, further reducing the overall capacitance value of the semiconductor light-emitting device 31000.

[0313] In one or more embodiments, the light-emitting device may be a semiconductor light-emitting device, as shown in Figures 32A-32C. Figure 32A is a schematic top perspective view of a semiconductor light-emitting device 32000 according to one embodiment, and Figures 32B and 32C are schematic cross-sectional views taken along lines 32B-32B' and 32C-32C' in Figure 32A, respectively. In this embodiment, as shown in Figures 32B and 32C, the semiconductor light-emitting device 32000 is a flip-chip laser device, which can then be bonded to an external carrier board (e.g., a printed circuit board or the driver chip 21010 shown in Figure 21) using solder via a flip-chip bonding process. can.

[0314] According to one or more embodiments of the present application, when forming light emitting holes in a semiconductor light emitting device, the density and addressing flexibility of the light emitting holes in the light emitting area can be further increased by adjusting the structural design of the light emitting area to change the position and number of the light emitting holes, and the light emitting holes can be formed, for example, using a wet oxidation process.

[0315] As shown in the embodiment of FIG. 32A , the semiconductor light emitting device 32000 includes a plurality of light emitting holes 32825A, such as openings 32825A1, 32825A2, 32825A3, and 32825A4 shown in FIGS. 32B and 32C , and these light emitting holes 32825A are arranged in an array. In the top view shown in FIG. 32A , the plurality of openings (light emitting holes) 32825A in the semiconductor light emitting device 32000 are arranged in a close-packed manner. For example, the plurality of openings 32825A are arranged in a hexagonal close-packed manner. That is, six adjacent openings 32825A are formed around each opening 32825A, and each opening 32825A is surrounded by six recessed structures 32840. These recess structures 32840 are used to perform an oxidation process to form current limiting areas in each of the current limiting layers 328251-328254 in the semiconductor light emitting device 32000, but the present invention is not limited thereto. In this manner, six evenly distributed recess structures are formed in the epitaxial structure around each light emitting hole (i.e., arranged at 60-degree intervals around the periphery). Therefore, by performing a wet oxidation process through the six recess structures, a substantially circular opening (i.e., the light emitting hole of the semiconductor light emitting device) can be formed in the epitaxial structure of the semiconductor light emitting device. According to one or more embodiments of the present application, each recess structure is shared by two adjacent light emitting holes, so that the multiple light emitting holes in the semiconductor light emitting device of the present application can be arranged in a close-packed manner, thereby reducing the arrangement space of the light emitting hole structures in the semiconductor light emitting device. decrease It can be done.

[0316] 32A, there is no recessed structure between the openings (i.e., light emitting holes) 32825A1 and 32825A2, i.e., the current limiting areas in the current limiting layers 328252 and 328251 are formed by a wet oxidation process by the outer wall surfaces of the recessed structures 32850A and 32850B on both sides of the same platform structure 32826, respectively, so that the openings (i.e., light emitting holes) 32825A1 and 32825A2 are located in the same platform structure 32826. As shown in FIG. 32C, in addition to the outer recessed structures 32850C and 32850D, two recessed structures 32840 are further formed between the opening 32825A3 and the adjacent opening 32825A4 in the cross section shown in FIG. 32A, 32825A1 and 32825A2. That is, the outer wall surface of the recessed structure 32850C and the side wall surface of the recessed structure 32840 are subjected to a wet oxidation process to form a current limiting area in the current limiting layer 328253 and define the opening 32825A3, and the side wall surface of the recessed structure 32840 and the outer wall surface of the recessed structure 32850D are subjected to a wet oxidation process to form the current limiting layer 328254 and define the opening 32825A4. In one embodiment, two adjacent openings may share a recessed structure therebetween, or there may be only one recessed structure between two adjacent openings. This further reduces the distance between adjacent openings and allows the light emitting holes of the semiconductor light emitting elements to be arranged more closely together.

[0317] 32B and 32C, the semiconductor light emitting device 32000 of this embodiment further includes a metal connection layer 32040 located between the platform structure 32326 and the base layer 32010. As shown in FIGS. 32B and 32C, the semiconductor light emitting device 32000 of this embodiment further includes an adhesive layer 32901, and the platform structure 32326 is connected to the base layer 32010 via the adhesive layer 32901. As shown in FIGS. 32B and 32C, the semiconductor light emitting device 32000 of this embodiment further includes an insulating layer 32090 covering the sides and top surfaces of the epitaxial structures, and the insulating layer 32090 is optically transparent to light emitted from each epitaxial structure.

[0318] In one or more embodiments, the light-emitting device may be a semiconductor light-emitting device 33000, as shown in FIG. 33. FIG. 33 is a schematic cross-sectional view illustrating a semiconductor light-emitting device according to one embodiment. In this embodiment, a semiconductor light-emitting device 33000 is provided. The semiconductor light-emitting device 33000 includes a semiconductor laminate 33200 formed on a growth substrate 33900. The semiconductor laminate 33200 sequentially includes a semiconductor layer 33206, an active layer 33204, and a semiconductor layer 33202 located on the growth substrate 33900. Next, a portion of an epitaxial columnar structure P33 to be formed later on the semiconductor light-emitting device 33000 is formed to form a corresponding contact structure 33220. Next, an insulating layer 33090 is formed as a protective layer on the contact structure 33220 and the semiconductor laminate 33200. Next, an etching process is performed to form a through-hole U33 and expose an end face of the growth substrate 33900. Here, the shape of the through-hole is not limited, and in other words, the through-hole may be an arc-shaped columnar hole, a polygonal columnar hole, or a columnar hole of any shape. Next, an etching process is further performed to form the epitaxial columnar structure P33 and the recessed structure 33104 that exposes a part of the end face of the semiconductor layer 33206. The epitaxial columnar structure P33 has a side surface PB33.

[0319] Next, a wet oxidation process is used to form a current limiting layer in the epitaxial columnar structure P33. In this embodiment, a current limiting layer 33225 is formed between the semiconductor layer 33202 and the active layer 33204. The current limiting layer 33225 includes a current limiting area 33225B and a current conducting area 33225A surrounded by the current limiting area 33225B. An insulating layer 33090 is formed in the through hole U33 and the recessed structure 33104, covering the side surface PB33 of the epitaxial columnar structure P33, the end surface of the semiconductor layer 33206, and the end surface of the growth substrate 33900. Next, an insulating layer opening 33090A is formed in the insulating layer 33090 to expose a portion of the surface of the contact structure 33220. Here, the shape of the insulating layer opening 33090A in a top view may be, for example, annular, circular, elliptical, rectangular, irregular, etc. In this embodiment, the insulating layer opening 33090A has a ring shape when viewed from above, but the present application is not limited to this.

[0320] Next, a metal connection layer 33040 is formed on the insulating layer 33090. The metal connection layer 33040 covers the insulating layer 33090, fills the insulating layer opening 33090A, and is connected to the contact structure 33220, thereby further electrically connecting to the semiconductor layer 33202. The metal connection layer 33040 has a connection layer opening 33040A above the epitaxial columnar structure P33. The position of the connection layer opening 33040A corresponds to the position of the current conducting area 33225A, exposing the insulating layer 33090 underneath. Next, the epitaxial columnar structure P33 and the semiconductor layer 33206 are bonded to the substrate 33100 via an adhesive layer 33901. In this embodiment, the substrate 33100 is a permanent substrate.

[0321] Next, a portion of the growth substrate 33900 is removed to expose portions of the surfaces of the metal connection layer 33040 and the insulating layer 33090. In this embodiment, the growth substrate 33900 is, for example, a GaAs substrate. Next, an electrode connection layer 33420 is formed on the substrate 33900. Next, an insulating layer 33082 is formed to cover a portion of the electrode connection layer 33420. A plurality of openings 33082A and 33082B are provided in the insulating layer 33082 to expose at least a portion of the electrode connection layer 33420 and the metal connection layer 33040.

[0322] Finally, the openings 33082A, 33082B are filled with a conductive material to form electrode structures 33105 and 33106, respectively, of the semiconductor light-emitting element, as shown in FIG. 33 . In one or more embodiments, the light-emitting device may be a semiconductor laser, as shown in FIG. 34 . Referring to FIG. 34 , FIG. 34 is a cross-sectional schematic diagram illustrating a semiconductor laser element 34000 according to one embodiment. The semiconductor laser element 34000 includes a semiconductor laminate 34010, an electrode structure 34020, an insulating layer 34030, and a base layer 34040. The semiconductor laminate 34010 includes a first-type semiconductor layer 34101, a second-type semiconductor layer 34102, and an active layer 34103, with the active layer 34103 located between the first-type semiconductor layer 34101 and the second-type semiconductor layer 34102. In this embodiment, as shown in FIG. 34, the first-type semiconductor layer 34101 is, for example, a P-type semiconductor layer, and the second-type semiconductor layer 34102 is, for example, an N-type semiconductor layer, but the present invention is not limited to this, and in another embodiment, the first-type semiconductor layer 34101 is, for example, an N-type semiconductor layer, and the second-type semiconductor layer 34102 is, for example, a P-type semiconductor layer.

[0323] 34, the base layer 34040 may be a semiconductor layer or a growth substrate for the semiconductor stack 34010. In one or more embodiments, the base layer 34040 may be a packaging substrate for the semiconductor stack 34010. That is, the semiconductor stack 34010 is first grown on a growth substrate and then transferred to the base layer 34040.

[0324] Referring again to the embodiment of FIG. 34, the semiconductor laser device 34000 further includes an electrode structure 34050 located on the front surface 34011 and the side surface 34013, and an insulating layer 34030 is located between the semiconductor laminate layer 34010 and the electrode structure 34050.

[0325] 34, the base layer 34040 may be conductive or insulating. As shown in FIG. 34, the base layer 34040 has a surface 34041 and a side surface 34042 connected to the surface 34041. The second-type semiconductor layer 34102 of the semiconductor laminate layer 34010 extends laterally and further includes platform portions 34102A and 34102B distributed on the surface 34041. The insulating layer 34030 and the electrode structure 34050 are further located on the surfaces of the platform portions 34102A and 34102B. The insulating layer 34030 has an insulating layer opening 34032 in the platform portion 34102A, and the electrode structure 34050 is distributed in the insulating layer opening 34032 and contacts the platform portion 34102A of the second-type semiconductor layer 34102. In this embodiment, not only is the electrode structure 34050 located in the insulating layer opening 34032 of the insulating layer 34030 and extends to the side surface 34042 of the base layer 34040, but the electrode structure 34020 also extends from the side surface 34013 of the semiconductor laminated layer 34010, through the platform portion 34102B, and extends to the side surface 34042 of the base layer 34040. Therefore, according to the semiconductor laser device 34000 of this embodiment, by bonding to a carrier board (e.g., a printed circuit board or a driver chip 21010 as shown in FIG. 21 ) via a flip-chip bonding process or lateral solder bonding, the bonding area between the electrode structure 34020 and the electrode structure 34050 of the semiconductor laser device 34000 can be further increased.

[0326] The foregoing description of the present embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the embodiments of the invention to the precise forms disclosed.

[0327] Based on the description of the above embodiments, it will be apparent to those skilled in the art that various modifications, variations, or combinations can be made to the above embodiments. [Explanation of symbols]

[0328] 2, 2', 2-1, 2-2, 2-1', 2-2', 5, 6: Photoelectric unit 2C, 2D, 2D': Light-emitting sensing package body 3A, 3B, 3C, 4A, 4B, 4C, 4D: Photoelectric device 1100, 24015, 26001, 27010: transparent base layer 1101, 1401: Integrated optical elements 1101A, 1101B: Microlens 1200, 2500, 25050, 26002, 27040, 30901, 31901, 32901: Adhesive layer 1300, 19900, 20900, 23900: Carrier board 1310: First compatible pad 1320: Second compatible pad 1330: 3rd compatible pad 1400: Housing 1401: Integrated optical element 1401A, 1401B: Optical elements 2000, 1500, 1600: Laminated structure 2000B, 2200B, 10000B, 27206B: Bottom side 2000T, 2100UT, 2100LT, 5100UT, 10000T, 15020T, 16020, 24020T, 25021T, P271: Top 2000V, 2100V: Through-hole structure 2000VI, 2100VI: Insulated structure 2100, 2100', 2100-1, 2100-2, 2100-1', 2100-2', 5100, 6100: Light-emitting epitaxial structure 2100A, 2100A', 5100A: Active structure 2100L, 2100L', 5100L: Lower distributed Bragg reflector 2100L1, 2100L2, 2210', 5100L1, 5100L2: Distributed Bragg reflector structure 2100U, 2100U', 5100U: Top distributed Bragg reflector 2100e, 2200e, 2200e1, 2200e2, 2200e3, 2400e, 20900e: Electrode pads 2100P, 2100P1, 2100P2, 2200N, 2200N1, 2200N2, 2200N3, 2400, 2401, 2402, 5100P, 5400, 6400, 7100P, 7200N, 7400: Conductive structure 2125, 5125, 7125, 14104, 15104, 16104, 27205, 28125, 29225, 29325, 328251, 328252, 328253, 328254, 33225: Current limiting layer 2125A, 5125A, 7125A, 14104A, 27205A, 28125A, 29225A, 33225A: Current conduction area 2125B, 5125B, 7125B, 14104B, 27205B, 28125B, 29225B, 33225B: Current limit area 2200, 2200', 2200-1, 2200-2: Light receiving structure 5500, 7700: Conductive base layer 7100: Light-emitting epitaxial layer 7100A, 15020A, 16020A, 20010A, 26033, 33204, 34103: Active layer 7100L, 15020L, 16020L, 20010L, 26035, 34102: Second-type semiconductor layer 7100M1, 7100M2, 7200M: Boss structure 7100R: Ring-shaped electrode structure 7100U, 15020U, 16020U, 20010U, 26031, 34101: Type 1 semiconductor layer 7200: Light receiving layer 7409: Electrode structure 7409E: Extension electrode 7901A, 7902A, 20031, 29082A, 29082B, 29084A, 29084B, 32825A1, 32825A2, 32825A3, 32825A4, 33082A, 33082B: Opening 9000: VCSEL wafer 9000F: Front 9100: Epitaxial layer 9200: Thin wafer layer 9300: Bottom metal layer 9900, 10900, 12900: Ablation laser or dicing machine 10000, 11000A, 11000B, 11000C, 11000D, 12000, 19001: Epitaxial wafers 10010, 12010, 13010, 14010, 19100, 20040, 30010, 31010, 32010, 34040: Base layer 10011: Processing area 10012: Breaking point 10013, 12013: Street 10020, 12020, 19020, 20010, 33200, 34010: Semiconductor stacked layer 10030, 12030: Metal layer 11011A, 11011B, 11011C, 11011D: First processing area 11011A', 11011B', 11011C', 11011D': Second processing area 11012A, 11012B, 11012C, 11012D: First breaking point 11012A', 11012B', 11012C', 11012D': Second breaking point 13000, 14000, 15000, 16000, 20000: VCSEL chip 13020, 14020, 15020, 16020, 27020, 29020, 29030, 31720, 31730: Epitaxial structure 13020A, 14020A: Active area 13020L, 14020L: Lower reflector 13020U, 14020U: Upper reflector 13040, 27702: 1st electrode 13050, 27704: 2nd electrode 14030, 14050, 15030, 15050, 16030, 16050: Electrode 13011: Break point 15100, 16100, 33900: Growth substrate 13030, 14040, 15040, 16040, 16060, 7901, 7902, 20030, 26036, 26340, 29090, 29082, 29084, 30090, 31090, 31782, 32090, 33082, 33090, 34030: Insulation layer 19000: Semiconductor laser chip 19001B: Back 19000B: Bottom 19000S: Step structure 19030: Upper electrode 19040: Lower electrode 20020, 28132: First electrode structure 20041: Bottom 20042: Boss Club 20042A: Boss Level 20042B:Boss side 20041A: Bottom 1st side 20041B: Bottom 2nd side 20041C: Bottom side 20012A, 20012B, 34102A, 34102B: Platform section 20050, 28134: Second electrode structure 20011, 28110A: Front page 20012, 28110B: 2nd side 20013, 34013, 34042, E13, E14: Side 21000: Photoelectric module 21010, 22010, 23010: driving chip 21011: Lens group 21020, 22020, 23020, 24000A, 24000B, 24000C, 25000A, 25000B, 25000C, 25000D, 25000E: Light emitting device 21030:SPAD 21040, 22040: BGA structure 22000, 23000: Radiation module 22030, 23030: Passive elements 23050: Metal wire 23060:Molding material 24010, 25010, 33202, 33206: Semiconductor layer 24020: Spacer layer 24031, 25031: First pattern layer 24040, 25040: Covering layer 24032, 25032: Second pattern layer 24033: 3rd pattern layer 25021: First transparent base layer 25022: Second transparent base layer 25030: Pattern layer 25023: Third transparent base layer 26000, 27000: Laser element 26003: Laser unit 26034: Channel 1 26010, 29421, 29422, 30421: Conductive layer 26003S: Idemitsu side 26030: Front conductive structure 26032: Back conductive structure 26320: Channel 1 26032A, 26032B: Detection electrodes 26032C, 26032D: Conductive electrode 27032: First insulating layer 27034: First metal interconnect layer 27050: Second metal interconnect layer 27060: Second insulating layer 27060A: Side 27080: Third insulating layer 27101: Anti-reflection structure 27202, 28121, 30222: First semiconductor structure 27204, 28126: Active Structure 27206, 28122: Second semiconductor structure 27206A: End face 27322: First opening 27341a: 1st protrusion 27341b:Second protrusion 27342: Second opening 27344A, 27344B, 27344C, 27344D: Marking structure 27602a: 1st opening 27602b:Second opening 27602c: Third opening 27602d: 4th opening 27603: 5th opening 27802: 1st hole 27804: 2nd hole 27902: Pad structure 27904: Second pad structure 27902A, 27904A, 29502, 29602, 29702, 29802, 30502A, 30702A: Middle layer 27902B, 27904B, 29504, 29604, 29704, 29804, 30504A, 30704A: Bonding layer 28000, 29000, 30000, 31000, 32000, 33000, 34000: Semiconductor light-emitting element 28110: Bass 28120: Epitaxial stacked layer 28123: Middle class 28124:Third Semiconductor Structure 28127: Fourth Semiconductor Structure 28132A: Part 1 28132B:Second part 28140, 32840, 32850A, 32850B, 32850C, 32850D, 33104: Recessed structure 28160: Optical elements 29010, 33100: Circuit board 29020A, 29030A, 34011: Surface 29040, 30040, 31040, 32040, 33040: Metal connection layers 29040A, 33040A: Connection layer opening 29050, 29060, 29070, 29080, 30050A, 30050B, 30060A, 30060B, 30070A, 30070B, 30080A, 30080B, 31750, 31760, 31770, 31780, 33105, 33106, 34020, 34050: Electrode structure 29090A, 29090B, 33090A, 34032: Insulation layer opening 29040B, 30040B: Spacer 29201, 29301, U33: Through hole 29220, 29320, 33220: Contact structure 29222, 29322: Semiconductor structures 29224, 29324: Active area 29226, 29326, 30226, 31726, 31736, 32826: Platform Structure 29420, 29520, 30420, 31242, 31342, 33420: Electrode connection layer 29821: Side 29822: Upper 29901: Adhesive layer 30000A, 30000B, 30000C, 30000D: Light-emitting area 30040a, 30040b: Part 31010A, 31010B: Side 31720B, 34041: Surface 32825A: Light emitting hole 510, 511, 512, 520, 521, 522, 523, 524, 525, 526: Pattern 620, 621, 622, 623, 624, 625, 626, 627: Pattern structure A: Plane size C: Arrow C271: 1st boundary C272:Second boundary D10, D12: dicing depth D019:Depth D271: First distance D272: 2nd distance G010, G012: Cracks G019: Groove G27: Gap G271: First gap G272: Second gap G273: Third gap G274: 4th gap L1, L2: Connection lines L019: Width L26: Laser light LD: Length direction Lf: Focused light Lg: Interference light Lo, Lo1, Lo2, Lo': Coherent light Lr, Lr1, Lr2: Reflected light O27: Center position O14: Idemitsu Exit P27: Columnar structure P272, PB33: Side 291, P292, P293, P294, P30, P3011, P3012, P3013, P3014, P3015, P3016, P3021, P3022, P3023, P3024, P3031, P3032, P311, P312, P33: Epitaxial columnar structure 28150, PL: Protective layer S271: First side S272: Second side W10, W12: dicing width W291, W292, W311, W312: Width WD: Width direction θ, θ': included angle

Claims

1. A package structure comprising: a light-emitting epitaxial structure in which an upper distributed Bragg reflector, an active structure, and a lower distributed Bragg reflector are stacked in this order; a light-receiving structure located below the active structure and in contact with the light-emitting epitaxial structure; a first conductive structure contacting the upper distributed Bragg reflector; a second conductive structure contacting the light receiving structure at the lower surface; and a third conductive structure contacting an upper surface of the lower distributed Bragg reflector; a packaging structure, wherein the first conductive structure is insulated from the second conductive structure, the first conductive structure is insulated from the third conductive structure, and the second conductive structure is insulated from the third conductive structure.

2. The package structure of claim 1 , wherein the upper distributed Bragg reflector comprises a P-type semiconductor structure and the lower distributed Bragg reflector comprises an N-type semiconductor structure.

3. The package structure of claim 2 , wherein the first conductive structure is a P-electrode of the illuminant epitaxial structure.

4. The package structure of claim 2 , wherein the second conductive structure is an N-electrode of the light-receiving structure.

5. The package structure according to claim 2 , wherein the third conductive structure is a common electrode of the light-emitting epitaxial structure and the light-receiving structure.

6. The package structure of claim 1 , wherein the light receiving structure is integrally formed as part of the lower distributed Bragg reflector.

7. 2. The package structure of claim 1, further comprising a transparent base layer adhered to the luminescent epitaxial structure via a first adhesive layer, wherein the transparent base layer and the first adhesive layer are transparent to light emitted from the luminescent epitaxial structure.

8. The package structure of claim 1 , wherein the light-receiving structure is adhered to the lower distributed Bragg reflector via a second adhesive layer.

9. The package structure of claim 8 , wherein the second adhesive layer is electrically conductive.

10. The package structure of claim 9 , further comprising another distributed Bragg reflector located below the light-receiving structure.

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