Gated trench power semiconductor device with self-aligned trench shield region and related method

Abstract

A method for forming a semiconductor device includes forming a first mask on a semiconductor layer structure, the first mask including a longitudinally extending first opening having a first width. Forming spacers on sidewalls of the first mask exposed by the first opening to form a second mask, the first and second masks forming a mask structure having a longitudinally extending second opening having a second width smaller than the first width. Dopants are implanted through the second opening to form implanted regions in the semiconductor layer structure. The spacers are at least partially removed from the sidewalls of the first mask to form third openings in the mask structure. The mask structure is then etched using the mask structure as an etch mask to form gate trenches in the semiconductor layer structure directly below the third openings.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 18 / 093,343, filed January 5, 2023, the entire contents of which are incorporated herein by reference as if set forth in their entirety.

[0002] The present invention relates to power semiconductor devices, and more particularly to power semiconductor devices having gate trenches, and methods of manufacturing such devices. [Background technology]

[0003] A metal-insulating semiconductor field-effect transistor (MISFET) is a well-known type of semiconductor transistor that is sometimes used as a switching device. A MISFET is a three-terminal device having a gate terminal, a drain terminal, and a source terminal, as well as a semiconductor body. The semiconductor body is referred to herein as a "semiconductor layer structure." Source and drain regions are formed within the semiconductor layer structure, separated by a channel region. A gate electrode (which may function as the gate terminal or be electrically connected to the gate terminal) is disposed adjacent to the channel region and separated from it by a thin insulating layer. A MISFET can be turned on or off by setting a bias voltage applied to the gate electrode above or below a threshold voltage. When a MISFET is turned on (i.e., the MISFET is in the "on state"), current flows through the MISFET's channel region between the source and drain regions. When the bias voltage is reduced below the threshold level, current no longer flows through the channel region.

[0004] An n-type MISFET has source and drain regions with n-type (electron) conductivity and a channel with p-type (hole) conductivity. Thus, an n-type MISFET has an "npn" design. An n-type MISFET is turned on when a gate bias voltage sufficient to form a conductive n-type inversion layer in the p-type channel region electrically connecting the n-type source and drain regions is applied to the gate electrode, thereby allowing majority carriers to flow between the source and drain regions. A p-type MISFET has a "pnp" design and is turned on when a gate bias voltage sufficient to form a conductive p-type inversion layer in the n-type channel region electrically connecting the p-type source and drain regions is applied to the gate electrode. As used herein, the terms "first conductivity type" and "second conductivity type" are used to refer to either n-type or p-type, with the first conductivity type and the second conductivity type being distinct. Thus, when a first region of a device has a first conductivity type and a second region of the device has a second conductivity type, this means that the first region has n-type conductivity and the second region has p-type conductivity, or alternatively, the first region has p-type conductivity and the second region has n-type conductivity.

[0005] As described above, the gate electrode of a MISFET is separated from the channel region by a thin dielectric layer called the gate dielectric layer. Typically, power MISFETs implement the thin gate dielectric layer using an oxide layer, such as a silicon oxide layer. A MISFET including an oxide gate dielectric layer is called a metal oxide semiconductor field effect transistor (MOSFET), and the gate dielectric layer is called a gate oxide layer. Because oxide gate dielectric layers are often implemented and used as gate oxide layers in most applications due to their superior properties, the description herein will focus on MOSFETs rather than MISFETs. However, it will be understood that the techniques according to embodiments of the present invention described herein are equally applicable to devices having gate dielectric layers formed of materials other than oxide.

[0006] Because the gate electrode of a MOSFET is insulated from the channel region by a gate oxide layer, a minimal gate current is required to maintain the MOSFET in the on state or to switch the MOSFET between the on and off states. The gate current is kept small during switching because the gate forms a capacitor with the channel region. Therefore, only minimal charging and discharging currents are required during switching, reducing the complexity of the gate drive circuit and enabling faster switching speeds. MOSFETs can be standalone devices or combined with other circuit devices. For example, an insulated gate bipolar transistor (IGBT) is a semiconductor device that includes both a MOSFET and a bipolar junction transistor (BJT), combining the high-impedance gate electrode of a MOSFET with the low on-state conduction losses that a BJT can offer. An IGBT is sometimes implemented, for example, as a Darlington pair, including a high-voltage n-channel MOSFET at the input and a BJT at the output. The base current of the BJT is supplied through the channel of the MOSFET, which simplifies the external drive circuitry (since the drive circuitry only charges and discharges the gate electrode of the MOSFET).

[0007] In some applications, MOSFETs may be required to pass large currents and / or be able to block high voltages. Such MOSFETs are often referred to as "power" MOSFETs. Power MOSFETs are often fabricated from wide-bandgap semiconductor materials (as used herein, the term "wide-bandgap semiconductor" encompasses any semiconductor with a bandgap of at least 1.4 eV). Power semiconductor devices are often formed in silicon carbide ("SiC"), which has several advantageous properties including, for example, high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity.

[0008] A power semiconductor device, such as a power MOSFET, can have a lateral structure or a vertical structure. In a device having a lateral structure, the terminals of the device (e.g., the drain terminal, gate terminal, and source terminal of a power MOSFET) are on the same major surface (i.e., the top or bottom surface) of a semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET, the source and gate may be on the top surface of the semiconductor layer structure, and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate, such as a growth substrate. As used herein, the term "semiconductor layer structure" refers to a structure including one or more semiconductor layers, such as a semiconductor substrate and / or a semiconductor epitaxial layer.

[0009] The semiconductor layer structure of a power semiconductor device typically includes an "active region" in which one or more functional semiconductor devices are formed. The active region functions as a primary junction for blocking voltage during reverse-bias (off-state) operation and for sourcing current during forward-bias (on-state) operation. A power semiconductor device may also have an edge termination in a termination region of the semiconductor layer structure adjacent to (typically surrounding) the active region. Multiple power semiconductor devices are typically formed in or on a common wafer, with each power semiconductor device typically having its own edge termination. After the wafer is fully processed, the resulting structure may be diced to separate the individual edge-terminated power semiconductor devices. Each power semiconductor device may have a unit cell structure in which the active region of each power semiconductor device includes multiple individual "unit cell" devices electrically connected in parallel and functioning together as a single power semiconductor device.

[0010] Vertical power semiconductor devices, including MOSFETs, can have a standard gate electrode design, in which the transistor's gate electrode is formed on top of the semiconductor layer structure, or alternatively, the gate electrode may be recessed in a gate trench within the semiconductor layer structure. MOSFETs with a recessed gate electrode are typically referred to as gate-trench MOSFETs. In a standard gate electrode design, the channel region of each unit cell transistor is located horizontally directly beneath the gate electrode. In contrast, in a gate-trench MOSFET design, the channel is typically located vertically. While gate-trench MOSFETs may offer improved performance, they typically require a more complex manufacturing process.

[0011] One of the failure mechanisms in power MOSFETs is the so-called "dielectric breakdown" of the gate oxide layer. The gate oxide layer is exposed to high electric fields during normal device operation. These electric fields create stresses on the gate oxide layer, creating defects in the oxide material that accumulate over time. When the defect concentration reaches a critical value, a so-called "percolation path" can form through the gate oxide layer, electrically connecting the gate electrode to the source or drain region and thereby creating a short circuit that can destroy the device. The "lifetime" of the gate oxide layer (i.e., how long the device can operate before breakdown occurs) is a function of, among other things, the magnitude of the electric field to which the gate oxide layer is exposed and the length of time the field is applied. Figure 1 is a schematic graph showing the relationship between the operating time before breakdown ("gate oxide lifetime") and the level of the electric field applied to the gate oxide layer. This graph assumes (but is not necessarily) that the same electric field is always applied and that the gate oxide layer has a certain thickness. As shown in Figure 1, this relationship can sometimes be approximately linear when gate oxide lifetime is plotted on a logarithmic scale. An important takeaway from Figure 1 is that the lifetime of the gate oxide layer decreases exponentially as the electric field level increases. Although the lifetime of the gate oxide layer can be extended by increasing the thickness of the gate oxide layer, various performance parameters of the MOSFET can be a function of the gate oxide layer thickness, and therefore, increasing the gate oxide layer thickness is typically not an accepted method of extending the lifetime of the gate oxide layer. Summary of the Invention [Means for solving the problem]

[0012] According to some embodiments of the present invention, a semiconductor device is provided that includes a wide bandgap semiconductor layer structure. The wide bandgap semiconductor layer structure includes a drift region having a first conductivity type, a well region having a second conductivity type above the drift region, a source region having the first conductivity type above the well region, a gate electrode in a gate trench, and a trench shield region having the second conductivity type directly below the gate trench. The width of the trench shield region exceeds the width of the gate trench.

[0013] In some embodiments, a trench shield region is formed beneath the gate trench and extends onto the lower portion of opposing sidewalls of the gate trench.

[0014] In some embodiments, the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, and the left side of the trench shield region extends laterally beyond a lower edge of the left sidewall of the gate trench by at least 0.1 microns, and the right side of the trench shield region extends laterally beyond a lower edge of the right sidewall of the gate trench by at least 0.1 microns.

[0015] In some embodiments, the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, and the gate trench overlaps less than 95% of the lateral width of the trench shield region.

[0016] In some embodiments, the corners of the bottom of the gate trench are rounded corners.

[0017] In some embodiments, the drift region, the well region, the source region, and the shield region each comprise silicon carbide.

[0018] In some embodiments, the trench shield region extends continuously across the entire width of the gate trench.

[0019] In some embodiments, the trench shield region defines the bottom of the gate trench.

[0020] In some embodiments, the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, and the left side of the trench shield region extends laterally beyond a lower edge of the left sidewall of the gate trench by at least 0.3 microns, and the right side of the trench shield region extends laterally beyond a lower edge of the right sidewall of the gate trench by at least 0.3 microns.

[0021] According to a further embodiment of the present invention, there is provided a semiconductor device including a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a well region having a second conductivity type above the drift region, a source region having the first conductivity type above the well region, a gate electrode in a gate trench, and a trench shield region having the second conductivity type directly below the gate trench, wherein a portion of the drift region having the first conductivity type is interposed between a bottom surface of the gate trench and the trench shield region.

[0022] In some embodiments, the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, and the left side of the trench shield region extends laterally beyond a lower edge of the left sidewall of the gate trench by at least 0.1 microns, and the right side of the trench shield region extends laterally beyond a lower edge of the right sidewall of the gate trench by at least 0.1 microns.

[0023] In some embodiments, the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, and the gate trench overlaps less than 95% of the lateral width of the trench shield region.

[0024] In some embodiments, the corners of the bottom of the gate trench are rounded corners.

[0025] In some embodiments, the trench shield region extends continuously across the entire width of the gate trench.

[0026] In some embodiments, the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, and the left side of the trench shield region extends laterally beyond a lower edge of the left sidewall of the gate trench by at least 0.3 microns, and the right side of the trench shield region extends laterally beyond a lower edge of the right sidewall of the gate trench by at least 0.3 microns.

[0027] Further embodiments of the present invention provide methods for forming a semiconductor device. According to these methods, a first mask is formed on a semiconductor layer structure, the first mask including a first longitudinally extending opening having a first width. Spacers are formed on sidewalls of the first mask exposed by the first opening to form a second mask, and the first and second masks form a mask structure having a second longitudinally extending opening having a second width smaller than the first width. Dopants are implanted into the semiconductor layer structure through the second opening to form an implanted region in the semiconductor layer structure. The spacers are at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. Finally, the semiconductor layer structure is etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure directly below the third opening.

[0028] In some embodiments, the second mask comprises silicon. In some embodiments, the second mask further comprises oxygen. In some embodiments, the first mask comprises both silicon and nitrogen.

[0029] In some embodiments, forming spacers on the sidewalls of the first mask exposed by the first opening to form the second mask includes oxidizing the sidewalls of the first mask exposed by the first opening.

[0030] In some embodiments, the implanted region is directly below the gate trench and the width of the implanted region is greater than the width of the gate trench.

[0031] In some embodiments, the implanted regions extend onto the lower portions of opposing sidewalls of the gate trench.

[0032] In some embodiments, the corners of the bottom of the gate trench are rounded corners.

[0033] In some embodiments, the drift region, the well region, the source region, and the shield region each comprise silicon carbide.

[0034] In some embodiments, the drift region has a first conductivity type, the well region has a second conductivity type, the source region has the first conductivity type, at least a portion of the well region is disposed between the drift region and the source region, and the implant region has the second conductivity type.

[0035] In some embodiments, the implanted region is self-aligned with the gate trench.

[0036] In some embodiments, the method further includes removing some but not all of the portion of the second mask that is within the second opening before implanting the dopant into the semiconductor layer structure.

[0037] In some embodiments, the semiconductor layer structure is etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure directly beneath the third opening, thereby exposing the implanted region.

[0038] In some embodiments, the method further includes etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure directly below the third opening, followed by performing an oxidation process on the semiconductor layer structure and then removing the oxidized portion of the semiconductor layer structure.

[0039] In some embodiments, the method further includes etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure beneath the third opening, and then annealing the semiconductor layer structure in a hydrogen-containing environment.

[0040] In some embodiments, at least partially removing the spacers from the sidewalls of the first mask to form a third opening in the mask structure comprises completely removing the spacers from the sidewalls of the first mask such that the third opening has a first width.

[0041] According to a further embodiment of the present invention, there is provided a method for forming a semiconductor device, wherein a first mask is formed on a semiconductor layer structure, the first mask including a first opening. A second mask is formed by forming spacers on sidewalls of the first mask exposed by the first opening, and the first and second masks constitute a mask structure having a second opening. A dopant is implanted into the semiconductor layer structure through the second opening to form an implanted region in the semiconductor layer structure. The spacers are at least partially removed from the sidewalls of the first mask. The semiconductor layer structure is etched to form a gate trench self-aligned with the implanted region.

[0042] In some embodiments, the semiconductor layer structure is a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a well layer having a second conductivity type, and a source region having the first conductivity type on the well layer, and the dopant implanted into the semiconductor layer structure through the second opening is a dopant of the second conductivity type.

[0043] In some embodiments, at least partially removing the spacers from the sidewalls of the first mask comprises completely removing the spacers from the sidewalls of the first mask such that the semiconductor layer structure is etched using only the first mask as an etch mask.

[0044] In some embodiments, the implanted region is a trench shield region having the second conductivity type.

[0045] In some embodiments, the second opening exposes the semiconductor layer structure.

[0046] In some embodiments, the spacer covers the semiconductor layer structure exposed by the first opening such that the second opening does not expose the semiconductor layer structure.

[0047] In some embodiments, the method further includes, after etching the semiconductor layer structure to form the gate trench, removing the first mask, oxidizing exposed portions of the semiconductor layer structure, and removing the oxidized portions of the semiconductor layer structure.

[0048] In some embodiments, the method further includes, after etching the semiconductor layer structure to form the gate trench, rounding a bottom corner of the gate trench and / or activating the implanted second conductivity dopant via a heating step.

[0049] In some embodiments, the second mask comprises silicon. In some embodiments, the second mask further comprises oxygen. In some embodiments, the first mask comprises both silicon and nitrogen.

[0050] In some embodiments, forming spacers on the sidewalls of the first mask exposed by the first opening to form the second mask includes oxidizing the sidewalls of the first mask.

[0051] In some embodiments, the implanted region is directly below the gate trench and the width of the implanted region is greater than the width of the gate trench.

[0052] In some embodiments, the implanted regions extend onto the lower portions of opposing sidewalls of the gate trench.

[0053] According to further embodiments of the present invention, methods for forming a semiconductor device are provided. These methods include a semiconductor layer structure including a drift region having a first conductivity type, a well region having a second conductivity type above the drift region, and a source region having the first conductivity type above the well region. A first mask is formed on the semiconductor layer structure, the first mask including a first opening. Dopants of the second conductivity type are implanted into the semiconductor layer structure through at least a portion of the semiconductor layer structure exposed by the first opening to form an implanted region of the second conductivity type in the drift region. After the dopants of the second conductivity type are implanted into the semiconductor layer structure, the portion of the source region exposed through the first opening still has the first conductivity type.

[0054] In some embodiments, after dopants of the second conductivity type are implanted into the semiconductor layer structure, a portion of the drift region between the well region and the implanted region still has the first conductivity type.

[0055] In some embodiments, the first opening is a longitudinally extending first opening having a first width, and the method further includes forming spacers on sidewalls of the first mask exposed by the first opening to form a second mask, the first and second masks constituting a mask structure having a longitudinally extending second opening having a second width smaller than the first width. In such embodiments, dopants of a second conductivity type may be implanted into the semiconductor layer structure through the second opening.

[0056] In some embodiments, the method further includes at least partially removing spacers from sidewalls of the first mask to form a third opening in the mask structure, and then etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure directly beneath the third opening.

[0057] In some embodiments, the first mask includes a material that includes both silicon and nitrogen, and the second mask includes silicon.

[0058] In some embodiments, the second mask further comprises oxygen.

[0059] In some embodiments, the implanted region is directly below the gate trench and the width of the implanted region is greater than the width of the gate trench.

[0060] In some embodiments, the implanted regions extend onto the lower portions of opposing sidewalls of the gate trench. [Brief explanation of the drawings]

[0061] [Figure 1] 1 is a schematic graph illustrating the relationship between operating time to breakdown and electric field level applied to a gate oxide layer of a power semiconductor device. [Figure 2A] 1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2B] 1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2C] 1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2D] 1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2E] 1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2F] 1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2G] 1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2H] 1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2I]1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2J] 1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2K] 1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2L] 1A to 1C are schematic vertical cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2M] 1A to 1C are schematic horizontal cross-sectional views illustrating a method for fabricating a gate trench power MOSFET according to an embodiment of the present invention. [Figure 2N] FIG. 2C is a schematic horizontal cross section showing a different possible connection scheme between the p-well and the source contact, which can be used instead of the connection scheme shown in Figure 2M. [Figure 2O] FIG. 2C is a schematic horizontal cross section showing a different possible connection scheme between the p-well and the source contact, which can be used instead of the connection scheme shown in Figure 2M. [Figure 3A] 2H is a schematic vertical cross-sectional view corresponding to FIG. 2H showing a modified version of the gate trench power MOSFET of FIGS. 2A-2M. FIG. [Figure 3B] 2H is a schematic vertical cross-sectional view corresponding to FIG. 2H showing a modified version of the gate trench power MOSFET of FIGS. 2A-2M. FIG. [Figure 4] 2D and 2E are schematic vertical cross-sectional views corresponding to FIG. 2D, illustrating another method for fabricating the gate trench power MOSFET of FIGS. 2L-2M. [Figure 5A] 5A-5C are schematic vertical cross-sectional views illustrating a method of fabricating a gate trench power MOSFET according to a further embodiment of the present invention. [Figure 5B] 5A-5C are schematic vertical cross-sectional views illustrating a method of fabricating a gate trench power MOSFET according to a further embodiment of the present invention. [Figure 5C]5A-5C are schematic vertical cross-sectional views illustrating a method of fabricating a gate trench power MOSFET according to a further embodiment of the present invention. [Figure 5D] 5A-5C are schematic vertical cross-sectional views illustrating a method of fabricating a gate trench power MOSFET according to a further embodiment of the present invention. [Figure 5E] 5A-5C are schematic vertical cross-sectional views illustrating a method of fabricating a gate trench power MOSFET according to a further embodiment of the present invention. [Figure 5F] 5A-5C are schematic cross-sectional side views illustrating a method of fabricating a gate trench power MOSFET according to a further embodiment of the present invention. [Figure 6] 5B is a schematic vertical cross-sectional view corresponding to FIG. 5C, showing a modified version of the gated trench power MOSFET of FIGS. 5A-5F. FIG. [Figure 7] 1 is a flow chart illustrating a method for fabricating a gate trench semiconductor device according to an embodiment of the present invention. [Figure 8] 1 is a flow chart illustrating a method for fabricating a gate trench semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0062] Vertical silicon carbide-based power semiconductor devices with gate trenches, such as vertical power MOSFETs and IGBTs, are attractive for many applications due to their relatively low intrinsic on-resistance, potentially resulting in more efficient power switching operation. Gate-trench vertical power devices exhibit lower resistivity during on-state operation because the channel is formed on the sidewalls of the gate trench. Furthermore, the carrier mobility of the sidewall channel can be approximately two to four times higher than the corresponding carrier mobility in the horizontal channel of a standard (i.e., non-gated trench) vertical power device, thereby enabling higher current densities during on-state operation and faster switching speeds. Furthermore, gate-trench designs allow for a smaller overall device pitch, enabling increased integration density. The reduced conduction losses (due to reduced on-state resistance) and increased switching speeds make gate-trench power devices well suited for high-frequency power applications with low- to moderate-voltage blocking requirements (e.g., 600 to 1200 volts). These devices also have fewer requirements for associated passive components and require relatively simple cooling schemes. Because MOSFETs are the most widely used silicon carbide-based trench-type power semiconductor gate devices, the following description will focus on MOSFET embodiments. However, it will be understood that each of the described embodiments may alternatively be implemented using a non-oxide gate dielectric layer (e.g., nitride, high-k materials, etc.), and that the same techniques can be used to form other gated trench power semiconductor devices, such as IGBTs, gate-controlled thyristors, etc.

[0063] As mentioned above, gate-trench power MOSFETs are susceptible to oxide reliability issues due to the presence of high electric fields in the gate oxide layer lining the bottom and sidewalls of the gate trench. The high electric fields can degrade the gate oxide layer over time, ultimately resulting in device failure. When a gate-trench MOSFET operates in reverse blocking mode (i.e., when the MOSFET is in the off state), the MOSFET's source terminal is typically grounded, the gate terminal is typically grounded or biased at a negative voltage, and the drain terminal is typically subjected to a high positive voltage. Under such reverse blocking mode, a high electric field extends upward from the drain terminal (at the bottom of the semiconductor layer structure) toward the top surface of the semiconductor layer structure. Therefore, under reverse blocking mode, the bottom of the gate dielectric layer experiences the highest electric field level. Due to field crowding effects, the electric field level can be particularly high at the lower "corners" of the gate oxide layer at the bottom edge of the gate trench (i.e., the portion of the gate oxide layer covering the area where the gate trench sidewalls meet the bottom of the gate trench). Furthermore, due to the difference in the dielectric constants of silicon carbide and silicon oxide, the electric field in a silicon oxide gate oxide layer can be approximately 2.6 times higher than that in the adjacent silicon carbide. When the electric field reaches a critical level, Ecr, dielectric breakdown of the silicon oxide occurs. To avoid such breakdown, power MOSFETs are sometimes operated at lower drain voltages during reverse blocking operation to prevent the electric field from reaching levels that would cause dielectric breakdown. In other words, the voltage rating of a power MOSFET is sometimes set to prevent premature gate oxide breakdown.

[0064] To reduce the electric field level in the gate oxide layer during reverse blocking operation, conventional gate trench power MOSFETs often incorporate so-called "trench shield regions" directly beneath the gate trench. These trench shield regions comprise a heavily doped semiconductor layer with the same conductivity type as the device's channel region. The following discussion focuses on n-type devices with p-type channels and trench shield regions. The trench shield regions may extend, for example, 0.5 to 1.0 microns or more downward from the bottom of the gate trench into the device's semiconductor layer structure. The protection these trench shield regions provide to the gate oxide layer increases with increasing trench shield region depth. The trench shield regions are electrically connected to the MOSFET's source terminal by p-type trench shield region connection patterns. These trench shield connection patterns may be within and / or outside the active region of the device.

[0065] The trench shield region is typically formed through one or more ion implantation processes in which p-type dopant ions are implanted into the bottom of the gate trench. However, the sidewalls of the gate trenches are typically not perfectly vertical; instead, they slope outward with increasing distance from the bottom of each gate trench. As a result, some p-type dopant ions are implanted directly into the sidewalls of each gate trench during the ion implantation process. Furthermore, some of the p-type dopant ions bounce off the exposed portion of the n-type drift region directly below each gate trench, and some of these "reflected" p-type dopant ions are implanted into the sidewalls of the gate trench. The implantation of p-type dopant ions into the sidewalls of the gate trenches via these two mechanisms during the ion implantation process performed to form the trench shield region can be problematic for two reasons.

[0066] First, the additional p-type dopant ions implanted into the sidewalls of the gate trench act to increase the doping concentration of the p-type channel region formed on those sidewalls. This can degrade MOSFET performance, since the p-type channel region is typically doped to a level that optimizes device performance. Second, the p-type ions implanted into the sidewalls can also convert portions of the lightly doped n-type drift region that forms the bottom of each sidewall to p-type material. When this occurs, the unit cell no longer operates as a transistor. While oxide spacers or other masks can be formed on the sidewalls of the gate trench to prevent p-type dopant ions from implanting into the sidewalls during the ion implantation process, using such masks complicates the manufacturing process and also limits the width of the trench shield region relative to the width of the gate trench.

[0067] Another potential problem with conventional techniques for forming trench shield regions is that the trench shield region may not always be perfectly aligned with the gate trench. For example, if the trench shield region is misaligned such that its center is offset to the left (e.g., by 0.1 to 0.6 microns) relative to the center of the associated gate trench, the trench shield region may provide reduced protection to the portion of the gate oxide layer lining the lower right side of the gate trench. As a result, a higher electric field will form in the gate oxide layer on the lower right side of the gate trench during device operation. The presence of such misalignment may require a reduction in the device voltage rating and / or a reduction in device yield (to filter out devices with high levels of misalignment).

[0068] According to an embodiment of the present invention, a gate trench power semiconductor device is provided that includes a trench shield pattern that is self-aligned with each gate trench. A gate trench power semiconductor device according to an embodiment of the present invention can be fabricated by forming a mask structure on a suitable semiconductor layer structure, patterning the mask structure to expose areas where gate trenches will be formed, and then performing a high-energy ion implantation process to form trench shield regions in portions of the semiconductor layer structure directly beneath the subsequently formed gate trenches. Portions of the mask structure can be removed, and the remaining mask material can then be used as an etch mask during the gate trench formation process. By using at least a portion of the same mask structure for both the trench shield region ion implantation process and the gate trench etching process, the trench shield regions can be self-aligned with each gate trench.

[0069] In some embodiments, a multi-level mask structure can be used during the ion implantation process performed to form the trench shield regions. The multi-level mask structure can include, for example, a first mask (e.g., a nitride, oxynitride, or polysilicon mask) patterned to form openings above regions of the semiconductor layer structure where the gate trenches will be formed. For example, a second mask in the form of oxide spacers is formed over the first mask (e.g., on the top surface of the first mask and on the sidewalls of the first mask exposed by the openings). The second mask acts to reduce the width of each opening in the first mask. The trench shield region ion implantation process is performed while the entire mask structure remains intact. The second mask can then be removed (or partially removed), which acts to widen the openings in the mask structure, allowing the etching process used to form the gate trenches to be performed. The thickness of the oxide spacers can be selected to optimize the width of each trench shield region compared to the width of the associated gate trench. This approach allows for the formation of trench shield regions that extend well beyond the sidewalls of the associated gate trench without the use of angled ion implantation, while still allowing each trench shield region to be self-aligned with its associated gate trench.

[0070] In some embodiments, the ion implantation step used to form the trench shield region may be a high-energy ion implantation step that primarily implants ions into portions of the semiconductor layer structure near or below the bottom of a gate trench that will be formed in the semiconductor layer structure in a subsequent processing step, thereby allowing for the use of a single implantation step and also reducing the impact of the ion implantation step on portions of the semiconductor layer structure that will ultimately function as the channel region of the device.

[0071] Because the ion implantation step used to form the trench shield region is performed before the gate trench is formed, the problem of dopant ions being implanted into the non-vertical sidewalls of the gate trench is eliminated, as is the possibility of dopant ions bouncing off the bottom of the gate trench and implanting them into the sidewalls of the gate trench. This avoids the aforementioned problem of unintentional implantation into the sidewalls of the gate trench adversely affecting the doping concentration of the channel region or the portion of the drift region below the channel region. Additionally, in at least some embodiments, the use of a multi-layer mask structure allows for easy control of the relative widths of the gate trench and the trench shield region. This allows designers to optimize the trade-off between specific on-resistance and maximum gate oxide electric field when the device is operated at its rated voltage level. This is important because in some applications, the limiting factor for device performance may be the maximum specific on-resistance, while in other applications, the limiting factor may be the maximum gate oxide electric field (which acts to limit the device's voltage rating). The techniques disclosed herein therefore enable designers to produce devices that are optimized for different applications, meaning that the invention allows the production of devices that exhibit higher performance for a variety of applications than could be provided using conventional manufacturing techniques.

[0072] According to an embodiment of the present invention, there is provided a semiconductor device including a wide bandgap semiconductor layer structure, the wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, a source region having the first conductivity type on the well region, a gate electrode in a gate trench, and a trench shield region having the second conductivity type directly below the gate trench, the width of the trench shield region exceeding the width of the gate trench.

[0073] According to a further embodiment of the present invention, there is provided a semiconductor device including a wide bandgap semiconductor layer structure, wherein the wide bandgap semiconductor layer structure again includes a drift region having a first conductivity type, a well region having a second conductivity type above the drift region, a source region having the first conductivity type above the well region, a gate electrode in a gate trench, and a trench shield region having the second conductivity type directly below the gate trench, wherein a portion of the drift region having the first conductivity type is interposed between a bottom surface of the gate trench and the trench shield region.

[0074] Further embodiments of the present invention provide methods for fabricating a power semiconductor device. According to certain of these methods, a first mask including a longitudinally extending first opening having a first width is formed on a semiconductor layer structure. Spacers are formed on sidewalls of the first mask exposed by the first opening to form a second mask, and the first and second masks form a mask structure having a longitudinally extending second opening having a second width smaller than the first width. Dopants are implanted through the second opening to form an implanted region in the semiconductor layer structure. The spacers are at least partially removed from the sidewalls of the first mask to form a third opening in the mask structure. The mask structure is then etched using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure directly below the third opening.

[0075] According to a further embodiment of the present invention, there is provided a method for manufacturing a power semiconductor device, in which a first mask including a first opening is formed on a semiconductor layer structure. A second mask is formed by forming spacers on sidewalls of the first mask exposed by the first opening, and the first and second masks constitute a mask structure having a second opening. Dopants are implanted into the semiconductor layer structure through the second opening to form an implanted region in the semiconductor layer structure. The spacers are at least partially removed from the sidewalls of the first mask. The semiconductor layer structure is then etched to form a gate trench self-aligned with the implanted region.

[0076] According to further embodiments of the present invention, methods for manufacturing a power semiconductor device are provided. These methods include providing a semiconductor layer structure including a drift region having a first conductivity type, a well region having a second conductivity type above the drift region, and a source region having the first conductivity type above the well region. A first mask is formed on the semiconductor layer structure, the first mask including a first opening. Dopants of the second conductivity type are implanted into the semiconductor layer structure through at least a portion of the semiconductor layer structure exposed by the first opening to form an implanted region of the second conductivity type in the drift region. After the dopants of the second conductivity type are implanted into the semiconductor layer structure, the portion of the source region exposed through the first opening still has the first conductivity type.

[0077] Next, embodiments of the present invention will be described in more detail with reference to FIGS. 2A-8. It will be understood that the features of different embodiments disclosed herein may be combined in any manner to provide many additional embodiments. Accordingly, while various features of the present invention are described below with reference to specific examples, it will be understood that these features may be added to other embodiments and / or substituted for exemplary features of other embodiments to provide many additional embodiments. Accordingly, the present invention should be understood to encompass these different combinations. Furthermore, while the exemplary embodiments focus on MOSFET implementations, it will be understood that the same techniques can be used in other gate trench power semiconductor devices, such as insulated gate bipolar transistors (IGBTs), gate-controlled thyristors, and the like.

[0078] 2A-2M are schematic cross-sectional views illustrating a method for fabricating a gated trench power MOSFET 100 according to an embodiment of the present invention. More specifically, FIGS. 2A-2L are schematic vertical cross-sectional views illustrating a method for fabricating the semiconductor layer structure of the gated trench power MOSFET 100. FIG. 2M is a schematic horizontal cross-sectional view of the MOSFET 100 taken along line 2M-2M in FIG. 2L. As used herein, a vertical cross-sectional view of a power semiconductor device refers to a cross-sectional view of the device taken along a plane perpendicular to the major surfaces of the semiconductor layer structure of the device. Similarly, a horizontal cross-sectional view of a power semiconductor device refers to a cross-sectional view of the device taken along a plane parallel to the major surfaces of the semiconductor layer structure of the device.

[0079] Referring to FIG. 2A, an n-type silicon carbide substrate 110 is provided. The substrate 110 may include, for example, a 4H-silicon carbide or a 6H-silicon carbide substrate. In other embodiments, the substrate 110 may be or include a different semiconductor material (e.g., a III-nitride based material, silicon, gallium arsenide, zinc oxide, etc.). The substrate 110 may be heavily doped with n-type impurities (n + ) may be (i.e., n + The impurities may include, for example, nitrogen or phosphorus. The n-type doping concentration of the substrate 110 is, for example, 1×10 18 atoms / cm 3 ~1×10 21 atoms / cm 3 Although other doping concentrations may be used, substrate 110 may be relatively thick in some embodiments (e.g., 20-100 microns or more). It should be noted that while the substrate is shown in the figures as a relatively thin layer, this is done to allow for the thicknesses of other layers and regions in the figures to be magnified, and it will be understood that substrate 110 is typically much thicker than shown. The thicknesses of various other layers in MOSFETs according to embodiments of the invention may likewise not be shown to scale in the figures to allow for the magnification of other portions of the device.

[0080] Lightly doped (n- ) A silicon carbide drift region 120 (sometimes referred to herein as drift layer 120) is provided on the upper surface of substrate 110. N-type drift region 120 can be formed, for example, by epitaxial growth on substrate 110. N-type drift region 120 can have a thickness of, for example, 5×10 15 ~5×10 17 dopant / cm 3 The n-type drift region 120 may have a doping concentration of, for example, 5×10. The n-type drift region 120 may be a thick region having a vertical height above the substrate 110 of, for example, 3 to 50 microns. In some embodiments, the upper portion of the n-type drift region 120 may include an n-type current spreading layer (not shown) that is more highly doped than the lower portion of the n-type drift region 120. If an n-type current spreading layer is provided, its dopant concentration may be, for example, 5×10. 16 ~1×10 18 may be.

[0081] 2A , a moderately doped (p)p-type silicon carbide well layer 130 is then formed on top of the n-type drift region 120. The moderately doped (p)p-type silicon carbide well layer 130 can be formed by epitaxial growth or, as shown in FIG. 2A , by implanting p-type dopant ions into the top of the n-type drift region 120 to convert the top of the n-type drift layer into a p-well layer 130. The moderately doped p-type well layer 130 may have a graded doping profile in some embodiments.

[0082] Referring to FIG. 2B, the heavily doped (n + A heavily doped (n) silicon carbide source layer 140 is formed on or on top of the p-type silicon carbide well layer 130. As shown, the heavily doped n-type silicon carbide source layer 140 is typically formed by ion implantation. When formed by ion implantation, the top of the p-type silicon carbide well layer 130 is left as a heavily doped (n +) into a silicon carbide source layer 140. The heavily doped n-type silicon carbide source layer 140 is, for example, 1×10 19 atoms / cm 3 ~5×10 21 atoms / cm 3 2B (see FIG. 2M), n-type dopants may be selectively implanted into p-type silicon carbide well layer 130 such that p-type well layer 130 extends to the top surface of semiconductor layer structure 150 in selected regions. Substrate 110, drift region 120, well layer 130, and source layer 140, along with various regions / patterns formed therein, such as trench shield regions and trench shield connection patterns (described below), comprise semiconductor layer structure 150 of power MOSFET 100.

[0083] Referring to FIG. 2C, a first mask 162 is formed on the top surface of the source layer 140. The first mask 162 may include, for example, a nitride mask (e.g., silicon nitride) or an oxynitride mask (e.g., silicon oxynitride), or a multi-layer mask, such as a thin oxide (e.g., silicon oxide) layer formed with a nitride layer. However, it will be understood that a wide variety of other materials may be used. For example, the first mask 162 may include a polysilicon mask in other embodiments. As shown in FIG. 2C, the first mask 162 is then patterned (e.g., using standard photolithographic patterning techniques) to form an opening 164 that exposes a selected portion of the semiconductor layer structure 150. The opening 164 may be located above a location within the semiconductor layer structure 150 where a trench shield region will be formed in a subsequent processing step.

[0084] 2D , a second mask 166 in the form of spacers is formed on the first mask 162 and the semiconductor layer structure 150. For example, the second mask 166 may be conformally formed on the first mask 162 and the semiconductor layer structure 150. Alternatively, the second mask 166 may be selectively deposited on the first mask 162 (and, as shown, may also optionally be formed on portions of the semiconductor layer structure 150 exposed by the openings 164 in the first mask 162). The first mask 162 and the second mask 166 together form the mask structure 160. The second mask 166 may include, for example, oxide spacers (e.g., silicon oxide spacers). Regardless of how the second mask 166 is formed, the second mask / spacers 166 may conformally cover the sidewalls of the first mask 162 exposed by the openings 164. Thus, the second mask / spacers 166 formed on the sidewalls of the first mask 162 reduce the size of the first openings 164, thereby forming second openings 168 in the mask structure 160. As shown, the second mask may be formed on exposed portions of the semiconductor layer structure 150, so the second openings 168 may not extend completely through the mask structure 160. The thickness of the second mask 166, particularly the thickness of the portion of the second mask 166 formed on the sidewalls of the first mask 162, may be carefully controlled to control the width of each second opening 168.

[0085] 2E, the second mask 166 may be patterned to remove portions formed on the semiconductor layer structure 150 in the second openings 168 (if such portions of the second mask 166 were formed initially) to expose selected portions of the semiconductor layer structure 150 in preparation for a subsequent ion implantation operation. However, it will be understood that in some embodiments, the patterning step shown with reference to FIG. 2E may be omitted, the portions of the second mask 166 formed on the semiconductor layer structure 150 in the second openings 168 may be left intact, and ion implantation may be performed through these portions of the second mask 166.

[0086] Referring to FIG. 2F, an ion implantation process is performed to implant p-type dopant ions into the portion of the semiconductor layer structure 150 directly under the second opening 168. The combined thickness (as used herein, "thickness" refers to any extent in the z-direction) of the first mask 162 and the second mask 166 may be sufficient to substantially block p-type dopant ions implanted into the portion of the mask structure 160 where the first and second masks 162, 166 are vertically stacked from reaching the semiconductor layer structure 150. As shown in FIG. 2F, the ion implantation step forms a plurality of preliminary trench shield regions 172 in the semiconductor layer structure 150. The preliminary trench shield regions 172 are formed by heavily doped (p + ) silicon carbide region.

[0087] In an exemplary embodiment, the preliminary trench shield region 172 is approximately 1×10 17 ~1×10 21 and may extend to a depth of 0.5 to 3.0 microns from the top surface of semiconductor layer structure 150. In other embodiments, preliminary trench shield region 172 may have a doping concentration of about 1×10 18 ~1×10 20 , about 1×10 19 ~1×10 20 , about 1×10 17 ~1×10 20 , or approximately 1 × 10 18 ~1×10 21In other embodiments, the depth of the preliminary trench shield region 172 may be 1.0-3.0 microns, 1.0-2.5 microns, 1.5-3.0 microns, 1.5-2.5 microns, or 0.5-2.5 microns. Any of the above dopant concentrations may be compatible with any of the above depths of the preliminary trench shield region 172. As shown, the preliminary trench shield region 172 extends through the silicon carbide source layer 140, through the silicon carbide well layer 130, and into the silicon carbide drift region 120. The trench shield region 170 (described below) formed from the preliminary trench shield region 172 in later processing steps can both act to reduce the electric field levels formed in the gate oxide layer (described below) formed in the gate trench (described below) of the device during operation, as described in more detail below.

[0088] 2F, the p-type dopant ions are scattered to some extent when they collide with the protons and neutrons of the material forming semiconductor layer structure 150. This causes pre-trench shield region 172 to "bloom" in the sense that the width of pre-trench shield region 172 increases with increasing depth from the top surface of semiconductor layer structure 150.

[0089] 2F, this ion implantation step can implant at least some of the p-type dopant ions relatively deeply into the semiconductor layer structure 150. In the illustrated embodiment, p-type ions are shown implanted at various depths into the semiconductor layer structure 150, thereby, for example, implanting the heavily doped n-type ions directly beneath the second opening 168. +Sufficient p-type ions are implanted into the source layer 140 and portions of the lightly doped n-type drift region 120 to convert these n-type regions to p-type material, such that the preliminary trench shield region 172 can convert the moderately doped p-type silicon carbide well layer 130 into a plurality of moderately doped p-wells 132 and the heavily doped n-type silicon carbide source layer 140 into a plurality of heavily doped n-type source regions 142 that function as source regions of the power MOSFET 100.

[0090] 5A-5F, some embodiments of the present invention may use so-called "deep" ion implantation techniques in which ions are implanted at high energy, with the ions being implanted substantially entirely through the source layer 140 and the p-well 130. Using such deep ion implantation techniques, the heavily doped n + The source layer 140 and the portion of the drift region 120 below the p-well layer 130 directly below the second opening 168 (this portion of the drift region 120 is removed when the gate trench is formed) may remain n-type material. It will be understood that either type of ion implantation process may be used here. In other words, in other embodiments, the deep ion implantation technique described below with reference to Figures 5A-5F may be used instead of the "shallow and deep" ion implantation technique shown in Figure 2F.

[0091] Referring to FIG. 2G, after forming preliminary trench shield region 172, second mask 166 is at least partially removed to convert second opening 168 into third opening 169 that is wider than second opening 168. In the illustrated embodiment, second mask 166 is completely removed so that the only mask remaining on the device is first mask 162. In this case, third opening 169 is identical to first opening 164. Third opening 169 exposes preliminary trench shield region 172 and a portion of source region 142 in semiconductor layer structure 150. In other embodiments (not shown), second mask 166 may be thinned but not completely removed. In such embodiments, third opening 169 is wider than second opening 168 but narrower than first opening 164.

[0092] Referring to FIG. 2H , a plurality of gate trenches 180 are formed in the top surface of the semiconductor layer structure 150 via etching using the remaining mask structure 160 (here, the first mask 162) as an etch mask. Each gate trench 180 extends to the top surface of the n-type drift region 120. While FIG. 2H shows only one complete gate trench 180 and a portion of a second gate trench 180, it will be understood that typically a large number of gate trenches 180 are provided, with the longitudinal axis of each gate trench 180 extending in a first direction above the substrate 110 (here, the gate trenches 180 extend in the x-direction) and the gate trenches 180 being spaced apart from one another in a second direction (here, the y-direction) such that the gate trenches 180 extend longitudinally parallel to one another. Each gate trench 180 has a length (corresponding to the distance in the x-direction), a width (corresponding to the distance in the y-direction), and a depth (corresponding to the distance in the z-direction). The length direction is the longest direction, and thus the longitudinal axis of each gate trench 180 refers to the axis extending lengthwise through the center of the gate trench 180. Each gate trench 180 has first and second opposing sidewalls and a bottom surface, each extending in the x-direction and thus parallel to the longitudinal axis. As used herein, references to the "width" of a gate trench 180 refer to the shortest distance between opposing longitudinal sidewalls of the gate trench 180 (i.e., the shortest distance between opposing longitudinal sidewalls in the y-direction).

[0093] As described above, when the preliminary trench shield region 172 extends to the top surface of the semiconductor layer structure 150, the formation of the preliminary trench shield region 172 acts to convert the moderately doped p-type silicon carbide well layer 130 into a plurality of moderately doped p-wells 132 and the heavily doped n-type silicon carbide source layer 140 into a plurality of heavily doped n-type source regions 142. When only a high-energy ion implantation process is used such that the preliminary trench shield region 172 is formed as a deep buried region (see the description of Figures 5A-5F below), the formation of the gate trench 180 acts to convert the moderately doped p-type silicon carbide well layer 130 into a plurality of moderately doped p-wells 132 and the heavily doped n-type silicon carbide source layer 140 into a plurality of heavily doped n-type source regions 142. In either case, the portion of each p-well 132 adjacent to the gate trench 180 functions as a transistor channel 134, as described below.

[0094] While FIG. 2H illustrates a MOSFET 100 having multiple gate trenches 180 that all extend parallel to one another in a first direction, it will be understood that embodiments of the present invention are not so limited. Power MOSFETs having a wide variety of gate trench designs are known in the art. For example, some power MOSFETs have both a first set of gate trenches that extend through the semiconductor layer structure in a first direction and a second set of gate trenches that extend through the semiconductor layer structure in a second (typically perpendicular) direction, such that the two sets of trenches intersect with one another. As another example, some MOSFETs have gate trenches formed in a rectangular, hexagonal, octagonal, or circular shape (when viewed from above), where the trenches surround a well region (within which the source region resides). It will be understood that the techniques disclosed herein can be used with MOSFETs having any gate trench design, including the additional exemplary designs described above.

[0095] The etching step performed to form the gate trenches 180 removes the upper portion of each preliminary trench shield region 172, thereby forming multiple trench shield regions 170 beneath the respective gate trenches 180. In the illustrated embodiment, each gate trench 180 is narrower (in width) than the associated trench shield region 170 beneath it. As a result, each trench shield region 170 extends onto the lower sidewall of its associated gate trench 180. Because the width of the second mask 166 formed on the sidewall of the first mask 162 can be set to any desired value, the width W2 of each gate trench 180 relative to the width W1 of the associated trench shield region 170 can be set to any desired value. As mentioned above, FIG. 2H illustrates an embodiment in which the width W1 of the trench shield region 170 (measured at the depth of the bottom of the gate trench 180) is slightly wider than the width W2 of the associated gate trench 180.

[0096] 3A is a cross-section (corresponding to the cross-section of FIG. 2H) of a MOSFET 100A according to a further embodiment of the invention, in which the width of second mask 166 on the sidewalls of first mask 162 has been reduced from that shown in FIGS. 2D-2F. As can be seen in FIG. 3A, this results in width W1 of trench shield region 170 (measured at the depth of the bottom of associated gate trench 180) being significantly wider than width W2 of associated gate trench 180.

[0097] In contrast, Figure 3B is a cross-section (corresponding to the cross-section of Figure 2H) of a MOSFET 100B according to a further embodiment of the present invention, in which the width of second mask 166 on the sidewalls of first mask 162 has been increased from that shown in Figures 2D-2F. As can be seen in Figure 3B, this results in a width W1 of trench shield region 170 (measured at the depth of the bottom of associated gate trench 180) that is narrower than the width W2 of associated gate trench 180.

[0098] 2H and 3A, the gate trench 180 has left and right sidewalls that extend parallel to the longitudinal axis of the gate trench 180, the left and right sidewalls being laterally spaced apart from one another. In some embodiments, the left side of the trench shield region 170 can extend laterally at least 0.1 microns beyond the lower edge of the left sidewall of the gate trench, and the right side of the trench shield region can extend laterally at least 0.1 microns beyond the lower edge of the right sidewall of the gate trench. In other embodiments, the left side of the trench shield region 170 can extend laterally at least 0.3 microns beyond the lower edge of the left sidewall of the gate trench, and the right side of the trench shield region can extend laterally at least 0.3 microns beyond the lower edge of the right sidewall of the gate trench. In yet another embodiment, the left side of the trench shield region 170 can extend laterally at least 0.4 microns beyond the lower edge of the left sidewall of the gate trench, and the right side of the trench shield region extends laterally at least 0.4 microns beyond the lower edge of the right sidewall of the gate trench.

[0099] In some embodiments, the left side of trench shield region 170 can extend laterally 0.1 microns to 0.8 microns beyond the lower edge of the left sidewall of the gate trench, and the right side of trench shield region can extend laterally 0.1 microns to 0.8 microns beyond the lower edge of the right sidewall of the gate trench. In other embodiments, the left side of trench shield region 170 can extend laterally 0.1 microns to 0.6 microns beyond the lower edge of the left sidewall of the gate trench, and the right side of trench shield region can extend laterally 0.1 microns to 0.6 microns beyond the lower edge of the right sidewall of the gate trench. In yet other embodiments, the left side of trench shield region 170 can extend laterally 0.1 microns to 0.5 microns beyond the lower edge of the left sidewall of the gate trench, and the right side of trench shield region can extend laterally 0.1 microns to 0.5 microns beyond the lower edge of the right sidewall of the gate trench. In yet additional embodiments, the left side of trench shield region 170 can extend laterally 0.2 microns to 0.5 microns beyond the lower edge of the left sidewall of the gate trench, and the right side of trench shield region can extend laterally 0.2 microns to 0.5 microns beyond the lower edge of the right sidewall of the gate trench. Note that in some embodiments, the left side of trench shield region 170 can extend laterally beyond the lower edge of the left sidewall of the gate trench by a different amount than the right side of trench shield region extends laterally beyond the lower edge of the right sidewall of the gate trench.

[0100] In some embodiments, the gate trench may overlap less than 98% of the lateral width of the trench shield region. In this context, "overlapping" means that, in a vertical cross section, such as in FIG. 2H, the bottom of the gate trench 180 is located above the trench shield region 170. Thus, for example, in FIG. 2H, if width W2 is 8 arbitrary units and width W1 is 10 arbitrary units, the gate trench overlaps 80% of the lateral width of the trench shield region 170. In other embodiments, the gate trench may overlap less than 95%, less than 90%, or less than 85% of the lateral width of the trench shield region 170.

[0101] 2I, the remaining portion of the mask structure 160 may be removed. If the remaining portion of the mask structure 160 is the first mask 162 and is formed as a nitride mask, the first mask 162 may be removed using a stripping operation.

[0102] Referring to FIG. 2J, a sacrificial oxidation process can be performed to convert exposed portions of the semiconductor layer structure 150 to silicon oxide. The “depth” to which the exposed silicon carbide is converted to silicon oxide can be controlled based on the length of the oxidation process, its temperature, pressure, and the amount of oxygen in the environment. An etching process is then performed to remove the oxidized silicon carbide. This sacrificial oxidation process can be used to remove surface portions of the silicon carbide that may have been damaged (e.g., roughened) during the ion implantation process. The sacrificial oxidation process can also widen the gate trench 180, as shown. In the illustrated embodiment, the gate trench 180 is widened so that the associated trench shield region 170 extends only slightly onto the lower sidewall of the gate trench 180. It will be appreciated that in other embodiments, the trench shield region 170 may be designed such that the trench shield region 170 is formed thicker on the lower sidewall of the associated gate trench 180 and / or extends further above the lower sidewall of the associated gate trench 180 (see, e.g., FIG. 3A).

[0103] Referring to FIG. 2K, a hydrogen etch can be performed. The hydrogen etch can further widen the gate trenches 180 and etch the top surface of the semiconductor layer structure 150. The hydrogen etch can also advantageously round the bottom corners of each gate trench 180 (note that these “corners” extend the entire length of each gate trench 180 in the x-direction). The rounding of the bottom corners of each gate trench 180 is transferred to the gate oxide layer formed in each respective gate trench 180 during subsequent processing operations (see FIG. 2L), thereby causing the gate oxide layer formed at the corners of each trench 180 to also have a rounded cross-sectional profile. These rounded gate oxide layers act to reduce the electric field levels at the bottom corners of the gate oxide layer during reverse blocking operation by reducing the electric field crowding effect that occurs in layers with sharp corners. This reduced electric field value potentially enables a higher voltage rating for power semiconductor devices according to embodiments of the present invention. Although not shown, the hydrogen etch can also act to round the corners at the top of each gate trench 180. This rounding of the corners at the top of the gate trench 180 can also advantageously reduce the value of the electric field at the top of the gate oxide layer during on-state operation.

[0104] After performing the hydrogen etch, an annealing process may be performed to activate the p-type dopants in the trench shield region 170 .

[0105] Referring to FIG. 2L, a gate insulating layer 182 is formed on the bottom and sidewalls of each gate trench 180. Typically, the gate insulating layer 182 is an oxide layer and is therefore referred to herein as a gate oxide layer 182. The gate oxide layer 182 can be formed by conformally forming an oxide layer on the bottom and sidewalls of each gate trench 180. The conformal gate oxide layer 182 may be formed by oxidizing the exposed silicon carbide via annealing in an oxygen-containing environment. Alternatively, the conformal gate oxide layer 182 may be formed by an oxide deposition step. Portions of the conformal gate oxide layer 182 may be removed to form openings through which source contacts 190 can connect to the source regions 142 and p-well extensions (described below). Removing these portions of the conformal gate oxide layer 182 leaves the gate oxide layer 182 in each gate trench 180.

[0106] A gate electrode 184 is formed on each gate oxide layer 182 to fill the respective gate trench 180. The gate electrodes 184 may each comprise a conductive material, such as polysilicon, silicate, or metal. An inter-metal dielectric layer 186 is formed on the exposed portions of the gate oxide layer 182 and the gate electrode 184. Source contacts 190 are formed on top of the device. The source contacts 190 are physically and electrically connected to the n-type source regions 142. The source contacts 190 may constitute or be electrically connected to the source terminal of the MOSFET 100. Although not visible in the cross-section of FIG. 2L, p-well extensions 136 may be formed in the MOSFET 100 that physically and electrically connect the p-well 132 to the source contacts 190 in selected regions of the device. These p-well extensions 136 are shown in plan view in FIG. 2M, and methods of forming these p-well extensions are known in the art. Additionally, trench shield connection regions (not shown) may be provided in either the active and / or inactive regions of MOSFET 100, electrically connecting p-well 132 to trench shield region 170. Drain contact 192 is formed on the underside of substrate 110. A gate contact (not shown) is also provided, typically connected to gate electrode 184 outside the cross-sectional view of FIG. 2L via one or more gate buses (not shown).

[0107] As mentioned above, the portion of each p-well 132 adjacent to the gate trench 180 functions as the vertical transistor channel 134. Thus, when a sufficient gate bias voltage is applied, current flows from the source contact 190 to the drain contact 192 along the current path indicated by the arrows in FIG.

[0108] 2M is a horizontal cross-section of the device shown in FIG. 2L taken along line 2M-2M (i.e., the cross-section is taken along the top surface of semiconductor layer structure 150). FIG. 2M shows how p-well extension 136 forms a series of islands that extend upward through source region 142 to the top surface of semiconductor layer structure 150. P-well extension 136 is formed by a heavily doped (p + ) p-type region. P-well extension 136 electrically connects p-well 132 to source contact 190. It will be understood that FIG. 2M shows one possible design in which p-well extension 136 is formed as an island within source region 142 when viewed from the top. Other designs are possible. For example, FIG. 2N shows a modified version of MOSFET 100 in which p-well extension 136 is formed as a horizontal stripe. FIG. 2O shows another modified version of MOSFET 100 in which p-well extension 136 is formed as a vertical stripe within source region 142.

[0109] The trench shield region 170 helps protect the corners of the gate oxide layer 182 from high electric fields during reverse blocking operation. However, there is a trade-off between the specific on-resistance of the MOSFET 100 and the maximum electric field that can occur in the gate oxide layer 182. In particular, the trench shield region 170 forms a so-called JFET region 176 in the drift layer. Current flows through this JFET region 176 from the source contact 190, through the channel 134, and then to the drain contact 192. If the trench shield region 170 is wider than the gate trench 180, the trench shield region 170 associated with the adjacent gate trench 180 acts to narrow the width of the JFET region 176, which acts to increase the specific on-resistance of the MOSFET 100 (because the current is forced to pass through a narrower region). This can be seen, for example, with reference to FIG. 3A (discussed above), where the trench shield region 180 is significantly wider than the gate trench 180. In some applications, low on-resistance may be more important than a high voltage rating, and in such embodiments, it may be beneficial to keep the width W1 of the trench shield region 170 equal to or less than the width W2 of the associated gate trench 180.

[0110] Because the thickness of the second mask 166 formed on the sidewalls of the first mask 162 can be carefully controlled, the methods of forming power semiconductor devices disclosed herein enable careful control of the relative widths of the trench shield regions 170 and the gate trenches 180, such that each trench shield region 170 can extend beyond the sidewalls of its associated gate trench 180 to any desired width. The methods described herein allow designers to easily account for any widening of the gate trench 180 that may occur during the sacrificial oxidation and / or hydrogen etch processing steps described above. In some applications, a particular on-resistance may be a limiting factor, while in other applications, voltage ratings may be more important. The techniques disclosed herein allow designers to easily optimize the relative widths of the trench shield regions 170 and the gate trenches 180 to optimize performance for any particular application.

[0111] Another potential problem in the fabrication of gate trench power semiconductor devices is misalignment of the device's trench shield regions and gate trenches. In some conventional fabrication techniques, different masks are used for the ion implantation step used to form the trench shield regions and the etching step used to form the gate trenches. If the second of these masks is not perfectly aligned with the first, the trench shield regions 170 will be laterally misaligned (i.e., in the y-direction) with respect to their respective gate trenches 180. When this occurs, the trench shield regions 170 extend laterally beyond the gate trenches 180 on one side of each gate trench 180, narrowing the JFET region 176 and increasing the on-resistance. This lateral misalignment problem in conventional power semiconductor devices can be reduced or eliminated by reducing the width of the trench shield regions 170. However, as discussed above, reducing the width of trench shield region 170 reduces its effectiveness, and therefore may reduce the voltage rating of MOSFET 100 to keep the electric field across the gate oxide layer at a level that does not degrade the gate oxide. As discussed above, techniques according to embodiments of the present invention automatically self-align each trench shield region 170 with its associated gate trench 180, thereby avoiding the performance degradation associated with misaligned trench shield regions 170.

[0112] It will be understood that the processing steps described above with reference to Figures 2A-2M may be performed in different orders in further embodiments. As an example, the hydrogen etch step described with reference to Figure 2J may be performed before the sacrificial oxidation step described with reference to Figure 2K. It will also be understood that in other embodiments, some of the processing steps (e.g., hydrogen etch step, sacrificial oxidation, etc.) may be omitted.

[0113] 2A-2M illustrate a method for forming MOSFET 100 in which spacers (e.g., oxide spacers) are deposited as second mask 166 on patterned first mask 162. According to a further embodiment of the invention, second mask 166A may alternatively be formed by oxidizing first mask 162A. This is shown schematically in FIG. 4, which corresponds to FIG. 2D.

[0114] As shown in FIG. 4, in embodiments of the present invention in which the second mask 166A is formed by oxidation, the first mask 162A may be formed using an easily oxidizable material, such as polysilicon. Once the first mask 162A has been patterned as described above with reference to FIG. 2D, the second mask 166A may be formed by performing an oxidation process on the device (e.g., by heating the device in an oxygen-containing environment). Because polysilicon oxidizes more easily than silicon carbide, a second mask 166A is formed on the top surface and sidewalls of the polysilicon first mask 162A, the second mask 166A being thicker than the exposed portion of the top surface of the semiconductor layer structure 150. As described above with reference to FIG. 2E, the oxidized material formed on the exposed portion of the top surface of the semiconductor layer structure 150 may then be removed, or may be left intact and the ion implantation step described above with reference to FIG. 2F may be performed through the oxidized silicon carbide material. The device shown in FIG. 4 may then be fabricated using the same processing steps as described above with reference to FIGS. 2D-2M, and therefore further description thereof will not be provided here.

[0115] 5A-5F are schematic cross-sectional views illustrating a gated trench power MOSFET 200 according to a further embodiment of the present invention. More specifically, FIGS. 5A-5E are schematic vertical cross-sectional views illustrating a method of fabricating the semiconductor layer structure of MOSFET 200. FIG. 5F is a schematic horizontal cross-sectional view of MOSFET 200 taken along line 5F-5F in FIG. 5E.

[0116] Referring to FIG. 5A , optional spacers (e.g., nitride spacers) 265 may be formed on the top surface of the semiconductor layer structure 150. The semiconductor layer structure 150 may be formed in the manner described above with reference to FIGS. 2A-2B . A mask 262 is then formed on the spacers 266 (or on the top surface of the semiconductor layer structure 150 if the spacers 266 are not provided). The mask 262 may comprise, for example, an oxide mask (e.g., silicon oxide). The mask 262 is patterned (e.g., using standard photolithographic patterning techniques) to form openings 264 and 266 that expose selected portions of the semiconductor layer structure 150. The opening 264 may be located above a location in the semiconductor layer structure 150 where a trench shield region will be formed in a subsequent processing step. The opening 266 may be located above a location in the semiconductor layer structure 150 where a trench support shield will be formed in a subsequent processing step. It will be understood that in some embodiments, the trench support shield may be omitted. In such an embodiment, openings 266 are not formed in mask 262 .

[0117] Referring to FIG. 5B, a high-energy "deep" ion implantation process is performed to implant p-type dopant ions through openings 264, 266. Due to the high energy level of the implantation, a majority of the p-type ions penetrate through source layer 140, p-well layer 130, and into drift region 120. Therefore, source layer 140 may remain n-type after the ion implantation step is performed, and in some cases, the portion of drift layer 120 directly below p-well layer 130 may also remain n-type after the ion implantation process is completed. As shown in FIG. 5B, the ion implantation process forms a plurality of recessed preliminary trench shield regions 272 in semiconductor layer structure 150. The preliminary trench shield regions 272 may be heavily doped (p-type) with any of the doping concentrations listed above for preliminary trench shield regions 172. +) silicon carbide regions. Pre-trench shield region 272 may similarly extend to any of the depths listed above for pre-trench shield region 172. As further shown in FIG. 5B, the ion implantation process also forms a plurality of buried trench support shields 274 within semiconductor layer structure 150. Trench support shields 274 (if included in the device) may be heavily doped (p + ) silicon carbide region. Trench support shield 274 can act to reduce the electric field levels that form in the gate oxide layer (described below) during device operation. Trench support shield 274 can also provide a low-resistance current path between the source and drain terminals of MOSFET 200 in the event of an avalanche breakdown. This low-resistance current path helps reduce the amount of heating of the device during an avalanche breakdown event, increasing the likelihood that MOSFET 200 can withstand such an event without damage.

[0118] As can be seen in FIG. 5B , p-type dopant ions scatter to some extent when they collide with protons and neutrons of the material forming semiconductor layer structure 150. This causes preliminary trench shield region 272 and trench support shield 274 to "bloom," in the sense that the width of these regions 272 increases with increasing depth from the top surface of semiconductor layer structure 150. Note that in the example of FIG. 5B , mask 262 is used as an etch mask to form both preliminary trench shield region 172 and trench support shield 274. It will be appreciated that in other embodiments, separate masks and ion implantation steps may be used to form preliminary trench shield region 172 and trench support shield 274. In such embodiments, preliminary trench shield region 172 may be formed, for example, using a high-energy "deep" ion implantation process (and thus have the shape shown in FIG. 5B ), while trench support shield 274 may be formed using shallow and deep ion implantation processes. This allows the trench support shield 274 to extend further toward the top surface of the semiconductor layer structure 150 such that the trench support shield 274 physically and electrically connects to the p-well layer 130 .

[0119] Referring to FIG. 5C , additional mask material may be formed to fill opening 266 in the mask structure while leaving opening 264. For example, selective oxide deposition may be performed to fill opening 266. Next, a plurality of gate trenches 180 are etched into the top surface of semiconductor layer structure 150. Gate trenches 180 are formed using mask 262 as an etch mask. Each gate trench 180 extends to the top surface of n-type drift region 120. While FIG. 5C shows only one complete gate trench 180 and a portion of a second gate trench 180, it will be understood that multiple gate trenches 180 are typically provided, as described above with reference to MOSFET 100. The gate trenches 180 convert the moderately doped p-type silicon carbide well layer 130 into a plurality of moderately doped p-wells 132 and the heavily doped n-type silicon carbide source layer 140 into a plurality of heavily doped n-type source regions 142. The portion of each p-well 132 adjacent to the gate trench 180 functions as a transistor channel 134. While FIG. 5C illustrates a device having a plurality of gate trenches 180 all extending parallel to one another in a first direction, as described above with reference to MOSFET 100, embodiments of the invention are not limited in this respect.

[0120] The etching step performed to form the gate trenches 180 may remove the upper portion of each preliminary trench shield region 272, thereby forming multiple trench shield regions 270 beneath each gate trench 180.

[0121] Referring to Figure 5D, the mask 262 and optional spacers 265 may be removed. A sacrificial oxidation process and / or hydrogen etching may then be performed. These processes may be identical to those described above with reference to Figures 2J-2K and will not be further described here. An annealing process may then be performed to activate the p-type dopants in the trench shield region 270.

[0122] As shown in Figure 5E, gate oxide layer 182, gate electrode 184, intermetal dielectric layer 186, source contact 190, and drain contact 192 are formed in the manner described above with reference to Figure 2L to form MOSFET 200. MOSFET 200 may also include p-well extensions 136 that physically and electrically connect p-well 132 to source contact 190. These p-well extensions 136 are shown in plan view in Figure 5F. Additionally, trench shield connection regions (not shown) that electrically connect p-well 132 to trench shield region 170 may be provided in either the active and / or inactive regions of MOSFET 200.

[0123] 5F is a horizontal cross-section of the device shown in FIG. 5E taken along line 5F-5F (i.e., the cross-section is taken along the top surface of semiconductor layer structure 150). FIG. 5F shows how p-well extension 136 forms a series of islands that extend upward through source region 142 to the top surface of semiconductor layer structure 150. P-well extension 136 is formed by a heavily doped (p + ) p-type region. P-well extension 136 electrically connects p-well 132 to source contact 190.

[0124] The top surfaces of the preliminary trench shield regions 272 of MOSFET 200 are formed at a depth from the top surface of semiconductor layer structure 150 that is shallower than the depth of gate trench 180. As a result, the etching step performed to create gate trench 180 (see FIG. 5C ) removes the upper portion of each preliminary trench shield region 272 to form trench shield region 270. However, it will be appreciated that further embodiments of the present invention may provide MOSFETs in which preliminary trench shield region 272 is formed such that its top surface is at a depth within semiconductor layer structure 150 that is below the depth of the bottom of gate trench 180. In such MOSFETs, the formation of the gate trench does not alter the preliminary trench shield region 272, and therefore trench shield region 270 may be identical to preliminary trench shield region 272. FIG. 6 is a schematic cross-sectional view of a MOSFET 300 having such a configuration.

[0125] As can be seen, MOSFET 300 of FIG. 6 is very similar to MOSFET 200 of FIG. 5E , except that trench shield regions 270 and trench support shields 274 are formed deeper within semiconductor layer structure 150. This modification results in a portion of lightly doped n-type drift region 120 being interposed between each trench shield region 270 and its associated gate trench 180. This design may further help protect gate oxide layer 182 lining the bottom of each gate trench 180, as the trench shield regions extend deeper into semiconductor layer structure 150.

[0126] FIG. 7 is a flow chart illustrating a method according to an embodiment of the present invention for fabricating a gate trench semiconductor device, such as a power wide bandgap gate trench semiconductor device.

[0127] As shown in FIG. 7 , a first mask is formed on a semiconductor layer structure ("SLS") (operation 400). The first mask includes a first longitudinally extending opening having a first width. A second mask is formed by forming spacers on sidewalls of the first mask exposed by the first opening (operation 410). The first and second masks form a mask structure having a second longitudinally extending opening having a second width smaller than the first width. Dopants are implanted into the semiconductor layer structure through the second opening to form implanted regions in the semiconductor layer structure (operation 420). The spacers are then at least partially removed from the sidewalls of the first mask to form third openings in the mask structure (operation 430). The mask structure is then etched using an etch mask to form gate trenches in the semiconductor layer structure directly below the third openings (operation 440).

[0128] FIG. 8 is a flow chart illustrating a method according to an embodiment of the present invention for fabricating a gate trench semiconductor device, such as a power wide bandgap gate trench semiconductor device.

[0129] As shown in FIG. 8 , a first mask is formed on a semiconductor layer structure, the first mask including a first opening (operation 500). A second mask is formed by forming spacers on the sidewalls of the first mask exposed by the first opening, and the first and second masks constitute a mask structure having a second opening (operation 510). Dopants are implanted into the semiconductor layer structure through the second openings to form implanted regions in the semiconductor layer structure (operation 520). The spacers are at least partially removed from the sidewalls of the first mask (operation 530). The semiconductor layer structure is then etched to form gate trenches self-aligned with the implanted regions (operation 540).

[0130] In the above description, each exemplary embodiment has a particular conductivity type. It will be understood that in each of the above embodiments, a device of the opposite conductivity type can be formed by simply reversing the conductivity of the n-type and p-type layers. It will therefore be understood that the present invention covers both n-channel and p-channel devices for each of the different device structures (e.g., MOSFETs, IGBTs, etc.).

[0131] The present invention has been described above primarily with reference to silicon carbide-based power semiconductor devices. However, it will be understood that silicon carbide is used herein as an example and that the devices described herein may be formed in any suitable wide bandgap semiconductor material system. By way of example, a gallium nitride-based semiconductor material (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used in place of silicon carbide in any of the above-described embodiments.

[0132] Embodiments of the present invention are described above with reference to the accompanying drawings, in which embodiments of the invention are shown. It should be understood, however, that the invention may be embodied in many different forms and should not be construed as limited to the embodiments described above. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

[0133] As used herein, the term "plurality" means two or more. As used herein, "substantially" means within + / - 10%.

[0134] Although terms such as first, second, etc. are used throughout this specification to describe various elements, it will be understood that these elements are not to be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0135] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0136] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that the element is directly on or extending directly onto the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Also, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element may be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0137] Relative terms such as "below" or "above" or "upper" or "lower" or "top" or "bottom" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0138] Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations are to be expected as a result, for example, of manufacturing techniques and / or tolerances. Embodiments of the present invention are also described with reference to flowcharts. It will be understood that the steps depicted in the flowcharts do not necessarily have to be performed in the order shown.

[0139] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions, which are characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration in that layer and / or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated with a "+" or "-" (e.g., n+, n-, p+, p-, n++, n--, p++, p--) to indicate a relatively greater ("+") or lesser ("-") concentration of majority carriers compared to another layer or region. However, such designations do not imply the presence of a particular concentration of majority or minority carriers in the layer or region.

[0140] In the drawings and specification, there are disclosed exemplary embodiments of the invention, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being indicated in the following claims.

Claims

1. 1. A semiconductor device including a wide bandgap semiconductor layer structure, the wide bandgap semiconductor layer structure comprising: a drift region having a first conductivity type; a well region having a second conductivity type provided on the drift region; a source region having the first conductivity type on the well region; a gate electrode in the gate trench; a trench shield region having the second conductivity type directly below the gate trench; Equipped with A semiconductor device, wherein the width of the trench shield region exceeds the width of the gate trench.

2. 2. The semiconductor device of claim 1, wherein the trench shield region is formed beneath the gate trench and extends onto a lower portion of opposing sidewalls of the gate trench.

3. 2. The semiconductor device of claim 1, wherein the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, a left side of the trench shield region extending laterally beyond a lower edge of the left sidewall of the gate trench by at least 0.1 microns, and a right side of the trench shield region extending laterally beyond a lower edge of the right sidewall of the gate trench by at least 0.1 microns.

4. 4. The semiconductor device of claim 1, wherein the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, and the gate trench overlaps less than 95% of a lateral width of the trench shield region.

5. The semiconductor device according to claim 1 , wherein the corners of the bottom of the gate trench are rounded.

6. The semiconductor device of claim 1 , wherein the drift region, the well region, the source region, and the shield region comprise silicon carbide.

7. The semiconductor device of claim 1 , wherein the trench shield region extends continuously across the entire width of the gate trench.

8. 1. A semiconductor device including a wide bandgap semiconductor layer structure, the wide bandgap semiconductor layer structure comprising: a drift region having a first conductivity type; a well region having a second conductivity type provided on the drift region; a source region having the first conductivity type on the well region; a gate electrode in the gate trench; a trench shield region having the second conductivity type directly below the gate trench; Equipped with a portion of the drift region having the first conductivity type interposed between a bottom surface of the gate trench and the trench shield region;

9. 9. The semiconductor device of claim 8, wherein the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, a left side of the trench shield region extending laterally beyond a lower edge of the left sidewall of the gate trench by at least 0.1 microns, and the right side of the trench shield region extending laterally beyond a lower edge of the right sidewall of the gate trench by at least 0.1 microns.

10. 9. The semiconductor device of claim 8, wherein the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, and the gate trench overlaps less than 95% of a lateral width of the trench shield region.

11. 11. The semiconductor device according to claim 8, wherein the corners of the bottom of the gate trench are rounded.

12. 11. The semiconductor device of claim 8, wherein the trench shield region extends continuously across the entire width of the gate trench.

13. forming a first mask over the semiconductor layer structure, the first mask including a first longitudinally extending opening having a first width; forming spacers on sidewalls of the first mask exposed by the first opening to form a second mask, the first and second masks constituting a mask structure having a second longitudinally extending opening having a second width smaller than the first width; implanting a dopant into the semiconductor layer structure through the second opening to form an implanted region in the semiconductor layer structure; at least partially removing the spacers from the sidewalls of the first mask to form a third opening in the mask structure; etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure beneath the third opening; 1. A method for forming a semiconductor device, comprising:

14. The method of claim 13 , wherein the second mask comprises silicon.

15. The method of claim 14 , wherein the second mask further comprises oxygen.

16. The method of claim 13 , wherein the first mask comprises both silicon and nitrogen.

17. 17. The method of claim 13, wherein forming the spacers on sidewalls of the first mask exposed by the first opening to form the second mask comprises oxidizing the sidewalls of the first mask exposed by the first opening.

18. 14. The method of claim 13, wherein the implanted region is directly below the gate trench and the width of the implanted region is greater than the width of the gate trench.

19. 20. The method of claim 18, wherein the implanted regions extend onto the lower portions of opposing sidewalls of the gate trench.

20. 17. The method of claim 13, wherein the corners of the bottom of the gate trench are rounded.

21. 17. The method of claim 13, wherein the drift region, the well region, the source region, and the shield region each comprise silicon carbide.

22. 17. The method of claim 13, wherein the semiconductor layer structure comprises a drift region having a first conductivity type, a well region having a second conductivity type, and a source region having the first conductivity type, at least a portion of the well region being disposed between the drift region and the source region, and the implanted region having the second conductivity type.

23. 17. The method of any one of claims 13 to 16, wherein the implanted region is self-aligned with the gate trench.

24. 17. The method of claim 13, further comprising removing some but not all of the portion of the second mask that is in the second opening before implanting the dopant into the semiconductor layer structure.

25. 17. The method of any one of claims 13 to 16, further comprising etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure beneath the third opening, thereby exposing the implanted region.

26. 17. The method of claim 13, further comprising the steps of: etching the semiconductor layer structure using the mask structure as an etching mask to form a gate trench in the semiconductor layer structure directly below the third opening; and then performing an oxidation treatment on the semiconductor layer structure; and then removing the oxidized portion of the semiconductor layer structure.

27. 17. The method of claim 13, further comprising the step of etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure beneath the third opening, and then annealing the semiconductor layer structure in a hydrogen-containing environment.

28. 17. The method of claim 13, wherein at least partially removing the spacers from the sidewalls of the first mask to form the third opening in the mask structure comprises completely removing the spacers from the sidewalls of the first mask such that the third opening has the first width.

29. forming a first mask over the semiconductor layer structure, the first mask including a first opening; forming a spacer on a sidewall of the first mask exposed by the first opening to form a second mask, the first and second masks constituting a mask structure having a second opening; implanting a dopant into the semiconductor layer structure through the second opening to form an implanted region in the semiconductor layer structure; at least partially removing the spacers from the sidewalls of the first mask; etching the semiconductor layer structure to form a gate trench self-aligned with the implanted region; 1. A method for forming a semiconductor device, comprising:

30. 30. The method of claim 29, wherein the semiconductor layer structure is a wide bandgap semiconductor layer structure including a drift region having a first conductivity type, a well layer having a second conductivity type, and a source region having the first conductivity type on the well layer, and the dopant implanted into the semiconductor layer structure through the second opening is a dopant of the second conductivity type.

31. 31. The method of claim 30, wherein at least partially removing the spacers from the sidewalls of the first mask comprises completely removing the spacers from the sidewalls of the first mask such that the semiconductor layer structure is etched using only the first mask as an etch mask.

32. 31. The method of claim 30, wherein the implanted region is a trench shield region having the second conductivity type.

33. 30. The method of claim 29, wherein the second opening exposes the semiconductor layer structure.

34. 30. The method of claim 29, wherein the spacer covers the semiconductor layer structure exposed by the first opening such that the second opening does not expose the semiconductor layer structure.

35. after etching the semiconductor layer structure to form the gate trench; removing the first mask; oxidizing exposed portions of the semiconductor layer structure; removing the oxidized portion of the semiconductor layer structure; 30. The method of claim 29, further comprising:

36. after etching the semiconductor layer structure to form the gate trench; rounding the bottom corners of the gate trench; activating the implanted second conductivity dopant; 30. The method of claim 29, further comprising:

37. 30. The method of claim 29, wherein the second mask comprises silicon.

38. 38. The method of claim 37, wherein the second mask further comprises oxygen.

39. 39. The method of claim 38, wherein the first mask comprises both silicon and nitrogen.

40. 40. The method of any one of claims 29 to 39, wherein forming the spacers on sidewalls of the first mask exposed by the first opening to form the second mask comprises oxidizing the sidewalls of the first mask.

41. 40. The method of any one of claims 29 to 39, wherein the implanted region is directly below the gate trench and the width of the implanted region is greater than the width of the gate trench.

42. 42. The method of claim 41, wherein the implanted regions extend onto the lower portions of opposing sidewalls of the gate trench.

43. providing a semiconductor layer structure including a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, and a source region having the first conductivity type on the well region; forming a first mask over the semiconductor layer structure, the first mask including a first opening; implanting dopants of a second conductivity type into the semiconductor layer structure through at least a portion of the semiconductor layer structure exposed by the first opening to form an implanted region having the second conductivity type in the drift region; 1. A method of forming a semiconductor device, comprising: the portion of the source region exposed through the first opening still having the first conductivity type after the dopants of the second conductivity type are implanted into the semiconductor layer structure.

44. 44. The method of claim 43, wherein after the dopants of the second conductivity type are implanted into the semiconductor layer structure, a portion of the drift region between the well region and the implanted region still has the first conductivity type.

45. the first opening is a longitudinally extending first opening having a first width, the method further comprising forming a second mask by forming spacers on sidewalls of the first mask exposed by the first opening, the first and second masks constituting a mask structure having a longitudinally extending second opening having a second width smaller than the first width; 45. The method of claim 44, wherein implanting dopants of a second conductivity type into the semiconductor layer structure through at least the portion of the semiconductor layer structure exposed by the first opening to form an implanted region having the second conductivity type in the drift region comprises implanting dopants of the second conductivity type into the semiconductor layer structure through the second opening.

46. at least partially removing the spacers from the sidewalls of the first mask to form a third opening in the mask structure; etching the semiconductor layer structure using the mask structure as an etch mask to form a gate trench in the semiconductor layer structure beneath the third opening; 46. ​​The method of claim 45, further comprising:

47. 46. ​​The method of claim 45, wherein the first mask comprises a material that includes both silicon and nitrogen, and the second mask comprises silicon.

48. 48. The method of claim 47, wherein the second mask further comprises oxygen.

49. 47. The method of claim 46, wherein the implanted region is directly below the gate trench, and the width of the implanted region is greater than the width of the gate trench.

50. 50. The method of claim 49, wherein the implanted regions extend onto the lower portions of opposing sidewalls of the gate trench.

51. 2. The semiconductor device of claim 1, wherein the trench shield region defines the bottom of the gate trench.

52. 2. The semiconductor device of claim 1, wherein the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, a left side of the trench shield region extending laterally beyond a lower edge of the left sidewall of the gate trench by at least 0.3 microns, and a right side of the trench shield region extending laterally beyond a lower edge of the right sidewall of the gate trench by at least 0.3 microns.

53. 9. The semiconductor device of claim 8, wherein the gate trench has left and right sidewalls extending parallel to a longitudinal axis of the gate trench, the left and right sidewalls being laterally spaced apart from one another, a left side of the trench shield region extending laterally beyond a lower edge of the left sidewall of the gate trench by at least 0.3 microns, and the right side of the trench shield region extending laterally beyond a lower edge of the right sidewall of the gate trench by at least 0.3 microns.

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