Power semiconductor device having a non-rectangular semiconductor die for improved mechanical robustness and reduced stress and electric field concentration

Abstract

The semiconductor device includes a semiconductor die including a substrate having a hexagonal crystal structure, wherein first and second sides of the semiconductor die extend along respective first and second crystal axes of the hexagonal crystal structure of the substrate.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 18 / 107,537, filed February 9, 2023, which is incorporated herein by reference in its entirety.

[0002] The present invention relates to semiconductor devices, and more particularly to power semiconductor devices having a semiconductor die with a non-rectangular shape. [Background technology]

[0003] Semiconductor devices are often used in applications where they must pass large current levels in their "on" state and block large voltages in their reverse blocking or "off" state. For example, there is a demand for metal oxide semiconductor field effect transistors (MOSFETs) that can pass tens or hundreds of amperes of current in their "on" state and block hundreds or thousands of volts in their reverse blocking state. To handle large current densities and block such high voltages, power MOSFETs, as well as other power semiconductor devices such as power junction barrier Schottky (JBS) diodes, insulated gate bipolar junction transistors (IGBTs), junction field effect transistors (JFETs), and gate-controlled thyristors, typically have a vertical structure with at least one contact on each of two opposing sides of a thick semiconductor layer structure. As used herein, the term "semiconductor layer structure" refers to a structure that includes one or more semiconductor layers, such as a semiconductor substrate and / or a semiconductor epitaxial layer.

[0004] The semiconductor layer structure of a power semiconductor device typically includes an "active region" having one or more functional semiconductor devices with junctions, such as pn junctions. The active region functions as a primary junction for blocking voltage during reverse bias operation and conducting current during forward bias operation. Power semiconductor devices may also have edge termination structures in the termination region of the semiconductor layers, such as a series of guard rings or junction termination extensions (JTEs). Edge termination structures can be designed to reduce the buildup of electric field concentrations that would otherwise naturally occur along the edges of the semiconductor die during device operation. When the semiconductor die is viewed in plan view, the termination region can surround the active region. As used herein, a "plan view" of a semiconductor die refers to a view of the semiconductor die taken along an axis perpendicular to the center of the major surface of the semiconductor layer structure of the semiconductor die. A plan view is typically a view of the top surface of the semiconductor die.

[0005] Multiple power semiconductor devices are typically formed on a wafer. A wafer refers to a relatively large substrate typically formed from a semiconductor material such as 4H silicon carbide. Multiple semiconductor epitaxial layers are grown or otherwise formed on the wafer to form a semiconductor layer structure. Each power semiconductor device grown on the wafer typically has an active area and its own edge termination. After the semiconductor layer structure is formed and additional processing steps (e.g., deposition of metal layers) are completed, the resulting structure can be diced to separate the individual edge termination power semiconductor dies. Each power semiconductor die can have a unit cell structure in which the active area of ​​each power semiconductor die includes multiple individual "unit cell" devices electrically connected in parallel. The power semiconductor die can then be packaged to provide multiple power semiconductor devices.

[0006] For very high power applications, power semiconductor devices are typically formed in wide-bandgap semiconductor material systems, such as silicon carbide (as used herein, the term "wide-bandgap semiconductor" encompasses any semiconductor with a bandgap of at least 1.4 eV), which have several advantageous properties, including high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity. Compared to devices formed in other semiconductor materials, such as silicon, electronic devices formed in silicon carbide can have the ability to operate at higher temperatures, greater power densities, higher speeds, higher power levels, and / or higher radiation densities.

[0007] Silicon carbide-based power devices offer several performance advantages, including high voltage blocking, low on-resistance, high current carrying capability, fast switching speeds, low switching losses, and the ability to withstand high junction temperatures. These properties result in significant increases in potential power density, which is the power handled per area or volume. Summary of the Invention

[0008] According to some embodiments of the present invention, a semiconductor device is provided, comprising a semiconductor die comprising a substrate having a hexagonal crystal structure, wherein first and second sides of the semiconductor die extend along respective first and second crystal axes of the hexagonal crystal structure of the substrate.

[0009] In some embodiments, the first side and the second side meet to define an interior angle that is obtuse.

[0010] In some embodiments, the semiconductor die has at least five sides when viewed in a plan view. In some embodiments, the semiconductor die has a hexagonal shape when viewed in a plan view. In some embodiments, the semiconductor die has a polygonal shape when viewed in a plan view that is not a regular polygon. In some embodiments, the semiconductor die has a hexagonal shape with chamfered corners when viewed in a plan view.

[0011] In some embodiments, a semiconductor die comprises a MOSFET having an active area comprising a plurality of unit cell transistors.

[0012] In some embodiments, the gate runner of the MOSFET comprises a first segment and a second segment that connect at an obtuse angle. In some embodiments, the first and second segments of the gate runner each extend along a periphery of the active area. In some embodiments, the gate pad of the MOSFET is centrally located in the active area, and the gate runner comprises multiple additional segments extending outward from the gate pad.

[0013] In some embodiments, the gate runner of the MOSFET comprises a first segment and a second segment that connect at an angle between 115° and 125°.

[0014] In some embodiments, the semiconductor die has a polygonal shape when viewed in a plan view, with corners of the polygonal shape defining interior angles greater than 90°.

[0015] In some embodiments, the substrate comprises a silicon carbide substrate or a gallium nitride substrate.

[0016] According to a further embodiment of the present invention, there is provided a semiconductor device comprising a semiconductor die having at least five sides when viewed in plan view.

[0017] In some embodiments, the semiconductor die comprises a semiconductor layer having a hexagonal crystal structure.

[0018] In some embodiments, the semiconductor die has a hexagonal shape when viewed in plan view.

[0019] In some embodiments, the semiconductor die has a hexagonal shape when viewed in plan view that is not a regular hexagon.

[0020] In some embodiments, the semiconductor die has a hexagonal shape with chamfered corners when viewed in plan view.

[0021] In some embodiments, at least three of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

[0022] In some embodiments, all of the sides of the semiconductor die extend along the crystal axes of the hexagonal crystal structure of the semiconductor layer.

[0023] In some embodiments, the semiconductor die includes a MOSFET having an active area including a plurality of unit cell transistors, and the gate runner of the MOSFET includes a first segment and a second segment that connect at an obtuse angle. In some embodiments, the obtuse angle is an angle of 120°. In some embodiments, the first and second segments of the gate runner each extend along a periphery of the active area. In some embodiments, the gate pad of the MOSFET is centrally disposed in the active area, and the gate runner includes a plurality of additional segments that extend radially outward from the gate pad.

[0024] In some embodiments, the semiconductor die has a polygonal shape when viewed in a plan view, with corners of the polygonal shape defining interior angles greater than 90°.

[0025] In some embodiments, the semiconductor layer comprises a silicon carbide substrate or a gallium nitride substrate.

[0026] According to an additional embodiment of the present invention, there is provided a semiconductor device comprising a semiconductor die having a polygonal shape when viewed in plan view with corners defining interior angles greater than 90°.

[0027] In some embodiments, the semiconductor die comprises a semiconductor layer having a hexagonal crystal structure.

[0028] In some embodiments, the polygonal shape is a hexagon. In some embodiments, the polygonal shape is a hexagonal shape that is not a regular hexagon.

[0029] In some embodiments, at least two sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer, hi some embodiments, all sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

[0030] In some embodiments, the semiconductor die includes a MOSFET having an active area including a plurality of unit cell transistors, and the gate runner of the MOSFET includes a first segment and a second segment that connect at an obtuse angle. In some embodiments, the obtuse angle is an angle of 120°. In some embodiments, the first and second segments of the gate runner each extend along a periphery of the active area. In some embodiments, the gate pad of the MOSFET is centrally disposed in the active area, and the gate runner includes a plurality of additional segments that extend radially outward from the gate pad.

[0031] In some embodiments, the semiconductor layer comprises a silicon carbide substrate or a gallium nitride substrate.

[0032] According to a further embodiment of the present invention, there is provided a semiconductor device comprising a semiconductor die having a polygonal shape with chamfered corners when viewed in plan.

[0033] In some embodiments, the semiconductor die comprises a semiconductor layer having a hexagonal crystal structure.

[0034] In some embodiments, the polygonal shape has six major sides and the chamfered corners include six chamfered corners.

[0035] In some embodiments, at least two of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the substrate, and in some embodiments, all of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

[0036] In some embodiments, the semiconductor die includes a MOSFET having an active area including a plurality of unit cell transistors, and the gate runner of the MOSFET includes a first segment and a second segment that connect at an obtuse angle. In some embodiments, the obtuse angle is an angle of 120°. In some embodiments, the first and second segments of the gate runner each extend along a periphery of the active area. In some embodiments, the gate pad of the MOSFET is centrally disposed in the active area, and the gate runner includes a plurality of additional segments that extend radially outward from the gate pad.

[0037] According to a further embodiment of the present invention, there is provided a semiconductor device comprising a semiconductor die comprising a semiconductor layer structure comprising an active region and a gate runner of the semiconductor layer structure comprising a first segment and a second segment that connect at an obtuse angle.

[0038] In some embodiments, the obtuse angle is a 120° angle.

[0039] In some embodiments, the first and second segments of the gate runner each extend along the periphery of the active area.

[0040] In some embodiments, the gate runner further comprises third and fourth segments, the first through fourth segments defining respective first through fourth sides of a hexagon when viewed in plan.

[0041] In some embodiments, the gate pad of the MOSFET is centrally located in the active area, and the gate runner comprises a plurality of additional segments extending radially outward from the gate pad, hi some embodiments, the plurality of additional segments are radially spaced apart by 60° from one another.

[0042] In some embodiments, the semiconductor die is a hexagonal shaped semiconductor die.

[0043] According to a further embodiment of the present invention, there is provided a semiconductor device comprising a semiconductor die comprising a semiconductor layer structure comprising an active region and a gate runner of the semiconductor layer structure comprising first, second, and third segments extending along respective first, second, and third crystal axes of a semiconductor substrate of the semiconductor layer structure.

[0044] In some embodiments, the first, second, and third segments of the gate runner each extend along the perimeter of the active area.

[0045] In some embodiments, the gate runner further comprises a fourth segment, the first through fourth segments defining respective first through fourth sides of a hexagon when viewed in plan.

[0046] In some embodiments, the semiconductor die is a hexagonal shaped semiconductor die.

[0047] According to a further embodiment of the present invention, a semiconductor device is provided comprising a semiconductor die comprising a semiconductor layer structure having an active region, a gate pad in the semiconductor layer structure, and a plurality of gate runner segments extending radially from the gate pad to corners of the semiconductor die.

[0048] In some embodiments, the gate pad is located in the center of the active area.

[0049] In some embodiments, the semiconductor device further comprises an additional plurality of gate runner segments extending along the periphery of the active area.

[0050] In some embodiments, the semiconductor die is a hexagonal shaped semiconductor die.

[0051] In some embodiments, the gate pad is located in the center of the active area.

[0052] In some embodiments, the semiconductor layer structure comprises a 4H silicon carbide substrate. [Brief explanation of the drawings]

[0053] [Figure 1A] 1 is a schematic plan (top) view of a conventional semiconductor die attached to a submount. [Figure 1B] FIG. 1 is a perspective view of a conventional semiconductor die mounted on a submount. [Figure 2] FIG. 2 is a schematic side view of the structure shown in FIGS. 1A-1B. [Figure 3] FIG. 1 is a diagram of a series of regular polygons with different numbers of sides. [Figure 4] 1 is a schematic plan view of a conventional silicon carbide semiconductor wafer showing the longitudinal and lateral "cut lines" along which the wafer is cut with a saw to singulate the wafer into individual semiconductor dies; [Figure 5] 1 is a schematic plan view of a silicon carbide semiconductor wafer configured to be diced into hexagonal-shaped semiconductor dies according to an embodiment of the present invention; [Figure 6] 1 is a collage of plan views of square, hexagonal, and circular semiconductor dies showing the relative stress levels across each die when the dies are bonded to an underlying submount and heated. [Figure 7] 1 is a collage of plan views of square semiconductor dies with sharp, rounded, and chamfered corners, illustrating the relative stress levels across each die when the dies are bonded to an underlying submount and heated. [Figure 8] 1 is a collage of plan views of hexagonal semiconductor dies with sharp and rounded corners, illustrating the relative heat-generated stress levels across each die when the dies are bonded to an underlying submount and heated. [Figure 9] 1 is an example of a stress concentration factor design chart illustrating how the degree of rounding of the corners of a semiconductor die affects the maximum stress concentration level of the semiconductor die. [Figure 10]1 is a plan view illustrating how a semiconductor die having a regular hexagonal shape can be replaced with a semiconductor die having two long sides to increase the semiconductor die area. FIG. [Figure 11A] 1 is a schematic plan view of a silicon carbide based power diode semiconductor die according to an embodiment of the present invention; [Figure 11B] 1 is a schematic perspective view of a silicon carbide based power diode semiconductor die according to an embodiment of the present invention; [Figure 12A] FIG. 2 is a schematic plan view of a silicon carbide based power MOSFET semiconductor die according to a further embodiment of the present invention. [Figure 12B] FIG. 2 is a schematic perspective view of a silicon carbide based power MOSFET semiconductor die according to a further embodiment of the present invention. [Figure 12C] FIG. 1C is a schematic side view of a portion of the semiconductor die of FIGS. 12A-12B. [Figure 13A] 1A-1C are schematic plan views of a three-terminal hexagonal-shaped power semiconductor die (e.g., a power MOSFET) according to an embodiment of the present invention, with gate pads located at various positions. [Figure 13B] 1A-1C are schematic plan views of a three-terminal hexagonal-shaped power semiconductor die (e.g., a power MOSFET) according to an embodiment of the present invention, with gate pads located at various positions. [Figure 13C] 1A-1C are schematic plan views of a three-terminal hexagonal-shaped power semiconductor die (e.g., a power MOSFET) according to an embodiment of the present invention, with gate pads located at various positions. [Figure 13D] 1A-1C are schematic plan views of a three-terminal hexagonal-shaped power semiconductor die (e.g., a power MOSFET) according to an embodiment of the present invention, with gate pads located at various positions. [Figure 13E] 1A-1C are schematic plan views of a three-terminal hexagonal-shaped power semiconductor die (e.g., a power MOSFET) according to an embodiment of the present invention, with gate pads located at various positions. [Figure 13F]1A-1C are schematic plan views of a three-terminal hexagonal-shaped power semiconductor die (e.g., a power MOSFET) according to an embodiment of the present invention, with gate pads located at various positions. [Figure 14A] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die having a circular gate pad or a gate pad including at least a semicircular portion according to an embodiment of the present invention. FIG. [Figure 14B] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die having a circular gate pad or a gate pad including at least a semicircular portion according to an embodiment of the present invention. FIG. [Figure 14C] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die having a circular gate pad or a gate pad including at least a semicircular portion according to an embodiment of the present invention. FIG. [Figure 14D] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die having a circular gate pad or a gate pad including at least a semicircular portion according to an embodiment of the present invention. FIG. [Figure 15A] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die according to an embodiment of the present invention having a rectangular gate pad or a non-regular pentagonal gate pad. [Figure 15B] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die according to an embodiment of the present invention having a rectangular gate pad or a non-regular pentagonal gate pad. [Figure 15C] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die according to an embodiment of the present invention having a rectangular gate pad or a non-regular pentagonal gate pad. [Figure 15D] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die according to an embodiment of the present invention having a rectangular gate pad or a non-regular pentagonal gate pad. [Figure 16A] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die according to an embodiment of the present invention, having a rectangular or pentagonal-shaped gate pad in which at least some of the corners of the gate pad are rounded, and which is not a regular pentagon. [Figure 16B] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die according to an embodiment of the present invention, having a rectangular or pentagonal-shaped gate pad in which at least some of the corners of the gate pad are rounded, and which is not a regular pentagon. [Figure 16C] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die according to an embodiment of the present invention, having a rectangular or pentagonal-shaped gate pad in which at least some of the corners of the gate pad are rounded, and which is not a regular pentagon. [Figure 16D] 1 is a schematic plan view of a three-terminal hexagonal-shaped power semiconductor die according to an embodiment of the present invention, having a rectangular or pentagonal-shaped gate pad in which at least some of the corners of the gate pad are rounded, and which is not a regular pentagon. [Figure 17A] 1 is a schematic plan view of a hexagonal-shaped power MOSFET according to an embodiment of the present invention, showing exemplary locations of gate runners. [Figure 17B] 1 is a schematic plan view of a hexagonal-shaped power MOSFET according to an embodiment of the present invention, showing exemplary locations of gate runners. [Figure 17C] 1 is a schematic plan view of a hexagonal-shaped power MOSFET according to an embodiment of the present invention, showing exemplary locations of gate runners. [Figure 18A] 1 is a schematic plan view of a hexagonal-shaped power MOSFET according to an embodiment of the present invention, showing additional exemplary locations of gate runners. [Figure 18B] 1 is a schematic plan view of a hexagonal-shaped power MOSFET according to an embodiment of the present invention, showing additional exemplary locations of gate runners. [Figure 18C] 1 is a schematic plan view of a hexagonal-shaped power MOSFET according to an embodiment of the present invention, showing an example location of an additional gate runner. [Figure 19A] 10 is a schematic plan view of a hexagonal-shaped power MOSFET according to an embodiment of the present invention, showing further exemplary locations of gate runners. [Figure 19B] 10 is a schematic plan view of a hexagonal-shaped power MOSFET according to an embodiment of the present invention, showing further exemplary locations of gate runners. [Figure 19C] 10 is a schematic plan view of a hexagonal-shaped power MOSFET according to an embodiment of the present invention, showing further exemplary locations of gate runners. [Figure 20A] FIG. 1 is a diagram of an exemplary semiconductor die having additional top contact pads. [Figure 20B] FIG. 1 is a diagram of an exemplary semiconductor die having additional top contact pads. [Figure 20C] FIG. 1 is a diagram of an exemplary semiconductor die having additional top contact pads. [Figure 20D] FIG. 1 is a diagram of an exemplary semiconductor die having additional top contact pads. DETAILED DESCRIPTION OF THE INVENTION

[0054] Power semiconductor devices typically have parasitic resistance, capacitance, and / or inductance, which may be within the semiconductor die itself, the electrical leads connecting the semiconductor die to external components, and / or the device's protective packaging. These parasitic resistances, capacitances, and inductances act to store and / or dissipate electrical and thermal energy. These imperfections manifest as wasted energy during device operation. For example, processing power generates wasted heat due to conduction and switching losses. Removing this wasted heat results in temperature rise due to thermal resistance and capacitance.

[0055] As power semiconductor devices operate over their useful life, they typically experience temperature increases and decreases over and over again. Furthermore, many power semiconductor devices, such as those used in electric vehicles and power generation substations, are exposed to extreme environments, including cold weather conditions, high ambient temperatures (e.g., under the hood of a vehicle), and high humidity. As the temperature of a semiconductor device increases and decreases, the materials of the semiconductor die and protective packaging expand and contract. The degree to which the various materials of the die and packaging expand and contract is governed by their respective coefficients of thermal expansion (CTE), which can vary considerably for different materials. When two different materials are joined together, tensile and compressive stresses are generated within each material and at the interface between the materials as one material attempts to expand or contract more than the other.

[0056] The stresses and strains generated by the thermal cycling described above, when repeated multiple times, can fatigue the semiconductor die and / or package structure. In particular, these stresses can damage the device, resulting in reduced functionality, even catastrophic failure, if cracks occur. The stresses and strains can also significantly reduce the effectiveness of the connection, or attachment, of the semiconductor die to the package. For example, the semiconductor die in a packaged semiconductor device is often attached to a heat spreader, copper pad, lead frame, or insulating power substrate, depending on the type of package used and the application. Such heat spreaders, pads, etc., may be attached to one or both sides of the semiconductor die and are attached to the die by a die attach material. These die attach layers can be important because they can function as all three electrical, thermal, and mechanical connections between the semiconductor die and the package. When a packaged semiconductor device undergoes thermal (heating and cooling) cycles, the stresses and strains generated in the die attach layer can crack, fracture, etc., ultimately resulting in degradation of the die attach layer that is critical to its electrical, thermal, and / or mechanical functions.

[0057] Thermal strains and stresses that can occur in packaged semiconductor devices can be the result of the structural geometry of the components that form the device, the method of attaching these components, the material composition of the assembly, and the difference between the extreme temperatures experienced during device operation and the temperature assumed to be in a stress-free state. Therefore, one way to reduce thermal contamination and stress is to select materials with similar thermal expansion coefficients. Unfortunately, this is often impractical, as materials perform many different functions, and trading off one performance characteristic for another is often not possible or practical. For example, softer die attach materials are often more resistant to fatigue, but they also exhibit significantly worse thermal conductivity. Therefore, the selection of a die attach material involves an inherent trade-off between reliability and performance, and the reliability gains offered by using a softer die attach material may not be worth the performance compromise.

[0058] As discussed above, semiconductor dies are typically formed using “wafer-level” operations that grow, form, and / or deposit semiconductor, insulating, and metal layers / structures on a semiconductor wafer. The semiconductor wafer is then cut, or “diced,” into individual semiconductor dies by a sawing operation that uses a diamond dicing blade to cut the wafer into columns and rows. As a result, most power semiconductor dies have a rectangular (typically square) shape with right-angled corners as a result of sawing the wafer along a straight line. Corners are where thermal expansion and the associated stresses and strains are greatest. Corners are also abrupt transitions that can act as failure initiation points. Furthermore, the sharper the corner, the greater the stresses and strains and the more likely the corner will act as a failure initiation point. Unfortunately, rectangular shapes present challenges from a stress perspective because they have relatively sharp corners and, therefore, sharp corners are potential failure points. In this specification, the “shape” of a semiconductor die refers to the shape of the die when viewed in a plan view. Thus, a rectangular shaped semiconductor die is one that appears rectangular when viewed from above.

[0059] 1A and 1B are schematic plan (top) and perspective views, respectively, of a conventional semiconductor die 10 attached to a submount 12, such as a metal pad. The semiconductor die 10 may be soldered, sintered, or epoxy-bonded to the underlying submount 12 via a die attach material 14. When subjected to sufficient thermal cycling, cracks in the semiconductor die 10 or die attach material 14 often initiate at one of the corners of the semiconductor die 10 or die attach material 14 because stresses and strains are typically greatest in these corner areas. The crack can then propagate through the bulk of the semiconductor die 10 or die attach material 14 in response to further thermal cycling.

[0060] FIG. 2 is a side view of semiconductor die 10 attached to submount 12, as depicted in FIGS. 1A-1B. In response to thermal cycling or other physical stresses, cracks can initiate at the transition between different materials, such as the interface between semiconductor die 10 and die attach material 14, or the interface between die attach material 14 and submount 12, as shown in FIG. 2. Die attach material 14 is a thin layer that requires the die attach material 14 to be a material with good electrical, thermal, and mechanical properties to be able to serve as the interface between semiconductor die 10 and submount 12. As discussed above and shown in FIG. 2, cracks often form at the corners of semiconductor die 10 or die attach material 14 because thermally induced stresses are highest in these corner areas.

[0061] The "mechanical robustness" of a device refers to the ability of the device to withstand stresses and strains, such as those caused by thermal cycling or other physical forces. There are several potential ways to improve the mechanical robustness of a packaged semiconductor device, including reducing the mismatch in the thermal expansion coefficients between the materials forming the device, reducing abrupt changes in the geometry (such as sharp corners) of the elements forming the semiconductor device, introducing notches or grooves to relieve stress concentrations, and / or using materials that are more resistant to stress-related failure modes.

[0062] In accordance with embodiments of the present invention, semiconductor devices are provided that can exhibit high mechanical robustness and / or reduced electric field concentration at the device edges. In some embodiments, the semiconductor device can include a semiconductor die having a non-rectangular shape, such as a polygonal shape with more than four sides. Such semiconductor die can have corners that form interior angles greater than 90° and are therefore less "sharp" than the corners of a rectangular semiconductor die with 90° interior angles. Such "softer" corners may exhibit less stress buildup in response to thermal cycling or physical forces and thus may be less susceptible to crack formation, delamination, and / or device failure. In other embodiments, the semiconductor die can have rounded or chamfered corners, which exhibit the same advantage of reduced stress buildup. In each of the above embodiments, the shape selected for the semiconductor die preferably has good packing density to utilize the wafer as efficiently as possible. It should be noted that electric field concentration effects can result in high electric field concentrations in the corner regions of the semiconductor die, and the amount of electric field buildup generally increases with sharper die corners. Therefore, providing a semiconductor die with "softer" corners can reduce electric field concentration effects in the edge regions of the semiconductor die. This can improve the robustness of the semiconductor device or it can reduce the size of the termination region, thereby increasing the active die area.

[0063] In yet another embodiment of the present invention, semiconductor dies are provided that are diced along the crystallographic axis of the substrate of the semiconductor layer structure. Pieces cut along the crystallographic axis of the substrate can be "cleaner" than pieces cut off-axis. A less "clean" off-axis cut can create disturbances in the lattice structure of the semiconductor material, which can act as initiation points for cracks, delamination, performance degradation, and / or device failure. Thus, dicing a semiconductor wafer into semiconductor dies that have shapes that match the crystallographic structure of the wafer's substrate results in more robust semiconductor dies that are more tolerant to stress and therefore less susceptible to damage in response to thermal cycling.

[0064] According to further embodiments of the present invention, a semiconductor device is provided having a semiconductor die with a gate runner and / or gate pad designed / positioned to improve device performance. For example, in some embodiments, a semiconductor die is provided having a gate runner with segments that connect to each other at angles greater than 90°, such as an angle of 120°. For example, a semiconductor die is provided having a gate runner that includes at least first, second, third, and fourth segments that form first, second, third, and fourth sides of a hexagon, respectively. In other words, the gate runner forms at least four sides of the hexagonal shape and can include additional segments such that the gate runner has a hexagonal shape or a nearly perfect hexagonal shape (e.g., a hexagonal shape with one or more narrow gaps). Such a gate runner can extend around at least four sides of the hexagonal-shaped semiconductor die. As another example, a semiconductor die is provided having a gate runner that extends radially outward from a gate pad located at the center of the hexagonal-shaped semiconductor die. Such a gate runner can further include additional segments that extend at least partially around the periphery of the die. This gate runner design allows for a relatively short path for the gate signal to each unit cell transistor.

[0065] Semiconductor dies according to embodiments of the present invention having novel shapes / characteristics can be formed using less traditional dicing techniques, such as plasma dicing, laser ablation, stealth dicing, or thermal laser separation. Plasma dicing, also known as deep reactive ion etching, refers to a dry etching process that uses a plasma gas, such as sulfur hexafluoride, to etch narrow cuts into a wafer. Stealth dicing refers to an internal absorption laser dicing process in which a laser beam is passed along a cutting line, with its focal point below the surface of the wafer. The dies are then separated using a tape expander. These less traditional dicing techniques allow semiconductor wafers to be cut along more than two axes and / or to be cut to provide semiconductor dies with rounded corners.

[0066] Thus, according to various embodiments of the present invention, a semiconductor device is provided that includes a semiconductor die that includes a substrate having a hexagonal crystal structure. In some embodiments, first and second sides of the semiconductor die extend along respective first and second crystal axes of the hexagonal crystal structure of the substrate. In other embodiments, the semiconductor die can have at least five sides when viewed in a plan view. In still other embodiments, the semiconductor die can have a polygonal shape when viewed in a plan view with corners that define internal angles greater than 90°. In yet additional embodiments, the semiconductor die can have a polygonal shape when viewed in a plan view with chamfered corners.

[0067] In any or all of the above embodiments, the first and second sides can intersect to define an obtuse interior angle. The semiconductor die may have, for example, a regular hexagonal or non-regular hexagonal shape when viewed in a plan view, and may or may not have chamfered or rounded corners. The semiconductor die may include, for example, a MOSFET having an active area including a plurality of unit cell transistors. In some embodiments, the MOSFET may include a gate runner having first and second segments that connect at an angle greater than 90°, such as an angle of 120°. The first and second segments of the gate runner may, for example, each extend along the perimeter of the active area. These MOSFETs may alternatively or additionally include a gate pad centrally disposed in the active area. In such embodiments, the gate runner may further include multiple additional segments extending outward from the gate pad. The semiconductor die may include, for example, a 4H silicon carbide substrate.

[0068] In yet another embodiment of the present invention, a semiconductor device is provided, including a semiconductor die including a semiconductor layer structure having an active region. A gate runner is provided in the semiconductor layer structure. The gate runner may, for example, include a first segment and a second segment that connect at a 120° angle, and / or may include first, second, and third segments that extend along first, second, and third crystal axes of the semiconductor substrate, respectively. In some embodiments, the semiconductor die may further include a gate pad in the semiconductor layer structure. In such embodiments, multiple gate runner segments may extend radially from the gate pad to corners of the semiconductor die.

[0069]

[0023] Next, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. It will be understood that the features of the different embodiments disclosed herein can be combined in any manner to provide many additional embodiments. Thus, although various features of the present invention will be described below with reference to specific examples, it will be understood that these features can be added to other embodiments and / or used in place of exemplary features of other embodiments to provide many additional embodiments. Thus, the present invention should be understood to encompass these various combinations.

[0070] Thermally and / or physically induced stresses in a semiconductor die accumulate more at the corners of the die than at the center of the die. Generally speaking, stress-induced defects in a device or material are most likely to occur in areas where stress is highest, and therefore, the corners of a semiconductor die are areas of the semiconductor die most susceptible to stress-induced failures. The sharper the interior corner angle, the more stress accumulates. Therefore, one way to reduce the magnitude of thermally and / or physically induced stress is to increase the size of the interior corner angle. As shown in FIG. 3, the more sides added to a regular polygon-shaped device (a regular polygon refers to a shape formed from straight line segments all having the same length joined to form a closed shape), the larger the interior corner angle. For example, as shown in FIG. 3, an equilateral triangle has corners that define 60° interior angles, a rectangle has corners that define 60° interior angles, a pentagon has corners that define 108° interior angles, a hexagon has corners that define 120° interior angles, and so on. As further shown in Figure 3, if the length of each side is made infinitesimally short, the polygon turns into a circle. Thus, a semiconductor die having the shape shown in Figure 3 will experience increasing stresses at its corners as it moves from the shape on the right side of the figure to the shape on the left side of the figure.

[0071] It has been recognized that failure in many materials generally begins either at a defect or flaw (e.g., a crystalline defect, a damaged area of ​​the crystal, or a void, crack, or chip within the crystal), or in an area of ​​highest stress concentration. Various techniques described herein focus on dicing semiconductor wafers into geometries (when viewing the die / wafer in a plan view) that reduce abrupt geometric changes and / or thereby dicing the wafer along the crystal axes of the wafer substrate in order to reduce stress concentrations in the semiconductor die and / or strengthen weak areas that may naturally exist in the semiconductor die.

[0072] Silicon carbide-based semiconductor devices are typically formed by growing semiconductor epitaxial layers on a silicon carbide substrate to form a semiconductor layer structure, then processing the wafer (e.g., depositing metal and / or insulating layers on the wafer, performing ion implantation steps, and performing various etching steps), and then dicing the completed wafer into a plurality of individual semiconductor dies, each of which is a separate semiconductor device. The silicon carbide wafers on which the semiconductor epitaxial layers are grown almost always have a round shape in plan view, and these wafers are diced by sawing the wafer along longitudinal and lateral cut lines to singulate the wafer into a plurality of individual semiconductor dies.

[0073] Figure 4 is a plan view of a conventional silicon carbide semiconductor wafer 20, showing longitudinal and lateral cut lines 22, 24. In the example of Figure 4, the wafer 20 is diced to provide a total of 57 semiconductor dies 26. As discussed above, rectangular semiconductor dies 26 formed using such conventional dicing techniques can be prone to defects for two reasons.

[0074] First, the relatively sharp 90-degree angles formed at the corners of the semiconductor die 26 act to accumulate stress in these areas, creating potential failure points. This can be seen, for example, by referring to FIG. 6, which is a collage of plan views of a square semiconductor die 30, a hexagonal semiconductor die 32, and a round semiconductor die 34, showing stress concentrations at the corners of each die. A magnified view of the corner area of ​​each semiconductor die is shown as a callout. In these callouts, the darker the area, the greater the stress. As can be seen, very high stress concentrations are generated at the corners of the square semiconductor die 30. The corners of the hexagonal semiconductor die 32 also exhibit high stress, but at significantly lower levels than the square semiconductor die 30. The round semiconductor die 34 represents an optimal shape for reducing maximum stress concentrations. In all cases, the stress concentrations in the center or "bulk" of the semiconductor die (i.e., away from the outer edges and all corners) are lower than the corners, and the stress concentrations in the bulk of each semiconductor die 30, 32, and 34 are comparable. However, because failures tend to occur in areas of highest stress concentration, increasing the interior angles defined by the corners of the semiconductor die by increasing the number of sides acts to significantly reduce the likelihood of crack formation that can lead to delamination and / or failure of the semiconductor die.

[0075] Second, when 4H silicon carbide semiconductor wafers 20 are used (4H silicon carbide is the type of silicon carbide almost always used to form power semiconductor devices), because 4H silicon carbide has a hexagonal crystal structure, at most only one of the longitudinal cut lines 22 or lateral cut lines 24 shown in FIG. 4 can extend along a crystal axis of the 4H silicon carbide wafer 20. When the material is diced along a direction that is not along a crystal axis (such cuts are referred to herein as "off-axis" cuts), disruptions are created in the lattice of the material that weaken the structure of the lattice. These disruptions can manifest as initiation points for cracking, delamination, performance degradation, and / or failure of the semiconductor die.

[0076] According to embodiments of the present invention, a semiconductor die is provided that has a polygonal shape with more than four sides when viewed in a plan view. As used herein, a "side" of a semiconductor die refers to a surface connecting the top and bottom (major) surfaces of the die. For example, a semiconductor die is provided that has a hexagonal shape (or a generally hexagonal shape, such as a hexagonal-shaped die with small chamfers at each corner) when viewed in a plan view. By forming the semiconductor die to have a polygonal shape with more than four sides, the amount of stress generated at the corners of the semiconductor die can be reduced. Furthermore, as discussed above, the use of a hexagonal-shaped semiconductor die can be particularly advantageous because 4H silicon carbide has a hexagonal crystal structure, and therefore, a semiconductor wafer formed from such a material can be diced along the crystal axes of the material to form a hexagonal-shaped 4H silicon carbide-based semiconductor die. Additionally, various other materials that are good candidates for power semiconductor devices, such as gallium nitride-based materials, also have a hexagonal crystal structure, and therefore hexagonal-shaped power semiconductor dies formed using gallium nitride or sapphire wafers can also be diced along the crystal axes of the substrate material. As discussed above, dicing the semiconductor dies along the crystal axes of the substrate reduces or eliminates lattice disturbances that can occur when the semiconductor dies are cut off-axis.

[0077] Additionally, some semiconductor dies having polygonal shapes with more than four sides, such as hexagonal-shaped semiconductor dies, can be "packed" to utilize a larger area of ​​a circular semiconductor wafer, thus enabling more semiconductor dies to be produced from a single wafer. This can be seen, for example, by comparing FIG. 4 , which illustrates semiconductor wafer 20 being cut to form square semiconductor dies 26, with FIG. 5 , which illustrates semiconductor wafer 40 according to an embodiment of the present invention, on which hexagonal-shaped semiconductor dies 46 have been formed. Semiconductor wafer 40 is cut, for example, using a laser beam cutting technique to dice the wafer into 61 hexagonal-shaped semiconductor dies 46. Wafers 20, 40 and semiconductor dies 26, 46 each have the same area; therefore, FIGS. 4 and 5 illustrate that the use of hexagonal-shaped semiconductor dies 46 can increase the amount of circular wafer that can be used to form individual semiconductor dies, compared to a wafer having square semiconductor dies.

[0078] Another technique that can be used to reduce the inherently high stress concentrations that can naturally occur at the corners of a semiconductor die is to include one or more chamfer cuts in the corner area that replace the sharp angle with two or more larger angles. The chamfer effectively adds an additional edge to each corner of the semiconductor die. Thus, for example, if a semiconductor wafer is diced into square semiconductor dies with each corner of the square chamfered, the stress concentrations created at each corner can be reduced.

[0079] Figure 7 illustrates how adding one or more chamfers to the corners of a semiconductor die can reduce maximum stress concentrations. In particular, Figure 7 is a collage that includes plan views of (1) a square semiconductor die 50 with sharp corners, (2) a square semiconductor die 52 with rounded corners, and (3) a square semiconductor die 54 with chamfered corners. The light and dark shading of the callouts in Figure 7 indicates the relative stress levels across each semiconductor die when the semiconductor die is bonded to an underlying submount and heated, with darker shading indicating higher stress levels.

[0080] As shown in FIG. 7, semiconductor die 50 with sharp corners exhibits the highest stress concentrations. The illustration of semiconductor die 54 shows that the stress concentrations can be significantly reduced by adding a 45° chamfer to each corner of a square, effectively converting the square shape into an octagonal shape rather than a regular octagon. As can be seen with reference to semiconductor die 52, the maximum stress concentrations can be further reduced by rounding the corners. The degree of rounding determines how much the stress concentrations are further reduced. It will be appreciated that techniques using semiconductor dies with more than four major sides can be combined with chamfering or rounding of corners. For example, FIG. 8 illustrates the relative stress levels generated in semiconductor die 60 compared to semiconductor die 62 when a hexagonal-shaped semiconductor die 60 with sharp corners and a hexagonal-shaped semiconductor die 62 with rounded corners are bonded to an underlying submount and heated. For silicon carbide-based semiconductor dies (or other semiconductor dies with a hexagonal crystal structure), hexagonal shaped semiconductor dies with rounded corners can represent a very attractive option for reducing the risk of defects because the hexagonal shape allows cutting along the crystal axes of the material to form the semiconductor die.

[0081] The "stress concentration factor" K is a scalar value that indicates the percentage increase in the magnitude of the maximum stress level due to differences in the shapes of different semiconductor dies. For example, when K is equal to 1.5, this means that the magnitude of the maximum stress is 50% greater than the default case. FIG. 9 is an example of a stress concentration factor design chart that shows how increasing the interior angles defined by each corner of the semiconductor die and rounding the corners of the semiconductor die affect the maximum stress concentration level of the semiconductor die. As shown in FIG. 9, the parameter "r" is the distance from the center of the semiconductor die to the radius of the corner apex, the parameter "d" is the distance from the center of the semiconductor die to the corner of the semiconductor die without the radius, the parameter "a" is the interior angle defined by the corner of the first (default) semiconductor die (here, 90°), and the parameter "b" is the interior angle defined by the corner of the second semiconductor die (here, shown as 120°). As shown in FIG. 9, as d / r increases (i.e., as the radius of the corner of the semiconductor die increases), the stress concentration factor "K" decreases. Also, as shown in Figure 9, the stress concentration factor "K" decreases as the ratio "a / b" decreases (which occurs as the interior angle defined by the corners of the second semiconductor die increases relative to the 90° interior angle defined by the corners of the first (default) semiconductor die). Thus, Figure 9 shows that two ways to reduce stress in the corner areas of the semiconductor die are (1) rounding the corners of the semiconductor die and (2) increasing the number of corners included in the semiconductor die (which increases the interior angle defined by each corner).

[0082] When the corners of the semiconductor die are not rounded, the parameter "d / r" in FIG. 9 is equal to 1.0. Because a hexagon has 120° interior angles and a rectangle has 90° interior angles, the parameter "a / b" is equal to 0.75 when comparing the maximum stress of a hexagonal semiconductor die to the maximum stress of a rectangular semiconductor die. As shown in FIG. 9, by changing from a rectangular semiconductor die to a hexagonal semiconductor die (in each case, the corners are not rounded), the stress concentration factor K can be reduced from approximately 2.0 to approximately 1.5. FIG. 9 also shows that rounding the corners of the semiconductor die (which increases the parameter d / r) acts to further reduce the stress concentration factor K. As shown in FIG. 9, the greatest reduction in the stress concentration factor K occurs initially with rounding the corners, and further rounding of the corners results in a gradual reduction in the stress concentration factor K.

[0083] Thus, according to some embodiments of the present invention, a semiconductor die is provided having a maximum stress level that is at least 10%, at least 15%, at least 20%, or at least 25% lower than the maximum stress level in a default semiconductor die, where the default semiconductor die is identical to a semiconductor die according to embodiments of the present invention except that the default semiconductor die has a rectangular shape. By "identical," we mean that the two semiconductor dies are the same in all aspects (e.g., materials, layer structure, etc.) except for shape, and have the same parameter "d" and, in some embodiments, the same parameter "r."

[0084] As discussed above, semiconductor wafers are traditionally singulated using a diamond dicing saw. Generally speaking, this technique can only be used to make linear cuts across the entire length or width of the semiconductor die and therefore cannot be used to singulate semiconductor wafers into semiconductor dies having polygonal shapes with more than four sides. Therefore, alternative dicing methods, such as dicing with a focused laser beam (including lasers that produce beams outside the visible spectrum, such as ultraviolet laser beams), may be used to form semiconductor dies according to embodiments of the present invention. In this type of dicing, the laser beam is passed along the cut line, typically multiple times, to separate the material. Because the beam of energy moves across the wafer, it is not limited to straight or orthogonal lines. Therefore, more complex semiconductor die shapes can be achieved. While the laser beam can completely remove material along the cut line (i.e., completely cut the wafer), often the laser beam can partially cut the material along the cut line, and then the tape to which the wafer is attached can be stretched, thereby separating the remaining material along the cut line. Dicing wafers using a laser beam can be cost-effective because it is fast and less material needs to be removed between devices, thus potentially allowing more devices to be formed on each wafer. Other less traditional dicing techniques, such as plasma dicing, stealth dicing, or thermal laser separation, can also be used.

[0085] A semiconductor die according to embodiments of the present invention can have a regular polygon shape or a non-regular polygon shape. A regular polygon is a polygon in which all sides have the same length. On the other hand, a non-regular polygon is a polygon in which some sides have different lengths. As discussed above, a regular polygon can be transformed into a non-regular polygon when the corners of the regular polygon are chamfered at an appropriate angle. Furthermore, in some devices, it may be advantageous to form the semiconductor die to have a non-regular polygon shape, which can increase flexibility in the placement and location of semiconductor die elements such as bond pads, gate runners, and gate fingers. A semiconductor die having a non-regular polygon shape can also better fit into a given package and provide an alternative technique for increasing device area. 10 illustrates how a semiconductor die 70 having a regular hexagonal shape can be replaced with a semiconductor die 72 having two long sides (converting a regular hexagon into a non-regular hexagon) to increase the die area. It should be noted that the above-discussed advantages of cutting along crystal axes, reducing corner stress concentrations, and increasing packing density can also all be achieved with the non-regular hexagonal shaped semiconductor die 72 shown in FIG.

[0086] 11A-19C illustrate exemplary semiconductor dies that can be formed using the techniques discussed above.

[0087] 11A and 11B are plan and perspective views, respectively, of a silicon carbide-based power diode semiconductor die 100 according to an embodiment of the present invention. As shown in FIGS. 11A-11B, the power diode semiconductor die 100 includes a top side having a metal anode contact pad 102 and a bottom or "back" side having a metal cathode contact pad (not visible in the figures). The center of the power diode semiconductor die 100 below the anode contact pad 102 may form an active area 106 of the power diode semiconductor die 100 that conducts current when the power diode semiconductor die 100 is in an on-state. This active area 106 is surrounded by an edge termination region 108 designed to reduce electric field levels along the periphery of the power diode semiconductor die 100. These electric fields could otherwise reach very high levels during device operation due to electric field crowding effects that occur around the periphery of the semiconductor die, particularly during reverse blocking operation. The sharper (smaller) the interior angles defined by each corner, the greater the electric field concentration effect and therefore the higher the electric field generated at the corners of the semiconductor die. Power diode semiconductor die 100 can have a 4H silicon carbide substrate and multiple silicon carbide semiconductor layers formed thereon.

[0088] The power diode semiconductor die 100 has a regular hexagonal shape. Therefore, as shown in FIG. 11A , the interior angles defined by the corners of the semiconductor die exceed 90° (here, each angle is 120°). As discussed above, these large interior angles (compared to a square-shaped semiconductor die) reduce stress concentrations at the corners of the semiconductor die 100. Additionally, because the power diode semiconductor die 100 has a silicon carbide substrate, all cutting lines can be aligned with the respective crystal axes of the silicon carbide substrate, and therefore, each of the six cuts (cuts along each side of the semiconductor die 100) used to singulate the semiconductor die 100 can be aligned with the respective crystal axes of the silicon carbide substrate. This results in “cleaner” cuts that are less likely to damage the silicon carbide substrate and semiconductor epitaxial layers, thereby creating fewer weak points in the crystal lattice that can act as initiation points that can later lead to damage or failure of the semiconductor die 100. Additionally, because the interior angle defined by the corners of hexagonal semiconductor die 100 is larger (120°) than the interior angle (90°) present in a conventional square-shaped semiconductor die, the electric field levels within semiconductor die 100 may be smaller (all else being equal) than the corresponding electric field levels within a conventional square semiconductor die. Thus, the size of the edge termination can be reduced in semiconductor die 100 while maintaining the same electric field levels as in a conventional square semiconductor die.

[0089] 11A-11B illustrate, by way of example, a power diode semiconductor die 100 having a regular hexagonal shape, it will be understood that in accordance with the techniques disclosed herein, the power diode semiconductor die may have any polygonal shape having more than four sides (or corners with angles greater than 90°), and may have a regular or irregular polygonal shape. Additionally, the corners of the hexagonal shape may be chamfered in some embodiments.

[0090] The power diode semiconductor die 100 discussed above with reference to FIGS. 11A-11B is a two-terminal device. Most power semiconductor devices are three-terminal devices, such as MOSFETs, JFETs, IGBTs, and gate-controlled thyristors. A three-terminal semiconductor die typically has a large pad on the top side that serves as the first current-carrying terminal (e.g., source terminal, emitter terminal, etc.) and a smaller pad on the top side that serves as the gate terminal (i.e., the terminal that controls the current through the device). In some device technologies (e.g., many MOSFETs and IGBTs), low-impedance traces called gate runners are used to reduce the impedance of the conductive structure that distributes signals input at the gate pad to the gate fingers through the active area of ​​the semiconductor die. These semiconductor dies also typically have a large pad on the backside that serves as the second current-carrying terminal (e.g., drain terminal, collector terminal, etc.). The top periphery of the semiconductor die typically includes a termination region designed to reduce the electric field level along the periphery of the semiconductor die.

[0091] 12A and 12B are plan and perspective views, respectively, of a silicon carbide-based power MOSFET semiconductor die 110 according to an embodiment of the present invention. As shown in FIGS. 12A-12B, the power MOSFET semiconductor die 110 includes a large metal source contact pad 112 and a smaller gate contact pad 114 on its top side that is electrically isolated from the source contact pad 112. A gate runner 116 is electrically connected to the gate contact pad 114 (and is isolated from the source contact pad 116) and extends substantially around the periphery of the semiconductor die 110. The MOSFET 110 includes an active area (not visible in FIGS. 12A-12B because the active area is below the source contact pad 112), which is a portion of the semiconductor layer structure that is substantially within the area bounded by the gate runner 116. An edge termination region 118 extends around the periphery of the semiconductor die 110 outside the gate runner 116. The “back” side of semiconductor die 110 has a metal drain contact pad 120 on its surface, which may cover substantially all of the back side of semiconductor die 110 .

[0092] Figure 12C is a schematic side view of a portion of semiconductor die 110 of Figures 12A-12B. As shown, semiconductor die 110 includes a semiconductor layer structure 122 comprising a semiconductor substrate 124 and a plurality of semiconductor epitaxial layers 126 formed on an upper surface of semiconductor substrate 124. Drain contact pads 120 are formed on the lower surface of semiconductor substrate 124, and source contact pads 112 and gate contact pads 114 are formed on the upper surface of semiconductor epitaxial layer 126. Insulating pattern 113 (not visible in the plan and perspective views of Figures 12A-12B) insulates gate contact pad 114 from source contact pad 112.

[0093] The power MOSFET semiconductor die 110 has a hexagonal shape. As shown in FIGS. 12A-12B , the gate contact pad 114 is disposed along one side of the hexagon. The gate runner 116 extends from the upper left corner of the gate contact pad 114 and runs around most of the periphery of the top surface of the semiconductor die 110. The gate runner 116 includes a plurality of interconnected linear segments, including first and fifth segments 117-1, 117-5 extending from the respective upper corners of the gate contact pad 114; second, third, sixth, and seventh segments 117-2, 117-3, 117-6, and 117-7, each extending completely along one side of the hexagon; and fourth and eighth segments 117-4, 117-8, each extending partially along the side of the hexagon opposite the gate contact pad 114. The first segment 117-1 is disposed between the gate contact pad 114 and the second segment 117-2 and is connected to the gate contact pad 114 and the second segment 117-2, the second segment 117-2 is disposed between the first segment 117-1 and the third segment 117-3 and is connected to the first segment 117-1 and the third segment 117-3, and the third segment 117-3 is disposed between the second segment 117-2 and the fourth segment 117-4 and is connected to the second segment 117-2 and the fourth segment 117-4. Similarly, the fifth segment 117-5 is disposed between the gate contact pad 114 and the sixth segment 117-6 and is connected to the gate contact pad 114 and the sixth segment 117-6, the sixth segment 117-6 is disposed between the fifth segment 117-5 and the seventh segment 117-7 and is connected to the fifth segment 117-5 and the seventh segment 117-7, and the seventh segment 117-7 is disposed between the sixth segment 117-6 and the eighth segment 117-8 and is connected to the sixth segment 117-6 and the eighth segment 117-8. Each segment 117 is connected to an adjacent segment at an interior angle of 120°.

[0094] Power MOSFET semiconductor die 110 has a regular hexagonal shape and, therefore, has the same advantages over conventional square semiconductor dies as discussed above with reference to power diode semiconductor die 100 of Figures 11A-11B. Additionally, while Figures 12A-12B illustratively show power MOSFET semiconductor die 110 having a regular hexagonal shape, it will be understood that in accordance with the techniques disclosed herein, power MOSFET semiconductor die (and other three-terminal power semiconductor dies) may have any polygonal shape having more than four sides (or corners with angles greater than 90°), may have a regular or non-regular polygonal shape, and / or may include chamfered or rounded corners.

[0095] 12A-12B, in accordance with some embodiments of the present invention, a semiconductor device is provided that includes a semiconductor die 110 that includes a semiconductor substrate 124 having a hexagonal crystal structure. In some embodiments, the semiconductor substrate 124 may include a 4H silicon carbide substrate. In some embodiments, first and second sides of the semiconductor die 110 extend along respective first and second crystal axes of the hexagonal crystal structure of the semiconductor substrate 124. In other embodiments, the semiconductor die 110 may include at least five sides when viewed in a plan view. In still other embodiments, the semiconductor die 110 may have a polygonal shape with corners that define interior angles greater than 90° when viewed in a plan view. The semiconductor die 110 may include, for example, a MOSFET that includes an active region that includes a plurality of unit cell transistors.

[0096] According to further embodiments of the present invention, power MOSFET semiconductor dies (and other three-terminal semiconductor dies) are provided having a variety of different designs for gate pads and / or gate runners. For example, FIGS. 13A-13F illustrate three-terminal hexagonally shaped power semiconductor dies (e.g., power MOSFETs) having gate pads located in a variety of different positions. For example, in semiconductor die 130 shown in FIG. 13A, gate pad 132 is located adjacent to a first edge of semiconductor die 130 and is generally centered along the middle of the edge. Note that semiconductor die 130 may be identical to semiconductor die 120 of FIGS. 12A-12B. In contrast, FIG. 13B illustrates semiconductor die 140 having gate pad 142 located at the intersection of two edges of semiconductor die 140. FIG. 13C illustrates semiconductor die 150 having gate pad 152 located at the center of semiconductor die 150. Finally, FIG. 13D illustrates a semiconductor die 160 having gate pads 162-1 through 162-6 located at each of the intersections of two sides of the semiconductor die 160. While not individually illustrated, it will be appreciated that other embodiments may provide a semiconductor die having gate pads located at the center of each side of the semiconductor die (i.e., a die having five additional gate pads along the remaining five sides of the semiconductor die of FIG. 13A). It will also be appreciated that a device having more than two gate pads may have fewer than five gate pads. For example, FIG. 13E illustrates a semiconductor die 170 having two gate pads 172-1 and 172-2 located adjacent to each other on opposing sides of the semiconductor die 170, and FIG. 13F illustrates a semiconductor die 180 having three gate pads 182-1 through 182-3 located at three of the six intersections of the two sides of the semiconductor die 180. Having multiple gate pads can involve a trade-off between gate resistance and packaging flexibility on the one hand and active area size on the other.

[0097] It will also be understood that the gate pad may have a shape other than the square or pentagonal shape shown in Figures 13A-13F. For example, Figures 14A-14D show semiconductor dies corresponding to the semiconductor dies of Figures 13A-13D, except that the semiconductor dies of Figures 14A-14D have circular gate pads or gate pads including at least a semicircular portion. Circular or rounded gate pads can be used to increase and / or maximize the size of the active area of ​​the device. Figures 15A-15D show semiconductor dies corresponding to the semiconductor dies of Figures 13A-13D, except that the semiconductor dies of Figures 15A-15D have rectangular gate pads or pentagonal gate pads that are not regular pentagons. The size of the gate pad is typically based on the method by which external circuitry is electrically connected to the gate pad (e.g., wire bonding, soldering, sintering, etc.), the size of the structure (e.g., wire bond) attached to the gate pad, and the process window of the attachment procedure. Changing from a square gate pad to a rectangular gate pad is a convenient way to increase the size of the gate pad (e.g., for devices with larger diameter bond wires). Figures 16A-16D show semiconductor dies that correspond to the semiconductor dies of Figures 15A-15D, except that the semiconductor dies of Figures 16A-16D have gate pads that are rectangular with at least some of the corners rounded or pentagonal in shape rather than regular pentagonal.

[0098] 17A-17C illustrate exemplary locations of gate runners in a three-terminal power semiconductor die according to embodiments of the present invention. The gate runners can provide connections between the gate pad and gate fingers of a device. Often, the gate runners are formed of metal to provide low impedance. The gate runners may include segments that match the shape of the semiconductor die (e.g., a hexagonal shape) or may include additional segments.

[0099] For example, FIG. 17A illustrates a semiconductor die 200 including a gate pad 202 and a gate runner 204 having multiple segments 206 that extend substantially all around the periphery of the semiconductor die 200 and an additional segment 208 that extends through the center of the semiconductor die 200. Multiple gate fingers 210 (e.g., silicon gate fingers) are electrically connected (and, in some embodiments, may also be physically connected) to the gate runner 204. A gate signal input at the gate pad 202 is passed to the gate fingers 210 via the gate runner 204. As shown, in this configuration, the gate fingers 210 are divided into two groups, and each gate finger 210 is fed from both sides, thereby reducing the resistance of the path the gate signal follows as it travels from the gate pad 202 along the individual gate fingers 210. FIG. 17B illustrates a semiconductor die 220 that modifies the semiconductor die 200 of FIG. 17A. Semiconductor die 220 includes a gate pad 222 and a gate runner 224 having multiple segments 226 that extend substantially all the way around the periphery of semiconductor die 200 and two additional segments 228 that extend through the central region of semiconductor die 220. In the device of FIG. 17B, three groups of gate fingers 230 are provided, with each gate finger 230 being fed from both sides. Semiconductor die 220 can exhibit a lower gate resistance than semiconductor die 200, but this comes at the expense of a smaller active area size for the device. FIG. 17C shows semiconductor die 240 that includes a gate pad 242 and a gate runner 244 that extends substantially all the way around the periphery of semiconductor die 200 and also includes additional segments 228 that extend radially from the periphery of semiconductor die 240 into the active area. The radial gate runner segments divide gate fingers 250 into six groups that extend at different angles relative to each other.

[0100] 18A-18C show a semiconductor die having a gate runner design similar to that shown in FIGS. 17A-17C, except that the semiconductor die in FIGS. 18A-18C has gate pads located at the ends of two sides, whereas the semiconductor die in FIGS. 17A-17C has gate pads located centrally along each edge of the semiconductor die. FIGS. 19A-19C similarly show a semiconductor die having a gate runner design similar to that shown in FIGS. 17A-17C, except that the semiconductor die in FIGS. 19A-19C has gate pads located in the center of the device. For simplicity, gate fingers are not shown in FIGS. 18A-19C.

[0101] In some cases, a three-terminal semiconductor die may require additional contact (bonding) pads necessary for secondary functions. For example, in devices with soldered or sintered topside connections, a dedicated source Kelvin wire bond pad may also be provided. As another example, additional secondary bond pads may be required in some cases for on-chip sensors, such as temperature or current sensors. FIGS. 20A-20D show an exemplary semiconductor die with additional topside contact pads (i.e., source contact pad 300, gate contact pad 302, and one or more additional contact pads 304). Many more configurations are possible, in which some or all of the gate contact pads and / or additional contact pads have circular (or partially circular) or rectangular shapes.

[0102] Semiconductor dies according to embodiments of the present invention can be used in a myriad of applications, including motor drives, battery chargers, wind / solar inverters, power supplies, and the like.

[0103] Although the present invention has been described above primarily with respect to embodiments of power MOSFETs, it will be appreciated that the techniques described herein apply to other power semiconductor devices as well, and therefore embodiments of the present invention are not limited to MOSFETs.

[0104] While embodiments of the present invention are discussed above primarily with respect to semiconductor die having at least five sides and / or corners that define interior angles greater than 90° when viewed in plan view, it will be understood that embodiments of the present invention are not limited thereto. In other embodiments, the semiconductor die may have fewer than four sides (e.g., three sides to form a triangle) when viewed in plan view and / or corners that define interior angles less than 90°, such as a 60° angle. Thus, it will be understood that all of the hexagonal-shaped semiconductor die discussed above may be embodied as triangular-shaped dies in other embodiments.

[0105] The present invention has been discussed above primarily with respect to silicon carbide-based power semiconductor devices. However, silicon carbide is used herein as an example, and it will be understood that the devices discussed herein may be formed in any suitable wide bandgap semiconductor material system. By way of example, a gallium nitride-based semiconductor material (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used in place of silicon carbide in any of the above examples.

[0106]

[0023] Embodiments of the present invention have been described above with reference to the accompanying drawings, in which embodiments of the invention are shown. It should be understood, however, that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth above. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

[0107] As used herein, the term "plurality" means two or more. As used herein, "substantially" means within ±10%.

[0108] Throughout this specification, terms such as first, second, etc. are used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used merely to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0109] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that as used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0110] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another element, it is understood that it may be directly on or extending directly onto the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. When an element is referred to as being "connected" or "coupled" to another element, it is understood that it may be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0111] Relative terms such as "lower" or "upper" or "upper" or "lower" or "top" or "bottom" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It will be understood that these terms are intended to encompass various orientations of the device in addition to the orientation depicted in the figures.

[0112] Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations are expected as a result, for example, of manufacturing techniques and / or tolerances. Embodiments of the present invention are also described with reference to flow charts. It will be understood that the steps illustrated in the flow charts do not have to be performed in the order shown.

[0113] In the drawings and specification, there are disclosed exemplary embodiments of the invention, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being indicated in the following claims.

Claims

1. a semiconductor die comprising a substrate having a hexagonal crystal structure; a semiconductor device, wherein first and second sides of the semiconductor die extend along respective first and second crystal axes of the hexagonal crystal structure of the substrate;

2. The semiconductor device of claim 1 , wherein the first side and the second side intersect to define an interior angle that is obtuse.

3. 10. The semiconductor device of claim 1, wherein the semiconductor die comprises at least five sides when viewed in plan view.

4. The semiconductor device of claim 3 , wherein the semiconductor die has a hexagonal shape when viewed in plan view.

5. 4. The semiconductor device of claim 3, wherein the semiconductor die has a polygonal shape when viewed in plan view that is not a regular polygon.

6. 4. The semiconductor device of claim 3, wherein the semiconductor die has a hexagonal shape with chamfered corners when viewed in plan view.

7. 7. The semiconductor device of claim 1, wherein the semiconductor die comprises a MOSFET having an active area comprising a plurality of unit cell transistors.

8. 8. The semiconductor device of claim 7, wherein the gate runner of the MOSFET comprises a first segment and a second segment that connect at an obtuse angle.

9. 9. The semiconductor device of claim 8, wherein the first and second segments of the gate runner each extend along a periphery of the active area.

10. 10. The semiconductor device of claim 9, wherein a gate pad of the MOSFET is centrally located in the active area, and the gate runner comprises a plurality of additional segments extending outward from the gate pad.

11. 8. The semiconductor device of claim 7, wherein the MOSFET gate runner comprises a first segment and a second segment that connect at an angle between 115° and 125°.

12. 4. The semiconductor device of claim 1, wherein the semiconductor die has a polygonal shape when viewed in plan, the corners of the polygonal shape defining interior angles greater than 90 degrees.

13. The semiconductor device of claim 1 , wherein the substrate comprises a silicon carbide substrate.

14. The semiconductor device of claim 1 , wherein the substrate comprises a gallium nitride substrate.

15. a semiconductor die; 1. A semiconductor device, wherein the semiconductor die has at least five sides when viewed in plan view.

16. 16. The semiconductor device of claim 15, wherein the semiconductor die comprises a semiconductor layer having a hexagonal crystal structure.

17. 17. The semiconductor device of claim 16, wherein the semiconductor die has a hexagonal shape when viewed in plan view.

18. 20. The semiconductor device of claim 17, wherein the semiconductor die has a hexagonal shape when viewed in plan view that is not a regular hexagon.

19. 20. The semiconductor device of claim 17, wherein the semiconductor die has a hexagonal shape with chamfered corners when viewed in a plan view.

20. 20. The semiconductor device of claim 16, wherein at least three of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

21. 20. The semiconductor device of claim 16, wherein all of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

22. the semiconductor die comprises a MOSFET having an active area comprising a plurality of unit cell transistors; 20. The semiconductor device of claim 16, wherein the gate runner of the MOSFET comprises a first segment and a second segment that connect at an obtuse angle.

23. 23. The semiconductor device of claim 22, wherein the obtuse angle is an angle of 120 degrees.

24. 23. The semiconductor device of claim 22, wherein the first and second segments of the gate runner each extend along a perimeter of the active area.

25. 22. The semiconductor device of claim 21, wherein a gate pad of the MOSFET is centrally located in the active area, and the gate runner comprises a plurality of additional segments extending radially outward from the gate pad.

26. 20. The semiconductor device of claim 16, wherein the semiconductor die has a polygonal shape when viewed in a plan view, the corners of the polygonal shape defining interior angles greater than 90 degrees.

27. 27. The semiconductor device of any of claims 16 to 26, wherein the semiconductor layer comprises a silicon carbide substrate.

28. 27. The semiconductor device of any of claims 16 to 26, wherein the semiconductor layer comprises a gallium nitride substrate.

29. a semiconductor die; 1. A semiconductor device wherein, when viewed in plan, the semiconductor die has a polygonal shape with corners defining interior angles greater than 90°.

30. 30. The semiconductor device of claim 29, wherein the semiconductor die comprises a semiconductor layer having a hexagonal crystal structure.

31. 31. The semiconductor device of claim 30, wherein the polygonal shapes are hexagons.

32. 32. The semiconductor device of claim 31, wherein the polygonal shape is a hexagonal shape that is not a regular hexagon.

33. 31. The semiconductor device of claim 30, wherein at least two sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

34. 31. The semiconductor device of claim 30, wherein all sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

35. the semiconductor die comprises a MOSFET having an active area comprising a plurality of unit cell transistors; 35. The semiconductor device of any of claims 30 to 34, wherein the MOSFET gate runner comprises a first segment and a second segment that connect at an obtuse angle.

36. 36. The semiconductor device of claim 35, wherein the obtuse angle is an angle of 120 degrees.

37. 36. The semiconductor device of claim 35, wherein the first and second segments of the gate runner each extend along a perimeter of the active area.

38. 38. The semiconductor device of claim 37, wherein a gate pad of the MOSFET is centrally located in the active area, and the gate runner comprises a plurality of additional segments extending radially outward from the gate pad.

39. 39. The semiconductor device of any of claims 30 to 38, wherein the semiconductor layer comprises a silicon carbide substrate or a gallium nitride substrate.

40. a semiconductor die; A semiconductor device wherein the semiconductor die has a polygonal shape with chamfered corners when viewed in plan.

41. 41. The semiconductor device of claim 40, wherein the semiconductor die comprises a semiconductor layer having a hexagonal crystal structure.

42. 42. The semiconductor device of claim 41, wherein the polygonal shape has six major sides and the chamfered corners include six chamfered corners.

43. 43. The semiconductor device of claim 42, wherein at least two of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the substrate.

44. 43. The semiconductor device of claim 42, wherein all of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

45. the semiconductor die comprises a MOSFET having an active area comprising a plurality of unit cell transistors; 45. The semiconductor device of any of claims 40 to 44, wherein the MOSFET gate runner comprises a first segment and a second segment that connect at an obtuse angle.

46. 46. ​​The semiconductor device of claim 45, wherein the obtuse angle is an angle of 120 degrees.

47. 47. The semiconductor device of claim 45 or 46, wherein the first and second segments of the gate runner each extend along a periphery of the active area.

48. 48. The semiconductor device of claim 45, wherein a gate pad of the MOSFET is centrally located in the active area, and the gate runner comprises a plurality of additional segments extending radially outward from the gate pad.

49. a semiconductor layer structure comprising an active region; a gate runner of the semiconductor layer structure comprising a first segment and a second segment that connect at an obtuse angle; 1. A semiconductor device comprising: a semiconductor die comprising:

50. 50. The semiconductor device of claim 49, wherein the obtuse angle is an angle of 120 degrees.

51. 51. The semiconductor device of claim 50, wherein the first and second segments of the gate runner each extend along a perimeter of the active area.

52. 51. The semiconductor device of claim 50, wherein the gate runner further comprises third and fourth segments, the first through fourth segments defining respective first through fourth sides of a hexagon when viewed in a plan view.

53. 51. The semiconductor device of claim 50, wherein a gate pad of the MOSFET is centrally located in the active area, and the gate runner comprises a plurality of additional segments extending radially outward from the gate pad.

54. 54. The semiconductor device of claim 53, wherein the plurality of additional segments are radially spaced apart from one another by 60 degrees.

55. 54. The semiconductor device of claim 53, wherein the semiconductor die is a hexagonal shaped semiconductor die.

56. a semiconductor layer structure comprising an active region; a gate runner of the semiconductor layer structure comprising first, second, and third segments extending along respective first, second, and third crystal axes of a semiconductor substrate of the semiconductor layer structure; 1. A semiconductor device comprising: a semiconductor die comprising:

57. 57. The semiconductor device of claim 56, wherein the first, second, and third segments of the gate runner each extend along a perimeter of the active area.

58. 57. The semiconductor device of claim 56, wherein the gate runner further comprises a fourth segment, the first through fourth segments defining respective first through fourth sides of a hexagon when viewed in a plan view.

59. 59. The semiconductor device of any of claims 56 to 58, wherein the semiconductor die is a hexagonal shaped semiconductor die.

60. a semiconductor layer structure comprising an active region; a gate pad of the semiconductor layer structure; a plurality of gate runner segments extending radially from the gate pad to corners of the semiconductor die; A semiconductor device comprising:

61. 61. The semiconductor device of claim 60, wherein the gate pad is located in a central portion of the active area.

62. 61. The semiconductor device of claim 60, further comprising an additional plurality of gate runner segments extending along a perimeter of the active area.

63. 63. The semiconductor device of any of claims 60 to 62, wherein the semiconductor die is a hexagonal shaped semiconductor die.

64. 63. The semiconductor device of any of claims 60 to 62, wherein the gate pad is located in the center of the active area.

65. 63. The semiconductor device of any of claims 60 to 62, wherein the semiconductor layer structure comprises a 4H silicon carbide substrate.

66. 66. The semiconductor device of any of claims 1 to 65, wherein the semiconductor die is a first semiconductor die and the second semiconductor die has a maximum stress level that is at least 20% less than a maximum stress level in the second semiconductor die, the second semiconductor die being identical to the first semiconductor die except for having a rectangular shape.

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