Method for fabricating a semiconductor-on-insulator wafer having a charge trapping layer with controlled stress

Abstract

The method for fabricating a multilayer structure includes providing a monocrystalline semiconductor handle substrate including a front surface, a rear surface, a peripheral edge connecting the front and rear surfaces, and a central surface between the front and rear surfaces. The monocrystalline semiconductor handle substrate has a minimum bulk area resistivity of at least about 500 ohm-cm. The method also includes depositing a semiconductor layer on the front surface of the monocrystalline semiconductor handle substrate. The depositing of the semiconductor layer is carried out by two or more cycles of depositing a portion of the semiconductor layer, interrupting deposition after the portion of the semiconductor layer has been deposited, and annealing the portion of the semiconductor layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Patent Application No. 18 / 162,951, filed February 1, 2023, the disclosure of which is incorporated herein by reference in its entirety. [Technical Field]

[0002] The present disclosure relates generally to the field of semiconductor wafer manufacturing. More particularly, the present disclosure relates to methods of making handle substrates for use in manufacturing semiconductor-on-insulator (e.g., silicon-on-insulator) structures, and more particularly to methods of producing a polycrystalline semiconductor layer on a handle wafer of a semiconductor-on-insulator structure, where stress in the polycrystalline semiconductor layer is controlled without introducing crystallographic slip defects into the handle wafer. [Background technology]

[0003] Semiconductor wafers are typically made from a single crystal ingot (e.g., a silicon ingot) that is trimmed and ground to have one or more flats or notches to properly orient the wafer in subsequent steps. The ingot is then sliced ​​into individual wafers. While reference is made herein to semiconductor wafers constructed from silicon, other materials, such as germanium, silicon carbide, silicon germanium, or gallium arsenide, may also be used to make semiconductor wafers.

[0004] Semiconductor wafers (e.g., silicon wafers) can be used to fabricate composite layer structures. Composite layer structures (e.g., semiconductor-on-insulator, more specifically, silicon-on-insulator (SOI) structures) generally include a handle wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle and device layers. The device layer is typically 0.01-20 micrometers thick, e.g., 0.05-20 micrometers thick. Composite layer structures, such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz, are typically produced by intimately contacting two wafers followed by heat treatment to strengthen the bond.

[0005] After thermal annealing, the bonded structure undergoes further processing to remove a significant portion of the donor wafer to achieve layer transfer. For example, wafer thinning techniques such as etching or grinding, often referred to as back-etch SOI (i.e., BESOI), can be used, in which a silicon wafer is bonded to a handle wafer and then slowly etched until only a thin layer of silicon remains on the handle wafer. See, for example, U.S. Pat. No. 5,189,500, the disclosure of which is incorporated herein by reference as if set forth in its entirety. This method is time-consuming and expensive, wastes one of the substrates, and generally does not have suitable thickness uniformity for layers thinner than a few microns.

[0006] Another common method for achieving layer transfer utilizes hydrogen implantation followed by thermally induced layer splitting. Particles (e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted to a specific depth below the front surface of the donor wafer. The implanted particles form a cleavage plane within the donor wafer at the specific depth at which they were implanted. The surface of the donor wafer is then cleaned to remove any organic compounds that may have deposited on the wafer during the implantation process.

[0007] The front surface of the donor wafer is then bonded to the handle wafer to form a bonded wafer by a hydrophilic bonding process. Prior to bonding, the donor wafer and / or the handle wafer may be activated by exposing the wafer surface to a plasma containing, for example, oxygen or nitrogen. The plasma exposure modifies the surface structure in a process often referred to as surface activation, which makes one or both surfaces of the donor wafer and the handle wafer hydrophilic. The wafers are then pressed together to form a bond between them. This bond may be relatively weak and may be strengthened before further processing occurs.

[0008] In some processes, the hydrophilic bond between the donor wafer and the handle wafer (i.e., the bonded wafer) is strengthened by heating or annealing the bonded wafer pair. In some processes, wafer bonding may occur at low temperatures, such as between about 300°C and 500°C. In some processes, wafer bonding may occur at high temperatures, such as between about 800°C and 1100°C. As the temperature increases, covalent bonds form between the adjacent surfaces of the donor and handle wafers, thus solidifying the bond between the donor and handle wafers. Upon heating or annealing the bonded wafers, particles previously implanted in the donor wafer weaken the cleavage plane.

[0009] A portion of the donor wafer is then separated (e.g., cleaved) from the bonded wafer along the cleavage plane to form an SOI wafer. Cleaving can be performed by placing the bonded wafer in a fixture where a mechanical force is applied perpendicular to opposite sides of the bonded wafer to pull the portion of the donor wafer away from the bonded wafer. According to some methods, a suction cup is utilized to apply the mechanical force. Separation of the portion of the donor wafer is initiated by applying a mechanical wedge to the edge of the bonded wafer at the cleavage plane to initiate propagation of a crack along the cleavage plane. The mechanical force applied by the suction cup then pulls the portion of the donor wafer from the bonded wafer, thus forming the SOI wafer.

[0010] According to another method, the bonded pair may instead be subjected to high temperatures for a period of time to separate a portion of the donor wafer from the bonded wafer. Exposure to high temperatures causes the initiation and propagation of cracks along the cleavage plane, thus separating the portion of the donor wafer. This method can promote better uniformity of the transferred layer and allow for the reuse of the donor wafer, but typically requires heating the implanted and bonded pair to temperatures approaching 500°C.

[0011] The use of high-resistivity semiconductor-on-insulator (e.g., silicon-on-insulator) wafers for radio frequency (RF)-related devices, such as antenna switches, offers advantages over conventional substrates in terms of cost and integration density. To reduce parasitic power losses and minimize harmonic distortion inherent when using conductive substrates for high-frequency applications, using a high-resistivity substrate wafer is necessary, but not sufficient. Therefore, the resistivity of handle wafers for RF devices is generally greater than about 500 ohm-cm or greater than about 1000 ohm-cm. Referring now to Figure 1, a silicon-on-insulator structure 2 is shown, comprising a very high-resistivity silicon wafer 4, a buried oxide (BOX) layer 6, and a silicon device layer 10. Such substrates are susceptible to the formation of a highly conductive charge inversion or accumulation layer 12 at the BOX / handle interface, which causes the generation of free carriers (electrons or holes). This reduces the effective resistivity of the substrate and leads to parasitic power losses and device nonlinearity when the device operates at RF frequencies. These inversion / accumulation layers can result from BOX fixed charges, oxide trapped charges, interface trapped charges, and even the DC bias applied to the device itself.

[0012] Therefore, a method is needed to trap charge in any induced inversion or accumulation layer so that the high resistivity of the substrate is maintained even in regions very close to the surface. It is known that a charge trapping layer (CTL) between a high-resistivity handle substrate and a buried oxide (BOX) can improve the performance of RF devices fabricated using SOI wafers. Several methods have been proposed for forming these high-interface trapping layers. For example, referring now to FIG. 2, one method for creating a semiconductor-on-insulator (e.g., silicon-on-insulator, or SOI) with a CTL for RF device applications is based on depositing an undoped polycrystalline silicon film 28 on a silicon substrate 22 with high resistivity, followed by forming a stack of an oxide 24 and a top silicon layer 26 thereon. The polycrystalline silicon layer 28 acts as a high-defect layer between the silicon substrate 22 and the buried oxide layer 24. See FIG. 2, which illustrates a polycrystalline silicon film for use as the charge trapping layer 28 between the high-resistivity substrate 22 and the buried oxide layer 24 in the silicon-on-insulator structure 20. An alternative method is the implantation of heavy ions to create a damaged layer near the surface.Devices, such as radio frequency (RF) devices, are built in the top silicon layer 26.

[0013] A polysilicon layer between the oxide and substrate has been shown in academic studies to improve device isolation, lower transmission line losses, and reduce harmonic distortion. For example, HSGamble, et al. "Low-loss CPW lines on surface stabilized high resistivity silicon", Microwave Guided Wave Lett., 9(10), pp. 395-397, 1999; D. Lederer, R. Lobet and J.-P. Raskin "Enhanced high resistivity SOI wafers for RF applications", IEEE Intl. SOI Conf., pp. 46-47, 2004; D. Lederer and J.-P. Raskin, "New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity", IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, 2005; D. Lederer, B. Aspar, C. Laghae and J.-P. Raskin "Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate", IEEE International SOI Conference, pp. 29-30, 2006; and Daniel C. Kerret et al., "Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer," Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008 (IEEE Topical Meeting), pp. 151-154, 2008. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] U.S. Patent No. 5,189,500 [Non-patent literature]

[0015] [Non-Patent Document 1] HSGamble, et al. “Low-loss CPW lines on surface stabilized high resistivity silicon”, Microwave Guided Wave Lett., 9(10), pp. 395-397, 1999 [Non-patent document 2] D. Lederer, R. Lobet, and J.-P. Raskin, "Enhanced high resistivity SOI wafers for RF applications," IEEE Intl. SOI Conf., pp. 46-47, 2004 [Non-patent document 3] D. Lederer and J.-P. Raskin, "New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity," IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, 2005. [Non-patent document 4] D. Lederer, B. Aspar, C. Laghae and J.-P. Raskin, "Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate", IEEE International SOI Conference, pp.29-30, 2006. [Non-patent document 5] Daniel C. Kerret al. “Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer”, Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008 (IEEE Topical Meeting), pp. 151-154, 2008 Summary of the Invention

[0016] Embodiments disclosed herein include methods for fabricating a semiconductor-on-insulator (e.g., silicon-on-insulator) wafer having a semiconductor charge trapping layer deposited on a semiconductor handle substrate, wherein stress in the semiconductor charge trapping layer is controlled without creating crystallographic slip defects in the handle wafer. Preferably, the stress in the semiconductor charge trapping layer is controlled such that compressive stress induced by the deposition of the semiconductor charge trapping layer transitions to tensile stress. The methods described herein can include annealing the semiconductor charge trapping layer at a relatively low temperature. The annealing can be performed intermittently during deposition of the semiconductor charge trapping layer, with the deposition being paused after a portion of the semiconductor charge trapping layer is deposited and the deposited portion being annealed. The deposited portion can be annealed at an annealing temperature close to or substantially equal to the deposition temperature.

[0017] In one embodiment, a method for fabricating a multilayer structure is provided. The method includes preparing a single-crystal semiconductor handle substrate. The single-crystal semiconductor handle substrate includes two major substantially parallel surfaces, one of which is a front surface of the single-crystal semiconductor handle substrate and the other of which is a rear surface of the single-crystal semiconductor handle substrate, a peripheral edge connecting the front and rear surfaces of the single-crystal semiconductor handle substrate, and a central plane between the front and rear surfaces of the single-crystal semiconductor handle substrate. The single-crystal semiconductor handle substrate has a minimum bulk area resistivity of at least about 500 ohm-cm. The method also includes depositing a semiconductor layer on the front surface of the single-crystal semiconductor handle substrate. The depositing of the semiconductor layer is carried out by two or more cycles of depositing a portion of the semiconductor layer, interrupting deposition after the portion of the semiconductor layer has been deposited, and annealing the portion of the semiconductor layer.

[0018] In another aspect, a method for fabricating a multilayer structure is provided. The method includes preparing a monocrystalline semiconductor handle substrate. The monocrystalline semiconductor handle substrate includes two major substantially parallel surfaces, one of which is a front surface of the monocrystalline semiconductor handle substrate and the other of which is a rear surface of the monocrystalline semiconductor handle substrate, a peripheral edge connecting the front and rear surfaces of the monocrystalline semiconductor handle substrate, and a central plane between the front and rear surfaces of the monocrystalline semiconductor handle substrate. The monocrystalline semiconductor handle substrate has a minimum bulk area resistivity of at least about 500 ohm-cm. The method also includes depositing a polycrystalline semiconductor seed layer on the front surface of the monocrystalline semiconductor handle substrate and annealing the polycrystalline semiconductor seed layer. The method also includes depositing a first layer of polycrystalline semiconductor material on the annealed polycrystalline semiconductor seed layer at a deposition temperature and annealing the first layer of polycrystalline semiconductor material at a temperature lower than the temperature at which the polycrystalline semiconductor seed layer is annealed.

[0019] Other advantages and features of the embodiments disclosed herein will be in part apparent and in part pointed out hereinafter. [Brief explanation of the drawings]

[0020] [Figure 1] A diagram of a silicon-on-insulator wafer containing a high resistivity substrate and a buried oxide layer. [Figure 2] Diagram of a silicon-on-insulator wafer. SOI wafers contain a polycrystalline silicon charge trapping layer between a high resistivity substrate and a buried oxide layer. [Figure 3] FIG. 1 is a diagram of an exemplary single crystal semiconductor handle substrate for use in making a multilayer structure according to the method of the present disclosure. [Figure 4] FIG. 4 is a diagram of a multilayer structure made according to the method of the present disclosure, the multilayer structure including the handle substrate of FIG. 3 having a semiconductor charge trapping layer deposited on its front surface. [Figure 5] FIG. 1 is a diagram of an exemplary single crystal semiconductor donor substrate for use in fabricating a multilayer structure according to the method of the present disclosure, the donor substrate having a dielectric layer formed on its front surface. [Figure 6] 6 is a diagram of a multilayer structure made according to the method of the present disclosure, the multilayer structure including the dielectric layer of the donor substrate of FIG. 5 bonded to a semiconductor charge trapping layer deposited on the front surface of the handle substrate of FIG. 4. [Figure 7] FIG. 1 is a diagram of a multilayer structure made according to the method of the present disclosure, the multilayer structure including a handle substrate having a semiconductor charge trapping layer, a dielectric layer, and a semiconductor device layer deposited on its front surface. [Figure 8] 10 shows a probability plot comparing the change in three-point wafer bow after deposition of a polycrystalline semiconductor layer with a single post-deposition anneal and after deposition of a polycrystalline semiconductor layer in which intermittent anneals are performed. [Figure 9] 1 shows a probability plot comparing the change in three-point wafer curvature after deposition of a polycrystalline semiconductor layer with a single post-deposition anneal and after deposition of a polycrystalline semiconductor layer where intermittent anneals are performed, and the deposited polycrystalline semiconductor wafer is polished. [Figure 10]10 shows a probability plot comparing wafer SFQR after deposition of a polycrystalline semiconductor layer with a single post-deposition anneal and after deposition of a polycrystalline semiconductor layer in which intermittent anneals are performed. DETAILED DESCRIPTION OF THE INVENTION

[0021] In an exemplary embodiment, a method is provided that includes depositing a semiconductor charge trapping layer (also referred to herein as a "semiconductor layer" or "charge trapping layer") on a monocrystalline semiconductor handle substrate, e.g., a monocrystalline semiconductor handle wafer, such as a monocrystalline silicon handle wafer. The charge trapping layer may be deposited by various processes, for example, by chemical vapor deposition. Monocrystalline semiconductor handle wafers including a charge trapping layer are useful for producing semiconductor-on-insulator (e.g., silicon-on-insulator) structures. Preferably, the charge trapping layer includes a polycrystalline semiconductor material, such as silicon, SiGe, SiC, and Ge, which is deposited on the exposed front surface of a monocrystalline semiconductor handle substrate, e.g., a wafer, having high resistivity. The charge trapping layer may also be referred to as a "polycrystalline semiconductor layer." In some embodiments, the charge trapping layer may additionally and / or alternatively include an amorphous semiconductor material. In some embodiments, a dielectric layer (also referred to herein as a "buried oxide layer" or "BOX layer") is bonded to and / or formed on the polycrystalline semiconductor layer (e.g., by bonding a single-crystal semiconductor donor substrate with a dielectric layer to the polycrystalline layer) to form a multilayer structure including a handle substrate, a polycrystalline semiconductor layer, and a dielectric layer. The polycrystalline semiconductor layer acts as a high-density trapping region to prevent and / or eliminate electrical conductivity within the high-resistivity handle substrate that might otherwise occur at the interface between the high-resistivity handle substrate and the dielectric layer. The polycrystalline semiconductor layer also prevents the formation of induced charge inversion or accumulation layers in semiconductor-on-insulator structures fabricated by the methods described herein, which can contribute to power loss and nonlinear behavior in electronic devices designed for radio frequency (RF) device operation.

[0022] One problem associated with the deposition of semiconductor materials to create charge trapping layers is that the deposited semiconductor layer can have internal compressive stress resulting from the diffusion of deposited semiconductor (e.g., silicon) atoms into the semiconductor (e.g., polycrystalline semiconductor, such as polycrystalline silicon) grain boundaries. Compressive stress in the deposited semiconductor layer can cause curvature and / or warpage in the shape of semiconductor-on-insulator (SOI) structures, rendering the structures unsuitable for use in subsequent device fabrication. For example, SOI structures with a high degree of curvature and / or warpage can be difficult to process, particularly on equipment with precise wafer handling automation, and can cause focusing problems during lithography steps. Therefore, the semiconductor handle substrate with the deposited charge trapping layer must have a suitable level of curvature and warpage. This may be controlled during the semiconductor layer deposition process or corrected in subsequent processing (e.g., polishing). Furthermore, other aspects of the creation of SOI structures, such as the formation of a dielectric (e.g., buried oxide) layer over the semiconductor charge trapping layer, can adversely affect the structure and / or contribute to curvature and warpage. For example, compressive stresses resulting from the deposition of semiconductor layers and the formation of buried oxide layers (e.g., by thermal oxidation or chemical vapor oxidation deposition) are additive and, when combined, can cause the SOI structure to bow and / or warp out of specification.

[0023] In some processes, stress in the deposited semiconductor charge trapping layer (or "semiconductor layer") can be controlled by a post-deposition annealing step that allows interstitial atoms in the semiconductor layer to diffuse from the grain boundaries. This creates tensile stress in the semiconductor layer that can favorably offset the compressive stress resulting from the buried oxide layer, facilitating minimizing overall wafer bow and warpage. Typically, the semiconductor layer is annealed at temperatures higher than those used for the semiconductor layer deposition, such as temperatures above 1000°C or even above 1050°C. However, extra thermal processing can introduce other defects into the handle substrate. For example, the high temperatures and time required for the out-diffusion of interstitial semiconductor atoms from the grain boundaries can cause crystallographic slippage defects in the handle substrate. The slippage defects render the handle substrate unsuitable for subsequent device fabrication, even after the bow and warpage issues are corrected. High resistivity handle substrates (e.g., handle substrates having a resistivity of at least about 500 ohm-cm) used in SOI structures and RF devices are particularly susceptible to crystallographic slip due to the lack of lattice and interstitial atoms (e.g., dopant atoms and / or interstitial oxygen atoms) that would otherwise strengthen the wafer.

[0024] Exemplary methods described herein include depositing a semiconductor charge trapping layer (or "semiconductor layer") on a single crystal semiconductor handle substrate and annealing the semiconductor layer at or near the deposition temperature (e.g., within 10°C, within 5°C, or within 1°C). Preferably, the exemplary methods described herein provide a semiconductor layer with tensile stress rather than compressive stress due to the diffusion of interstitials from the grain boundaries of the deposited semiconductor material induced by annealing the semiconductor layer. The tensile stress in the semiconductor layer offsets compressive stress later introduced by, for example, a dielectric layer bonded to and / or formed on the semiconductor layer, thereby controlling the overall curvature and bowing of the multilayer structure. Advantageously, annealing the semiconductor layer to create tensile stress, as performed according to the methods described herein, also reduces or eliminates undesirable defects that can occur in single crystal semiconductor handle wafers due to higher thermal treatments. For example, in various embodiments, the single crystal semiconductor handle wafer is a high resistivity wafer (e.g., having a resistivity greater than about 500 ohm-cm), and the exemplary methods described herein include intermittently annealing the semiconductor layer to cause out-diffusion of interstitials from grain boundaries at relatively low temperatures (e.g., less than 1000°C) to reduce or eliminate crystallographic slip defects that may otherwise occur in high resistivity wafers at higher annealing temperatures.

[0025] In the exemplary methods described herein, the semiconductor charge trapping layer (or "semiconductor layer") is suitably produced by two or more cycles of depositing a portion of the semiconductor layer, interrupting the deposition process, and annealing the deposited portion. Stated another way, deposition of the semiconductor layer is carried out by a cyclic process in which a portion of the semiconductor layer is deposited, deposition is interrupted by pausing the deposition gas flow, the portion of the semiconductor layer is annealed (preferably at or near the deposition temperature), and the next portion of the semiconductor layer is deposited on the previously annealed portion. Each portion of the semiconductor charge trapping layer may also be referred to herein as a "layer of semiconductor material." Thus, in the exemplary methods, the semiconductor layer is produced by depositing a first layer of semiconductor material, annealing the first layer of semiconductor material, depositing a second layer of semiconductor material on the annealed first layer, annealing the second layer of semiconductor material, etc. By depositing the semiconductor layer in this manner, the semiconductor layer can include two or more annealed layers, such as, for example, three or more annealed layers of semiconductor material, or three to about 50 annealed layers, or three to about 40 annealed layers, or three to about 30 annealed layers, or three to about 25 annealed layers, or three to about 20 annealed layers, or three to about 10 annealed layers of semiconductor material. Multiple layers of semiconductor material can be deposited and annealed to create the semiconductor charge trapping layer, which is limited in part by throughput requirements and the minimum practical layer thickness that can be deposited, which can be about 20 nanometers. In some embodiments, the thickness of each annealed layer of semiconductor material (i.e., each portion of the semiconductor charge trapping layer) can be 0.05 micrometers (μm) to 5 μm, e.g., 0.1 μm to 1 μm, and the semiconductor charge trapping layer can have a thickness of 0.1 μm to 50 μm, e.g., 1 μm to 10 μm. The thickness of each portion of the semiconductor charge trapping layer may depend on the desired thickness of the charge trapping layer and the number of cycles performed to produce the charge trapping layer. Each deposited portion of the semiconductor charge trapping layer is suitably annealed at or near the deposition temperature, the annealing being performed to out-diffuse interstitials from the grain boundaries of the deposited layer of semiconductor material.It has been observed that intermittent annealing of portions of the semiconductor layer at or near the deposition temperature contributes to significant improvements in site flatness, which can be measured as the site frontside reference least squares focal plane coverage (SFQR). Furthermore, intermittent annealing during deposition can reduce or eliminate the need for post-deposition annealing of the semiconductor layer at higher temperatures. This shortens processing times otherwise associated with increased temperatures for post-deposition anneals, thereby improving overall efficiency and throughput.

[0026] The methods described herein can also facilitate controlled bowing and warping of semiconductor-on-insulator structures, such as silicon-on-insulator structures, that include a dielectric layer of a single-crystal semiconductor donor substrate bonded to a semiconductor charge trapping layer of a handle substrate. The dielectric layer may be formed as a semiconductor oxide film (e.g., a silicon oxide film) on the front surface of the donor substrate (e.g., a single-crystal silicon donor substrate). Due to the difference in thermal expansion coefficients between silicon oxide and silicon, for example, high intrinsic compressive stress occurs in oxide films on silicon wafers. In embodiments in which the dielectric oxide film is contributed by oxide on the surface of the donor structure, the final semiconductor-on-insulator structure contains only oxide from one wafer and is therefore deformed by compressive oxide stress. The tensile stress generated in the semiconductor layer offsets the compressive stress in the dielectric layer, thereby reducing the overall bowing and warping of the semiconductor-on-insulator structure. It has also been observed that polishing (e.g., by chemical-mechanical polishing) the semiconductor layer produced by the intermittent annealing according to the present disclosure results in greater tensile stress that contributes to the negative curvature of the handle substrate, further balancing the compressive stress induced by the dielectric layer, thereby reducing bowing and warpage of the final semiconductor-on-insulator structure.

[0027] Referring now to the drawings, a single crystal semiconductor substrate 100 for use in the exemplary methods described herein is shown in FIG. 3 . The substrate 100 can be used as a semiconductor handle substrate, e.g., a single crystal semiconductor handle wafer. The substrate 100 can also be used as a semiconductor donor substrate, e.g., a single crystal semiconductor donor wafer (e.g., donor substrate 200 shown in FIG. 5 ). As the description progresses, the terms “substrate” and “wafer” can be used interchangeably. Generally, the substrate 100 includes two major, generally parallel surfaces. One of the parallel surfaces is a front surface 102 of the substrate, and the other parallel surface is a rear surface 104 of the substrate. The substrate 100 also includes a peripheral edge 106 connecting the front surface 102 and the rear surface 104, a bulk region 108 between the front surface 102 and the rear surface 104, and a central plane C between the front surface 102 and the rear surface 104. P The substrate 100 has a central plane C P Virtual central axis C is substantially perpendicular to A The radial length of the substrate 100 is defined by the central axis C A The diameter of the substrate 100 is measured as the distance between the front surface 102 and the periphery 106. The diameter of the substrate 100 is measured across the periphery 106. In addition, a semiconductor substrate 100, such as a silicon wafer, typically has some total thickness variation (TTV), warp, and curvature, so that the midpoints between all points on the front surface 102 and all points on the back surface 104 may not lie exactly in a plane. However, as a practical matter, the TTV, warp, and curvature are typically very slight, so that, as an approximation, the midpoints lie on an imaginary center plane C that is approximately equidistant between the front surface 102 and the back surface 104. P You can say it goes inside.

[0028] Prior to any operations as described herein, the front surface 102 and the back surface 104 of the substrate 100 may be substantially identical. The surfaces 102 or 104 are referred to as the "front surface" or "back surface," respectively, merely for convenience and to generally distinguish the surfaces on which the operations of exemplary methods are performed. In the context of the present disclosure, the front surface 102 of a monocrystalline semiconductor handle substrate 100, e.g., a monocrystalline silicon handle wafer, refers to the major surface of the substrate 100 that will be the inner surface of a bonded structure or a semiconductor-on-insulator structure (e.g., those shown in Figures 6 and 7). On this front surface 102, a charge trapping layer 110 is formed (shown in Figure 4). Accordingly, the back surface 104 of the monocrystalline semiconductor handle substrate 100 refers to the major surface that will be the outer surface of a bonded structure or a semiconductor-on-insulator structure.

[0029] In some embodiments, the front surface 102 of the monocrystalline semiconductor substrate 100 can include a dielectric layer, e.g., a silicon dioxide layer, that will form a buried oxide (BOX) layer in the final structure. For example, if the substrate 100 is a monocrystalline semiconductor donor substrate 200 (shown in FIG. 5 ), a dielectric layer 210 can be formed on the front surface 202 of the donor substrate 200, which will form a BOX layer in the final structure. The back surface 204 of the monocrystalline semiconductor donor substrate 200, e.g., a monocrystalline silicon donor wafer, refers to the major surface that will be the exterior surface of a bonded structure or a semiconductor-on-insulator structure (e.g., those shown in FIGS. 6 and 7 ). As discussed above for the substrate 100, the substrate 200 shown in FIG. 5 also includes a peripheral edge 206 connecting the front surface 202 and the back surface 204, a bulk region 208 between the front surface 202 and the back surface 204, and a central plane C between the front surface 202 and the back surface 204. P2 and the central plane C P2 Virtual central axis C is substantially perpendicular to A2 The radial length of the substrate 200 is A2and the periphery 206, and the diameter of the substrate 200 is measured across the periphery 206. Upon completion of the bonding and wafer thinning operations described in further detail below, the single crystal semiconductor donor substrate 200 forms the semiconductor device layer 402 of a semiconductor-on-insulator (e.g., silicon-on-insulator) composite structure 400 (shown in FIG. 7).

[0030] The monocrystalline semiconductor handle substrate 100 and the monocrystalline semiconductor donor substrate 200 may be monocrystalline semiconductor wafers. In various embodiments, the semiconductor wafers comprise a semiconductor material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Monocrystalline semiconductor wafers, such as the monocrystalline silicon handle wafer 100 and the monocrystalline silicon donor wafer 200, typically have a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm. The thickness of the wafer may vary within a range of about 250 μm to about 1500 μm, such as about 300 μm to about 1000 μm, and preferably about 500 μm to about 1000 μm. In some specific embodiments, the thickness of the wafer may be about 775 μm. The thickness of the wafer is measured as the distance between opposing major surfaces, for example, the distance between the front surface 102, 202 and the rear surface 104, 204.

[0031] In a specific embodiment, the monocrystalline semiconductor handle substrate 100 and the monocrystalline semiconductor donor substrate 200 comprise monocrystalline silicon wafers sliced ​​from monocrystalline ingots grown according to the Czochralski crystal growth method or the float zone growth method. Such methods, as well as silicon slicing, lapping, etching, and polishing techniques, are disclosed, for example, in F. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, 1989, and Silicon Chemical Etching (edited by J. Grabmaier), Springer-Verlag, NY, 1982, the entire disclosures of which are incorporated herein by reference. Preferably, the wafers are polished and cleaned by methods known to those skilled in the art. See, for example, WCO'Mara et al., Handbook of Semiconductor Silicon Technology, Noyes Publications. The wafers may also be cleaned, for example, in an SC1 / SC2 solution. Preferably, both the monocrystalline silicon handle wafer 100 and the monocrystalline silicon donor wafer 200 have a mirror-polished front surface finish free of surface defects such as scratches and large particles.

[0032] In some embodiments, the single crystal semiconductor handle substrate 100 and the single crystal semiconductor donor substrate 200 have a concentration of interstitial oxygen typically achieved by Czochralski growth. In some embodiments, the substrates 100 and 200 have a concentration of interstitial oxygen between about 4 ppmA and about 18 ppmA. In some embodiments, the substrates 100 and 200 have a concentration of interstitial oxygen between about 10 ppmA and about 35 ppmA. Preferably, the substrates 100 and 200 have a concentration of interstitial oxygen of about 10 ppmA or less. Interstitial oxygen can be measured according to SEMI MF 1188-1105.

[0033] In some embodiments, a single crystal semiconductor handle substrate 100, such as a single crystal silicon handle wafer, has a relatively high minimum bulk resistivity. The single crystal semiconductor donor substrate 200 can also have a relatively high minimum bulk resistivity. High-resistivity single crystal semiconductor substrates are typically sliced ​​from single crystal ingots grown by the Czochralski or float-zone methods. Single crystal semiconductor conductor substrates sliced ​​from Czochralski-grown ingots can be subjected to thermal annealing at temperatures ranging from about 600°C to about 1000°C to eliminate thermal donors caused by oxygen incorporated during crystal growth. In some embodiments, the single crystal semiconductor wafer has a minimum bulk resistivity of at least about 500 ohm-cm, at least about 1000 ohm-cm, or even at least about 3000 ohm-cm, e.g., from about 500 ohm-cm to about 100,000 ohm-cm, from about 1000 ohm-cm to about 100,000 ohm-cm, from about 500 ohm-cm to about 10,000 ohm-cm, from about 750 ohm-cm to about 10,000 ohm-cm, from about 1000 ohm-cm to about 10,000 ohm-cm, from about 2000 ohm-cm to about 10,000 ohm-cm, from about 3000 ohm-cm to about 10,000 ohm-cm, or from about 3000 ohm-cm to about 5000 ohm-cm. Methods for making high resistivity wafers are known in the art, and such high resistivity wafers are available from commercial suppliers such as GlobalWafers Co., Ltd. of Taiwan.

[0034] In some embodiments, the rear surface 104, 204 of the single crystal semiconductor substrate 100, 200 may be intentionally damaged by a sandblasting process or caustic etching, hi other embodiments, the rear surface 104, 204 of the substrate 100, 200 is a polished surface that is free of surface defects such as scratches and large particles.

[0035] The front surface 102, and optionally the back surface 104, of the monocrystalline semiconductor handle substrate 100 can be treated, for example, by an oxidation process, to form an interface layer prior to the formation of the charge trapping layer 110. The interface layer can comprise a material selected from silicon dioxide, silicon nitride, and silicon oxynitride. In certain embodiments, the interface layer may comprise silicon dioxide. To form a silicon dioxide interface layer, the front surface 102 of the substrate 100 is oxidized prior to the formation of the charge trapping layer 110 so that the front surface 102 comprises an oxide film. The oxidation of the front surface 102 can be achieved by thermal oxidation (in which some portion of the deposited semiconductor material film is consumed), CVD oxide deposition, and / or atomic layer deposition. In some embodiments, the monocrystalline semiconductor handle substrate 100, e.g., a monocrystalline silicon handle wafer, can be thermally oxidized in a furnace such as ASM A400 or ASM A412. The temperature can range from 750°C to 1200°C in an oxidizing ambient. The oxidizing ambient atmosphere may be a mixture of an inert gas, such as Ar or N2, and O2. The oxygen content may vary from 1 to 10%, or more. In some embodiments, the oxidizing ambient atmosphere may be up to 100% oxygen ("dry oxidation"). In some embodiments, the oxidizing ambient atmosphere may include oxygen and ammonia, which are suitable for depositing silicon oxynitride. In some embodiments, the ambient atmosphere may include a mixture of an inert gas, such as Ar or N2, and an oxidizing gas, such as O2 and water vapor ("wet oxidation"). In some embodiments, the ambient atmosphere may include a mixture of an inert gas, such as Ar or N2, and an oxidizing gas, such as O2 and water vapor ("wet oxidation"), and a nitriding gas, such as ammonia. In some embodiments, the ambient atmosphere may include a mixture of an inert gas, such as Ar or N2, and a nitriding gas, such as ammonia, which are suitable for depositing silicon nitride. In an exemplary embodiment, the single-crystal semiconductor handle substrate 100 can be loaded into a vertical furnace, such as ASM A400 or ASM A412. The temperature is raised to the oxidation temperature using a mixture of N2 and O2. At the desired temperature, water vapor can be introduced into the gas flow. After the desired oxide thickness is achieved, the water vapor and O2 are turned off, the furnace temperature is reduced, and the substrate 100 is removed from the furnace.The oxide layer on the front surface 102, the back surface 104, or both, may be between about 100 angstroms and about 100,000 angstroms.

[0036] In some embodiments, the oxide layer may be relatively thin, such as about 5 Å to about 25 Å, e.g., about 10 Å to about 15 Å. A thin oxide layer can be obtained on both sides of a semiconductor wafer by exposure to an aqueous solution containing an oxidizing agent, such as SC1 and / or SC2 cleaning solutions. In some embodiments, the SC1 solution includes 5 parts deionized water, 1 part aqueous HOH (ammonium hydroxide, 29% by weight NH), and 1 part aqueous H0 (hydrogen peroxide, 30%). In some embodiments, the substrate 100 may be oxidized by exposure to an aqueous solution containing an oxidizing agent, such as an SC2 solution. In some embodiments, the SC2 solution includes 5 parts deionized water, 1 part aqueous HCl (hydrochloric acid, 39% by weight), and 1 part aqueous H0 (hydrogen peroxide, 30%).

[0037] In some embodiments, the exposed front surface 102 of the single crystal semiconductor handle substrate 100 is not oxidized prior to the formation of the charge trapping layer 110 .

[0038] Prior to the formation of the charge trapping layer 110, and optionally after oxidation of the front surface 102 of the monocrystalline semiconductor handle substrate 100, the monocrystalline semiconductor handle substrate 100 may be subjected to a pretreatment operation that includes exposing the surfaces 102, 104 to an ambient atmosphere containing a reducing agent and / or an etching agent. Exposure to an ambient atmosphere containing a reducing agent and / or an etching agent can advantageously clean the front surface 102, and optionally the rear surface 104, of the substrate 100, which may include an interfacial oxide front surface layer, and texture the front surface 102 for subsequent semiconductor material deposition. Handling the substrate 100 can result in the undesired deposition of organic contaminants and contaminants such as boron, aluminum, phosphorus, etc. on the front surface 102 and rear surface 104 of the handle substrate 100. The contaminants can disrupt the nucleation process of the subsequently deposited charge trapping layer 110 or become undesired dopants in the handle substrate 100 that change the resistivity of the substrate 100 and / or the charge trapping layer 110. This can result in increased distortion and power loss of high frequency signals. These contaminants can be cleaned or otherwise removed by exposing the surfaces 102, 104 of the substrate 100 to an ambient atmosphere containing reducing and / or etching agents. For example, reducing agents such as hydrogen can react with common contaminants such as boron oxide and aluminum oxide, while etching gases such as chlorine or hydrogen chloride react with aluminum, boron, and phosphorus to form volatile chloride products that are carried away from the surface 102 of the substrate 100 by hydrogen gas.

[0039] The presence of semiconductor oxides, such as silicon oxides, on the surfaces 102, 104 of the single-crystal semiconductor handle substrate 100 can cause carbon atoms in organic contaminants to replace semiconductor atoms, forming carbon monoxide, which is purged from the surfaces 102, 104 by the hydrogen carrier gas. Performing a cleaning and etching operation prior to the deposition of the semiconductor material can be advantageous for obtaining a pure and highly efficient charge trapping layer 110. Additionally, the cleaning and etching process can open holes in the interfacial oxide pre-surface layer to form a textured oxide structure, thus exposing the pre-surface 102 to precursors during the deposition of the charge trapping layer 110. The density and size of the holes in the textured oxide pre-surface layer can be controlled by the temperature, time, and gas flow during the cleaning and etching operation. For example, the size of the holes can be controlled within a range of about 5 nanometers to about 1000 nanometers, e.g., about 5 nanometers to about 500 nanometers, or about 5 nanometers to about 200 nanometers, which allows for control of the grain size of the semiconductor material and the film stress of the charge trapping layer 110. The open pores in the interfacial oxide front surface layer provide nucleation sites for the charge trapping layer 110. The textured oxide front surface layer can be controlled to achieve a uniform density of open pores across the front surface 102 without removing the entire oxide front surface layer. The residual oxide can improve the thermal stability of the charge trapping layer 110. For example, during subsequent thermal processes in semiconductor-on-insulator structure and RF device fabrication, the charge trapping layer 110, which preferably includes a polycrystalline or amorphous structure, can transition to a single-crystal structure through recrystallization promoted by direct contact between the polycrystalline or amorphous semiconductor particles and the monocrystalline (i.e., single crystal) semiconductor handle substrate 100. The residual oxide at the interface between the semiconductor charge trapping layer 110 and the front surface 102 of the substrate 100 can effectively prevent the recrystallization process and thus prevent the charge trapping layer 110 from transitioning to a single-crystal structure that does not have charge trapping function.

[0040] The cleaning and etching operations can advantageously be performed in the same chamber, e.g., a CVD reaction chamber, in which the deposition of the charge trapping layer 110 is performed. As described above, the reducing atmosphere can include an etchant to further enhance the cleaning operation. For example, the ambient atmosphere for cleaning can include hydrogen, hydrogen chloride, chlorine, or any combination of hydrogen, hydrogen chloride, and chlorine. Additionally, cleaning can be performed at elevated temperatures, such as above about 850°C, e.g., from about 850°C to about 1100°C, or from about 850°C to about 1000°C. The pressure in the chamber can be atmospheric or reduced, e.g., from about 1 Torr to about 760 Torr, e.g., from about 1 Torr to about 400 Torr. At the desired temperature for cleaning, the substrate can be exposed to the ambient atmosphere containing hydrogen, hydrogen chloride, chlorine, or any combination of hydrogen, hydrogen chloride, and chlorine for a period of about 1 second to about 300 seconds, e.g., from about 5 seconds to about 60 seconds, or from about 10 seconds to about 40 seconds.

[0041] After suitable operations have been performed to prepare and process the front surface 102 of the monocrystalline semiconductor handle substrate 100, a semiconductor material is deposited on the exposed front surface 102 of the substrate 100. The deposition of the semiconductor material produces a charge trapping layer 110 on the front surface 102 of the substrate 100 (shown in FIG. 4 ). The charge trapping layer 110 may also be referred to herein as a semiconductor charge trapping layer 110 or a semiconductor layer 110.

[0042] Semiconductor materials suitable for use in forming the charge trapping layer 110 are preferably capable of forming a highly defective layer between the monocrystalline semiconductor substrate 100 and a dielectric layer (e.g., dielectric layer 210, described below) subsequently bonded and / or formed on the charge trapping layer 110. Such semiconductor materials include polycrystalline and amorphous semiconductor materials. Semiconductor materials that may be polycrystalline or amorphous include, for example, silicon (Si), silicon germanium (SiGe), silicon doped with carbon or silicon carbide (SiC), and germanium (Ge). Silicon germanium includes alloys of silicon germanium in any molar ratio of silicon to germanium. For example, when the semiconductor material includes silicon germanium, the mole percent of germanium can be at least about 1 mole%, at least about 5 mole%, at least about 20 mole%, at least about 50 mole%, at least about 90 mole%, or at least about 99.9 mole%. Carbon-doped silicon includes compounds of silicon and carbon in which the molar ratio of silicon to carbon can vary. As used herein, the term "polycrystalline" refers to a semiconductor material containing small semiconductor crystals with random crystal orientation. For example, polycrystalline silicon grains may be as small as about 20 nanometers in size. The smaller the grain size of the deposited polycrystalline semiconductor material, the higher the defects in the charge trapping layer 110. The term "amorphous" refers to a non-crystalline allotropic form of semiconductor material that lacks short- and long-range order. Silicon grains with crystallinity ranging from about 10 nanometers or less may also be considered essentially amorphous silicon.

[0043] The charge trapping layer 110 preferably has a resistivity of at least about 1000 ohm-cm, or at least about 3000 ohm-cm, for example, from about 1000 ohm-cm to about 100,000 ohm-cm, from about 1000 ohm-cm to about 10,000 ohm-cm, from about 2000 ohm-cm to about 10,000 ohm-cm, from about 3000 ohm-cm to about 10,000 ohm-cm, or from about 3000 ohm-cm to about 5000 ohm-cm.

[0044] The semiconductor material for deposition on the front surface 102 of the monocrystalline semiconductor handle substrate 100 may be deposited by means known in the art to produce the charge trapping layer 110. For example, the semiconductor material may be deposited using metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). Silicon precursors for LPCVD or PECVD include, among others, methylsilane, silicon tetrahydride (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), silicon tetrachloride (SiCl4). For example, polycrystalline silicon may be deposited on the surface oxide layer by pyrolyzing silane (SiH) at a temperature ranging from about 550°C to about 690°C, e.g., from about 580°C to about 650°C. The chamber pressure may be in the range of about 70 to about 400 mTorr. In some embodiments, deposition may be performed at subatmospheric pressure, e.g., from about 1 Torr to about 760 Torr, from about 10 Torr to about 760 Torr, or from about 1 Torr to about 400 Torr. Amorphous silicon can generally be deposited by plasma enhanced chemical vapor deposition (PECVD) at temperatures ranging from about 75°C to about 300°C. Silicon germanium, particularly amorphous silicon germanium, may be deposited at temperatures up to about 300°C by chemical vapor deposition using organogermanium compounds such as isobutylgermane, alkylgermanium trichloride, and dimethylaminogermanium trichloride. Carbon-doped silicon can be deposited by thermal plasma chemical vapor deposition in an epitaxial reactor using precursors such as silicon tetrachloride and methane. Suitable carbon precursors for CVD or PECVD include methylsilane, methane, ethane, and ethylene, among others. For LPCVD deposition, methylsilane is a particularly preferred precursor because it provides both carbon and silicon. For PECVD deposition, preferred precursors include silane and methane.In some embodiments, the silicon layer may include a carbon concentration of at least about 1% on an atomic basis, e.g., from about 1% on an atomic basis to about 10% on an atomic basis. Precursor gases for depositing semiconductor materials may be mixed with a carrier gas such as hydrogen (e.g., trichlorosilane in hydrogen for depositing polycrystalline silicon). The concentration of the precursor gas can be determined based on the desired deposition effect (e.g., deposition rate).

[0045] In one particular embodiment, the charge trapping layer 110 is formed by the deposition of a polycrystalline semiconductor material. The charge trapping layer 110 may also be referred to herein as a polycrystalline semiconductor charge trapping layer 110 or a polycrystalline semiconductor layer 110.

[0046] In some embodiments, deposition of the semiconductor material to produce the charge trapping layer 110 is performed in an atmospheric reactor, such as might typically be used for epitaxial deposition on the exposed outer layer of a semiconductor-on-insulator structure. For example, deposition of the semiconductor material can be performed in an ASM E3000 epi-reactor, which includes a gas panel for supplying the necessary process gases (e.g., H2, HCl, dichlorosilane, and / or trichlorosilane) at desired flow rates to a quartz reaction chamber. The quartz reaction chamber may be rectangular in cross section and includes a silicon carbide-coated graphite susceptor that supports the substrate 100 during processing. The susceptor can rotate the substrate 100 and has a recess or pocket of a size suitable for supporting the substrate 100 (e.g., a 300 mm wafer). The substrate 100 sits within a recess in the susceptor during processing and is supported on its backside by a ledge within the recess that contacts the substrate 100 at a height that holds the front surface 102 of the substrate 100 close to (e.g., within a few millimeters of) the peripheral edge 106 of the substrate 100 and slightly above the upper surface of the susceptor. The area of ​​the susceptor below the substrate 100 and within the susceptor's support ledge may be perforated to allow ventilation of the rear surface 104 of the substrate 100 that faces the susceptor. The substrate 100 may be delivered to a reaction chamber by a robot that handles the substrate 100 without substantially introducing contamination or causing damage to the surfaces 102, 104 of the substrate. The reaction chamber is positioned adjacent to a heating element (e.g., a flat lamp bank), which is nominally parallel to, or may be above or below, the substrate 100 and susceptor, and heats the substrate 100 and susceptor to the desired process temperature. The desired gas flow rates, susceptor rotation speed, and temperature are typically varied at various times throughout the process. Variations in process parameters such as gas flow rates, rotation speed, temperature, and wafer loading and unloading are controlled by computer automation based on predetermined "recipe" developed to produce a substrate 100 with desired properties upon completion of processing.Desired characteristics for controlling process parameters include crystallographic slip in the high-resistivity substrate 100, resistivity, deposited film thickness (e.g., the thickness of the semiconductor layer 110), film quality parameters such as the resistivity of the semiconductor layer 110, semiconductor material grain size, surface roughness, post-deposition wafer flatness (e.g., site flatness, often characterized by SFQR parameters), and other characteristics. An exemplary epitaxial reactor suitable for depositing the semiconductor layer 110 is the Epsilon E3000 single-wafer epitaxial reactor manufactured by ASM International. Other reactor chambers include those marketed by Applied Materials under the Centura trade name. Advantageously, performing semiconductor layer deposition in these reactors may enable several different processes used in semiconductor-on-insulator and RF device fabrication to be performed on the same processing tool (e.g., semiconductor charge trapping layer deposition, post-cleave top semiconductor device layer smoothing by vapor-phase etching with HCl, top semiconductor device layer thickening by epitaxial deposition, and standard blanket epitaxial layer deposition).

[0047] The reaction chamber within which deposition of semiconductor layer 110 is performed may be at any suitable pressure (e.g., atmospheric) during deposition. For example, deposition may be performed at subatmospheric pressure, such as from about 1 Torr to about 760 Torr, from about 10 Torr to about 760 Torr, or from about 1 Torr to about 400 Torr. Deposition time may vary depending on the deposition temperature, concentration, and desired thickness of semiconductor layer 110. In some embodiments, semiconductor layer 110 is at least about 0.1 μm thick, or at least about 0.5 μm, at least about 1 μm, at least about 2.5 μm, or at least about 4 μm thick (e.g., from about 0.1 μm to about 50 μm, from about 0.25 μm to about 20 μm, or from about 1 μm to about 10 μm).

[0048] The semiconductor material used to form the semiconductor charge trapping layer 110 may be deposited at any suitable temperature based on the semiconductor material being deposited, the deposition method, and other considerations, and the deposition temperature may be selected to enhance or promote certain properties of the semiconductor layer 110. For example, the deposition temperature of the semiconductor material may be suitable for increasing the surface area of ​​the semiconductor layer 110. In some embodiments, the semiconductor layer 110 is deposited at a temperature suitable for reducing the grain size of the deposited semiconductor material. As described above, the semiconductor layer 110 may be deposited using chemical or physical vapor deposition methods, such as metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the semiconductor layer 110 comprises polycrystalline silicon deposited by CVD, and suitable silicon precursors for CVD include methylsilane, silicon tetrahydride (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and silicon tetrachloride (SiCl4), among others. For example, silicon precursors for depositing polycrystalline silicon by CVD can be selected from silane, dichlorosilane (SiH2Cl2), and trichlorosilane (SiHCl3). In embodiments where a silicon precursor is used to deposit polycrystalline silicon, the polycrystalline silicon may be deposited at a temperature of about 800°C to about 1150°C. In some embodiments, the deposition temperature of the polycrystalline semiconductor layer 110 is less than about 1125°C, less than about 1100°C, less than about 1075°C, less than about 1050°C, less than about 1000°C, or less than about 900°C, or a temperature between about 800°C and about 1150°C, between about 800°C and about 1100°C, or between about 850°C and about 1000°C. The temperature can also contribute to a high growth rate, thereby contributing to throughput and cost reduction. The CVD deposition rate can be at least about 0.1 micrometers / minute, for example, between about 0.1 micrometers / minute and about 10 micrometers / minute, or between about 0.1 micrometers / minute and about 2 micrometers / minute.It will be appreciated that the deposition temperature for a particular precursor gas, which depends on whether the semiconductor material comprises, for example, polycrystalline or amorphous silicon, SiGe, SiC, or Ge, can be selected based on known suitable temperatures (e.g., according to published methods).

[0049] In an exemplary method for producing the semiconductor layer 110, deposition of the semiconductor material is temporarily interrupted at least once, and preferably multiple times. Between deposition stages to produce the semiconductor layer 110, the supply of precursor gases to the reaction chamber is temporarily paused, and the previously deposited semiconductor material is annealed at or near deposition conditions (e.g., at or near the deposition temperature and pressure). After the temporary anneal, the supply of precursor gases to the reaction chamber is resumed for the next deposition stage. Thus, the semiconductor layer 110 is suitably produced by two or more cycles of depositing a portion of the semiconductor layer 110, interrupting the deposition process, and annealing the deposited portion. In other words, deposition of the semiconductor layer 110 is performed by a cyclic process in which a portion of the semiconductor layer 110 is deposited, deposition is interrupted by temporarily stopping the precursor gas flow, a portion of the semiconductor layer 110 is annealed, and the next portion of the semiconductor material 110 is deposited on the previously annealed portion. Each portion of the semiconductor charge trapping layer 110 may also be referred to herein as a "layer of semiconductor material." Thus, in an exemplary method, semiconductor layer 110 is produced by depositing a first layer of semiconductor material, annealing the first layer of semiconductor material, depositing a second layer of semiconductor material on the annealed first layer, annealing the second layer of semiconductor material, etc. By depositing semiconductor layer 110 in this manner, semiconductor layer 110 can include two or more annealed layers of semiconductor material, such as, for example, three or more annealed layers, or three to about 50 annealed layers, or three to about 40 annealed layers, or three to about 30 annealed layers, or three to about 25 annealed layers, or three to about 20 annealed layers, or three to about 10 annealed layers of semiconductor material. The number of annealed layers of semiconductor material that produce semiconductor layer 110 is equal to the number of cycles of depositing portions of semiconductor layer 110, interrupting the deposition process, and annealing the deposited portions that are performed. Thus, two cycles will produce two annealed layers of semiconductor material, three cycles will produce three annealed layers, ten cycles will produce ten annealed layers, and so on.Multiple layers of semiconductor material can be deposited and annealed to create the semiconductor charge trapping layer 110, limited in part by throughput requirements and the minimum practical layer thickness that can be deposited, which may be approximately 20 nanometers.

[0050] The duration of each cycle of depositing a portion of the semiconductor layer 110 and interrupting the deposition process to anneal the deposited portion can depend on the desired thickness of each annealed layer of semiconductor material. In some embodiments, the thickness of each deposited layer of semiconductor material may be at least about 0.1 μm, at least about 0.2 μm, or at least about 0.5 μm, e.g., about 0.05 μm to about 5 μm, about 0.1 μm to about 5 μm, or about 0.1 μm to about 1 μm. The deposited layers of semiconductor material may have the same thickness, or the thickness may vary between layers. The duration of depositing each layer of semiconductor material for each cycle may be about 1 second to about 60 seconds, e.g., about 1 second to about 15 seconds, about 1 second to about 10 seconds, about 10 seconds to about 30 seconds, about 15 seconds to about 30 seconds, about 15 seconds to about 20 seconds, about 20 seconds to about 30 seconds, or about 30 seconds to about 45 seconds. The duration for annealing each deposited layer of semiconductor material for each cycle may be from 1 second to about 60 seconds, e.g., from about 1 second to about 15 seconds, from about 1 second to about 10 seconds, from about 10 seconds to about 30 seconds, from about 15 seconds to about 30 seconds, from about 15 seconds to about 20 seconds, from about 20 seconds to about 30 seconds, or from about 30 seconds to about 45 seconds. The thickness of each layer of semiconductor material is selected based on the desired number of cycles used to produce semiconductor layer 110 and the desired thickness of semiconductor layer 110. In some embodiments, semiconductor layer 110 is at least about 0.1 μm thick, or at least about 0.5 μm, at least about 1 μm, at least about 2.5 μm, or at least about 4 μm thick (e.g., from about 0.1 μm to about 50 μm, from about 0.25 μm to about 20 μm, or from about 1 μm to about 10 μm). The total duration of annealing the layer of semiconductor material is known as a suitable annealing time at a given temperature for out-diffusing interstitials from grain boundaries in semiconductor layer 110 having a given thickness, or can be empirically determined as the annealing time, distributed across cycles according to the thickness of the layer of material deposited in each cycle. For example, the annealing time can be distributed equally across cycles where the cycles produce layers of semiconductor material of approximately equal thickness. Thus, if a total annealing time of approximately 140 seconds is determined to be suitable for semiconductor layer 110 produced by seven cycles of depositing and annealing layers of semiconductor material having approximately equal thicknesses, each cycle would include an anneal of approximately 20 seconds.

[0051] Each layer of semiconductor material deposited and annealed to produce semiconductor layer 110 is deposited at a deposition temperature and annealed at an annealing temperature. As described above, deposition is interrupted by stopping the flow of precursor gases into the reaction chamber. After deposition is interrupted, the previously deposited layer of semiconductor material is annealed in the ambient atmosphere of the reaction chamber, which may include hydrogen, hydrogen chloride, and / or chlorine gas. The annealing operations performed throughout the cyclic process preferably produce a semiconductor layer 110 that has tensile stress rather than compressive stress. Otherwise, compressive stress may develop in the semiconductor layer 110 during deposition of the semiconductor material. Each annealing operation may be performed at reduced or atmospheric pressure, for example, from about 1 Torr to about 760 Torr, or from about 10 Torr to about 760 Torr. Preferably, once deposition of the semiconductor material is interrupted, the temperature is not intentionally increased in the reaction chamber so that the annealing temperature is substantially the same as or close to the deposition temperature. The annealing temperature may be preferably within about 10°C, about 5°C, or about 1°C of the deposition temperature. It will be understood that some incidental temperature change may occur when the supply of precursor gas is stopped, for example, due to the temperature difference between the precursor gas and the ambient atmosphere during annealing. In other embodiments, a slight increase or decrease in temperature may be intentionally introduced between the deposition temperature and the annealing temperature, for example, by varying the heat supplied to a heating element positioned adjacent to the reaction chamber. At least one of the deposition temperature and the annealing temperature, or both, may be the same for each cycle performed to produce the semiconductor layer 110, or the deposition temperature and / or the annealing temperature may vary from cycle to cycle. Preferably, the deposition temperature and the annealing temperature for each cycle are relatively low, less than about 1100°C, less than about 1050°C, or less than about 1000°C, respectively. The deposition temperature and the annealing temperature may also be greater than about 800°C, greater than about 850°C, or greater than about 900°C, respectively.For example, the deposition temperature and annealing temperature for each cycle may be from about 800°C to about 1100°C, e.g., from about 850°C to about 1000°C, from about 900°C to about 1000°C, from about 925°C to about 975°C, from about 925°C to about 950°C, or from about 950°C to about 1000°C.

[0052] Each annealing operation in each cycle is performed to generate tensile film stress in the layer of semiconductor material, i.e., the portion of the semiconductor layer 110, deposited during the respective cycle. That is, each annealing operation converts compressive stress induced during deposition of the layer of semiconductor material into tensile stress through the out-diffusion of interstitials from the grain boundaries of the semiconductor material. Distributing annealing operations over multiple cycles during the deposition process can facilitate improved out-diffusion of interstitials from the grain boundaries of the semiconductor layer 110 compared to an annealing operation performed for the same total duration and at the same temperature, but after the entire layer 110 has been deposited. This is because the annealing is performed on a relatively thin layer of deposited, pre-annealed semiconductor material, reducing the distance the interstitials must travel to out-diffuse from the grain boundaries of the deposited semiconductor material. Therefore, the time required for out-diffusion of interstitials due to annealing at a given temperature is reduced. In addition to the tensile stress in the semiconductor layer 110, each annealing operation can result in other desired properties, such as high purity of the semiconductor material, high resistivity, desired nuclei size and uniformity, and a clean exposed surface of the semiconductor layer 110. Additionally, performing the annealing operation at a relatively low temperature reduces or eliminates defects in the high resistivity substrate 100, such as crystallographic slip defects that can be induced by higher temperature anneals.

[0053] A semiconductor seed layer can be deposited on the front surface 102 of the substrate 100 and annealed prior to the cyclic process to deposit the semiconductor layer 110. The semiconductor seed layer is used to promote the growth of subsequent layers of semiconductor material and to improve the charge trapping efficiency of the semiconductor layer 110. Thus, the semiconductor layer 110 can include a semiconductor seed layer and a layer of semiconductor material deposited and annealed during the cyclic process described above. The semiconductor seed layer can include one or more semiconductor materials, such as silicon, SiGe, SiC, and Ge. The semiconductor material used to create the semiconductor seed layer can be the same material as the subsequently deposited layer of semiconductor material or can be a different semiconductor material. For example, if a polycrystalline semiconductor layer 110 is deposited, the semiconductor seed layer can be a polycrystalline semiconductor seed layer. The polycrystalline semiconductor seed layer can include, for example, polycrystalline silicon, SiGe, SiC, and / or Ge. The semiconductor seed layer is preferably deposited and annealed in the same reaction chamber as the layer of semiconductor material deposited and annealed during the cyclic process.

[0054] The semiconductor seed layer preferably has a thickness less than that of the semiconductor layer 110. In some embodiments, the semiconductor seed layer can have a thickness approximately equal to that of each of the layers of semiconductor material deposited and annealed during the cyclic process. In some embodiments, the semiconductor seed layer may be deposited to a thickness of less than about 20 μm, less than about 10 μm, less than about 5 μm, less than about 3 μm, less than about 2 μm, less than about 1 μm, or less than about 0.5 μm, such as from about 50 nanometers (nm) to about 20 μm, or from about 50 nm to about 10 μm, or from about 50 nm to about 5 μm, or from about 50 nm to about 3 μm, or from about 50 nm to about 2 μm, or from about 50 nm to about 1 μm, or from about 50 nm to about 500 nm, or from about 50 nm to about 200 nm. The thickness of the semiconductor seed layer is determined by the size of the semiconductor nuclei. To achieve effective stress release, the semiconductor seed layer must cover the substrate surface while leaving a gap of less than approximately 50 nm, allowing hydrogen gas (H) access to the interface between the semiconductor seed layer and the oxide. Hydrogen gas reduces the interfacial oxide and promotes the diffusion of atoms at the grain boundaries of the semiconductor seed layer into the substrate 100, thus relieving film stress. If the semiconductor seed layer is thick enough to completely prevent H access to the interfacial oxide, the subsequent annealing process cannot effectively release film stress. On the other hand, if the semiconductor seed layer is not continuous and the opening area between two adjacent nuclei is larger than approximately 50 nm, large nuclei will form after the oxide layer is removed during the seed layer annealing process. These large nuclei will grow into large particles (i.e., diameters >1 μm) after the semiconductor layer 110 is deposited, which reduces capture efficiency.

[0055] The semiconductor seed layer is subjected to a high-temperature anneal, followed by a cyclic process to deposit and anneal each layer of semiconductor material. Annealing the semiconductor seed layer contributes to desirable charge trapping layer properties, such as a clean surface, a high-purity film, a high-resistivity film, desired nucleus size and uniformity, and reduced compressive film stress. In some embodiments, the semiconductor seed layer is subjected to a high-temperature anneal to generate tensile stress in the semiconductor seed layer. The temperature at which the semiconductor seed layer is deposited is generally higher than the annealing temperature of each layer of semiconductor material annealed during the cyclic process. For example, the semiconductor seed layer may be annealed at temperatures greater than about 1000°C, greater than about 1025°C, or greater than about 1050°C, e.g., from about 1000°C to about 1200°C, from about 1000°C to about 1100°C, from about 1025°C to about 1050°C, or from about 1050°C to about 1100°C. The semiconductor seed layer may be annealed for a duration of about 1 second to about 300 seconds, for example, about 5 seconds to about 60 seconds, or about 10 seconds to about 40 seconds. The semiconductor seed layer may be annealed in an ambient atmosphere, which may contain hydrogen, hydrogen chloride, chlorine, or any combination of hydrogen, hydrogen chloride, and chlorine. The semiconductor seed layer may be annealed at reduced or atmospheric pressure, for example, about 1 Torr to about 760 Torr, or about 10 Torr to about 760 Torr. The grain size and stress of the semiconductor seed layer are controlled by the annealing temperature, duration, and gas flow rate.

[0056] Because the semiconductor seed layer can be annealed at a relatively high temperature, the exemplary method described herein can include cooling the single-crystal semiconductor handle substrate 100 after annealing the semiconductor seed layer. For example, the exemplary method can include cooling the substrate 100 to a temperature less than about 1000 ° C after annealing the semiconductor seed layer and before performing a cyclic process to deposit a layer of semiconductor material, i.e., a portion of the semiconductor layer 110, and annealing the portion of the semiconductor layer 110. The cyclic process can then begin once the substrate 100 has cooled to the desired temperature.

[0057] In some embodiments, an oxide film may be formed on the deposited semiconductor layer 110. This may be accomplished by means known in the art, such as thermal oxidation (which consumes some portion of the deposited semiconductor material film), CVD oxide deposition, and / or atomic layer deposition. For example, the semiconductor layer 110 may be thermally oxidized in a furnace such as ASM A400 or ASM A412. The temperature may range from about 750°C to about 1200°C in an oxidizing ambient. The oxidizing ambient may be a mixture of an inert gas, such as Ar or N2, and O2. The oxygen content may vary from 1 to 10% or more. In some embodiments, the oxidizing ambient may be up to 100% oxygen ("dry oxidation"). In some embodiments, the oxidizing ambient may contain oxygen and ammonia, which is suitable for depositing silicon oxynitride. In some embodiments, the ambient may contain a mixture of an inert gas, such as Ar or N2, and an oxidizing gas, such as O2 and water vapor ("wet oxidation"). In some embodiments, the ambient atmosphere may include a mixture of an inert gas such as Ar or N2, an oxidizing gas such as O2 and water vapor ("wet oxidation"), and a nitriding gas such as ammonia. In some embodiments, the ambient atmosphere may include a mixture of an inert gas such as Ar or N2, and a nitriding gas such as ammonia suitable for depositing silicon nitride. A single-crystal semiconductor handle substrate 100 having a semiconductor layer 110 formed on its front surface 102 can be loaded into a vertical furnace such as ASM A400 or ASM A412. The temperature is raised to the oxidation temperature using a mixture of N2 and O2. At the desired temperature, water vapor can be introduced into the gas flow. After the desired oxide thickness is achieved, the water vapor and O2 are turned off, the furnace temperature is reduced, and the substrate 100 is removed from the furnace. In some embodiments, the semiconductor layer 110 may be oxidized for a duration sufficient to provide an oxide layer at least about 0.01 μm thick.

[0058] In some embodiments, the semiconductor layer 110 produced as described above is then planarized to reduce the surface roughness of the exposed surface of the semiconductor layer 110 and to optimize the warpage and curvature of the substrate 100 shown in FIG. 4 for subsequent operations in producing the semiconductor-on-insulator structure. For example, the semiconductor layer 110 may be subjected to a polishing operation, such as a chemical mechanical polishing ("CMP") operation. The semiconductor layer 110 may have a relatively rough surface. For example, the deposited semiconductor layer 110 may have an RMS 2x2μm2 The semiconductor layer 110 can have a surface roughness of about 50 nm as measured by RMS. 2x2μm2 and can be subjected to a polishing operation to reduce the surface roughness to a level of less than about 5 angstroms, e.g., about 1 angstrom to about 2 angstroms, as measured by a root mean square (RMS) The roughness profile, TIFF2026506854000002.tif1635, contains regularly spaced points along the trace, and i is the vertical distance from the mean line to the data point. With a surface roughness preferably less than 2 Angstroms, the surface is ready for the subsequent bonding operation, which is further described below. In addition to polishing, cleaning of the substrate 100 with the semiconductor layer 110 is optional. If necessary, the wafer can be cleaned, for example, in standard SC1 and / or SC2 solutions.

[0059] The single crystal semiconductor handle substrate 100 fabricated according to the methods described herein to include the semiconductor layer 110 (shown in FIG. 4 ) is then bonded to a single crystal semiconductor donor substrate 200 (shown in FIG. 5 ), e.g., a single crystal semiconductor donor wafer, including a dielectric layer 210 formed on its front surface 202. The single crystal semiconductor donor substrate 200, like the substrate 100, may be a single crystal semiconductor wafer. In some embodiments, the donor substrate 200 includes a semiconductor material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Depending on the desired characteristics of the final integrated circuit device, the single crystal semiconductor (e.g., silicon) donor substrate 200 may include a dopant selected from the group consisting of boron, arsenic, and phosphorus. The resistivity of the single crystal semiconductor (e.g., silicon) donor substrate 200 can be in the range of 0.01 ohm-cm to 500 ohm-cm, e.g., 1 ohm-cm to 100 ohm-cm, 1 ohm-cm to 50 ohm-cm, typically 5 to 25 ohm-cm. The single crystal semiconductor donor substrate 200 can be subjected to standard process steps, including oxidation, implantation, and post-implant cleaning. Thus, a semiconductor donor substrate 200, such as an etched and polished, optionally oxidized, single crystal semiconductor wafer of a material conventionally used in the fabrication of multilayer semiconductor structures, e.g., a single crystal silicon donor wafer, is subjected to ion implantation to form a damaged layer or cleave plane 212 within the donor substrate 200.

[0060] As described above, the semiconductor donor substrate 200 can include a dielectric layer 210 formed on its front surface 202. Suitable dielectric layers 210 can include materials selected from silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and combinations thereof. In some embodiments, the dielectric layer 210 includes an oxide layer having a thickness of at least about 10 nm, e.g., from about 10 nm to about 10,000 nm, from about 10 nm to about 5,000 nm, or from about 100 nm to about 800 nm.

[0061] In some embodiments, the front surface 202 of the single crystal semiconductor donor substrate 200 (e.g., a single crystal silicon donor substrate) can be thermally oxidized (consuming some portion of the deposited semiconductor material film) to create the dielectric layer 210 (e.g., a semiconductor oxide film such as a silicon dioxide film), or a semiconductor oxide (e.g., silicon dioxide) film can be grown by CVD oxide deposition to form the dielectric layer 210. The oxidation operation performed on the front surface 202 of the donor substrate 200 can be similar to that described above for the front surface 102 of the handle substrate 100. In some embodiments, the front surface 202 of the single crystal semiconductor donor substrate 200 can be thermally oxidized in a furnace such as ASM A400 or ASM A412 in the same manner as described above. In some embodiments, the donor substrate 200 is oxidized to provide a dielectric layer 210 on the front surface 202 that is at least about 10 nm thick, for example, from about 10 nm to about 10,000 nm, from about 10 nm to about 5000 nm, or from about 100 nm to about 800 nm.

[0062] The semiconductor device layer 402 in the semiconductor-on-insulator composite structure 400 (shown in FIG. 7 ) originates from a single crystal semiconductor donor substrate 200. The semiconductor device layer 402 may be transferred onto the semiconductor handle substrate 100 by a wafer thinning technique, such as etching the semiconductor donor substrate 200, or by cleaving the semiconductor donor substrate 200, including the cleavage plane 212.

[0063] The cleave plane 212 can be formed in the donor substrate 200 by ion implantation techniques. The ion implantation can be performed in commercially available equipment such as Applied Materials Quantum H. The implanted ions include He, H, H2, or combinations thereof. The ion implantation is performed at a density and duration sufficient to form the cleave plane 212 in the semiconductor donor substrate 200. The implantation density is approximately 10 12 ions / cm 2 ~about 10 17 ions / cm 2 , for example, about 10 14 ions / cm2 ~about 10 17 ions / cm 2 The implant energy can range from about 1 keV to about 3,000 keV, for example, from about 10 keV to about 3,000 keV. The implant depth determines the thickness of the single crystal semiconductor device layer 402 in the final semiconductor-on-insulator structure 400 (shown in FIG. 7). In some embodiments, it may be desirable to subject the single crystal semiconductor donor substrate 200 to a cleaning operation after implantation. In some preferred embodiments, the cleaning may include a piranha clean, followed by a deionized water rinse and a clean using SC1 and / or SC2 solutions.

[0064] In some embodiments, the single crystal semiconductor donor substrate 200 having an ion-implanted region formed therein by helium and / or hydrogen ion implantation is annealed at a temperature sufficient to form a thermally activated cleave plane 212 in the donor substrate 200. An example of a suitable tool can be a simple box furnace, such as a Blue M model. In some preferred embodiments, the ion-implanted single crystal semiconductor donor substrate 200 is annealed at a temperature between about 200°C and about 350°C, between about 225°C and about 325°C, and preferably about 300°C. The thermal anneal may be performed for a duration between about 2 hours and about 10 hours, for example, between about 2 hours and about 8 hours. Thermal annealing within these temperature ranges is sufficient to form the thermally activated cleave plane 212. After thermal annealing to activate the cleaved surface 212, the front surface 202, which may optionally include the dielectric layer 210, and optionally the back surface 204 of the single crystal semiconductor donor substrate 200 surface may be cleaned using the cleaning operations described above.

[0065] In some embodiments, the ion-implanted, optionally cleaned, and optionally annealed single-crystal semiconductor donor substrate 200 is subjected to oxygen plasma and / or nitrogen plasma surface activation. In some embodiments, the oxygen plasma surface activation tool is a commercially available tool, such as one available from EV Group, such as the EVG® 810LT Low Temp Plasma Activation System. The ion-implanted and optionally cleaned single-crystal semiconductor donor substrate 200 is loaded into a chamber. The chamber is evacuated and backfilled with O to a subatmospheric pressure, thereby generating a plasma. The single-crystal semiconductor donor substrate 200 is exposed to this plasma for a desired time, which may range from about 1 second to about 120 seconds. The oxygen plasma surface oxidation is performed to render the front surface 202 of the single-crystal semiconductor donor substrate 200, and optionally the dielectric layer 210 formed on the front surface 202, hydrophilic and amenable to bonding to a single-crystal semiconductor handle substrate fabricated according to the above-described method.

[0066] 6, a hydrophilic front surface layer (e.g., a hydrophilic exposed surface of the dielectric layer 210) of the single crystal semiconductor donor substrate 200 is brought into intimate contact with the exposed surface of the semiconductor layer 110 on the front surface 102 of the single crystal semiconductor handle substrate 100, thereby forming a bonded structure 300. In the illustrated embodiment, the bonded structure 300 includes a dielectric layer 210, e.g., a buried oxide layer, contributed by the oxidized front surface 202 of the single crystal semiconductor donor substrate 200, in interfacial contact with the semiconductor charge trapping layer 110. In some embodiments, the dielectric layer 210, e.g., the buried oxide layer, has a thickness of at least about 10 nm, e.g., from about 10 nm to about 10,000 nm, from about 10 nm to about 5,000 nm, or from about 100 nm to about 800 nm.

[0067] Because the mechanical bond between the semiconductor charge trapping layer 110 and the dielectric layer 210 is relatively weak, the bonded structure 300 is further annealed to solidify the bond. In some embodiments, the bonded structure 300 is annealed at a temperature sufficient to form a thermally activated cleavage plane 212 in the single crystal semiconductor donor substrate 200. An example of a suitable tool may be a simple box furnace, such as a Blue M model. In some embodiments, the bonded structure 300 is annealed at a temperature between about 200°C and about 350°C, between about 225°C and about 325°C, and preferably about 300°C. The thermal anneal may be performed for a duration between about 0.5 hours and about 10 hours, and preferably for a duration of about 2 hours. Thermal annealing within these temperature ranges is sufficient to form the thermally activated cleavage plane 212. After the thermal anneal to activate the cleavage plane 212, the bonded structure 300 can be cleaved to produce the final cleaved composite structure 400 shown in FIG. 7.

[0068] After thermal annealing of the bonded structure 300, the bond between the single-crystal semiconductor donor substrate 200 and the single-crystal semiconductor handle substrate 100 is strong enough to initiate layer transfer by cleaving the bonded structure 300 at the cleavage plane 212. Cleaving can occur according to techniques known in the art. In some embodiments, the bonded structure 300 may be placed in a conventional cleaving station secured to a stationary suction cup on one side (e.g., on one of the rear surfaces 104, 204) and secured by an additional suction cup on a hinged arm on the other side (e.g., on the other of the rear surfaces 104, 204). A crack initiates near the suction cup attachment, causing the movable arm to pivot about the hinge and cleave the donor substrate 200. Cleaving removes a portion of the semiconductor donor substrate 200, thereby leaving a semiconductor device layer 402, preferably a silicon device layer, on the semiconductor-on-insulator composite structure 400 (shown in FIG. 7 ).

[0069] After cleaving, the cleaved structure 400 may be subjected to a high-temperature anneal to further strengthen the bond between the transferred device layer 402 and the single-crystal semiconductor handle substrate 100. An example of a suitable tool may be a vertical furnace, such as an ASM A400 or ASM A412. In some preferred embodiments, the cleaved structure 400 is annealed at a temperature of about 1000°C to about 1200°C, preferably about 1000°C. The thermal anneal may be performed for a duration of about 0.5 hours to about 8 hours. Thermal annealing within these temperature ranges is sufficient to strengthen the bond between the transferred device layer 402 and the single-crystal semiconductor handle substrate 100.

[0070] After cleaving and high-temperature annealing, the exposed surfaces of the cleaved structure 400 (e.g., the exposed surface 104 and / or the exposed surface of the transferred device layer 402) are sufficiently smooth as a result of the high-temperature annealing. In some embodiments, an epitaxial layer (not shown) may be deposited on the exposed surface of the transferred device layer 402. Referring to FIG. 7 , the completed multilayer structure 400, i.e., the semiconductor-on-insulator structure 400, includes a high-resistivity single-crystal semiconductor handle substrate 100 (e.g., a single-crystal silicon handle substrate), a semiconductor charge trapping layer 110, a dielectric layer 210 (e.g., a semiconductor oxide layer such as a silicon dioxide layer created from oxidation of the front surface 202 of the single-crystal semiconductor donor substrate 200), and a semiconductor device layer 402 (created by cleaving and / or thinning the donor substrate 200). Further oxidation may be performed, for example, on the exposed surface 104, to reduce curvature or warpage of the structure 400. The final structure 400 may then be subjected to end-of-line metrology inspection and finally cleaned using a typical SC1-SC2 process.

[0071] The following non-limiting examples further illustrate the present invention. [Example]

[0072] Example 1 Comparison of the change in three-point wafer bow after deposition of a polycrystalline semiconductor layer for various annealing conditions.

[0073] Various low-temperature annealing conditions for deposited polycrystalline silicon layers were compared with a control without a post-deposition anneal. In one approach, a polycrystalline silicon layer was deposited, the temperature was maintained at the polycrystalline silicon layer deposition temperature, and then a post-deposition anneal was performed for a certain duration. In another approach, the same duration of annealing was performed at the same temperature, but the annealing was dispersed by intermittently pausing the deposition process according to the deposition-anneal cycle process disclosed herein. Specifically, seven cycles of depositing portions of a polycrystalline silicon layer and annealing the deposited portions of the polycrystalline silicon layer were performed for a total duration approximately equal to the deposition and anneal duration of the PDA approach. For each of the three conditions evaluated, a polycrystalline silicon seed layer with various seed anneal times at temperatures above 1000°C was formed prior to deposition of the polycrystalline silicon layer.

[0074] Intermittent annealing of polycrystalline silicon material during deposition reduces the distance required for outdiffusion of interstitials from grain boundaries, thus shortening the time required for their removal. As a result, wafers with acceptable levels of bow and warpage are produced, signaling that the polycrystalline silicon layer has the desired level of tensile stress. While bow and warpage levels may be higher than those resulting from higher-temperature anneals (e.g., above 1000°C), the intermittent low-temperature annealing operation offers the advantage of significantly reducing or eliminating crystallographic slip defect levels in high-resistivity substrates. Additionally, improved bow and warpage levels were achieved in processes where the annealing time of the polycrystalline silicon seed layer was increased. Furthermore, performing intermittent anneals during polycrystalline silicon deposition was shown to be more effective at reducing three-point wafer bow than a single post-deposition anneal step of the same duration.

[0075] Figures 8 and 9 compare the difference in three-point wafer curvature after deposition of a polysilicon layer after a higher temperature post-deposition anneal (labeled POR) and an intermittent low-temperature anneal according to the present disclosure (labeled novel invention). Comparing the post-deposition data for the high-temperature anneal and novel intermittent anneal processes, as shown in Figure 8, the novel intermittent anneal process exhibits higher compressive stress (positive curvature values) than the POR process (tensile stress in the POR wafer, negative curvature values). However, as shown in Figure 9, after the subsequent CMP process, a larger negative curvature (greater tensile stress) is observed with the novel intermittent anneal process, which helps to better balance the compressive stress induced by the buried oxide layer and reduce bowing and warpage in the final semiconductor-on-insulator wafer.

[0076] Example 2 Comparison of wafer SFQR after deposition of polycrystalline semiconductor layer for various annealing conditions.

[0077] The comparison of the techniques described above in Example 1 was also performed on the site flatness of post-deposition wafers. In addition to controlling post-deposition three-point wafer bow and crystallographic slip, it is also important to control the increase in site flatness (measured as SFQR) during polysilicon deposition. During polysilicon processing, polysilicon is intentionally deposited on the front surface of the handle wafer. However, because the reaction chamber is filled with reactants, the reactants can also diffuse around the wafer edge and deposit on the rear surface of the handle wafer. In many cases, the rear surface deposition is not uniform, resulting in a decrease in SFQR site flatness measurement. While all conditions tested showed some improvement in SFQR with increasing seed layer anneal time, post-deposition wafers produced using intermittent pauses and anneals during deposition showed the greatest improvement in site flatness, especially at the edge sites where site flatness was poorest. Comparing the results of the novel intermittent annealing process with the high-temperature post-deposition annealing process, the SFQR results are significantly better for the intermittent deposition process, as shown in Figure 10.

[0078] As used herein, the terms "about," "substantially," "essentially," and "approximately," when used in conjunction with a range of dimensions, concentrations, temperatures, or other physical or chemical properties or characteristics, are meant to encompass variations that may exist at the upper and / or lower limits of the range of the property or characteristic, including, for example, variations that result from rounding, measurement methods, or other statistical variations.

[0079] When introducing elements of the present disclosure or embodiment(s) thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more elements. The terms "comprising," "including," "containing," and "having" are intended to be inclusive and mean that additional elements may be present other than the listed elements. The use of terms indicating a specific orientation (e.g., "top," "bottom," "side," "front," "back," etc.) is for convenience of description and does not require any particular orientation of the described items.

[0080] Because various changes can be made in the above-described structures and methods without departing from the scope of the present disclosure, it is intended that all matter contained in the above description and shown in the accompanying drawing(s) shall be interpreted as illustrative and not in a limiting sense.

Claims

1. 1. A method of making a multi-layer structure, comprising: providing a single crystal semiconductor handle substrate, the single crystal semiconductor handle substrate comprising two major substantially parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a rear surface of the single crystal semiconductor handle substrate, a peripheral edge joining the front and rear surfaces of the single crystal semiconductor handle substrate, and a central plane between the front and rear surfaces of the single crystal semiconductor handle substrate, the single crystal semiconductor handle substrate having a minimum bulk area resistivity of at least about 500 ohm-cm; Depositing a semiconductor layer on the front surface of the monocrystalline semiconductor handle substrate, wherein depositing the semiconductor layer is performed by two or more cycles of depositing a portion of the semiconductor layer, interrupting the deposition after the portion of the semiconductor layer has been deposited, and annealing the portion of the semiconductor layer; A method comprising:

2. The cycle of depositing the semiconductor layer comprises: depositing the portion of the semiconductor layer at a deposition temperature; annealing the portion of the semiconductor layer at an annealing temperature; Including, The method of claim 1.

3. the deposition temperature and the annealing temperature are within 10°C of each other; The method of claim 2.

4. the deposition temperature and the annealing temperature are within 5°C of each other; The method of claim 2.

5. the deposition temperature and the annealing temperature are within 1°C of each other; The method of claim 2.

6. no temperature rise occurs between the deposition temperature and the annealing temperature; The method of claim 2.

7. the deposition temperature and the annealing temperature are each less than 1000°C; The method of claim 2.

8. the deposition temperature and the annealing temperature each exceed 850°C; The method of claim 2.

9. The deposition temperature and the annealing temperature are each between 850°C and 1000°C; The method of claim 2.

10. at least one of the deposition temperature and the annealing temperature is the same for each of the two or more cycles; The method of claim 2.

11. each of the deposition temperature and the annealing temperature is the same for each cycle; The method of claim 10.

12. depositing the semiconductor layer is performed by at least three cycles of depositing the portion of the semiconductor layer, interrupting the deposition after the portion of the semiconductor layer has been deposited, and annealing the portion of the semiconductor layer; The method according to any one of claims 1 to 11.

13. depositing the semiconductor layer is performed by 3 to 10 cycles of depositing the portion of the semiconductor layer, interrupting the deposition after the portion of the semiconductor layer has been deposited, and annealing the portion of the semiconductor layer; The method according to any one of claims 1 to 12.

14. each cycle of said depositing said semiconductor layer produces a respective portion of said semiconductor layer having a thickness of 0.05 micrometers to 5 micrometers; The method according to any one of claims 1 to 13.

15. each cycle of said depositing said semiconductor layer produces a respective portion of said semiconductor layer having a thickness of between 0.1 micrometers and 1 micrometer; The method according to any one of claims 1 to 14.

16. the semiconductor layer has a thickness of 0.1 micrometers to 50 micrometers; The method according to any one of claims 1 to 15.

17. the semiconductor layer has a thickness of 1 micrometer to 10 micrometers; The method according to any one of claims 1 to 16.

18. further comprising planarizing the semiconductor layer after depositing the semiconductor layer. The method according to any one of claims 1 to 17.

19. planarizing the semiconductor layer includes polishing the semiconductor layer using chemical mechanical polishing; 20. The method of claim 18.

20. depositing the semiconductor layer further comprises depositing a semiconductor seed layer and annealing the semiconductor seed layer before performing the two or more cycles of depositing the portion of the semiconductor layer and interrupting the deposition after the portion of the semiconductor layer has been deposited and annealing the portion of the semiconductor layer.

20. The method according to any one of claims 1 to 19.

21. said annealing said semiconductor seed layer is performed at a higher temperature than said annealing during said two or more cycles; 21. The method of claim 20.

22. the annealing of the semiconductor seed layer is performed at a temperature greater than 1000°C, and the annealing during the two or more cycles is performed at a temperature less than 1000°C.

21. The method of claim 20.

23. After annealing the semiconductor seed layer and before performing the two or more cycles of depositing the portion of the semiconductor layer and annealing the portion of the semiconductor layer, further comprising cooling the single crystal semiconductor handle substrate to a temperature of less than 1000° C.

21. The method of claim 20.

24. the semiconductor layer comprises a polycrystalline semiconductor material and the semiconductor seed layer is a polycrystalline semiconductor seed layer; The method according to any one of claims 20 to 23.

25. the semiconductor seed layer having a thickness of less than 3 micrometers; The method according to any one of claims 20 to 24.

26. depositing the semiconductor layer is performed using chemical vapor deposition; 26. The method according to any one of claims 1 to 25.

27. the semiconductor layer comprises a polycrystalline or amorphous semiconductor material selected from the group consisting of silicon, silicon germanium (SiGe), silicon carbide (SiC), and germanium (Ge); 27. The method according to any one of claims 1 to 26.

28. the single crystal semiconductor handle substrate comprises silicon; 28. The method according to any one of claims 1 to 27.

29. The monocrystalline semiconductor handle substrate comprises a silicon wafer sliced ​​from a monocrystalline silicon ingot grown by the Czochralski method or the float zone method; 29. The method according to any one of claims 1 to 28.

30. the single crystal semiconductor handle substrate has a bulk resistivity of 500 ohm-cm to 100,000 ohm-cm, 1000 ohm-cm to 100,000 ohm-cm, 1000 ohm-cm to 10,000 ohm-cm, 2000 ohm-cm to 10,000 ohm-cm, 3000 ohm-cm to 10,000 ohm-cm, or 3000 ohm-cm to 5000 ohm-cm; 30. The method according to any one of claims 1 to 29.

31. bonding an exposed front surface layer of a single crystal semiconductor donor substrate to the semiconductor layer, wherein the single crystal semiconductor donor substrate comprises two major substantially parallel surfaces, one of the surfaces being a front surface of the single crystal semiconductor donor substrate and the other of the surfaces being a back surface of the single crystal semiconductor donor substrate, a peripheral edge connecting the front and back surfaces of the single crystal semiconductor donor substrate, and a central plane between the front and back surfaces of the single crystal semiconductor donor substrate, and the single crystal semiconductor donor substrate further comprises a cleavage plane, thereby forming a bonded structure comprising the single crystal semiconductor handle substrate, the semiconductor layer, and the single crystal semiconductor donor substrate. The method according to any one of claims 1 to 30.

32. the exposed front surface layer of the single crystal semiconductor donor substrate comprises a dielectric layer, and bonding the exposed front surface layer of the single crystal semiconductor donor substrate to the semiconductor layer comprises bonding the dielectric layer to the semiconductor layer, thereby forming a bonded structure comprising the single crystal semiconductor handle substrate, the semiconductor layer, the dielectric layer, and the single crystal semiconductor donor substrate.

32. The method of claim 31 .

33. the single crystal semiconductor donor substrate comprising a cleavage plane, the method further comprising cleaving the bonded structure at the cleavage plane, thereby forming a cleaved structure comprising the single crystal semiconductor handle substrate, the semiconductor layer, the dielectric layer, and a single crystal semiconductor device layer.

33. The method of claim 32.

34. 1. A method of making a multi-layer structure, comprising: providing a single crystal semiconductor handle substrate, the single crystal semiconductor handle substrate comprising two major substantially parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a rear surface of the single crystal semiconductor handle substrate, a peripheral edge joining the front and rear surfaces of the single crystal semiconductor handle substrate, and a central plane between the front and rear surfaces of the single crystal semiconductor handle substrate, the single crystal semiconductor handle substrate having a minimum bulk area resistivity of at least about 500 ohm-cm; depositing a polycrystalline semiconductor seed layer on the front surface of the monocrystalline semiconductor handle substrate; annealing the polycrystalline semiconductor seed layer; depositing a first layer of polycrystalline semiconductor material at a deposition temperature on the annealed polycrystalline semiconductor seed layer; annealing the first layer of polycrystalline semiconductor material at a temperature lower than the temperature at which the polycrystalline semiconductor seed layer is annealed; A method comprising:

35. the polycrystalline semiconductor seed layer is annealed at a temperature greater than 1000°C and the first layer of polycrystalline semiconductor material is annealed at a temperature less than 1000°C; 35. The method of claim 34.

36. depositing the first layer of polycrystalline semiconductor material at a deposition temperature; annealing the first layer of polycrystalline semiconductor material at an annealing temperature that is lower than the temperature at which the polycrystalline semiconductor seed layer is annealed; further comprising:

36. The method of claim 34 or 35.

37. 37. The method of claim 36, wherein the deposition temperature and the annealing temperature are within 10°C of each other.

38. the deposition temperature and the annealing temperature are within 5°C of each other; 37. The method of claim 36.

39. the deposition temperature and the annealing temperature are within 1°C of each other; 37. The method of claim 36.

40. no temperature rise occurs between the deposition temperature and the annealing temperature; 37. The method of claim 36.

41. the deposition temperature and the annealing temperature are each less than 1000°C; 37. The method of claim 36.

42. the deposition temperature and the annealing temperature each exceed 850°C; 37. The method of claim 36.

43. The deposition temperature and the annealing temperature are each between 850°C and 1000°C; 37. The method of claim 36.

44. depositing a second layer of polycrystalline semiconductor material on the annealed first layer of polycrystalline semiconductor material; annealing the second layer of polycrystalline semiconductor material at a temperature lower than the temperature at which the polycrystalline semiconductor seed layer is annealed; further comprising:

44. The method according to any one of claims 34 to 43.

45. depositing a third layer of polycrystalline semiconductor material on the annealed second polycrystalline semiconductor layer; annealing the third layer of polycrystalline semiconductor material at a temperature lower than the temperature at which the polycrystalline semiconductor seed layer is annealed; further comprising:

45. The method of claim 44.

46. each of the first, second, and third layers of polycrystalline semiconductor material having a thickness of 0.05 micrometers to 5 micrometers; 46. ​​The method of claim 45.

47. each of the first, second, and third layers of polycrystalline semiconductor material having a thickness between 0.1 micrometers and 1 micrometer; 46. ​​The method of claim 45.

48. the charge trapping layer including the first, second, and third layers of polycrystalline semiconductor material has a thickness of 0.1 micrometers to 50 micrometers; 46. ​​The method of claim 45.

49. the charge trapping layer including the first, second, and third layers of polycrystalline semiconductor material has a thickness of 1 micrometer to 10 micrometers; 46. ​​The method of claim 45.

50. after annealing the polycrystalline semiconductor seed layer and before depositing the first layer of polycrystalline semiconductor material, further comprising cooling the single crystal semiconductor handle substrate to a temperature less than 1000°C.

50. The method of any one of claims 34 to 49.

51. the polycrystalline semiconductor seed layer having a thickness of less than 3 micrometers; 51. The method of any one of claims 34 to 50.

52. depositing the first layer of polycrystalline semiconductor material is performed using chemical vapor deposition; 52. The method of any one of claims 34 to 51.

53. the first layer of polycrystalline semiconductor material comprises a semiconductor material selected from the group consisting of silicon, silicon germanium (SiGe), silicon carbide (SiC), and germanium (Ge); 53. The method of any one of claims 34 to 52.

54. the single crystal semiconductor handle substrate comprises silicon; 54. The method of any one of claims 34 to 53.

55. The monocrystalline semiconductor handle substrate comprises a silicon wafer sliced ​​from a monocrystalline silicon ingot grown by the Czochralski method or the float zone method; 55. The method of any one of claims 34 to 54.

56. the single crystal semiconductor handle substrate has a bulk resistivity of 500 ohm-cm to 100,000 ohm-cm, 1000 ohm-cm to 100,000 ohm-cm, 1000 ohm-cm to 10,000 ohm-cm, 2000 ohm-cm to 10,000 ohm-cm, 3000 ohm-cm to 10,000 ohm-cm, or 3000 ohm-cm to 5000 ohm-cm; 56. The method of any one of claims 34 to 55.

57. and further comprising bonding an exposed front surface layer of a single crystal semiconductor donor substrate to a charge trapping layer of the single crystal semiconductor handle substrate comprising the first layer of polycrystalline semiconductor material, wherein the single crystal semiconductor donor substrate comprises two major substantially parallel surfaces, one of the surfaces being a front surface of the single crystal semiconductor donor substrate and the other of the surfaces being a back surface of the single crystal semiconductor donor substrate, a peripheral edge connecting the front and back surfaces of the single crystal semiconductor donor substrate, and a central plane between the front and back surfaces of the single crystal semiconductor donor substrate, and the single crystal semiconductor donor substrate further comprises a cleavage plane, thereby forming a bonded structure comprising the single crystal semiconductor handle substrate, the charge trapping layer, and the single crystal semiconductor donor substrate.

57. The method of any one of claims 34 to 56.

58. the exposed front surface layer of the single crystal semiconductor donor substrate comprises a dielectric layer, and bonding the exposed front surface layer of the single crystal semiconductor donor substrate to the charge trapping layer comprises bonding the dielectric layer to the charge trapping layer, thereby forming a bonded structure comprising the single crystal semiconductor handle substrate, the charge trapping layer, the dielectric layer, and the single crystal semiconductor donor substrate.

58. The method of claim 57.

59. the single crystal semiconductor donor substrate comprising a cleavage plane, the method further comprising cleaving the bonded structure at the cleavage plane, thereby forming a cleaved structure comprising the single crystal semiconductor handle substrate, the charge trapping layer, the dielectric layer, and a single crystal semiconductor device layer.

59. The method of claim 58.

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